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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12 
13 #include "clk-alpha-pll.h"
14 #include "common.h"
15 
16 #define PLL_MODE(p)		((p)->offset + 0x0)
17 # define PLL_OUTCTRL		BIT(0)
18 # define PLL_BYPASSNL		BIT(1)
19 # define PLL_RESET_N		BIT(2)
20 # define PLL_OFFLINE_REQ	BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT	8
22 # define PLL_LOCK_COUNT_MASK	0x3f
23 # define PLL_BIAS_COUNT_SHIFT	14
24 # define PLL_BIAS_COUNT_MASK	0x3f
25 # define PLL_VOTE_FSM_ENA	BIT(20)
26 # define PLL_FSM_ENA		BIT(20)
27 # define PLL_VOTE_FSM_RESET	BIT(21)
28 # define PLL_UPDATE		BIT(22)
29 # define PLL_UPDATE_BYPASS	BIT(23)
30 # define PLL_FSM_LEGACY_MODE	BIT(24)
31 # define PLL_OFFLINE_ACK	BIT(28)
32 # define ALPHA_PLL_ACK_LATCH	BIT(29)
33 # define PLL_ACTIVE_FLAG	BIT(30)
34 # define PLL_LOCK_DET		BIT(31)
35 
36 #define PLL_L_VAL(p)		((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p)	((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p)	((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p)	((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40 
41 #define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT	8
43 # define PLL_POST_DIV_MASK(p)	GENMASK((p)->width, 0)
44 # define PLL_ALPHA_EN		BIT(24)
45 # define PLL_ALPHA_MODE		BIT(25)
46 # define PLL_VCO_SHIFT		20
47 # define PLL_VCO_MASK		0x3
48 
49 #define PLL_USER_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
51 
52 #define PLL_CONFIG_CTL(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
59 #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
60 #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
61 
62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
63 	[CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
64 		[PLL_OFF_L_VAL] = 0x04,
65 		[PLL_OFF_ALPHA_VAL] = 0x08,
66 		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
67 		[PLL_OFF_USER_CTL] = 0x10,
68 		[PLL_OFF_USER_CTL_U] = 0x14,
69 		[PLL_OFF_CONFIG_CTL] = 0x18,
70 		[PLL_OFF_TEST_CTL] = 0x1c,
71 		[PLL_OFF_TEST_CTL_U] = 0x20,
72 		[PLL_OFF_STATUS] = 0x24,
73 	},
74 	[CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
75 		[PLL_OFF_L_VAL] = 0x04,
76 		[PLL_OFF_ALPHA_VAL] = 0x08,
77 		[PLL_OFF_USER_CTL] = 0x10,
78 		[PLL_OFF_CONFIG_CTL] = 0x14,
79 		[PLL_OFF_CONFIG_CTL_U] = 0x18,
80 		[PLL_OFF_TEST_CTL] = 0x1c,
81 		[PLL_OFF_TEST_CTL_U] = 0x20,
82 		[PLL_OFF_STATUS] = 0x24,
83 	},
84 	[CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
85 		[PLL_OFF_L_VAL] = 0x04,
86 		[PLL_OFF_ALPHA_VAL] = 0x08,
87 		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
88 		[PLL_OFF_USER_CTL] = 0x10,
89 		[PLL_OFF_CONFIG_CTL] = 0x18,
90 		[PLL_OFF_TEST_CTL] = 0x1c,
91 		[PLL_OFF_STATUS] = 0x24,
92 	},
93 	[CLK_ALPHA_PLL_TYPE_FABIA] =  {
94 		[PLL_OFF_L_VAL] = 0x04,
95 		[PLL_OFF_USER_CTL] = 0x0c,
96 		[PLL_OFF_USER_CTL_U] = 0x10,
97 		[PLL_OFF_CONFIG_CTL] = 0x14,
98 		[PLL_OFF_CONFIG_CTL_U] = 0x18,
99 		[PLL_OFF_TEST_CTL] = 0x1c,
100 		[PLL_OFF_TEST_CTL_U] = 0x20,
101 		[PLL_OFF_STATUS] = 0x24,
102 		[PLL_OFF_OPMODE] = 0x2c,
103 		[PLL_OFF_FRAC] = 0x38,
104 	},
105 	[CLK_ALPHA_PLL_TYPE_TRION] = {
106 		[PLL_OFF_L_VAL] = 0x04,
107 		[PLL_OFF_CAL_L_VAL] = 0x08,
108 		[PLL_OFF_USER_CTL] = 0x0c,
109 		[PLL_OFF_USER_CTL_U] = 0x10,
110 		[PLL_OFF_USER_CTL_U1] = 0x14,
111 		[PLL_OFF_CONFIG_CTL] = 0x18,
112 		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
113 		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
114 		[PLL_OFF_TEST_CTL] = 0x24,
115 		[PLL_OFF_TEST_CTL_U] = 0x28,
116 		[PLL_OFF_TEST_CTL_U1] = 0x2c,
117 		[PLL_OFF_STATUS] = 0x30,
118 		[PLL_OFF_OPMODE] = 0x38,
119 		[PLL_OFF_ALPHA_VAL] = 0x40,
120 	},
121 	[CLK_ALPHA_PLL_TYPE_AGERA] =  {
122 		[PLL_OFF_L_VAL] = 0x04,
123 		[PLL_OFF_ALPHA_VAL] = 0x08,
124 		[PLL_OFF_USER_CTL] = 0x0c,
125 		[PLL_OFF_CONFIG_CTL] = 0x10,
126 		[PLL_OFF_CONFIG_CTL_U] = 0x14,
127 		[PLL_OFF_TEST_CTL] = 0x18,
128 		[PLL_OFF_TEST_CTL_U] = 0x1c,
129 		[PLL_OFF_STATUS] = 0x2c,
130 	},
131 	[CLK_ALPHA_PLL_TYPE_ZONDA] =  {
132 		[PLL_OFF_L_VAL] = 0x04,
133 		[PLL_OFF_ALPHA_VAL] = 0x08,
134 		[PLL_OFF_USER_CTL] = 0x0c,
135 		[PLL_OFF_CONFIG_CTL] = 0x10,
136 		[PLL_OFF_CONFIG_CTL_U] = 0x14,
137 		[PLL_OFF_CONFIG_CTL_U1] = 0x18,
138 		[PLL_OFF_TEST_CTL] = 0x1c,
139 		[PLL_OFF_TEST_CTL_U] = 0x20,
140 		[PLL_OFF_TEST_CTL_U1] = 0x24,
141 		[PLL_OFF_OPMODE] = 0x28,
142 		[PLL_OFF_STATUS] = 0x38,
143 	},
144 	[CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
145 		[PLL_OFF_OPMODE] = 0x04,
146 		[PLL_OFF_STATUS] = 0x0c,
147 		[PLL_OFF_L_VAL] = 0x10,
148 		[PLL_OFF_ALPHA_VAL] = 0x14,
149 		[PLL_OFF_USER_CTL] = 0x18,
150 		[PLL_OFF_USER_CTL_U] = 0x1c,
151 		[PLL_OFF_CONFIG_CTL] = 0x20,
152 		[PLL_OFF_CONFIG_CTL_U] = 0x24,
153 		[PLL_OFF_CONFIG_CTL_U1] = 0x28,
154 		[PLL_OFF_TEST_CTL] = 0x2c,
155 		[PLL_OFF_TEST_CTL_U] = 0x30,
156 		[PLL_OFF_TEST_CTL_U1] = 0x34,
157 	},
158 	[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
159 		[PLL_OFF_OPMODE] = 0x04,
160 		[PLL_OFF_STATUS] = 0x0c,
161 		[PLL_OFF_L_VAL] = 0x10,
162 		[PLL_OFF_USER_CTL] = 0x14,
163 		[PLL_OFF_USER_CTL_U] = 0x18,
164 		[PLL_OFF_CONFIG_CTL] = 0x1c,
165 		[PLL_OFF_CONFIG_CTL_U] = 0x20,
166 		[PLL_OFF_CONFIG_CTL_U1] = 0x24,
167 		[PLL_OFF_TEST_CTL] = 0x28,
168 		[PLL_OFF_TEST_CTL_U] = 0x2c,
169 	},
170 	[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] =  {
171 		[PLL_OFF_L_VAL] = 0x04,
172 		[PLL_OFF_ALPHA_VAL] = 0x08,
173 		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
174 		[PLL_OFF_TEST_CTL] = 0x10,
175 		[PLL_OFF_TEST_CTL_U] = 0x14,
176 		[PLL_OFF_USER_CTL] = 0x18,
177 		[PLL_OFF_USER_CTL_U] = 0x1c,
178 		[PLL_OFF_CONFIG_CTL] = 0x20,
179 		[PLL_OFF_STATUS] = 0x24,
180 	},
181 	[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] =  {
182 		[PLL_OFF_L_VAL] = 0x04,
183 		[PLL_OFF_ALPHA_VAL] = 0x08,
184 		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
185 		[PLL_OFF_TEST_CTL] = 0x10,
186 		[PLL_OFF_TEST_CTL_U] = 0x14,
187 		[PLL_OFF_USER_CTL] = 0x18,
188 		[PLL_OFF_CONFIG_CTL] = 0x1C,
189 		[PLL_OFF_STATUS] = 0x20,
190 	},
191 };
192 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
193 
194 /*
195  * Even though 40 bits are present, use only 32 for ease of calculation.
196  */
197 #define ALPHA_REG_BITWIDTH	40
198 #define ALPHA_REG_16BIT_WIDTH	16
199 #define ALPHA_BITWIDTH		32U
200 #define ALPHA_SHIFT(w)		min(w, ALPHA_BITWIDTH)
201 
202 #define PLL_HUAYRA_M_WIDTH		8
203 #define PLL_HUAYRA_M_SHIFT		8
204 #define PLL_HUAYRA_M_MASK		0xff
205 #define PLL_HUAYRA_N_SHIFT		0
206 #define PLL_HUAYRA_N_MASK		0xff
207 #define PLL_HUAYRA_ALPHA_WIDTH		16
208 
209 #define PLL_STANDBY		0x0
210 #define PLL_RUN			0x1
211 #define PLL_OUT_MASK		0x7
212 #define PLL_RATE_MARGIN		500
213 
214 /* TRION PLL specific settings and offsets */
215 #define TRION_PLL_CAL_VAL	0x44
216 #define TRION_PCAL_DONE		BIT(26)
217 
218 /* LUCID PLL specific settings and offsets */
219 #define LUCID_PCAL_DONE		BIT(27)
220 
221 /* LUCID 5LPE PLL specific settings and offsets */
222 #define LUCID_5LPE_PCAL_DONE		BIT(11)
223 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH	BIT(13)
224 #define LUCID_5LPE_PLL_LATCH_INPUT	BIT(14)
225 #define LUCID_5LPE_ENABLE_VOTE_RUN	BIT(21)
226 
227 /* LUCID EVO PLL specific settings and offsets */
228 #define LUCID_EVO_PCAL_NOT_DONE		BIT(8)
229 #define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)
230 #define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)
231 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16
232 
233 /* ZONDA PLL specific */
234 #define ZONDA_PLL_OUT_MASK	0xf
235 #define ZONDA_STAY_IN_CFA	BIT(16)
236 #define ZONDA_PLL_FREQ_LOCK_DET	BIT(29)
237 
238 #define pll_alpha_width(p)					\
239 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
240 				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
241 
242 #define pll_has_64bit_config(p)	((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
243 
244 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
245 					   struct clk_alpha_pll, clkr)
246 
247 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
248 					   struct clk_alpha_pll_postdiv, clkr)
249 
wait_for_pll(struct clk_alpha_pll * pll,u32 mask,bool inverse,const char * action)250 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
251 			const char *action)
252 {
253 	u32 val;
254 	int count;
255 	int ret;
256 	const char *name = clk_hw_get_name(&pll->clkr.hw);
257 
258 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
259 	if (ret)
260 		return ret;
261 
262 	for (count = 200; count > 0; count--) {
263 		ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
264 		if (ret)
265 			return ret;
266 		if (inverse && !(val & mask))
267 			return 0;
268 		else if ((val & mask) == mask)
269 			return 0;
270 
271 		udelay(1);
272 	}
273 
274 	WARN(1, "%s failed to %s!\n", name, action);
275 	return -ETIMEDOUT;
276 }
277 
278 #define wait_for_pll_enable_active(pll) \
279 	wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
280 
281 #define wait_for_pll_enable_lock(pll) \
282 	wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
283 
284 #define wait_for_zonda_pll_freq_lock(pll) \
285 	wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
286 
287 #define wait_for_pll_disable(pll) \
288 	wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
289 
290 #define wait_for_pll_offline(pll) \
291 	wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
292 
293 #define wait_for_pll_update(pll) \
294 	wait_for_pll(pll, PLL_UPDATE, 1, "update")
295 
296 #define wait_for_pll_update_ack_set(pll) \
297 	wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
298 
299 #define wait_for_pll_update_ack_clear(pll) \
300 	wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
301 
clk_alpha_pll_write_config(struct regmap * regmap,unsigned int reg,unsigned int val)302 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
303 					unsigned int val)
304 {
305 	if (val)
306 		regmap_write(regmap, reg, val);
307 }
308 
clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)309 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
310 			     const struct alpha_pll_config *config)
311 {
312 	u32 val, mask;
313 
314 	regmap_write(regmap, PLL_L_VAL(pll), config->l);
315 	regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
316 	regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
317 
318 	if (pll_has_64bit_config(pll))
319 		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
320 			     config->config_ctl_hi_val);
321 
322 	if (pll_alpha_width(pll) > 32)
323 		regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
324 
325 	val = config->main_output_mask;
326 	val |= config->aux_output_mask;
327 	val |= config->aux2_output_mask;
328 	val |= config->early_output_mask;
329 	val |= config->pre_div_val;
330 	val |= config->post_div_val;
331 	val |= config->vco_val;
332 	val |= config->alpha_en_mask;
333 	val |= config->alpha_mode_mask;
334 
335 	mask = config->main_output_mask;
336 	mask |= config->aux_output_mask;
337 	mask |= config->aux2_output_mask;
338 	mask |= config->early_output_mask;
339 	mask |= config->pre_div_mask;
340 	mask |= config->post_div_mask;
341 	mask |= config->vco_mask;
342 
343 	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
344 
345 	if (pll->flags & SUPPORTS_FSM_MODE)
346 		qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
347 }
348 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
349 
clk_alpha_pll_hwfsm_enable(struct clk_hw * hw)350 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
351 {
352 	int ret;
353 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
354 	u32 val;
355 
356 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
357 	if (ret)
358 		return ret;
359 
360 	val |= PLL_FSM_ENA;
361 
362 	if (pll->flags & SUPPORTS_OFFLINE_REQ)
363 		val &= ~PLL_OFFLINE_REQ;
364 
365 	ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
366 	if (ret)
367 		return ret;
368 
369 	/* Make sure enable request goes through before waiting for update */
370 	mb();
371 
372 	return wait_for_pll_enable_active(pll);
373 }
374 
clk_alpha_pll_hwfsm_disable(struct clk_hw * hw)375 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
376 {
377 	int ret;
378 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
379 	u32 val;
380 
381 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
382 	if (ret)
383 		return;
384 
385 	if (pll->flags & SUPPORTS_OFFLINE_REQ) {
386 		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
387 					 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
388 		if (ret)
389 			return;
390 
391 		ret = wait_for_pll_offline(pll);
392 		if (ret)
393 			return;
394 	}
395 
396 	/* Disable hwfsm */
397 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
398 				 PLL_FSM_ENA, 0);
399 	if (ret)
400 		return;
401 
402 	wait_for_pll_disable(pll);
403 }
404 
pll_is_enabled(struct clk_hw * hw,u32 mask)405 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
406 {
407 	int ret;
408 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
409 	u32 val;
410 
411 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
412 	if (ret)
413 		return ret;
414 
415 	return !!(val & mask);
416 }
417 
clk_alpha_pll_hwfsm_is_enabled(struct clk_hw * hw)418 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
419 {
420 	return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
421 }
422 
clk_alpha_pll_is_enabled(struct clk_hw * hw)423 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
424 {
425 	return pll_is_enabled(hw, PLL_LOCK_DET);
426 }
427 
clk_alpha_pll_enable(struct clk_hw * hw)428 static int clk_alpha_pll_enable(struct clk_hw *hw)
429 {
430 	int ret;
431 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
432 	u32 val, mask;
433 
434 	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
435 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
436 	if (ret)
437 		return ret;
438 
439 	/* If in FSM mode, just vote for it */
440 	if (val & PLL_VOTE_FSM_ENA) {
441 		ret = clk_enable_regmap(hw);
442 		if (ret)
443 			return ret;
444 		return wait_for_pll_enable_active(pll);
445 	}
446 
447 	/* Skip if already enabled */
448 	if ((val & mask) == mask)
449 		return 0;
450 
451 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
452 				 PLL_BYPASSNL, PLL_BYPASSNL);
453 	if (ret)
454 		return ret;
455 
456 	/*
457 	 * H/W requires a 5us delay between disabling the bypass and
458 	 * de-asserting the reset.
459 	 */
460 	mb();
461 	udelay(5);
462 
463 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
464 				 PLL_RESET_N, PLL_RESET_N);
465 	if (ret)
466 		return ret;
467 
468 	ret = wait_for_pll_enable_lock(pll);
469 	if (ret)
470 		return ret;
471 
472 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
473 				 PLL_OUTCTRL, PLL_OUTCTRL);
474 
475 	/* Ensure that the write above goes through before returning. */
476 	mb();
477 	return ret;
478 }
479 
clk_alpha_pll_disable(struct clk_hw * hw)480 static void clk_alpha_pll_disable(struct clk_hw *hw)
481 {
482 	int ret;
483 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
484 	u32 val, mask;
485 
486 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
487 	if (ret)
488 		return;
489 
490 	/* If in FSM mode, just unvote it */
491 	if (val & PLL_VOTE_FSM_ENA) {
492 		clk_disable_regmap(hw);
493 		return;
494 	}
495 
496 	mask = PLL_OUTCTRL;
497 	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
498 
499 	/* Delay of 2 output clock ticks required until output is disabled */
500 	mb();
501 	udelay(1);
502 
503 	mask = PLL_RESET_N | PLL_BYPASSNL;
504 	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
505 }
506 
507 static unsigned long
alpha_pll_calc_rate(u64 prate,u32 l,u32 a,u32 alpha_width)508 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
509 {
510 	return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
511 }
512 
513 static unsigned long
alpha_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u64 * a,u32 alpha_width)514 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
515 		     u32 alpha_width)
516 {
517 	u64 remainder;
518 	u64 quotient;
519 
520 	quotient = rate;
521 	remainder = do_div(quotient, prate);
522 	*l = quotient;
523 
524 	if (!remainder) {
525 		*a = 0;
526 		return rate;
527 	}
528 
529 	/* Upper ALPHA_BITWIDTH bits of Alpha */
530 	quotient = remainder << ALPHA_SHIFT(alpha_width);
531 
532 	remainder = do_div(quotient, prate);
533 
534 	if (remainder)
535 		quotient++;
536 
537 	*a = quotient;
538 	return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
539 }
540 
541 static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll * pll,unsigned long rate)542 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
543 {
544 	const struct pll_vco *v = pll->vco_table;
545 	const struct pll_vco *end = v + pll->num_vco;
546 
547 	for (; v < end; v++)
548 		if (rate >= v->min_freq && rate <= v->max_freq)
549 			return v;
550 
551 	return NULL;
552 }
553 
554 static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)555 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
556 {
557 	u32 l, low, high, ctl;
558 	u64 a = 0, prate = parent_rate;
559 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
560 	u32 alpha_width = pll_alpha_width(pll);
561 
562 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
563 
564 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
565 	if (ctl & PLL_ALPHA_EN) {
566 		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
567 		if (alpha_width > 32) {
568 			regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
569 				    &high);
570 			a = (u64)high << 32 | low;
571 		} else {
572 			a = low & GENMASK(alpha_width - 1, 0);
573 		}
574 
575 		if (alpha_width > ALPHA_BITWIDTH)
576 			a >>= alpha_width - ALPHA_BITWIDTH;
577 	}
578 
579 	return alpha_pll_calc_rate(prate, l, a, alpha_width);
580 }
581 
582 
__clk_alpha_pll_update_latch(struct clk_alpha_pll * pll)583 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
584 {
585 	int ret;
586 	u32 mode;
587 
588 	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
589 
590 	/* Latch the input to the PLL */
591 	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
592 			   PLL_UPDATE);
593 
594 	/* Wait for 2 reference cycle before checking ACK bit */
595 	udelay(1);
596 
597 	/*
598 	 * PLL will latch the new L, Alpha and freq control word.
599 	 * PLL will respond by raising PLL_ACK_LATCH output when new programming
600 	 * has been latched in and PLL is being updated. When
601 	 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
602 	 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
603 	 */
604 	if (mode & PLL_UPDATE_BYPASS) {
605 		ret = wait_for_pll_update_ack_set(pll);
606 		if (ret)
607 			return ret;
608 
609 		regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
610 	} else {
611 		ret = wait_for_pll_update(pll);
612 		if (ret)
613 			return ret;
614 	}
615 
616 	ret = wait_for_pll_update_ack_clear(pll);
617 	if (ret)
618 		return ret;
619 
620 	/* Wait for PLL output to stabilize */
621 	udelay(10);
622 
623 	return 0;
624 }
625 
clk_alpha_pll_update_latch(struct clk_alpha_pll * pll,int (* is_enabled)(struct clk_hw *))626 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
627 				      int (*is_enabled)(struct clk_hw *))
628 {
629 	if (!is_enabled(&pll->clkr.hw) ||
630 	    !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
631 		return 0;
632 
633 	return __clk_alpha_pll_update_latch(pll);
634 }
635 
__clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,int (* is_enabled)(struct clk_hw *))636 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
637 				    unsigned long prate,
638 				    int (*is_enabled)(struct clk_hw *))
639 {
640 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
641 	const struct pll_vco *vco;
642 	u32 l, alpha_width = pll_alpha_width(pll);
643 	u64 a;
644 
645 	rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
646 	vco = alpha_pll_find_vco(pll, rate);
647 	if (pll->vco_table && !vco) {
648 		pr_err("%s: alpha pll not in a valid vco range\n",
649 		       clk_hw_get_name(hw));
650 		return -EINVAL;
651 	}
652 
653 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
654 
655 	if (alpha_width > ALPHA_BITWIDTH)
656 		a <<= alpha_width - ALPHA_BITWIDTH;
657 
658 	if (alpha_width > 32)
659 		regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
660 
661 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
662 
663 	if (vco) {
664 		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
665 				   PLL_VCO_MASK << PLL_VCO_SHIFT,
666 				   vco->val << PLL_VCO_SHIFT);
667 	}
668 
669 	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
670 			   PLL_ALPHA_EN, PLL_ALPHA_EN);
671 
672 	return clk_alpha_pll_update_latch(pll, is_enabled);
673 }
674 
clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)675 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
676 				  unsigned long prate)
677 {
678 	return __clk_alpha_pll_set_rate(hw, rate, prate,
679 					clk_alpha_pll_is_enabled);
680 }
681 
clk_alpha_pll_hwfsm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)682 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
683 					unsigned long prate)
684 {
685 	return __clk_alpha_pll_set_rate(hw, rate, prate,
686 					clk_alpha_pll_hwfsm_is_enabled);
687 }
688 
clk_alpha_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)689 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
690 				     unsigned long *prate)
691 {
692 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
693 	u32 l, alpha_width = pll_alpha_width(pll);
694 	u64 a;
695 	unsigned long min_freq, max_freq;
696 
697 	rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
698 	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
699 		return rate;
700 
701 	min_freq = pll->vco_table[0].min_freq;
702 	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
703 
704 	return clamp(rate, min_freq, max_freq);
705 }
706 
707 static unsigned long
alpha_huayra_pll_calc_rate(u64 prate,u32 l,u32 a)708 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
709 {
710 	/*
711 	 * a contains 16 bit alpha_val in two’s complement number in the range
712 	 * of [-0.5, 0.5).
713 	 */
714 	if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
715 		l -= 1;
716 
717 	return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
718 }
719 
720 static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u32 * a)721 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
722 			    u32 *l, u32 *a)
723 {
724 	u64 remainder;
725 	u64 quotient;
726 
727 	quotient = rate;
728 	remainder = do_div(quotient, prate);
729 	*l = quotient;
730 
731 	if (!remainder) {
732 		*a = 0;
733 		return rate;
734 	}
735 
736 	quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
737 	remainder = do_div(quotient, prate);
738 
739 	if (remainder)
740 		quotient++;
741 
742 	/*
743 	 * alpha_val should be in two’s complement number in the range
744 	 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
745 	 * since alpha value will be subtracted in this case.
746 	 */
747 	if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
748 		*l += 1;
749 
750 	*a = quotient;
751 	return alpha_huayra_pll_calc_rate(prate, *l, *a);
752 }
753 
754 static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)755 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
756 {
757 	u64 rate = parent_rate, tmp;
758 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
759 	u32 l, alpha = 0, ctl, alpha_m, alpha_n;
760 
761 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
762 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
763 
764 	if (ctl & PLL_ALPHA_EN) {
765 		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
766 		/*
767 		 * Depending upon alpha_mode, it can be treated as M/N value or
768 		 * as a two’s complement number. When alpha_mode=1,
769 		 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
770 		 *
771 		 *		Fout=FIN*(L+(M/N))
772 		 *
773 		 * M is a signed number (-128 to 127) and N is unsigned
774 		 * (0 to 255). M/N has to be within +/-0.5.
775 		 *
776 		 * When alpha_mode=0, it is a two’s complement number in the
777 		 * range [-0.5, 0.5).
778 		 *
779 		 *		Fout=FIN*(L+(alpha_val)/2^16)
780 		 *
781 		 * where alpha_val is two’s complement number.
782 		 */
783 		if (!(ctl & PLL_ALPHA_MODE))
784 			return alpha_huayra_pll_calc_rate(rate, l, alpha);
785 
786 		alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
787 		alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
788 
789 		rate *= l;
790 		tmp = parent_rate;
791 		if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
792 			alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
793 			tmp *= alpha_m;
794 			do_div(tmp, alpha_n);
795 			rate -= tmp;
796 		} else {
797 			tmp *= alpha_m;
798 			do_div(tmp, alpha_n);
799 			rate += tmp;
800 		}
801 
802 		return rate;
803 	}
804 
805 	return alpha_huayra_pll_calc_rate(rate, l, alpha);
806 }
807 
alpha_pll_huayra_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)808 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
809 				     unsigned long prate)
810 {
811 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
812 	u32 l, a, ctl, cur_alpha = 0;
813 
814 	rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
815 
816 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
817 
818 	if (ctl & PLL_ALPHA_EN)
819 		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
820 
821 	/*
822 	 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
823 	 * without having to go through the power on sequence.
824 	 */
825 	if (clk_alpha_pll_is_enabled(hw)) {
826 		if (cur_alpha != a) {
827 			pr_err("%s: clock needs to be gated\n",
828 			       clk_hw_get_name(hw));
829 			return -EBUSY;
830 		}
831 
832 		regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
833 		/* Ensure that the write above goes to detect L val change. */
834 		mb();
835 		return wait_for_pll_enable_lock(pll);
836 	}
837 
838 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
839 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
840 
841 	if (a == 0)
842 		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
843 				   PLL_ALPHA_EN, 0x0);
844 	else
845 		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
846 				   PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
847 
848 	return 0;
849 }
850 
alpha_pll_huayra_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)851 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
852 					unsigned long *prate)
853 {
854 	u32 l, a;
855 
856 	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
857 }
858 
trion_pll_is_enabled(struct clk_alpha_pll * pll,struct regmap * regmap)859 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
860 				struct regmap *regmap)
861 {
862 	u32 mode_val, opmode_val;
863 	int ret;
864 
865 	ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
866 	ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
867 	if (ret)
868 		return 0;
869 
870 	return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
871 }
872 
clk_trion_pll_is_enabled(struct clk_hw * hw)873 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
874 {
875 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
876 
877 	return trion_pll_is_enabled(pll, pll->clkr.regmap);
878 }
879 
clk_trion_pll_enable(struct clk_hw * hw)880 static int clk_trion_pll_enable(struct clk_hw *hw)
881 {
882 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
883 	struct regmap *regmap = pll->clkr.regmap;
884 	u32 val;
885 	int ret;
886 
887 	ret = regmap_read(regmap, PLL_MODE(pll), &val);
888 	if (ret)
889 		return ret;
890 
891 	/* If in FSM mode, just vote for it */
892 	if (val & PLL_VOTE_FSM_ENA) {
893 		ret = clk_enable_regmap(hw);
894 		if (ret)
895 			return ret;
896 		return wait_for_pll_enable_active(pll);
897 	}
898 
899 	/* Set operation mode to RUN */
900 	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
901 
902 	ret = wait_for_pll_enable_lock(pll);
903 	if (ret)
904 		return ret;
905 
906 	/* Enable the PLL outputs */
907 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
908 				 PLL_OUT_MASK, PLL_OUT_MASK);
909 	if (ret)
910 		return ret;
911 
912 	/* Enable the global PLL outputs */
913 	return regmap_update_bits(regmap, PLL_MODE(pll),
914 				 PLL_OUTCTRL, PLL_OUTCTRL);
915 }
916 
clk_trion_pll_disable(struct clk_hw * hw)917 static void clk_trion_pll_disable(struct clk_hw *hw)
918 {
919 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
920 	struct regmap *regmap = pll->clkr.regmap;
921 	u32 val;
922 	int ret;
923 
924 	ret = regmap_read(regmap, PLL_MODE(pll), &val);
925 	if (ret)
926 		return;
927 
928 	/* If in FSM mode, just unvote it */
929 	if (val & PLL_VOTE_FSM_ENA) {
930 		clk_disable_regmap(hw);
931 		return;
932 	}
933 
934 	/* Disable the global PLL output */
935 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
936 	if (ret)
937 		return;
938 
939 	/* Disable the PLL outputs */
940 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
941 				 PLL_OUT_MASK, 0);
942 	if (ret)
943 		return;
944 
945 	/* Place the PLL mode in STANDBY */
946 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
947 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
948 }
949 
950 static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)951 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
952 {
953 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
954 	u32 l, frac, alpha_width = pll_alpha_width(pll);
955 
956 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
957 	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
958 
959 	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
960 }
961 
962 const struct clk_ops clk_alpha_pll_fixed_ops = {
963 	.enable = clk_alpha_pll_enable,
964 	.disable = clk_alpha_pll_disable,
965 	.is_enabled = clk_alpha_pll_is_enabled,
966 	.recalc_rate = clk_alpha_pll_recalc_rate,
967 };
968 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
969 
970 const struct clk_ops clk_alpha_pll_ops = {
971 	.enable = clk_alpha_pll_enable,
972 	.disable = clk_alpha_pll_disable,
973 	.is_enabled = clk_alpha_pll_is_enabled,
974 	.recalc_rate = clk_alpha_pll_recalc_rate,
975 	.round_rate = clk_alpha_pll_round_rate,
976 	.set_rate = clk_alpha_pll_set_rate,
977 };
978 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
979 
980 const struct clk_ops clk_alpha_pll_huayra_ops = {
981 	.enable = clk_alpha_pll_enable,
982 	.disable = clk_alpha_pll_disable,
983 	.is_enabled = clk_alpha_pll_is_enabled,
984 	.recalc_rate = alpha_pll_huayra_recalc_rate,
985 	.round_rate = alpha_pll_huayra_round_rate,
986 	.set_rate = alpha_pll_huayra_set_rate,
987 };
988 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
989 
990 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
991 	.enable = clk_alpha_pll_hwfsm_enable,
992 	.disable = clk_alpha_pll_hwfsm_disable,
993 	.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
994 	.recalc_rate = clk_alpha_pll_recalc_rate,
995 	.round_rate = clk_alpha_pll_round_rate,
996 	.set_rate = clk_alpha_pll_hwfsm_set_rate,
997 };
998 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
999 
1000 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1001 	.enable = clk_trion_pll_enable,
1002 	.disable = clk_trion_pll_disable,
1003 	.is_enabled = clk_trion_pll_is_enabled,
1004 	.recalc_rate = clk_trion_pll_recalc_rate,
1005 	.round_rate = clk_alpha_pll_round_rate,
1006 };
1007 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1008 
1009 static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1010 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1011 {
1012 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1013 	u32 ctl;
1014 
1015 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1016 
1017 	ctl >>= PLL_POST_DIV_SHIFT;
1018 	ctl &= PLL_POST_DIV_MASK(pll);
1019 
1020 	return parent_rate >> fls(ctl);
1021 }
1022 
1023 static const struct clk_div_table clk_alpha_div_table[] = {
1024 	{ 0x0, 1 },
1025 	{ 0x1, 2 },
1026 	{ 0x3, 4 },
1027 	{ 0x7, 8 },
1028 	{ 0xf, 16 },
1029 	{ }
1030 };
1031 
1032 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1033 	{ 0x0, 1 },
1034 	{ 0x1, 2 },
1035 	{ 0x3, 4 },
1036 	{ }
1037 };
1038 
1039 static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1040 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1041 				 unsigned long *prate)
1042 {
1043 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1044 	const struct clk_div_table *table;
1045 
1046 	if (pll->width == 2)
1047 		table = clk_alpha_2bit_div_table;
1048 	else
1049 		table = clk_alpha_div_table;
1050 
1051 	return divider_round_rate(hw, rate, prate, table,
1052 				  pll->width, CLK_DIVIDER_POWER_OF_TWO);
1053 }
1054 
1055 static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1056 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1057 				    unsigned long *prate)
1058 {
1059 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1060 	u32 ctl, div;
1061 
1062 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1063 
1064 	ctl >>= PLL_POST_DIV_SHIFT;
1065 	ctl &= BIT(pll->width) - 1;
1066 	div = 1 << fls(ctl);
1067 
1068 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1069 		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1070 
1071 	return DIV_ROUND_UP_ULL((u64)*prate, div);
1072 }
1073 
clk_alpha_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1074 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1075 					  unsigned long parent_rate)
1076 {
1077 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1078 	int div;
1079 
1080 	/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1081 	div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1082 
1083 	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1084 				  PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1085 				  div << PLL_POST_DIV_SHIFT);
1086 }
1087 
1088 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1089 	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1090 	.round_rate = clk_alpha_pll_postdiv_round_rate,
1091 	.set_rate = clk_alpha_pll_postdiv_set_rate,
1092 };
1093 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1094 
1095 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1096 	.round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1097 	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1098 };
1099 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1100 
clk_fabia_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1101 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1102 			     const struct alpha_pll_config *config)
1103 {
1104 	u32 val, mask;
1105 
1106 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1107 	clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1108 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1109 						config->config_ctl_val);
1110 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1111 						config->config_ctl_hi_val);
1112 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1113 						config->user_ctl_val);
1114 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1115 						config->user_ctl_hi_val);
1116 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1117 						config->test_ctl_val);
1118 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1119 						config->test_ctl_hi_val);
1120 
1121 	if (config->post_div_mask) {
1122 		mask = config->post_div_mask;
1123 		val = config->post_div_val;
1124 		regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1125 	}
1126 
1127 	if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1128 		regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1129 							PLL_FSM_LEGACY_MODE);
1130 
1131 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1132 							PLL_UPDATE_BYPASS);
1133 
1134 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1135 }
1136 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1137 
alpha_pll_fabia_enable(struct clk_hw * hw)1138 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1139 {
1140 	int ret;
1141 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1142 	u32 val, opmode_val;
1143 	struct regmap *regmap = pll->clkr.regmap;
1144 
1145 	ret = regmap_read(regmap, PLL_MODE(pll), &val);
1146 	if (ret)
1147 		return ret;
1148 
1149 	/* If in FSM mode, just vote for it */
1150 	if (val & PLL_VOTE_FSM_ENA) {
1151 		ret = clk_enable_regmap(hw);
1152 		if (ret)
1153 			return ret;
1154 		return wait_for_pll_enable_active(pll);
1155 	}
1156 
1157 	ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1158 	if (ret)
1159 		return ret;
1160 
1161 	/* Skip If PLL is already running */
1162 	if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1163 		return 0;
1164 
1165 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1166 	if (ret)
1167 		return ret;
1168 
1169 	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1170 	if (ret)
1171 		return ret;
1172 
1173 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1174 				 PLL_RESET_N);
1175 	if (ret)
1176 		return ret;
1177 
1178 	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1179 	if (ret)
1180 		return ret;
1181 
1182 	ret = wait_for_pll_enable_lock(pll);
1183 	if (ret)
1184 		return ret;
1185 
1186 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1187 				 PLL_OUT_MASK, PLL_OUT_MASK);
1188 	if (ret)
1189 		return ret;
1190 
1191 	return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1192 				 PLL_OUTCTRL);
1193 }
1194 
alpha_pll_fabia_disable(struct clk_hw * hw)1195 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1196 {
1197 	int ret;
1198 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1199 	u32 val;
1200 	struct regmap *regmap = pll->clkr.regmap;
1201 
1202 	ret = regmap_read(regmap, PLL_MODE(pll), &val);
1203 	if (ret)
1204 		return;
1205 
1206 	/* If in FSM mode, just unvote it */
1207 	if (val & PLL_FSM_ENA) {
1208 		clk_disable_regmap(hw);
1209 		return;
1210 	}
1211 
1212 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1213 	if (ret)
1214 		return;
1215 
1216 	/* Disable main outputs */
1217 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1218 	if (ret)
1219 		return;
1220 
1221 	/* Place the PLL in STANDBY */
1222 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1223 }
1224 
alpha_pll_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1225 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1226 						unsigned long parent_rate)
1227 {
1228 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1229 	u32 l, frac, alpha_width = pll_alpha_width(pll);
1230 
1231 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1232 	regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1233 
1234 	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1235 }
1236 
1237 /*
1238  * Due to limited number of bits for fractional rate programming, the
1239  * rounded up rate could be marginally higher than the requested rate.
1240  */
alpha_pll_check_rate_margin(struct clk_hw * hw,unsigned long rrate,unsigned long rate)1241 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1242 			unsigned long rrate, unsigned long rate)
1243 {
1244 	unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1245 
1246 	if (rrate > rate_margin || rrate < rate) {
1247 		pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1248 		       clk_hw_get_name(hw), rrate, rate, rate_margin);
1249 		return -EINVAL;
1250 	}
1251 
1252 	return 0;
1253 }
1254 
alpha_pll_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1255 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1256 						unsigned long prate)
1257 {
1258 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1259 	u32 l, alpha_width = pll_alpha_width(pll);
1260 	unsigned long rrate;
1261 	int ret;
1262 	u64 a;
1263 
1264 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1265 
1266 	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1267 	if (ret < 0)
1268 		return ret;
1269 
1270 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1271 	regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1272 
1273 	return __clk_alpha_pll_update_latch(pll);
1274 }
1275 
alpha_pll_fabia_prepare(struct clk_hw * hw)1276 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1277 {
1278 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1279 	const struct pll_vco *vco;
1280 	struct clk_hw *parent_hw;
1281 	unsigned long cal_freq, rrate;
1282 	u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1283 	const char *name = clk_hw_get_name(hw);
1284 	u64 a;
1285 	int ret;
1286 
1287 	/* Check if calibration needs to be done i.e. PLL is in reset */
1288 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1289 	if (ret)
1290 		return ret;
1291 
1292 	/* Return early if calibration is not needed. */
1293 	if (val & PLL_RESET_N)
1294 		return 0;
1295 
1296 	vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1297 	if (!vco) {
1298 		pr_err("%s: alpha pll not in a valid vco range\n", name);
1299 		return -EINVAL;
1300 	}
1301 
1302 	cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1303 				pll->vco_table[0].max_freq) * 54, 100);
1304 
1305 	parent_hw = clk_hw_get_parent(hw);
1306 	if (!parent_hw)
1307 		return -EINVAL;
1308 
1309 	rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1310 					&cal_l, &a, alpha_width);
1311 
1312 	ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1313 	if (ret < 0)
1314 		return ret;
1315 
1316 	/* Setup PLL for calibration frequency */
1317 	regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1318 
1319 	/* Bringup the PLL at calibration frequency */
1320 	ret = clk_alpha_pll_enable(hw);
1321 	if (ret) {
1322 		pr_err("%s: alpha pll calibration failed\n", name);
1323 		return ret;
1324 	}
1325 
1326 	clk_alpha_pll_disable(hw);
1327 
1328 	return 0;
1329 }
1330 
1331 const struct clk_ops clk_alpha_pll_fabia_ops = {
1332 	.prepare = alpha_pll_fabia_prepare,
1333 	.enable = alpha_pll_fabia_enable,
1334 	.disable = alpha_pll_fabia_disable,
1335 	.is_enabled = clk_alpha_pll_is_enabled,
1336 	.set_rate = alpha_pll_fabia_set_rate,
1337 	.recalc_rate = alpha_pll_fabia_recalc_rate,
1338 	.round_rate = clk_alpha_pll_round_rate,
1339 };
1340 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1341 
1342 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1343 	.enable = alpha_pll_fabia_enable,
1344 	.disable = alpha_pll_fabia_disable,
1345 	.is_enabled = clk_alpha_pll_is_enabled,
1346 	.recalc_rate = alpha_pll_fabia_recalc_rate,
1347 	.round_rate = clk_alpha_pll_round_rate,
1348 };
1349 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1350 
clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1351 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1352 					unsigned long parent_rate)
1353 {
1354 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1355 	u32 i, div = 1, val;
1356 	int ret;
1357 
1358 	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1359 	if (ret)
1360 		return ret;
1361 
1362 	val >>= pll->post_div_shift;
1363 	val &= BIT(pll->width) - 1;
1364 
1365 	for (i = 0; i < pll->num_post_div; i++) {
1366 		if (pll->post_div_table[i].val == val) {
1367 			div = pll->post_div_table[i].div;
1368 			break;
1369 		}
1370 	}
1371 
1372 	return (parent_rate / div);
1373 }
1374 
1375 static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1376 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1377 {
1378 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1379 	struct regmap *regmap = pll->clkr.regmap;
1380 	u32 i, div = 1, val;
1381 
1382 	regmap_read(regmap, PLL_USER_CTL(pll), &val);
1383 
1384 	val >>= pll->post_div_shift;
1385 	val &= PLL_POST_DIV_MASK(pll);
1386 
1387 	for (i = 0; i < pll->num_post_div; i++) {
1388 		if (pll->post_div_table[i].val == val) {
1389 			div = pll->post_div_table[i].div;
1390 			break;
1391 		}
1392 	}
1393 
1394 	return (parent_rate / div);
1395 }
1396 
1397 static long
clk_trion_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1398 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1399 				 unsigned long *prate)
1400 {
1401 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1402 
1403 	return divider_round_rate(hw, rate, prate, pll->post_div_table,
1404 				  pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1405 };
1406 
1407 static int
clk_trion_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1408 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1409 			       unsigned long parent_rate)
1410 {
1411 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1412 	struct regmap *regmap = pll->clkr.regmap;
1413 	int i, val = 0, div;
1414 
1415 	div = DIV_ROUND_UP_ULL(parent_rate, rate);
1416 	for (i = 0; i < pll->num_post_div; i++) {
1417 		if (pll->post_div_table[i].div == div) {
1418 			val = pll->post_div_table[i].val;
1419 			break;
1420 		}
1421 	}
1422 
1423 	return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1424 				  PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1425 				  val << PLL_POST_DIV_SHIFT);
1426 }
1427 
1428 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1429 	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1430 	.round_rate = clk_trion_pll_postdiv_round_rate,
1431 	.set_rate = clk_trion_pll_postdiv_set_rate,
1432 };
1433 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1434 
clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1435 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1436 				unsigned long rate, unsigned long *prate)
1437 {
1438 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1439 
1440 	return divider_round_rate(hw, rate, prate, pll->post_div_table,
1441 				pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1442 }
1443 
clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1444 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1445 				unsigned long rate, unsigned long parent_rate)
1446 {
1447 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1448 	int i, val = 0, div, ret;
1449 
1450 	/*
1451 	 * If the PLL is in FSM mode, then treat set_rate callback as a
1452 	 * no-operation.
1453 	 */
1454 	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1455 	if (ret)
1456 		return ret;
1457 
1458 	if (val & PLL_VOTE_FSM_ENA)
1459 		return 0;
1460 
1461 	div = DIV_ROUND_UP_ULL(parent_rate, rate);
1462 	for (i = 0; i < pll->num_post_div; i++) {
1463 		if (pll->post_div_table[i].div == div) {
1464 			val = pll->post_div_table[i].val;
1465 			break;
1466 		}
1467 	}
1468 
1469 	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1470 				(BIT(pll->width) - 1) << pll->post_div_shift,
1471 				val << pll->post_div_shift);
1472 }
1473 
1474 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1475 	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1476 	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1477 	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1478 };
1479 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1480 
1481 /**
1482  * clk_trion_pll_configure - configure the trion pll
1483  *
1484  * @pll: clk alpha pll
1485  * @regmap: register map
1486  * @config: configuration to apply for pll
1487  */
clk_trion_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1488 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1489 			     const struct alpha_pll_config *config)
1490 {
1491 	/*
1492 	 * If the bootloader left the PLL enabled it's likely that there are
1493 	 * RCGs that will lock up if we disable the PLL below.
1494 	 */
1495 	if (trion_pll_is_enabled(pll, regmap)) {
1496 		pr_debug("Trion PLL is already enabled, skipping configuration\n");
1497 		return;
1498 	}
1499 
1500 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1501 	regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1502 	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1503 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1504 				     config->config_ctl_val);
1505 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1506 				     config->config_ctl_hi_val);
1507 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1508 				     config->config_ctl_hi1_val);
1509 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1510 					config->user_ctl_val);
1511 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1512 					config->user_ctl_hi_val);
1513 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1514 					config->user_ctl_hi1_val);
1515 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1516 					config->test_ctl_val);
1517 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1518 					config->test_ctl_hi_val);
1519 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1520 					config->test_ctl_hi1_val);
1521 
1522 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1523 			   PLL_UPDATE_BYPASS);
1524 
1525 	/* Disable PLL output */
1526 	regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1527 
1528 	/* Set operation mode to OFF */
1529 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1530 
1531 	/* Place the PLL in STANDBY mode */
1532 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1533 }
1534 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1535 
1536 /*
1537  * The TRION PLL requires a power-on self-calibration which happens when the
1538  * PLL comes out of reset. Calibrate in case it is not completed.
1539  */
__alpha_pll_trion_prepare(struct clk_hw * hw,u32 pcal_done)1540 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1541 {
1542 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1543 	u32 val;
1544 	int ret;
1545 
1546 	/* Return early if calibration is not needed. */
1547 	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1548 	if (val & pcal_done)
1549 		return 0;
1550 
1551 	/* On/off to calibrate */
1552 	ret = clk_trion_pll_enable(hw);
1553 	if (!ret)
1554 		clk_trion_pll_disable(hw);
1555 
1556 	return ret;
1557 }
1558 
alpha_pll_trion_prepare(struct clk_hw * hw)1559 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1560 {
1561 	return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1562 }
1563 
alpha_pll_lucid_prepare(struct clk_hw * hw)1564 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1565 {
1566 	return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1567 }
1568 
__alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,u32 latch_bit,u32 latch_ack)1569 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1570 				      unsigned long prate, u32 latch_bit, u32 latch_ack)
1571 {
1572 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1573 	unsigned long rrate;
1574 	u32 val, l, alpha_width = pll_alpha_width(pll);
1575 	u64 a;
1576 	int ret;
1577 
1578 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1579 
1580 	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1581 	if (ret < 0)
1582 		return ret;
1583 
1584 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1585 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1586 
1587 	/* Latch the PLL input */
1588 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1589 	if (ret)
1590 		return ret;
1591 
1592 	/* Wait for 2 reference cycles before checking the ACK bit. */
1593 	udelay(1);
1594 	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1595 	if (!(val & latch_ack)) {
1596 		pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1597 		return -EINVAL;
1598 	}
1599 
1600 	/* Return the latch input to 0 */
1601 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1602 	if (ret)
1603 		return ret;
1604 
1605 	if (clk_hw_is_enabled(hw)) {
1606 		ret = wait_for_pll_enable_lock(pll);
1607 		if (ret)
1608 			return ret;
1609 	}
1610 
1611 	/* Wait for PLL output to stabilize */
1612 	udelay(100);
1613 	return 0;
1614 }
1615 
alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1616 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1617 				    unsigned long prate)
1618 {
1619 	return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1620 }
1621 
1622 const struct clk_ops clk_alpha_pll_trion_ops = {
1623 	.prepare = alpha_pll_trion_prepare,
1624 	.enable = clk_trion_pll_enable,
1625 	.disable = clk_trion_pll_disable,
1626 	.is_enabled = clk_trion_pll_is_enabled,
1627 	.recalc_rate = clk_trion_pll_recalc_rate,
1628 	.round_rate = clk_alpha_pll_round_rate,
1629 	.set_rate = alpha_pll_trion_set_rate,
1630 };
1631 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1632 
1633 const struct clk_ops clk_alpha_pll_lucid_ops = {
1634 	.prepare = alpha_pll_lucid_prepare,
1635 	.enable = clk_trion_pll_enable,
1636 	.disable = clk_trion_pll_disable,
1637 	.is_enabled = clk_trion_pll_is_enabled,
1638 	.recalc_rate = clk_trion_pll_recalc_rate,
1639 	.round_rate = clk_alpha_pll_round_rate,
1640 	.set_rate = alpha_pll_trion_set_rate,
1641 };
1642 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1643 
1644 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1645 	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1646 	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1647 	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1648 };
1649 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1650 
clk_agera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1651 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1652 			const struct alpha_pll_config *config)
1653 {
1654 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1655 	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1656 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1657 							config->user_ctl_val);
1658 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1659 						config->config_ctl_val);
1660 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1661 						config->config_ctl_hi_val);
1662 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1663 						config->test_ctl_val);
1664 	clk_alpha_pll_write_config(regmap,  PLL_TEST_CTL_U(pll),
1665 						config->test_ctl_hi_val);
1666 }
1667 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1668 
clk_alpha_pll_agera_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1669 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1670 							unsigned long prate)
1671 {
1672 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1673 	u32 l, alpha_width = pll_alpha_width(pll);
1674 	int ret;
1675 	unsigned long rrate;
1676 	u64 a;
1677 
1678 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1679 	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1680 	if (ret < 0)
1681 		return ret;
1682 
1683 	/* change L_VAL without having to go through the power on sequence */
1684 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1685 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1686 
1687 	if (clk_hw_is_enabled(hw))
1688 		return wait_for_pll_enable_lock(pll);
1689 
1690 	return 0;
1691 }
1692 
1693 const struct clk_ops clk_alpha_pll_agera_ops = {
1694 	.enable = clk_alpha_pll_enable,
1695 	.disable = clk_alpha_pll_disable,
1696 	.is_enabled = clk_alpha_pll_is_enabled,
1697 	.recalc_rate = alpha_pll_fabia_recalc_rate,
1698 	.round_rate = clk_alpha_pll_round_rate,
1699 	.set_rate = clk_alpha_pll_agera_set_rate,
1700 };
1701 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1702 
alpha_pll_lucid_5lpe_enable(struct clk_hw * hw)1703 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1704 {
1705 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1706 	u32 val;
1707 	int ret;
1708 
1709 	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1710 	if (ret)
1711 		return ret;
1712 
1713 	/* If in FSM mode, just vote for it */
1714 	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1715 		ret = clk_enable_regmap(hw);
1716 		if (ret)
1717 			return ret;
1718 		return wait_for_pll_enable_lock(pll);
1719 	}
1720 
1721 	/* Check if PLL is already enabled, return if enabled */
1722 	ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1723 	if (ret < 0)
1724 		return ret;
1725 
1726 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1727 	if (ret)
1728 		return ret;
1729 
1730 	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1731 
1732 	ret = wait_for_pll_enable_lock(pll);
1733 	if (ret)
1734 		return ret;
1735 
1736 	/* Enable the PLL outputs */
1737 	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1738 	if (ret)
1739 		return ret;
1740 
1741 	/* Enable the global PLL outputs */
1742 	return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1743 }
1744 
alpha_pll_lucid_5lpe_disable(struct clk_hw * hw)1745 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1746 {
1747 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1748 	u32 val;
1749 	int ret;
1750 
1751 	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1752 	if (ret)
1753 		return;
1754 
1755 	/* If in FSM mode, just unvote it */
1756 	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1757 		clk_disable_regmap(hw);
1758 		return;
1759 	}
1760 
1761 	/* Disable the global PLL output */
1762 	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1763 	if (ret)
1764 		return;
1765 
1766 	/* Disable the PLL outputs */
1767 	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1768 	if (ret)
1769 		return;
1770 
1771 	/* Place the PLL mode in STANDBY */
1772 	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1773 }
1774 
1775 /*
1776  * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1777  * when the PLL comes out of reset. Calibrate in case it is not completed.
1778  */
alpha_pll_lucid_5lpe_prepare(struct clk_hw * hw)1779 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1780 {
1781 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1782 	struct clk_hw *p;
1783 	u32 val = 0;
1784 	int ret;
1785 
1786 	/* Return early if calibration is not needed. */
1787 	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1788 	if (val & LUCID_5LPE_PCAL_DONE)
1789 		return 0;
1790 
1791 	p = clk_hw_get_parent(hw);
1792 	if (!p)
1793 		return -EINVAL;
1794 
1795 	ret = alpha_pll_lucid_5lpe_enable(hw);
1796 	if (ret)
1797 		return ret;
1798 
1799 	alpha_pll_lucid_5lpe_disable(hw);
1800 
1801 	return 0;
1802 }
1803 
alpha_pll_lucid_5lpe_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1804 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1805 					 unsigned long prate)
1806 {
1807 	return __alpha_pll_trion_set_rate(hw, rate, prate,
1808 					  LUCID_5LPE_PLL_LATCH_INPUT,
1809 					  LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1810 }
1811 
__clk_lucid_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,unsigned long enable_vote_run)1812 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1813 					    unsigned long parent_rate,
1814 					    unsigned long enable_vote_run)
1815 {
1816 	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1817 	struct regmap *regmap = pll->clkr.regmap;
1818 	int i, val, div, ret;
1819 	u32 mask;
1820 
1821 	/*
1822 	 * If the PLL is in FSM mode, then treat set_rate callback as a
1823 	 * no-operation.
1824 	 */
1825 	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1826 	if (ret)
1827 		return ret;
1828 
1829 	if (val & enable_vote_run)
1830 		return 0;
1831 
1832 	if (!pll->post_div_table) {
1833 		pr_err("Missing the post_div_table for the %s PLL\n",
1834 		       clk_hw_get_name(&pll->clkr.hw));
1835 		return -EINVAL;
1836 	}
1837 
1838 	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1839 	for (i = 0; i < pll->num_post_div; i++) {
1840 		if (pll->post_div_table[i].div == div) {
1841 			val = pll->post_div_table[i].val;
1842 			break;
1843 		}
1844 	}
1845 
1846 	mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1847 	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1848 				  mask, val << pll->post_div_shift);
1849 }
1850 
clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1851 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1852 					       unsigned long parent_rate)
1853 {
1854 	return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1855 }
1856 
1857 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1858 	.prepare = alpha_pll_lucid_5lpe_prepare,
1859 	.enable = alpha_pll_lucid_5lpe_enable,
1860 	.disable = alpha_pll_lucid_5lpe_disable,
1861 	.is_enabled = clk_trion_pll_is_enabled,
1862 	.recalc_rate = clk_trion_pll_recalc_rate,
1863 	.round_rate = clk_alpha_pll_round_rate,
1864 	.set_rate = alpha_pll_lucid_5lpe_set_rate,
1865 };
1866 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1867 
1868 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1869 	.enable = alpha_pll_lucid_5lpe_enable,
1870 	.disable = alpha_pll_lucid_5lpe_disable,
1871 	.is_enabled = clk_trion_pll_is_enabled,
1872 	.recalc_rate = clk_trion_pll_recalc_rate,
1873 	.round_rate = clk_alpha_pll_round_rate,
1874 };
1875 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1876 
1877 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1878 	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1879 	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1880 	.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1881 };
1882 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1883 
clk_zonda_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1884 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1885 			     const struct alpha_pll_config *config)
1886 {
1887 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1888 	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1889 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1890 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1891 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1892 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1893 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1894 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1895 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1896 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1897 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1898 
1899 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1900 
1901 	/* Disable PLL output */
1902 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1903 
1904 	/* Set operation mode to OFF */
1905 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1906 
1907 	/* Place the PLL in STANDBY mode */
1908 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1909 }
1910 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1911 
clk_zonda_pll_enable(struct clk_hw * hw)1912 static int clk_zonda_pll_enable(struct clk_hw *hw)
1913 {
1914 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1915 	struct regmap *regmap = pll->clkr.regmap;
1916 	u32 val;
1917 	int ret;
1918 
1919 	regmap_read(regmap, PLL_MODE(pll), &val);
1920 
1921 	/* If in FSM mode, just vote for it */
1922 	if (val & PLL_VOTE_FSM_ENA) {
1923 		ret = clk_enable_regmap(hw);
1924 		if (ret)
1925 			return ret;
1926 		return wait_for_pll_enable_active(pll);
1927 	}
1928 
1929 	/* Get the PLL out of bypass mode */
1930 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1931 
1932 	/*
1933 	 * H/W requires a 1us delay between disabling the bypass and
1934 	 * de-asserting the reset.
1935 	 */
1936 	udelay(1);
1937 
1938 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1939 
1940 	/* Set operation mode to RUN */
1941 	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1942 
1943 	regmap_read(regmap, PLL_TEST_CTL(pll), &val);
1944 
1945 	/* If cfa mode then poll for freq lock */
1946 	if (val & ZONDA_STAY_IN_CFA)
1947 		ret = wait_for_zonda_pll_freq_lock(pll);
1948 	else
1949 		ret = wait_for_pll_enable_lock(pll);
1950 	if (ret)
1951 		return ret;
1952 
1953 	/* Enable the PLL outputs */
1954 	regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
1955 
1956 	/* Enable the global PLL outputs */
1957 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1958 
1959 	return 0;
1960 }
1961 
clk_zonda_pll_disable(struct clk_hw * hw)1962 static void clk_zonda_pll_disable(struct clk_hw *hw)
1963 {
1964 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1965 	struct regmap *regmap = pll->clkr.regmap;
1966 	u32 val;
1967 
1968 	regmap_read(regmap, PLL_MODE(pll), &val);
1969 
1970 	/* If in FSM mode, just unvote it */
1971 	if (val & PLL_VOTE_FSM_ENA) {
1972 		clk_disable_regmap(hw);
1973 		return;
1974 	}
1975 
1976 	/* Disable the global PLL output */
1977 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1978 
1979 	/* Disable the PLL outputs */
1980 	regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
1981 
1982 	/* Put the PLL in bypass and reset */
1983 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
1984 
1985 	/* Place the PLL mode in OFF state */
1986 	regmap_write(regmap, PLL_OPMODE(pll), 0x0);
1987 }
1988 
clk_zonda_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1989 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
1990 				  unsigned long prate)
1991 {
1992 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1993 	unsigned long rrate;
1994 	u32 test_ctl_val;
1995 	u32 l, alpha_width = pll_alpha_width(pll);
1996 	u64 a;
1997 	int ret;
1998 
1999 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2000 
2001 	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2002 	if (ret < 0)
2003 		return ret;
2004 
2005 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2006 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2007 
2008 	/* Wait before polling for the frequency latch */
2009 	udelay(5);
2010 
2011 	/* Read stay in cfa mode */
2012 	regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2013 
2014 	/* If cfa mode then poll for freq lock */
2015 	if (test_ctl_val & ZONDA_STAY_IN_CFA)
2016 		ret = wait_for_zonda_pll_freq_lock(pll);
2017 	else
2018 		ret = wait_for_pll_enable_lock(pll);
2019 	if (ret)
2020 		return ret;
2021 
2022 	/* Wait for PLL output to stabilize */
2023 	udelay(100);
2024 	return 0;
2025 }
2026 
2027 const struct clk_ops clk_alpha_pll_zonda_ops = {
2028 	.enable = clk_zonda_pll_enable,
2029 	.disable = clk_zonda_pll_disable,
2030 	.is_enabled = clk_trion_pll_is_enabled,
2031 	.recalc_rate = clk_trion_pll_recalc_rate,
2032 	.round_rate = clk_alpha_pll_round_rate,
2033 	.set_rate = clk_zonda_pll_set_rate,
2034 };
2035 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2036 
clk_lucid_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2037 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2038 				 const struct alpha_pll_config *config)
2039 {
2040 	u32 lval = config->l;
2041 
2042 	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2043 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2044 	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2045 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2046 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2047 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2048 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2049 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2050 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2051 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2052 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2053 
2054 	/* Disable PLL output */
2055 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2056 
2057 	/* Set operation mode to STANDBY and de-assert the reset */
2058 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2059 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2060 }
2061 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2062 
alpha_pll_lucid_evo_enable(struct clk_hw * hw)2063 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2064 {
2065 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2066 	struct regmap *regmap = pll->clkr.regmap;
2067 	u32 val;
2068 	int ret;
2069 
2070 	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2071 	if (ret)
2072 		return ret;
2073 
2074 	/* If in FSM mode, just vote for it */
2075 	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2076 		ret = clk_enable_regmap(hw);
2077 		if (ret)
2078 			return ret;
2079 		return wait_for_pll_enable_lock(pll);
2080 	}
2081 
2082 	/* Check if PLL is already enabled */
2083 	ret = trion_pll_is_enabled(pll, regmap);
2084 	if (ret < 0) {
2085 		return ret;
2086 	} else if (ret) {
2087 		pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2088 		return 0;
2089 	}
2090 
2091 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2092 	if (ret)
2093 		return ret;
2094 
2095 	/* Set operation mode to RUN */
2096 	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2097 
2098 	ret = wait_for_pll_enable_lock(pll);
2099 	if (ret)
2100 		return ret;
2101 
2102 	/* Enable the PLL outputs */
2103 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2104 	if (ret)
2105 		return ret;
2106 
2107 	/* Enable the global PLL outputs */
2108 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2109 	if (ret)
2110 		return ret;
2111 
2112 	/* Ensure that the write above goes through before returning. */
2113 	mb();
2114 	return ret;
2115 }
2116 
_alpha_pll_lucid_evo_disable(struct clk_hw * hw,bool reset)2117 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2118 {
2119 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2120 	struct regmap *regmap = pll->clkr.regmap;
2121 	u32 val;
2122 	int ret;
2123 
2124 	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2125 	if (ret)
2126 		return;
2127 
2128 	/* If in FSM mode, just unvote it */
2129 	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2130 		clk_disable_regmap(hw);
2131 		return;
2132 	}
2133 
2134 	/* Disable the global PLL output */
2135 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2136 	if (ret)
2137 		return;
2138 
2139 	/* Disable the PLL outputs */
2140 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2141 	if (ret)
2142 		return;
2143 
2144 	/* Place the PLL mode in STANDBY */
2145 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2146 
2147 	if (reset)
2148 		regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2149 }
2150 
_alpha_pll_lucid_evo_prepare(struct clk_hw * hw,bool reset)2151 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2152 {
2153 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2154 	struct clk_hw *p;
2155 	u32 val = 0;
2156 	int ret;
2157 
2158 	/* Return early if calibration is not needed. */
2159 	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2160 	if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2161 		return 0;
2162 
2163 	p = clk_hw_get_parent(hw);
2164 	if (!p)
2165 		return -EINVAL;
2166 
2167 	ret = alpha_pll_lucid_evo_enable(hw);
2168 	if (ret)
2169 		return ret;
2170 
2171 	_alpha_pll_lucid_evo_disable(hw, reset);
2172 
2173 	return 0;
2174 }
2175 
alpha_pll_lucid_evo_disable(struct clk_hw * hw)2176 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2177 {
2178 	_alpha_pll_lucid_evo_disable(hw, false);
2179 }
2180 
alpha_pll_lucid_evo_prepare(struct clk_hw * hw)2181 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2182 {
2183 	return _alpha_pll_lucid_evo_prepare(hw, false);
2184 }
2185 
alpha_pll_reset_lucid_evo_disable(struct clk_hw * hw)2186 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2187 {
2188 	_alpha_pll_lucid_evo_disable(hw, true);
2189 }
2190 
alpha_pll_reset_lucid_evo_prepare(struct clk_hw * hw)2191 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2192 {
2193 	return _alpha_pll_lucid_evo_prepare(hw, true);
2194 }
2195 
alpha_pll_lucid_evo_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2196 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2197 						     unsigned long parent_rate)
2198 {
2199 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2200 	struct regmap *regmap = pll->clkr.regmap;
2201 	u32 l, frac;
2202 
2203 	regmap_read(regmap, PLL_L_VAL(pll), &l);
2204 	l &= LUCID_EVO_PLL_L_VAL_MASK;
2205 	regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2206 
2207 	return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2208 }
2209 
clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2210 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2211 					      unsigned long parent_rate)
2212 {
2213 	return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2214 }
2215 
2216 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2217 	.enable = alpha_pll_lucid_evo_enable,
2218 	.disable = alpha_pll_lucid_evo_disable,
2219 	.is_enabled = clk_trion_pll_is_enabled,
2220 	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2221 	.round_rate = clk_alpha_pll_round_rate,
2222 };
2223 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2224 
2225 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2226 	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2227 	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2228 	.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2229 };
2230 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2231 
2232 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2233 	.prepare = alpha_pll_lucid_evo_prepare,
2234 	.enable = alpha_pll_lucid_evo_enable,
2235 	.disable = alpha_pll_lucid_evo_disable,
2236 	.is_enabled = clk_trion_pll_is_enabled,
2237 	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2238 	.round_rate = clk_alpha_pll_round_rate,
2239 	.set_rate = alpha_pll_lucid_5lpe_set_rate,
2240 };
2241 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2242 
2243 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2244 	.prepare = alpha_pll_reset_lucid_evo_prepare,
2245 	.enable = alpha_pll_lucid_evo_enable,
2246 	.disable = alpha_pll_reset_lucid_evo_disable,
2247 	.is_enabled = clk_trion_pll_is_enabled,
2248 	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2249 	.round_rate = clk_alpha_pll_round_rate,
2250 	.set_rate = alpha_pll_lucid_5lpe_set_rate,
2251 };
2252 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2253 
clk_rivian_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2254 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2255 				  const struct alpha_pll_config *config)
2256 {
2257 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2258 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2259 	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2260 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2261 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2262 	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2263 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2264 	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2265 
2266 	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2267 
2268 	regmap_update_bits(regmap, PLL_MODE(pll),
2269 			   PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2270 			   PLL_RESET_N | PLL_BYPASSNL);
2271 }
2272 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2273 
clk_rivian_evo_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2274 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2275 						    unsigned long parent_rate)
2276 {
2277 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2278 	u32 l;
2279 
2280 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2281 
2282 	return parent_rate * l;
2283 }
2284 
clk_rivian_evo_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)2285 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2286 					  unsigned long *prate)
2287 {
2288 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2289 	unsigned long min_freq, max_freq;
2290 	u32 l;
2291 	u64 a;
2292 
2293 	rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2294 	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2295 		return rate;
2296 
2297 	min_freq = pll->vco_table[0].min_freq;
2298 	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2299 
2300 	return clamp(rate, min_freq, max_freq);
2301 }
2302 
2303 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2304 	.enable = alpha_pll_lucid_5lpe_enable,
2305 	.disable = alpha_pll_lucid_5lpe_disable,
2306 	.is_enabled = clk_trion_pll_is_enabled,
2307 	.recalc_rate = clk_rivian_evo_pll_recalc_rate,
2308 	.round_rate = clk_rivian_evo_pll_round_rate,
2309 };
2310 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2311