1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn314_resource.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "irq/dcn314/irq_service_dcn314.h"
49 #include "dcn30/dcn30_dpp.h"
50 #include "dcn314/dcn314_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hw_sequencer.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn31/dcn31_dio_link_encoder.h"
59 #include "dcn314/dcn314_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "virtual/virtual_stream_encoder.h"
70 #include "dce110/dce110_resource.h"
71 #include "dml/display_mode_vba.h"
72 #include "dml/dcn31/dcn31_fpu.h"
73 #include "dml/dcn314/dcn314_fpu.h"
74 #include "dcn314/dcn314_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77 #include "dcn314/dcn314_hwseq.h"
78
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn30/dcn30_mmhubbub.h"
81
82 #include "dcn/dcn_3_1_4_offset.h"
83 #include "dcn/dcn_3_1_4_sh_mask.h"
84 #include "dpcs/dpcs_3_1_4_offset.h"
85 #include "dpcs/dpcs_3_1_4_sh_mask.h"
86
87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
89
90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
92
93 #include "reg_helper.h"
94 #include "dce/dmub_abm.h"
95 #include "dce/dmub_psr.h"
96 #include "dce/dce_aux.h"
97 #include "dce/dce_i2c.h"
98 #include "dml/dcn314/display_mode_vba_314.h"
99 #include "vm_helper.h"
100 #include "dcn20/dcn20_vmid.h"
101
102 #include "link_enc_cfg.h"
103
104 #define DCN_BASE__INST0_SEG1 0x000000C0
105 #define DCN_BASE__INST0_SEG2 0x000034C0
106 #define DCN_BASE__INST0_SEG3 0x00009000
107
108 #define NBIO_BASE__INST0_SEG1 0x00000014
109
110 #define MAX_INSTANCE 7
111 #define MAX_SEGMENT 8
112
113 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
117 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
119
120 struct IP_BASE_INSTANCE {
121 unsigned int segment[MAX_SEGMENT];
122 };
123
124 struct IP_BASE {
125 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
126 };
127
128 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
135
136
137 #define DC_LOGGER_INIT(logger)
138
139 enum dcn31_clk_src_array_id {
140 DCN31_CLK_SRC_PLL0,
141 DCN31_CLK_SRC_PLL1,
142 DCN31_CLK_SRC_PLL2,
143 DCN31_CLK_SRC_PLL3,
144 DCN31_CLK_SRC_PLL4,
145 DCN30_CLK_SRC_TOTAL
146 };
147
148 /* begin *********************
149 * macros to expend register list macro defined in HW object header file
150 */
151
152 /* DCN */
153 /* TODO awful hack. fixup dcn20_dwb.h */
154 #undef BASE_INNER
155 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
156
157 #define BASE(seg) BASE_INNER(seg)
158
159 #define SR(reg_name)\
160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
161 reg ## reg_name
162
163 #define SRI(reg_name, block, id)\
164 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SRI2(reg_name, block, id)\
168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
169 reg ## reg_name
170
171 #define SRIR(var_name, reg_name, block, id)\
172 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
174
175 #define SRII(reg_name, block, id)\
176 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177 reg ## block ## id ## _ ## reg_name
178
179 #define SRII_MPC_RMU(reg_name, block, id)\
180 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
182
183 #define SRII_DWB(reg_name, temp_name, block, id)\
184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
185 reg ## block ## id ## _ ## temp_name
186
187 #define DCCG_SRII(reg_name, block, id)\
188 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 reg ## block ## id ## _ ## reg_name
190
191 #define VUPDATE_SRII(reg_name, block, id)\
192 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
193 reg ## reg_name ## _ ## block ## id
194
195 /* NBIO */
196 #define NBIO_BASE_INNER(seg) \
197 NBIO_BASE__INST0_SEG ## seg
198
199 #define NBIO_BASE(seg) \
200 NBIO_BASE_INNER(seg)
201
202 #define NBIO_SR(reg_name)\
203 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
204 regBIF_BX2_ ## reg_name
205
206 /* MMHUB */
207 #define MMHUB_BASE_INNER(seg) \
208 MMHUB_BASE__INST0_SEG ## seg
209
210 #define MMHUB_BASE(seg) \
211 MMHUB_BASE_INNER(seg)
212
213 #define MMHUB_SR(reg_name)\
214 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
215 reg ## reg_name
216
217 /* CLOCK */
218 #define CLK_BASE_INNER(seg) \
219 CLK_BASE__INST0_SEG ## seg
220
221 #define CLK_BASE(seg) \
222 CLK_BASE_INNER(seg)
223
224 #define CLK_SRI(reg_name, block, inst)\
225 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
226 reg ## block ## _ ## inst ## _ ## reg_name
227
228
229 static const struct bios_registers bios_regs = {
230 NBIO_SR(BIOS_SCRATCH_3),
231 NBIO_SR(BIOS_SCRATCH_6)
232 };
233
234 #define clk_src_regs(index, pllid)\
235 [index] = {\
236 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
237 }
238
239 static const struct dce110_clk_src_regs clk_src_regs[] = {
240 clk_src_regs(0, A),
241 clk_src_regs(1, B),
242 clk_src_regs(2, C),
243 clk_src_regs(3, D),
244 clk_src_regs(4, E)
245 };
246
247 static const struct dce110_clk_src_shift cs_shift = {
248 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
249 };
250
251 static const struct dce110_clk_src_mask cs_mask = {
252 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
253 };
254
255 #define abm_regs(id)\
256 [id] = {\
257 ABM_DCN302_REG_LIST(id)\
258 }
259
260 static const struct dce_abm_registers abm_regs[] = {
261 abm_regs(0),
262 abm_regs(1),
263 abm_regs(2),
264 abm_regs(3),
265 };
266
267 static const struct dce_abm_shift abm_shift = {
268 ABM_MASK_SH_LIST_DCN30(__SHIFT)
269 };
270
271 static const struct dce_abm_mask abm_mask = {
272 ABM_MASK_SH_LIST_DCN30(_MASK)
273 };
274
275 #define audio_regs(id)\
276 [id] = {\
277 AUD_COMMON_REG_LIST(id)\
278 }
279
280 static const struct dce_audio_registers audio_regs[] = {
281 audio_regs(0),
282 audio_regs(1),
283 audio_regs(2),
284 audio_regs(3),
285 audio_regs(4),
286 audio_regs(5),
287 audio_regs(6)
288 };
289
290 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
291 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
292 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
293 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
294
295 static const struct dce_audio_shift audio_shift = {
296 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
297 };
298
299 static const struct dce_audio_mask audio_mask = {
300 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
301 };
302
303 #define vpg_regs(id)\
304 [id] = {\
305 VPG_DCN31_REG_LIST(id)\
306 }
307
308 static const struct dcn31_vpg_registers vpg_regs[] = {
309 vpg_regs(0),
310 vpg_regs(1),
311 vpg_regs(2),
312 vpg_regs(3),
313 vpg_regs(4),
314 vpg_regs(5),
315 vpg_regs(6),
316 vpg_regs(7),
317 vpg_regs(8),
318 vpg_regs(9),
319 };
320
321 static const struct dcn31_vpg_shift vpg_shift = {
322 DCN31_VPG_MASK_SH_LIST(__SHIFT)
323 };
324
325 static const struct dcn31_vpg_mask vpg_mask = {
326 DCN31_VPG_MASK_SH_LIST(_MASK)
327 };
328
329 #define afmt_regs(id)\
330 [id] = {\
331 AFMT_DCN31_REG_LIST(id)\
332 }
333
334 static const struct dcn31_afmt_registers afmt_regs[] = {
335 afmt_regs(0),
336 afmt_regs(1),
337 afmt_regs(2),
338 afmt_regs(3),
339 afmt_regs(4),
340 afmt_regs(5)
341 };
342
343 static const struct dcn31_afmt_shift afmt_shift = {
344 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
345 };
346
347 static const struct dcn31_afmt_mask afmt_mask = {
348 DCN31_AFMT_MASK_SH_LIST(_MASK)
349 };
350
351 #define apg_regs(id)\
352 [id] = {\
353 APG_DCN31_REG_LIST(id)\
354 }
355
356 static const struct dcn31_apg_registers apg_regs[] = {
357 apg_regs(0),
358 apg_regs(1),
359 apg_regs(2),
360 apg_regs(3)
361 };
362
363 static const struct dcn31_apg_shift apg_shift = {
364 DCN31_APG_MASK_SH_LIST(__SHIFT)
365 };
366
367 static const struct dcn31_apg_mask apg_mask = {
368 DCN31_APG_MASK_SH_LIST(_MASK)
369 };
370
371 #define stream_enc_regs(id)\
372 [id] = {\
373 SE_DCN314_REG_LIST(id)\
374 }
375
376 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
377 stream_enc_regs(0),
378 stream_enc_regs(1),
379 stream_enc_regs(2),
380 stream_enc_regs(3),
381 stream_enc_regs(4)
382 };
383
384 static const struct dcn10_stream_encoder_shift se_shift = {
385 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
386 };
387
388 static const struct dcn10_stream_encoder_mask se_mask = {
389 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
390 };
391
392
393 #define aux_regs(id)\
394 [id] = {\
395 DCN2_AUX_REG_LIST(id)\
396 }
397
398 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
399 aux_regs(0),
400 aux_regs(1),
401 aux_regs(2),
402 aux_regs(3),
403 aux_regs(4)
404 };
405
406 #define hpd_regs(id)\
407 [id] = {\
408 HPD_REG_LIST(id)\
409 }
410
411 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
412 hpd_regs(0),
413 hpd_regs(1),
414 hpd_regs(2),
415 hpd_regs(3),
416 hpd_regs(4)
417 };
418
419 #define link_regs(id, phyid)\
420 [id] = {\
421 LE_DCN31_REG_LIST(id), \
422 UNIPHY_DCN2_REG_LIST(phyid), \
423 }
424
425 static const struct dce110_aux_registers_shift aux_shift = {
426 DCN_AUX_MASK_SH_LIST(__SHIFT)
427 };
428
429 static const struct dce110_aux_registers_mask aux_mask = {
430 DCN_AUX_MASK_SH_LIST(_MASK)
431 };
432
433 static const struct dcn10_link_enc_registers link_enc_regs[] = {
434 link_regs(0, A),
435 link_regs(1, B),
436 link_regs(2, C),
437 link_regs(3, D),
438 link_regs(4, E)
439 };
440
441 static const struct dcn10_link_enc_shift le_shift = {
442 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
443 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
444 };
445
446 static const struct dcn10_link_enc_mask le_mask = {
447 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
448 DPCS_DCN31_MASK_SH_LIST(_MASK)
449 };
450
451 #define hpo_dp_stream_encoder_reg_list(id)\
452 [id] = {\
453 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
454 }
455
456 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
457 hpo_dp_stream_encoder_reg_list(0),
458 hpo_dp_stream_encoder_reg_list(1),
459 hpo_dp_stream_encoder_reg_list(2),
460 hpo_dp_stream_encoder_reg_list(3)
461 };
462
463 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
464 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
465 };
466
467 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
468 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
469 };
470
471
472 #define hpo_dp_link_encoder_reg_list(id)\
473 [id] = {\
474 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
475 DCN3_1_RDPCSTX_REG_LIST(0),\
476 DCN3_1_RDPCSTX_REG_LIST(1),\
477 DCN3_1_RDPCSTX_REG_LIST(2),\
478 }
479
480 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
481 hpo_dp_link_encoder_reg_list(0),
482 hpo_dp_link_encoder_reg_list(1),
483 };
484
485 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
486 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
487 };
488
489 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
490 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
491 };
492
493 #define dpp_regs(id)\
494 [id] = {\
495 DPP_REG_LIST_DCN30(id),\
496 }
497
498 static const struct dcn3_dpp_registers dpp_regs[] = {
499 dpp_regs(0),
500 dpp_regs(1),
501 dpp_regs(2),
502 dpp_regs(3)
503 };
504
505 static const struct dcn3_dpp_shift tf_shift = {
506 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
507 };
508
509 static const struct dcn3_dpp_mask tf_mask = {
510 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
511 };
512
513 #define opp_regs(id)\
514 [id] = {\
515 OPP_REG_LIST_DCN30(id),\
516 }
517
518 static const struct dcn20_opp_registers opp_regs[] = {
519 opp_regs(0),
520 opp_regs(1),
521 opp_regs(2),
522 opp_regs(3)
523 };
524
525 static const struct dcn20_opp_shift opp_shift = {
526 OPP_MASK_SH_LIST_DCN20(__SHIFT)
527 };
528
529 static const struct dcn20_opp_mask opp_mask = {
530 OPP_MASK_SH_LIST_DCN20(_MASK)
531 };
532
533 #define aux_engine_regs(id)\
534 [id] = {\
535 AUX_COMMON_REG_LIST0(id), \
536 .AUXN_IMPCAL = 0, \
537 .AUXP_IMPCAL = 0, \
538 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
539 }
540
541 static const struct dce110_aux_registers aux_engine_regs[] = {
542 aux_engine_regs(0),
543 aux_engine_regs(1),
544 aux_engine_regs(2),
545 aux_engine_regs(3),
546 aux_engine_regs(4)
547 };
548
549 #define dwbc_regs_dcn3(id)\
550 [id] = {\
551 DWBC_COMMON_REG_LIST_DCN30(id),\
552 }
553
554 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
555 dwbc_regs_dcn3(0),
556 };
557
558 static const struct dcn30_dwbc_shift dwbc30_shift = {
559 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
560 };
561
562 static const struct dcn30_dwbc_mask dwbc30_mask = {
563 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
564 };
565
566 #define mcif_wb_regs_dcn3(id)\
567 [id] = {\
568 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
569 }
570
571 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
572 mcif_wb_regs_dcn3(0)
573 };
574
575 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
576 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
577 };
578
579 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
580 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
581 };
582
583 #define dsc_regsDCN314(id)\
584 [id] = {\
585 DSC_REG_LIST_DCN20(id)\
586 }
587
588 static const struct dcn20_dsc_registers dsc_regs[] = {
589 dsc_regsDCN314(0),
590 dsc_regsDCN314(1),
591 dsc_regsDCN314(2),
592 dsc_regsDCN314(3)
593 };
594
595 static const struct dcn20_dsc_shift dsc_shift = {
596 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
597 };
598
599 static const struct dcn20_dsc_mask dsc_mask = {
600 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
601 };
602
603 static const struct dcn30_mpc_registers mpc_regs = {
604 MPC_REG_LIST_DCN3_0(0),
605 MPC_REG_LIST_DCN3_0(1),
606 MPC_REG_LIST_DCN3_0(2),
607 MPC_REG_LIST_DCN3_0(3),
608 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
609 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
610 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
611 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
612 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
613 MPC_RMU_REG_LIST_DCN3AG(0),
614 MPC_RMU_REG_LIST_DCN3AG(1),
615 //MPC_RMU_REG_LIST_DCN3AG(2),
616 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
617 };
618
619 static const struct dcn30_mpc_shift mpc_shift = {
620 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
621 };
622
623 static const struct dcn30_mpc_mask mpc_mask = {
624 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
625 };
626
627 #define optc_regs(id)\
628 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
629
630 static const struct dcn_optc_registers optc_regs[] = {
631 optc_regs(0),
632 optc_regs(1),
633 optc_regs(2),
634 optc_regs(3)
635 };
636
637 static const struct dcn_optc_shift optc_shift = {
638 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
639 };
640
641 static const struct dcn_optc_mask optc_mask = {
642 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
643 };
644
645 #define hubp_regs(id)\
646 [id] = {\
647 HUBP_REG_LIST_DCN30(id)\
648 }
649
650 static const struct dcn_hubp2_registers hubp_regs[] = {
651 hubp_regs(0),
652 hubp_regs(1),
653 hubp_regs(2),
654 hubp_regs(3)
655 };
656
657
658 static const struct dcn_hubp2_shift hubp_shift = {
659 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
660 };
661
662 static const struct dcn_hubp2_mask hubp_mask = {
663 HUBP_MASK_SH_LIST_DCN31(_MASK)
664 };
665 static const struct dcn_hubbub_registers hubbub_reg = {
666 HUBBUB_REG_LIST_DCN31(0)
667 };
668
669 static const struct dcn_hubbub_shift hubbub_shift = {
670 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
671 };
672
673 static const struct dcn_hubbub_mask hubbub_mask = {
674 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
675 };
676
677 static const struct dccg_registers dccg_regs = {
678 DCCG_REG_LIST_DCN314()
679 };
680
681 static const struct dccg_shift dccg_shift = {
682 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
683 };
684
685 static const struct dccg_mask dccg_mask = {
686 DCCG_MASK_SH_LIST_DCN314(_MASK)
687 };
688
689
690 #define SRII2(reg_name_pre, reg_name_post, id)\
691 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
692 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
693 reg ## reg_name_pre ## id ## _ ## reg_name_post
694
695
696 #define HWSEQ_DCN31_REG_LIST()\
697 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
698 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
699 SR(DIO_MEM_PWR_CTRL), \
700 SR(ODM_MEM_PWR_CTRL3), \
701 SR(DMU_MEM_PWR_CNTL), \
702 SR(MMHUBBUB_MEM_PWR_CNTL), \
703 SR(DCCG_GATE_DISABLE_CNTL), \
704 SR(DCCG_GATE_DISABLE_CNTL2), \
705 SR(DCFCLK_CNTL),\
706 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
707 SRII(PIXEL_RATE_CNTL, OTG, 0), \
708 SRII(PIXEL_RATE_CNTL, OTG, 1),\
709 SRII(PIXEL_RATE_CNTL, OTG, 2),\
710 SRII(PIXEL_RATE_CNTL, OTG, 3),\
711 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
712 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
713 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
715 SR(MICROSECOND_TIME_BASE_DIV), \
716 SR(MILLISECOND_TIME_BASE_DIV), \
717 SR(DISPCLK_FREQ_CHANGE_CNTL), \
718 SR(RBBMIF_TIMEOUT_DIS), \
719 SR(RBBMIF_TIMEOUT_DIS_2), \
720 SR(DCHUBBUB_CRC_CTRL), \
721 SR(DPP_TOP0_DPP_CRC_CTRL), \
722 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
723 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
724 SR(MPC_CRC_CTRL), \
725 SR(MPC_CRC_RESULT_GB), \
726 SR(MPC_CRC_RESULT_C), \
727 SR(MPC_CRC_RESULT_AR), \
728 SR(DOMAIN0_PG_CONFIG), \
729 SR(DOMAIN1_PG_CONFIG), \
730 SR(DOMAIN2_PG_CONFIG), \
731 SR(DOMAIN3_PG_CONFIG), \
732 SR(DOMAIN16_PG_CONFIG), \
733 SR(DOMAIN17_PG_CONFIG), \
734 SR(DOMAIN18_PG_CONFIG), \
735 SR(DOMAIN19_PG_CONFIG), \
736 SR(DOMAIN0_PG_STATUS), \
737 SR(DOMAIN1_PG_STATUS), \
738 SR(DOMAIN2_PG_STATUS), \
739 SR(DOMAIN3_PG_STATUS), \
740 SR(DOMAIN16_PG_STATUS), \
741 SR(DOMAIN17_PG_STATUS), \
742 SR(DOMAIN18_PG_STATUS), \
743 SR(DOMAIN19_PG_STATUS), \
744 SR(D1VGA_CONTROL), \
745 SR(D2VGA_CONTROL), \
746 SR(D3VGA_CONTROL), \
747 SR(D4VGA_CONTROL), \
748 SR(D5VGA_CONTROL), \
749 SR(D6VGA_CONTROL), \
750 SR(DC_IP_REQUEST_CNTL), \
751 SR(AZALIA_AUDIO_DTO), \
752 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
753 SR(HPO_TOP_HW_CONTROL)
754
755 static const struct dce_hwseq_registers hwseq_reg = {
756 HWSEQ_DCN31_REG_LIST()
757 };
758
759 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
760 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
761 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
762 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
763 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
764 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
765 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
766 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
767 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
768 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
769 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
770 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
771 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
772 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
773 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
774 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
775 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
776 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
777 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
778 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
779 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
780 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
781 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
782 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
783 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
784 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
785 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
786 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
787 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
788 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
789 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
790 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
791 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
792 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
793 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
794 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
795 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
796
797 static const struct dce_hwseq_shift hwseq_shift = {
798 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
799 };
800
801 static const struct dce_hwseq_mask hwseq_mask = {
802 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
803 };
804 #define vmid_regs(id)\
805 [id] = {\
806 DCN20_VMID_REG_LIST(id)\
807 }
808
809 static const struct dcn_vmid_registers vmid_regs[] = {
810 vmid_regs(0),
811 vmid_regs(1),
812 vmid_regs(2),
813 vmid_regs(3),
814 vmid_regs(4),
815 vmid_regs(5),
816 vmid_regs(6),
817 vmid_regs(7),
818 vmid_regs(8),
819 vmid_regs(9),
820 vmid_regs(10),
821 vmid_regs(11),
822 vmid_regs(12),
823 vmid_regs(13),
824 vmid_regs(14),
825 vmid_regs(15)
826 };
827
828 static const struct dcn20_vmid_shift vmid_shifts = {
829 DCN20_VMID_MASK_SH_LIST(__SHIFT)
830 };
831
832 static const struct dcn20_vmid_mask vmid_masks = {
833 DCN20_VMID_MASK_SH_LIST(_MASK)
834 };
835
836 static const struct resource_caps res_cap_dcn314 = {
837 .num_timing_generator = 4,
838 .num_opp = 4,
839 .num_video_plane = 4,
840 .num_audio = 5,
841 .num_stream_encoder = 5,
842 .num_dig_link_enc = 5,
843 .num_hpo_dp_stream_encoder = 4,
844 .num_hpo_dp_link_encoder = 2,
845 .num_pll = 5,
846 .num_dwb = 1,
847 .num_ddc = 5,
848 .num_vmid = 16,
849 .num_mpc_3dlut = 2,
850 .num_dsc = 4,
851 };
852
853 static const struct dc_plane_cap plane_cap = {
854 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
855 .blends_with_above = true,
856 .blends_with_below = true,
857 .per_pixel_alpha = true,
858
859 .pixel_format_support = {
860 .argb8888 = true,
861 .nv12 = true,
862 .fp16 = true,
863 .p010 = true,
864 .ayuv = false,
865 },
866
867 .max_upscale_factor = {
868 .argb8888 = 16000,
869 .nv12 = 16000,
870 .fp16 = 16000
871 },
872
873 // 6:1 downscaling ratio: 1000/6 = 166.666
874 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
875 .max_downscale_factor = {
876 .argb8888 = 250,
877 .nv12 = 167,
878 .fp16 = 167
879 },
880 64,
881 64
882 };
883
884 static const struct dc_debug_options debug_defaults_drv = {
885 .disable_z10 = false,
886 .enable_z9_disable_interface = true,
887 .minimum_z8_residency_time = 2100,
888 .psr_skip_crtc_disable = true,
889 .disable_dmcu = true,
890 .force_abm_enable = false,
891 .timing_trace = false,
892 .clock_trace = true,
893 .disable_dpp_power_gate = true,
894 .disable_hubp_power_gate = true,
895 .disable_pplib_clock_request = false,
896 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
897 .force_single_disp_pipe_split = false,
898 .disable_dcc = DCC_ENABLE,
899 .vsr_support = true,
900 .performance_trace = false,
901 .max_downscale_src_width = 4096,/*upto true 4k*/
902 .disable_pplib_wm_range = false,
903 .scl_reset_length10 = true,
904 .sanity_checks = true,
905 .underflow_assert_delay_us = 0xFFFFFFFF,
906 .dwb_fi_phase = -1, // -1 = disable,
907 .dmub_command_table = true,
908 .pstate_enabled = true,
909 .use_max_lb = true,
910 .enable_mem_low_power = {
911 .bits = {
912 .vga = true,
913 .i2c = true,
914 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
915 .dscl = true,
916 .cm = true,
917 .mpc = true,
918 .optc = true,
919 .vpg = true,
920 .afmt = true,
921 }
922 },
923
924 .root_clock_optimization = {
925 .bits = {
926 .dpp = true,
927 .dsc = false,
928 .hdmistream = false,
929 .hdmichar = false,
930 .dpstream = false,
931 .symclk32_se = false,
932 .symclk32_le = false,
933 .symclk_fe = false,
934 .physymclk = false,
935 .dpiasymclk = false,
936 }
937 },
938
939 .seamless_boot_odm_combine = true
940 };
941
942 static const struct dc_debug_options debug_defaults_diags = {
943 .disable_dmcu = true,
944 .force_abm_enable = false,
945 .timing_trace = true,
946 .clock_trace = true,
947 .disable_dpp_power_gate = true,
948 .disable_hubp_power_gate = true,
949 .disable_clock_gate = true,
950 .disable_pplib_clock_request = true,
951 .disable_pplib_wm_range = true,
952 .disable_stutter = false,
953 .scl_reset_length10 = true,
954 .dwb_fi_phase = -1, // -1 = disable
955 .dmub_command_table = true,
956 .enable_tri_buf = true,
957 .use_max_lb = true
958 };
959
960 static const struct dc_panel_config panel_config_defaults = {
961 .psr = {
962 .disable_psr = false,
963 .disallow_psrsu = false,
964 },
965 .ilr = {
966 .optimize_edp_link_rate = true,
967 },
968 };
969
dcn31_dpp_destroy(struct dpp ** dpp)970 static void dcn31_dpp_destroy(struct dpp **dpp)
971 {
972 kfree(TO_DCN20_DPP(*dpp));
973 *dpp = NULL;
974 }
975
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)976 static struct dpp *dcn31_dpp_create(
977 struct dc_context *ctx,
978 uint32_t inst)
979 {
980 struct dcn3_dpp *dpp =
981 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
982
983 if (!dpp)
984 return NULL;
985
986 if (dpp3_construct(dpp, ctx, inst,
987 &dpp_regs[inst], &tf_shift, &tf_mask))
988 return &dpp->base;
989
990 BREAK_TO_DEBUGGER();
991 kfree(dpp);
992 return NULL;
993 }
994
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)995 static struct output_pixel_processor *dcn31_opp_create(
996 struct dc_context *ctx, uint32_t inst)
997 {
998 struct dcn20_opp *opp =
999 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1000
1001 if (!opp) {
1002 BREAK_TO_DEBUGGER();
1003 return NULL;
1004 }
1005
1006 dcn20_opp_construct(opp, ctx, inst,
1007 &opp_regs[inst], &opp_shift, &opp_mask);
1008 return &opp->base;
1009 }
1010
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1011 static struct dce_aux *dcn31_aux_engine_create(
1012 struct dc_context *ctx,
1013 uint32_t inst)
1014 {
1015 struct aux_engine_dce110 *aux_engine =
1016 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1017
1018 if (!aux_engine)
1019 return NULL;
1020
1021 dce110_aux_engine_construct(aux_engine, ctx, inst,
1022 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1023 &aux_engine_regs[inst],
1024 &aux_mask,
1025 &aux_shift,
1026 ctx->dc->caps.extended_aux_timeout_support);
1027
1028 return &aux_engine->base;
1029 }
1030 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1031
1032 static const struct dce_i2c_registers i2c_hw_regs[] = {
1033 i2c_inst_regs(1),
1034 i2c_inst_regs(2),
1035 i2c_inst_regs(3),
1036 i2c_inst_regs(4),
1037 i2c_inst_regs(5),
1038 };
1039
1040 static const struct dce_i2c_shift i2c_shifts = {
1041 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1042 };
1043
1044 static const struct dce_i2c_mask i2c_masks = {
1045 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1046 };
1047
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1048 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1049 struct dc_context *ctx,
1050 uint32_t inst)
1051 {
1052 struct dce_i2c_hw *dce_i2c_hw =
1053 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1054
1055 if (!dce_i2c_hw)
1056 return NULL;
1057
1058 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1059 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1060
1061 return dce_i2c_hw;
1062 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1063 static struct mpc *dcn31_mpc_create(
1064 struct dc_context *ctx,
1065 int num_mpcc,
1066 int num_rmu)
1067 {
1068 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1069 GFP_KERNEL);
1070
1071 if (!mpc30)
1072 return NULL;
1073
1074 dcn30_mpc_construct(mpc30, ctx,
1075 &mpc_regs,
1076 &mpc_shift,
1077 &mpc_mask,
1078 num_mpcc,
1079 num_rmu);
1080
1081 return &mpc30->base;
1082 }
1083
dcn31_hubbub_create(struct dc_context * ctx)1084 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1085 {
1086 int i;
1087
1088 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1089 GFP_KERNEL);
1090
1091 if (!hubbub3)
1092 return NULL;
1093
1094 hubbub31_construct(hubbub3, ctx,
1095 &hubbub_reg,
1096 &hubbub_shift,
1097 &hubbub_mask,
1098 dcn3_14_ip.det_buffer_size_kbytes,
1099 dcn3_14_ip.pixel_chunk_size_kbytes,
1100 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1101
1102
1103 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1104 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1105
1106 vmid->ctx = ctx;
1107
1108 vmid->regs = &vmid_regs[i];
1109 vmid->shifts = &vmid_shifts;
1110 vmid->masks = &vmid_masks;
1111 }
1112
1113 return &hubbub3->base;
1114 }
1115
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1116 static struct timing_generator *dcn31_timing_generator_create(
1117 struct dc_context *ctx,
1118 uint32_t instance)
1119 {
1120 struct optc *tgn10 =
1121 kzalloc(sizeof(struct optc), GFP_KERNEL);
1122
1123 if (!tgn10)
1124 return NULL;
1125
1126 tgn10->base.inst = instance;
1127 tgn10->base.ctx = ctx;
1128
1129 tgn10->tg_regs = &optc_regs[instance];
1130 tgn10->tg_shift = &optc_shift;
1131 tgn10->tg_mask = &optc_mask;
1132
1133 dcn314_timing_generator_init(tgn10);
1134
1135 return &tgn10->base;
1136 }
1137
1138 static const struct encoder_feature_support link_enc_feature = {
1139 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1140 .max_hdmi_pixel_clock = 600000,
1141 .hdmi_ycbcr420_supported = true,
1142 .dp_ycbcr420_supported = true,
1143 .fec_supported = true,
1144 .flags.bits.IS_HBR2_CAPABLE = true,
1145 .flags.bits.IS_HBR3_CAPABLE = true,
1146 .flags.bits.IS_TPS3_CAPABLE = true,
1147 .flags.bits.IS_TPS4_CAPABLE = true
1148 };
1149
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1150 static struct link_encoder *dcn31_link_encoder_create(
1151 struct dc_context *ctx,
1152 const struct encoder_init_data *enc_init_data)
1153 {
1154 struct dcn20_link_encoder *enc20 =
1155 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1156
1157 if (!enc20)
1158 return NULL;
1159
1160 dcn31_link_encoder_construct(enc20,
1161 enc_init_data,
1162 &link_enc_feature,
1163 &link_enc_regs[enc_init_data->transmitter],
1164 &link_enc_aux_regs[enc_init_data->channel - 1],
1165 &link_enc_hpd_regs[enc_init_data->hpd_source],
1166 &le_shift,
1167 &le_mask);
1168
1169 return &enc20->enc10.base;
1170 }
1171
1172 /* Create a minimal link encoder object not associated with a particular
1173 * physical connector.
1174 * resource_funcs.link_enc_create_minimal
1175 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1176 static struct link_encoder *dcn31_link_enc_create_minimal(
1177 struct dc_context *ctx, enum engine_id eng_id)
1178 {
1179 struct dcn20_link_encoder *enc20;
1180
1181 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1182 return NULL;
1183
1184 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1185 if (!enc20)
1186 return NULL;
1187
1188 dcn31_link_encoder_construct_minimal(
1189 enc20,
1190 ctx,
1191 &link_enc_feature,
1192 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1193 eng_id);
1194
1195 return &enc20->enc10.base;
1196 }
1197
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1198 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1199 {
1200 struct dcn31_panel_cntl *panel_cntl =
1201 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1202
1203 if (!panel_cntl)
1204 return NULL;
1205
1206 dcn31_panel_cntl_construct(panel_cntl, init_data);
1207
1208 return &panel_cntl->base;
1209 }
1210
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1211 static void read_dce_straps(
1212 struct dc_context *ctx,
1213 struct resource_straps *straps)
1214 {
1215 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1216 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1217
1218 }
1219
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1220 static struct audio *dcn31_create_audio(
1221 struct dc_context *ctx, unsigned int inst)
1222 {
1223 return dce_audio_create(ctx, inst,
1224 &audio_regs[inst], &audio_shift, &audio_mask);
1225 }
1226
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1227 static struct vpg *dcn31_vpg_create(
1228 struct dc_context *ctx,
1229 uint32_t inst)
1230 {
1231 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1232
1233 if (!vpg31)
1234 return NULL;
1235
1236 vpg31_construct(vpg31, ctx, inst,
1237 &vpg_regs[inst],
1238 &vpg_shift,
1239 &vpg_mask);
1240
1241 return &vpg31->base;
1242 }
1243
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1244 static struct afmt *dcn31_afmt_create(
1245 struct dc_context *ctx,
1246 uint32_t inst)
1247 {
1248 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1249
1250 if (!afmt31)
1251 return NULL;
1252
1253 afmt31_construct(afmt31, ctx, inst,
1254 &afmt_regs[inst],
1255 &afmt_shift,
1256 &afmt_mask);
1257
1258 // Light sleep by default, no need to power down here
1259
1260 return &afmt31->base;
1261 }
1262
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1263 static struct apg *dcn31_apg_create(
1264 struct dc_context *ctx,
1265 uint32_t inst)
1266 {
1267 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1268
1269 if (!apg31)
1270 return NULL;
1271
1272 apg31_construct(apg31, ctx, inst,
1273 &apg_regs[inst],
1274 &apg_shift,
1275 &apg_mask);
1276
1277 return &apg31->base;
1278 }
1279
dcn314_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1280 static struct stream_encoder *dcn314_stream_encoder_create(
1281 enum engine_id eng_id,
1282 struct dc_context *ctx)
1283 {
1284 struct dcn10_stream_encoder *enc1;
1285 struct vpg *vpg;
1286 struct afmt *afmt;
1287 int vpg_inst;
1288 int afmt_inst;
1289
1290 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1291 if (eng_id < ENGINE_ID_DIGF) {
1292 vpg_inst = eng_id;
1293 afmt_inst = eng_id;
1294 } else
1295 return NULL;
1296
1297 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1298 vpg = dcn31_vpg_create(ctx, vpg_inst);
1299 afmt = dcn31_afmt_create(ctx, afmt_inst);
1300
1301 if (!enc1 || !vpg || !afmt) {
1302 kfree(enc1);
1303 kfree(vpg);
1304 kfree(afmt);
1305 return NULL;
1306 }
1307
1308 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1309 eng_id, vpg, afmt,
1310 &stream_enc_regs[eng_id],
1311 &se_shift, &se_mask);
1312
1313 return &enc1->base;
1314 }
1315
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1316 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1317 enum engine_id eng_id,
1318 struct dc_context *ctx)
1319 {
1320 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1321 struct vpg *vpg;
1322 struct apg *apg;
1323 uint32_t hpo_dp_inst;
1324 uint32_t vpg_inst;
1325 uint32_t apg_inst;
1326
1327 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1328 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1329
1330 /* Mapping of VPG register blocks to HPO DP block instance:
1331 * VPG[6] -> HPO_DP[0]
1332 * VPG[7] -> HPO_DP[1]
1333 * VPG[8] -> HPO_DP[2]
1334 * VPG[9] -> HPO_DP[3]
1335 */
1336 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1337 vpg_inst = hpo_dp_inst + 5;
1338
1339 /* Mapping of APG register blocks to HPO DP block instance:
1340 * APG[0] -> HPO_DP[0]
1341 * APG[1] -> HPO_DP[1]
1342 * APG[2] -> HPO_DP[2]
1343 * APG[3] -> HPO_DP[3]
1344 */
1345 apg_inst = hpo_dp_inst;
1346
1347 /* allocate HPO stream encoder and create VPG sub-block */
1348 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1349 vpg = dcn31_vpg_create(ctx, vpg_inst);
1350 apg = dcn31_apg_create(ctx, apg_inst);
1351
1352 if (!hpo_dp_enc31 || !vpg || !apg) {
1353 kfree(hpo_dp_enc31);
1354 kfree(vpg);
1355 kfree(apg);
1356 return NULL;
1357 }
1358
1359 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1360 hpo_dp_inst, eng_id, vpg, apg,
1361 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1362 &hpo_dp_se_shift, &hpo_dp_se_mask);
1363
1364 return &hpo_dp_enc31->base;
1365 }
1366
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1367 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1368 uint8_t inst,
1369 struct dc_context *ctx)
1370 {
1371 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1372
1373 /* allocate HPO link encoder */
1374 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1375
1376 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1377 &hpo_dp_link_enc_regs[inst],
1378 &hpo_dp_le_shift, &hpo_dp_le_mask);
1379
1380 return &hpo_dp_enc31->base;
1381 }
1382
dcn314_hwseq_create(struct dc_context * ctx)1383 static struct dce_hwseq *dcn314_hwseq_create(
1384 struct dc_context *ctx)
1385 {
1386 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1387
1388 if (hws) {
1389 hws->ctx = ctx;
1390 hws->regs = &hwseq_reg;
1391 hws->shifts = &hwseq_shift;
1392 hws->masks = &hwseq_mask;
1393 /* DCN3.1 FPGA Workaround
1394 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1395 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1396 * function core_link_enable_stream
1397 */
1398 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1399 hws->wa.dp_hpo_and_otg_sequence = true;
1400 }
1401 return hws;
1402 }
1403 static const struct resource_create_funcs res_create_funcs = {
1404 .read_dce_straps = read_dce_straps,
1405 .create_audio = dcn31_create_audio,
1406 .create_stream_encoder = dcn314_stream_encoder_create,
1407 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1408 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1409 .create_hwseq = dcn314_hwseq_create,
1410 };
1411
1412 static const struct resource_create_funcs res_create_maximus_funcs = {
1413 .read_dce_straps = NULL,
1414 .create_audio = NULL,
1415 .create_stream_encoder = NULL,
1416 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1417 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1418 .create_hwseq = dcn314_hwseq_create,
1419 };
1420
dcn314_resource_destruct(struct dcn314_resource_pool * pool)1421 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1422 {
1423 unsigned int i;
1424
1425 for (i = 0; i < pool->base.stream_enc_count; i++) {
1426 if (pool->base.stream_enc[i] != NULL) {
1427 if (pool->base.stream_enc[i]->vpg != NULL) {
1428 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1429 pool->base.stream_enc[i]->vpg = NULL;
1430 }
1431 if (pool->base.stream_enc[i]->afmt != NULL) {
1432 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1433 pool->base.stream_enc[i]->afmt = NULL;
1434 }
1435 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1436 pool->base.stream_enc[i] = NULL;
1437 }
1438 }
1439
1440 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1441 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1442 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1443 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1444 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1445 }
1446 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1447 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1448 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1449 }
1450 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1451 pool->base.hpo_dp_stream_enc[i] = NULL;
1452 }
1453 }
1454
1455 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1456 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1457 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1458 pool->base.hpo_dp_link_enc[i] = NULL;
1459 }
1460 }
1461
1462 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1463 if (pool->base.dscs[i] != NULL)
1464 dcn20_dsc_destroy(&pool->base.dscs[i]);
1465 }
1466
1467 if (pool->base.mpc != NULL) {
1468 kfree(TO_DCN20_MPC(pool->base.mpc));
1469 pool->base.mpc = NULL;
1470 }
1471 if (pool->base.hubbub != NULL) {
1472 kfree(pool->base.hubbub);
1473 pool->base.hubbub = NULL;
1474 }
1475 for (i = 0; i < pool->base.pipe_count; i++) {
1476 if (pool->base.dpps[i] != NULL)
1477 dcn31_dpp_destroy(&pool->base.dpps[i]);
1478
1479 if (pool->base.ipps[i] != NULL)
1480 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1481
1482 if (pool->base.hubps[i] != NULL) {
1483 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1484 pool->base.hubps[i] = NULL;
1485 }
1486
1487 if (pool->base.irqs != NULL)
1488 dal_irq_service_destroy(&pool->base.irqs);
1489 }
1490
1491 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1492 if (pool->base.engines[i] != NULL)
1493 dce110_engine_destroy(&pool->base.engines[i]);
1494 if (pool->base.hw_i2cs[i] != NULL) {
1495 kfree(pool->base.hw_i2cs[i]);
1496 pool->base.hw_i2cs[i] = NULL;
1497 }
1498 if (pool->base.sw_i2cs[i] != NULL) {
1499 kfree(pool->base.sw_i2cs[i]);
1500 pool->base.sw_i2cs[i] = NULL;
1501 }
1502 }
1503
1504 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1505 if (pool->base.opps[i] != NULL)
1506 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1507 }
1508
1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1510 if (pool->base.timing_generators[i] != NULL) {
1511 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1512 pool->base.timing_generators[i] = NULL;
1513 }
1514 }
1515
1516 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1517 if (pool->base.dwbc[i] != NULL) {
1518 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1519 pool->base.dwbc[i] = NULL;
1520 }
1521 if (pool->base.mcif_wb[i] != NULL) {
1522 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1523 pool->base.mcif_wb[i] = NULL;
1524 }
1525 }
1526
1527 for (i = 0; i < pool->base.audio_count; i++) {
1528 if (pool->base.audios[i])
1529 dce_aud_destroy(&pool->base.audios[i]);
1530 }
1531
1532 for (i = 0; i < pool->base.clk_src_count; i++) {
1533 if (pool->base.clock_sources[i] != NULL) {
1534 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1535 pool->base.clock_sources[i] = NULL;
1536 }
1537 }
1538
1539 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1540 if (pool->base.mpc_lut[i] != NULL) {
1541 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1542 pool->base.mpc_lut[i] = NULL;
1543 }
1544 if (pool->base.mpc_shaper[i] != NULL) {
1545 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1546 pool->base.mpc_shaper[i] = NULL;
1547 }
1548 }
1549
1550 if (pool->base.dp_clock_source != NULL) {
1551 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1552 pool->base.dp_clock_source = NULL;
1553 }
1554
1555 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1556 if (pool->base.multiple_abms[i] != NULL)
1557 dce_abm_destroy(&pool->base.multiple_abms[i]);
1558 }
1559
1560 if (pool->base.psr != NULL)
1561 dmub_psr_destroy(&pool->base.psr);
1562
1563 if (pool->base.dccg != NULL)
1564 dcn_dccg_destroy(&pool->base.dccg);
1565 }
1566
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1567 static struct hubp *dcn31_hubp_create(
1568 struct dc_context *ctx,
1569 uint32_t inst)
1570 {
1571 struct dcn20_hubp *hubp2 =
1572 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1573
1574 if (!hubp2)
1575 return NULL;
1576
1577 if (hubp31_construct(hubp2, ctx, inst,
1578 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1579 return &hubp2->base;
1580
1581 BREAK_TO_DEBUGGER();
1582 kfree(hubp2);
1583 return NULL;
1584 }
1585
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1586 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1587 {
1588 int i;
1589 uint32_t pipe_count = pool->res_cap->num_dwb;
1590
1591 for (i = 0; i < pipe_count; i++) {
1592 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1593 GFP_KERNEL);
1594
1595 if (!dwbc30) {
1596 dm_error("DC: failed to create dwbc30!\n");
1597 return false;
1598 }
1599
1600 dcn30_dwbc_construct(dwbc30, ctx,
1601 &dwbc30_regs[i],
1602 &dwbc30_shift,
1603 &dwbc30_mask,
1604 i);
1605
1606 pool->dwbc[i] = &dwbc30->base;
1607 }
1608 return true;
1609 }
1610
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1611 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1612 {
1613 int i;
1614 uint32_t pipe_count = pool->res_cap->num_dwb;
1615
1616 for (i = 0; i < pipe_count; i++) {
1617 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1618 GFP_KERNEL);
1619
1620 if (!mcif_wb30) {
1621 dm_error("DC: failed to create mcif_wb30!\n");
1622 return false;
1623 }
1624
1625 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1626 &mcif_wb30_regs[i],
1627 &mcif_wb30_shift,
1628 &mcif_wb30_mask,
1629 i);
1630
1631 pool->mcif_wb[i] = &mcif_wb30->base;
1632 }
1633 return true;
1634 }
1635
dcn314_dsc_create(struct dc_context * ctx,uint32_t inst)1636 static struct display_stream_compressor *dcn314_dsc_create(
1637 struct dc_context *ctx, uint32_t inst)
1638 {
1639 struct dcn20_dsc *dsc =
1640 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1641
1642 if (!dsc) {
1643 BREAK_TO_DEBUGGER();
1644 return NULL;
1645 }
1646
1647 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1648 return &dsc->base;
1649 }
1650
dcn314_destroy_resource_pool(struct resource_pool ** pool)1651 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1652 {
1653 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1654
1655 dcn314_resource_destruct(dcn314_pool);
1656 kfree(dcn314_pool);
1657 *pool = NULL;
1658 }
1659
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1660 static struct clock_source *dcn31_clock_source_create(
1661 struct dc_context *ctx,
1662 struct dc_bios *bios,
1663 enum clock_source_id id,
1664 const struct dce110_clk_src_regs *regs,
1665 bool dp_clk_src)
1666 {
1667 struct dce110_clk_src *clk_src =
1668 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1669
1670 if (!clk_src)
1671 return NULL;
1672
1673 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1674 regs, &cs_shift, &cs_mask)) {
1675 clk_src->base.dp_clk_src = dp_clk_src;
1676 return &clk_src->base;
1677 }
1678
1679 BREAK_TO_DEBUGGER();
1680 kfree(clk_src);
1681 return NULL;
1682 }
1683
dcn314_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1684 static int dcn314_populate_dml_pipes_from_context(
1685 struct dc *dc, struct dc_state *context,
1686 display_e2e_pipe_params_st *pipes,
1687 bool fast_validate)
1688 {
1689 int pipe_cnt;
1690
1691 DC_FP_START();
1692 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1693 DC_FP_END();
1694
1695 return pipe_cnt;
1696 }
1697
1698 static struct dc_cap_funcs cap_funcs = {
1699 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1700 };
1701
dcn314_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1702 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1703 {
1704 DC_FP_START();
1705 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1706 DC_FP_END();
1707 }
1708
dcn314_get_panel_config_defaults(struct dc_panel_config * panel_config)1709 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1710 {
1711 *panel_config = panel_config_defaults;
1712 }
1713
filter_modes_for_single_channel_workaround(struct dc * dc,struct dc_state * context)1714 static bool filter_modes_for_single_channel_workaround(struct dc *dc,
1715 struct dc_state *context)
1716 {
1717 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
1718 if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
1719 int total_phy_pix_clk = 0;
1720
1721 for (int i = 0; i < context->stream_count; i++)
1722 if (context->res_ctx.pipe_ctx[i].stream)
1723 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
1724
1725 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
1726 return true;
1727 }
1728 return false;
1729 }
1730
dcn314_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1731 bool dcn314_validate_bandwidth(struct dc *dc,
1732 struct dc_state *context,
1733 bool fast_validate)
1734 {
1735 bool out = false;
1736
1737 BW_VAL_TRACE_SETUP();
1738
1739 int vlevel = 0;
1740 int pipe_cnt = 0;
1741 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1742 DC_LOGGER_INIT(dc->ctx->logger);
1743
1744 BW_VAL_TRACE_COUNT();
1745
1746 if (filter_modes_for_single_channel_workaround(dc, context))
1747 goto validate_fail;
1748
1749 DC_FP_START();
1750 // do not support self refresh only
1751 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
1752 DC_FP_END();
1753
1754 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1755 if (pipe_cnt == 0)
1756 fast_validate = false;
1757
1758 if (!out)
1759 goto validate_fail;
1760
1761 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1762
1763 if (fast_validate) {
1764 BW_VAL_TRACE_SKIP(fast);
1765 goto validate_out;
1766 }
1767
1768 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1769
1770 BW_VAL_TRACE_END_WATERMARKS();
1771
1772 goto validate_out;
1773
1774 validate_fail:
1775 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1776 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1777
1778 BW_VAL_TRACE_SKIP(fail);
1779 out = false;
1780
1781 validate_out:
1782 kfree(pipes);
1783
1784 BW_VAL_TRACE_FINISH();
1785
1786 return out;
1787 }
1788
1789 static struct resource_funcs dcn314_res_pool_funcs = {
1790 .destroy = dcn314_destroy_resource_pool,
1791 .link_enc_create = dcn31_link_encoder_create,
1792 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1793 .link_encs_assign = link_enc_cfg_link_encs_assign,
1794 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1795 .panel_cntl_create = dcn31_panel_cntl_create,
1796 .validate_bandwidth = dcn314_validate_bandwidth,
1797 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1798 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1799 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1800 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1801 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1802 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1803 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1804 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1805 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1806 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1807 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1808 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1809 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1810 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1811 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1812 };
1813
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1814 static struct clock_source *dcn30_clock_source_create(
1815 struct dc_context *ctx,
1816 struct dc_bios *bios,
1817 enum clock_source_id id,
1818 const struct dce110_clk_src_regs *regs,
1819 bool dp_clk_src)
1820 {
1821 struct dce110_clk_src *clk_src =
1822 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1823
1824 if (!clk_src)
1825 return NULL;
1826
1827 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1828 regs, &cs_shift, &cs_mask)) {
1829 clk_src->base.dp_clk_src = dp_clk_src;
1830 return &clk_src->base;
1831 }
1832
1833 BREAK_TO_DEBUGGER();
1834 kfree(clk_src);
1835 return NULL;
1836 }
1837
dcn314_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn314_resource_pool * pool)1838 static bool dcn314_resource_construct(
1839 uint8_t num_virtual_links,
1840 struct dc *dc,
1841 struct dcn314_resource_pool *pool)
1842 {
1843 int i;
1844 struct dc_context *ctx = dc->ctx;
1845 struct irq_service_init_data init_data;
1846
1847 ctx->dc_bios->regs = &bios_regs;
1848
1849 pool->base.res_cap = &res_cap_dcn314;
1850 pool->base.funcs = &dcn314_res_pool_funcs;
1851
1852 /*************************************************
1853 * Resource + asic cap harcoding *
1854 *************************************************/
1855 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1856 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1857 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1858 dc->caps.max_downscale_ratio = 400;
1859 dc->caps.i2c_speed_in_khz = 100;
1860 dc->caps.i2c_speed_in_khz_hdcp = 100;
1861 dc->caps.max_cursor_size = 256;
1862 dc->caps.min_horizontal_blanking_period = 80;
1863 dc->caps.dmdata_alloc_size = 2048;
1864 dc->caps.max_slave_planes = 2;
1865 dc->caps.max_slave_yuv_planes = 2;
1866 dc->caps.max_slave_rgb_planes = 2;
1867 dc->caps.post_blend_color_processing = true;
1868 dc->caps.force_dp_tps4_for_cp2520 = true;
1869 dc->caps.dp_hpo = true;
1870 dc->caps.dp_hdmi21_pcon_support = true;
1871 dc->caps.edp_dsc_support = true;
1872 dc->caps.extended_aux_timeout_support = true;
1873 dc->caps.dmcub_support = true;
1874 dc->caps.is_apu = true;
1875 dc->caps.seamless_odm = true;
1876
1877 dc->caps.zstate_support = true;
1878
1879 /* Color pipeline capabilities */
1880 dc->caps.color.dpp.dcn_arch = 1;
1881 dc->caps.color.dpp.input_lut_shared = 0;
1882 dc->caps.color.dpp.icsc = 1;
1883 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1884 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1885 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1886 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1887 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1888 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1889 dc->caps.color.dpp.post_csc = 1;
1890 dc->caps.color.dpp.gamma_corr = 1;
1891 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1892
1893 dc->caps.color.dpp.hw_3d_lut = 1;
1894 dc->caps.color.dpp.ogam_ram = 1;
1895 // no OGAM ROM on DCN301
1896 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1897 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1898 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1899 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1900 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1901 dc->caps.color.dpp.ocsc = 0;
1902
1903 dc->caps.color.mpc.gamut_remap = 1;
1904 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1905 dc->caps.color.mpc.ogam_ram = 1;
1906 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1907 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1908 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1909 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1910 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1911 dc->caps.color.mpc.ocsc = 1;
1912
1913 /* Use pipe context based otg sync logic */
1914 dc->config.use_pipe_ctx_sync_logic = true;
1915
1916 /* read VBIOS LTTPR caps */
1917 {
1918 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1919 enum bp_result bp_query_result;
1920 uint8_t is_vbios_lttpr_enable = 0;
1921
1922 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1923 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1924 }
1925
1926 /* interop bit is implicit */
1927 {
1928 dc->caps.vbios_lttpr_aware = true;
1929 }
1930 }
1931
1932 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1933 dc->debug = debug_defaults_drv;
1934 else
1935 dc->debug = debug_defaults_diags;
1936
1937 /* Disable root clock optimization */
1938 dc->debug.root_clock_optimization.u32All = 0;
1939
1940 // Init the vm_helper
1941 if (dc->vm_helper)
1942 vm_helper_init(dc->vm_helper, 16);
1943
1944 /*************************************************
1945 * Create resources *
1946 *************************************************/
1947
1948 /* Clock Sources for Pixel Clock*/
1949 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1950 dcn30_clock_source_create(ctx, ctx->dc_bios,
1951 CLOCK_SOURCE_COMBO_PHY_PLL0,
1952 &clk_src_regs[0], false);
1953 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1954 dcn30_clock_source_create(ctx, ctx->dc_bios,
1955 CLOCK_SOURCE_COMBO_PHY_PLL1,
1956 &clk_src_regs[1], false);
1957 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1958 dcn30_clock_source_create(ctx, ctx->dc_bios,
1959 CLOCK_SOURCE_COMBO_PHY_PLL2,
1960 &clk_src_regs[2], false);
1961 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1962 dcn30_clock_source_create(ctx, ctx->dc_bios,
1963 CLOCK_SOURCE_COMBO_PHY_PLL3,
1964 &clk_src_regs[3], false);
1965 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1966 dcn30_clock_source_create(ctx, ctx->dc_bios,
1967 CLOCK_SOURCE_COMBO_PHY_PLL4,
1968 &clk_src_regs[4], false);
1969
1970 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1971
1972 /* todo: not reuse phy_pll registers */
1973 pool->base.dp_clock_source =
1974 dcn31_clock_source_create(ctx, ctx->dc_bios,
1975 CLOCK_SOURCE_ID_DP_DTO,
1976 &clk_src_regs[0], true);
1977
1978 for (i = 0; i < pool->base.clk_src_count; i++) {
1979 if (pool->base.clock_sources[i] == NULL) {
1980 dm_error("DC: failed to create clock sources!\n");
1981 BREAK_TO_DEBUGGER();
1982 goto create_fail;
1983 }
1984 }
1985
1986 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1987 if (pool->base.dccg == NULL) {
1988 dm_error("DC: failed to create dccg!\n");
1989 BREAK_TO_DEBUGGER();
1990 goto create_fail;
1991 }
1992
1993 init_data.ctx = dc->ctx;
1994 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
1995 if (!pool->base.irqs)
1996 goto create_fail;
1997
1998 /* HUBBUB */
1999 pool->base.hubbub = dcn31_hubbub_create(ctx);
2000 if (pool->base.hubbub == NULL) {
2001 BREAK_TO_DEBUGGER();
2002 dm_error("DC: failed to create hubbub!\n");
2003 goto create_fail;
2004 }
2005
2006 /* HUBPs, DPPs, OPPs and TGs */
2007 for (i = 0; i < pool->base.pipe_count; i++) {
2008 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2009 if (pool->base.hubps[i] == NULL) {
2010 BREAK_TO_DEBUGGER();
2011 dm_error(
2012 "DC: failed to create hubps!\n");
2013 goto create_fail;
2014 }
2015
2016 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2017 if (pool->base.dpps[i] == NULL) {
2018 BREAK_TO_DEBUGGER();
2019 dm_error(
2020 "DC: failed to create dpps!\n");
2021 goto create_fail;
2022 }
2023 }
2024
2025 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2026 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2027 if (pool->base.opps[i] == NULL) {
2028 BREAK_TO_DEBUGGER();
2029 dm_error(
2030 "DC: failed to create output pixel processor!\n");
2031 goto create_fail;
2032 }
2033 }
2034
2035 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2036 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2037 ctx, i);
2038 if (pool->base.timing_generators[i] == NULL) {
2039 BREAK_TO_DEBUGGER();
2040 dm_error("DC: failed to create tg!\n");
2041 goto create_fail;
2042 }
2043 }
2044 pool->base.timing_generator_count = i;
2045
2046 /* PSR */
2047 pool->base.psr = dmub_psr_create(ctx);
2048 if (pool->base.psr == NULL) {
2049 dm_error("DC: failed to create psr obj!\n");
2050 BREAK_TO_DEBUGGER();
2051 goto create_fail;
2052 }
2053
2054 /* ABM */
2055 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2056 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2057 &abm_regs[i],
2058 &abm_shift,
2059 &abm_mask);
2060 if (pool->base.multiple_abms[i] == NULL) {
2061 dm_error("DC: failed to create abm for pipe %d!\n", i);
2062 BREAK_TO_DEBUGGER();
2063 goto create_fail;
2064 }
2065 }
2066
2067 /* MPC and DSC */
2068 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2069 if (pool->base.mpc == NULL) {
2070 BREAK_TO_DEBUGGER();
2071 dm_error("DC: failed to create mpc!\n");
2072 goto create_fail;
2073 }
2074
2075 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2076 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2077 if (pool->base.dscs[i] == NULL) {
2078 BREAK_TO_DEBUGGER();
2079 dm_error("DC: failed to create display stream compressor %d!\n", i);
2080 goto create_fail;
2081 }
2082 }
2083
2084 /* DWB and MMHUBBUB */
2085 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2086 BREAK_TO_DEBUGGER();
2087 dm_error("DC: failed to create dwbc!\n");
2088 goto create_fail;
2089 }
2090
2091 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2092 BREAK_TO_DEBUGGER();
2093 dm_error("DC: failed to create mcif_wb!\n");
2094 goto create_fail;
2095 }
2096
2097 /* AUX and I2C */
2098 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2099 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2100 if (pool->base.engines[i] == NULL) {
2101 BREAK_TO_DEBUGGER();
2102 dm_error(
2103 "DC:failed to create aux engine!!\n");
2104 goto create_fail;
2105 }
2106 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2107 if (pool->base.hw_i2cs[i] == NULL) {
2108 BREAK_TO_DEBUGGER();
2109 dm_error(
2110 "DC:failed to create hw i2c!!\n");
2111 goto create_fail;
2112 }
2113 pool->base.sw_i2cs[i] = NULL;
2114 }
2115
2116 /* DCN314 has 4 DPIA */
2117 pool->base.usb4_dpia_count = 4;
2118
2119 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2120 if (!resource_construct(num_virtual_links, dc, &pool->base,
2121 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2122 &res_create_funcs : &res_create_maximus_funcs)))
2123 goto create_fail;
2124
2125 /* HW Sequencer and Plane caps */
2126 dcn314_hw_sequencer_construct(dc);
2127
2128 dc->caps.max_planes = pool->base.pipe_count;
2129
2130 for (i = 0; i < dc->caps.max_planes; ++i)
2131 dc->caps.planes[i] = plane_cap;
2132
2133 dc->cap_funcs = cap_funcs;
2134
2135 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2136
2137 return true;
2138
2139 create_fail:
2140
2141 dcn314_resource_destruct(pool);
2142
2143 return false;
2144 }
2145
dcn314_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2146 struct resource_pool *dcn314_create_resource_pool(
2147 const struct dc_init_data *init_data,
2148 struct dc *dc)
2149 {
2150 struct dcn314_resource_pool *pool =
2151 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2152
2153 if (!pool)
2154 return NULL;
2155
2156 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2157 return &pool->base;
2158
2159 BREAK_TO_DEBUGGER();
2160 kfree(pool);
2161 return NULL;
2162 }
2163