1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #include "main.h"
4
5 static struct irdma_rsrc_limits rsrc_limits_table[] = {
6 [0] = {
7 .qplimit = SZ_128,
8 },
9 [1] = {
10 .qplimit = SZ_1K,
11 },
12 [2] = {
13 .qplimit = SZ_2K,
14 },
15 [3] = {
16 .qplimit = SZ_4K,
17 },
18 [4] = {
19 .qplimit = SZ_16K,
20 },
21 [5] = {
22 .qplimit = SZ_64K,
23 },
24 [6] = {
25 .qplimit = SZ_128K,
26 },
27 [7] = {
28 .qplimit = SZ_256K,
29 },
30 };
31
32 /* types of hmc objects */
33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = {
34 IRDMA_HMC_IW_QP,
35 IRDMA_HMC_IW_CQ,
36 IRDMA_HMC_IW_HTE,
37 IRDMA_HMC_IW_ARP,
38 IRDMA_HMC_IW_APBVT_ENTRY,
39 IRDMA_HMC_IW_MR,
40 IRDMA_HMC_IW_XF,
41 IRDMA_HMC_IW_XFFL,
42 IRDMA_HMC_IW_Q1,
43 IRDMA_HMC_IW_Q1FL,
44 IRDMA_HMC_IW_PBLE,
45 IRDMA_HMC_IW_TIMER,
46 IRDMA_HMC_IW_FSIMC,
47 IRDMA_HMC_IW_FSIAV,
48 IRDMA_HMC_IW_RRF,
49 IRDMA_HMC_IW_RRFFL,
50 IRDMA_HMC_IW_HDR,
51 IRDMA_HMC_IW_MD,
52 IRDMA_HMC_IW_OOISC,
53 IRDMA_HMC_IW_OOISCFFL,
54 };
55
56 /**
57 * irdma_iwarp_ce_handler - handle iwarp completions
58 * @iwcq: iwarp cq receiving event
59 */
irdma_iwarp_ce_handler(struct irdma_sc_cq * iwcq)60 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
61 {
62 struct irdma_cq *cq = iwcq->back_cq;
63
64 if (!cq->user_mode)
65 atomic_set(&cq->armed, 0);
66 if (cq->ibcq.comp_handler)
67 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
68 }
69
70 /**
71 * irdma_puda_ce_handler - handle puda completion events
72 * @rf: RDMA PCI function
73 * @cq: puda completion q for event
74 */
irdma_puda_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)75 static void irdma_puda_ce_handler(struct irdma_pci_f *rf,
76 struct irdma_sc_cq *cq)
77 {
78 struct irdma_sc_dev *dev = &rf->sc_dev;
79 u32 compl_error;
80 int status;
81
82 do {
83 status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
84 if (status == -ENOENT)
85 break;
86 if (status) {
87 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status);
88 break;
89 }
90 if (compl_error) {
91 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n",
92 compl_error);
93 break;
94 }
95 } while (1);
96
97 irdma_sc_ccq_arm(cq);
98 }
99
100 /**
101 * irdma_process_ceq - handle ceq for completions
102 * @rf: RDMA PCI function
103 * @ceq: ceq having cq for completion
104 */
irdma_process_ceq(struct irdma_pci_f * rf,struct irdma_ceq * ceq)105 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)
106 {
107 struct irdma_sc_dev *dev = &rf->sc_dev;
108 struct irdma_sc_ceq *sc_ceq;
109 struct irdma_sc_cq *cq;
110 unsigned long flags;
111
112 sc_ceq = &ceq->sc_ceq;
113 do {
114 spin_lock_irqsave(&ceq->ce_lock, flags);
115 cq = irdma_sc_process_ceq(dev, sc_ceq);
116 if (!cq) {
117 spin_unlock_irqrestore(&ceq->ce_lock, flags);
118 break;
119 }
120
121 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP)
122 irdma_iwarp_ce_handler(cq);
123
124 spin_unlock_irqrestore(&ceq->ce_lock, flags);
125
126 if (cq->cq_type == IRDMA_CQ_TYPE_CQP)
127 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);
128 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ ||
129 cq->cq_type == IRDMA_CQ_TYPE_IEQ)
130 irdma_puda_ce_handler(rf, cq);
131 } while (1);
132 }
133
irdma_set_flush_fields(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
135 struct irdma_aeqe_info *info)
136 {
137 qp->sq_flush_code = info->sq;
138 qp->rq_flush_code = info->rq;
139 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
140
141 switch (info->ae_id) {
142 case IRDMA_AE_AMP_BOUNDS_VIOLATION:
143 case IRDMA_AE_AMP_INVALID_STAG:
144 case IRDMA_AE_AMP_RIGHTS_VIOLATION:
145 case IRDMA_AE_AMP_UNALLOCATED_STAG:
146 case IRDMA_AE_AMP_BAD_PD:
147 case IRDMA_AE_AMP_BAD_QP:
148 case IRDMA_AE_AMP_BAD_STAG_KEY:
149 case IRDMA_AE_AMP_BAD_STAG_INDEX:
150 case IRDMA_AE_AMP_TO_WRAP:
151 case IRDMA_AE_PRIV_OPERATION_DENIED:
152 qp->flush_code = FLUSH_PROT_ERR;
153 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
154 break;
155 case IRDMA_AE_UDA_XMIT_BAD_PD:
156 case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
157 qp->flush_code = FLUSH_LOC_QP_OP_ERR;
158 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
159 break;
160 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
161 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
162 case IRDMA_AE_UDA_L4LEN_INVALID:
163 case IRDMA_AE_DDP_UBE_INVALID_MO:
164 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
165 qp->flush_code = FLUSH_LOC_LEN_ERR;
166 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
167 break;
168 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
169 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
170 qp->flush_code = FLUSH_REM_ACCESS_ERR;
171 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
172 break;
173 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
174 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
175 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
176 case IRDMA_AE_IB_REMOTE_OP_ERROR:
177 qp->flush_code = FLUSH_REM_OP_ERR;
178 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
179 break;
180 case IRDMA_AE_LCE_QP_CATASTROPHIC:
181 qp->flush_code = FLUSH_FATAL_ERR;
182 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
183 break;
184 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
185 qp->flush_code = FLUSH_GENERAL_ERR;
186 break;
187 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
188 qp->flush_code = FLUSH_RETRY_EXC_ERR;
189 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
190 break;
191 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS:
192 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED:
193 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS:
194 case IRDMA_AE_AMP_MWBIND_VALID_STAG:
195 qp->flush_code = FLUSH_MW_BIND_ERR;
196 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
197 break;
198 case IRDMA_AE_IB_INVALID_REQUEST:
199 qp->flush_code = FLUSH_REM_INV_REQ_ERR;
200 qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
201 break;
202 default:
203 qp->flush_code = FLUSH_GENERAL_ERR;
204 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
205 break;
206 }
207 }
208
209 /**
210 * irdma_process_aeq - handle aeq events
211 * @rf: RDMA PCI function
212 */
irdma_process_aeq(struct irdma_pci_f * rf)213 static void irdma_process_aeq(struct irdma_pci_f *rf)
214 {
215 struct irdma_sc_dev *dev = &rf->sc_dev;
216 struct irdma_aeq *aeq = &rf->aeq;
217 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq;
218 struct irdma_aeqe_info aeinfo;
219 struct irdma_aeqe_info *info = &aeinfo;
220 int ret;
221 struct irdma_qp *iwqp = NULL;
222 struct irdma_sc_cq *cq = NULL;
223 struct irdma_cq *iwcq = NULL;
224 struct irdma_sc_qp *qp = NULL;
225 struct irdma_qp_host_ctx_info *ctx_info = NULL;
226 struct irdma_device *iwdev = rf->iwdev;
227 unsigned long flags;
228
229 u32 aeqcnt = 0;
230
231 if (!sc_aeq->size)
232 return;
233
234 do {
235 memset(info, 0, sizeof(*info));
236 ret = irdma_sc_get_next_aeqe(sc_aeq, info);
237 if (ret)
238 break;
239
240 aeqcnt++;
241 ibdev_dbg(&iwdev->ibdev,
242 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n",
243 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state,
244 info->iwarp_state, info->ae_src);
245
246 if (info->qp) {
247 spin_lock_irqsave(&rf->qptable_lock, flags);
248 iwqp = rf->qp_table[info->qp_cq_id];
249 if (!iwqp) {
250 spin_unlock_irqrestore(&rf->qptable_lock,
251 flags);
252 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) {
253 atomic_dec(&iwdev->vsi.qp_suspend_reqs);
254 wake_up(&iwdev->suspend_wq);
255 continue;
256 }
257 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n",
258 info->qp_cq_id);
259 continue;
260 }
261 irdma_qp_add_ref(&iwqp->ibqp);
262 spin_unlock_irqrestore(&rf->qptable_lock, flags);
263 qp = &iwqp->sc_qp;
264 spin_lock_irqsave(&iwqp->lock, flags);
265 iwqp->hw_tcp_state = info->tcp_state;
266 iwqp->hw_iwarp_state = info->iwarp_state;
267 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE)
268 iwqp->last_aeq = info->ae_id;
269 spin_unlock_irqrestore(&iwqp->lock, flags);
270 ctx_info = &iwqp->ctx_info;
271 } else {
272 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR)
273 continue;
274 }
275
276 switch (info->ae_id) {
277 struct irdma_cm_node *cm_node;
278 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
279 cm_node = iwqp->cm_node;
280 if (cm_node->accept_pend) {
281 atomic_dec(&cm_node->listener->pend_accepts_cnt);
282 cm_node->accept_pend = 0;
283 }
284 iwqp->rts_ae_rcvd = 1;
285 wake_up_interruptible(&iwqp->waitq);
286 break;
287 case IRDMA_AE_LLP_FIN_RECEIVED:
288 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
289 if (qp->term_flags)
290 break;
291 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
292 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT;
293 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT &&
294 iwqp->ibqp_state == IB_QPS_RTS) {
295 irdma_next_iw_state(iwqp,
296 IRDMA_QP_STATE_CLOSING,
297 0, 0, 0);
298 irdma_cm_disconn(iwqp);
299 }
300 irdma_schedule_cm_timer(iwqp->cm_node,
301 (struct irdma_puda_buf *)iwqp,
302 IRDMA_TIMER_TYPE_CLOSE,
303 1, 0);
304 }
305 break;
306 case IRDMA_AE_LLP_CLOSE_COMPLETE:
307 if (qp->term_flags)
308 irdma_terminate_done(qp, 0);
309 else
310 irdma_cm_disconn(iwqp);
311 break;
312 case IRDMA_AE_BAD_CLOSE:
313 case IRDMA_AE_RESET_SENT:
314 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0,
315 0);
316 irdma_cm_disconn(iwqp);
317 break;
318 case IRDMA_AE_LLP_CONNECTION_RESET:
319 if (atomic_read(&iwqp->close_timer_started))
320 break;
321 irdma_cm_disconn(iwqp);
322 break;
323 case IRDMA_AE_QP_SUSPEND_COMPLETE:
324 if (iwqp->iwdev->vsi.tc_change_pending) {
325 if (!atomic_dec_return(&qp->vsi->qp_suspend_reqs))
326 wake_up(&iwqp->iwdev->suspend_wq);
327 }
328 if (iwqp->suspend_pending) {
329 iwqp->suspend_pending = false;
330 wake_up(&iwqp->iwdev->suspend_wq);
331 }
332 break;
333 case IRDMA_AE_TERMINATE_SENT:
334 irdma_terminate_send_fin(qp);
335 break;
336 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
337 irdma_terminate_received(qp, info);
338 break;
339 case IRDMA_AE_CQ_OPERATION_ERROR:
340 ibdev_err(&iwdev->ibdev,
341 "Processing an iWARP related AE for CQ misc = 0x%04X\n",
342 info->ae_id);
343 cq = (struct irdma_sc_cq *)(unsigned long)
344 info->compl_ctx;
345
346 iwcq = cq->back_cq;
347
348 if (iwcq->ibcq.event_handler) {
349 struct ib_event ibevent;
350
351 ibevent.device = iwcq->ibcq.device;
352 ibevent.event = IB_EVENT_CQ_ERR;
353 ibevent.element.cq = &iwcq->ibcq;
354 iwcq->ibcq.event_handler(&ibevent,
355 iwcq->ibcq.cq_context);
356 }
357 break;
358 case IRDMA_AE_RESET_NOT_SENT:
359 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
360 case IRDMA_AE_RESOURCE_EXHAUSTION:
361 break;
362 case IRDMA_AE_PRIV_OPERATION_DENIED:
363 case IRDMA_AE_STAG_ZERO_INVALID:
364 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
365 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
366 case IRDMA_AE_DDP_UBE_INVALID_MO:
367 case IRDMA_AE_DDP_UBE_INVALID_QN:
368 case IRDMA_AE_DDP_NO_L_BIT:
369 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
370 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
371 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
372 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
373 case IRDMA_AE_INVALID_ARP_ENTRY:
374 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
375 case IRDMA_AE_STALE_ARP_ENTRY:
376 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
377 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
378 case IRDMA_AE_LLP_SYN_RECEIVED:
379 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
380 case IRDMA_AE_LCE_QP_CATASTROPHIC:
381 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC:
382 case IRDMA_AE_LLP_TOO_MANY_RNRS:
383 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
384 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
385 default:
386 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n",
387 info->ae_id, info->qp, info->qp_cq_id, info->ae_src);
388 if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
389 ctx_info->roce_info->err_rq_idx_valid = info->rq;
390 if (info->rq) {
391 ctx_info->roce_info->err_rq_idx = info->wqe_idx;
392 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va,
393 ctx_info);
394 }
395 irdma_set_flush_fields(qp, info);
396 irdma_cm_disconn(iwqp);
397 break;
398 }
399 ctx_info->iwarp_info->err_rq_idx_valid = info->rq;
400 if (info->rq) {
401 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx;
402 ctx_info->tcp_info_valid = false;
403 ctx_info->iwarp_info_valid = true;
404 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va,
405 ctx_info);
406 }
407 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS &&
408 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) {
409 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0);
410 irdma_cm_disconn(iwqp);
411 } else {
412 irdma_terminate_connection(qp, info);
413 }
414 break;
415 }
416 if (info->qp)
417 irdma_qp_rem_ref(&iwqp->ibqp);
418 } while (1);
419
420 if (aeqcnt)
421 irdma_sc_repost_aeq_entries(dev, aeqcnt);
422 }
423
424 /**
425 * irdma_ena_intr - set up device interrupts
426 * @dev: hardware control device structure
427 * @msix_id: id of the interrupt to be enabled
428 */
irdma_ena_intr(struct irdma_sc_dev * dev,u32 msix_id)429 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id)
430 {
431 dev->irq_ops->irdma_en_irq(dev, msix_id);
432 }
433
434 /**
435 * irdma_dpc - tasklet for aeq and ceq 0
436 * @t: tasklet_struct ptr
437 */
irdma_dpc(struct tasklet_struct * t)438 static void irdma_dpc(struct tasklet_struct *t)
439 {
440 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet);
441
442 if (rf->msix_shared)
443 irdma_process_ceq(rf, rf->ceqlist);
444 irdma_process_aeq(rf);
445 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx);
446 }
447
448 /**
449 * irdma_ceq_dpc - dpc handler for CEQ
450 * @t: tasklet_struct ptr
451 */
irdma_ceq_dpc(struct tasklet_struct * t)452 static void irdma_ceq_dpc(struct tasklet_struct *t)
453 {
454 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet);
455 struct irdma_pci_f *rf = iwceq->rf;
456
457 irdma_process_ceq(rf, iwceq);
458 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx);
459 }
460
461 /**
462 * irdma_save_msix_info - copy msix vector information to iwarp device
463 * @rf: RDMA PCI function
464 *
465 * Allocate iwdev msix table and copy the msix info to the table
466 * Return 0 if successful, otherwise return error
467 */
irdma_save_msix_info(struct irdma_pci_f * rf)468 static int irdma_save_msix_info(struct irdma_pci_f *rf)
469 {
470 struct irdma_qvlist_info *iw_qvlist;
471 struct irdma_qv_info *iw_qvinfo;
472 struct msix_entry *pmsix;
473 u32 ceq_idx;
474 u32 i;
475 size_t size;
476
477 if (!rf->msix_count)
478 return -EINVAL;
479
480 size = sizeof(struct irdma_msix_vector) * rf->msix_count;
481 size += struct_size(iw_qvlist, qv_info, rf->msix_count);
482 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
483 if (!rf->iw_msixtbl)
484 return -ENOMEM;
485
486 rf->iw_qvlist = (struct irdma_qvlist_info *)
487 (&rf->iw_msixtbl[rf->msix_count]);
488 iw_qvlist = rf->iw_qvlist;
489 iw_qvinfo = iw_qvlist->qv_info;
490 iw_qvlist->num_vectors = rf->msix_count;
491 if (rf->msix_count <= num_online_cpus())
492 rf->msix_shared = true;
493 else if (rf->msix_count > num_online_cpus() + 1)
494 rf->msix_count = num_online_cpus() + 1;
495
496 pmsix = rf->msix_entries;
497 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) {
498 rf->iw_msixtbl[i].idx = pmsix->entry;
499 rf->iw_msixtbl[i].irq = pmsix->vector;
500 rf->iw_msixtbl[i].cpu_affinity = ceq_idx;
501 if (!i) {
502 iw_qvinfo->aeq_idx = 0;
503 if (rf->msix_shared)
504 iw_qvinfo->ceq_idx = ceq_idx++;
505 else
506 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX;
507 } else {
508 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX;
509 iw_qvinfo->ceq_idx = ceq_idx++;
510 }
511 iw_qvinfo->itr_idx = 3;
512 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx;
513 pmsix++;
514 }
515
516 return 0;
517 }
518
519 /**
520 * irdma_irq_handler - interrupt handler for aeq and ceq0
521 * @irq: Interrupt request number
522 * @data: RDMA PCI function
523 */
irdma_irq_handler(int irq,void * data)524 static irqreturn_t irdma_irq_handler(int irq, void *data)
525 {
526 struct irdma_pci_f *rf = data;
527
528 tasklet_schedule(&rf->dpc_tasklet);
529
530 return IRQ_HANDLED;
531 }
532
533 /**
534 * irdma_ceq_handler - interrupt handler for ceq
535 * @irq: interrupt request number
536 * @data: ceq pointer
537 */
irdma_ceq_handler(int irq,void * data)538 static irqreturn_t irdma_ceq_handler(int irq, void *data)
539 {
540 struct irdma_ceq *iwceq = data;
541
542 if (iwceq->irq != irq)
543 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n",
544 iwceq->irq, irq);
545 tasklet_schedule(&iwceq->dpc_tasklet);
546
547 return IRQ_HANDLED;
548 }
549
550 /**
551 * irdma_destroy_irq - destroy device interrupts
552 * @rf: RDMA PCI function
553 * @msix_vec: msix vector to disable irq
554 * @dev_id: parameter to pass to free_irq (used during irq setup)
555 *
556 * The function is called when destroying aeq/ceq
557 */
irdma_destroy_irq(struct irdma_pci_f * rf,struct irdma_msix_vector * msix_vec,void * dev_id)558 static void irdma_destroy_irq(struct irdma_pci_f *rf,
559 struct irdma_msix_vector *msix_vec, void *dev_id)
560 {
561 struct irdma_sc_dev *dev = &rf->sc_dev;
562
563 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx);
564 irq_update_affinity_hint(msix_vec->irq, NULL);
565 free_irq(msix_vec->irq, dev_id);
566 if (rf == dev_id) {
567 tasklet_kill(&rf->dpc_tasklet);
568 } else {
569 struct irdma_ceq *iwceq = (struct irdma_ceq *)dev_id;
570
571 tasklet_kill(&iwceq->dpc_tasklet);
572 }
573 }
574
575 /**
576 * irdma_destroy_cqp - destroy control qp
577 * @rf: RDMA PCI function
578 * @free_hwcqp: 1 if hw cqp should be freed
579 *
580 * Issue destroy cqp request and
581 * free the resources associated with the cqp
582 */
irdma_destroy_cqp(struct irdma_pci_f * rf)583 static void irdma_destroy_cqp(struct irdma_pci_f *rf)
584 {
585 struct irdma_sc_dev *dev = &rf->sc_dev;
586 struct irdma_cqp *cqp = &rf->cqp;
587 int status = 0;
588
589 status = irdma_sc_cqp_destroy(dev->cqp);
590 if (status)
591 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status);
592
593 irdma_cleanup_pending_cqp_op(rf);
594 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va,
595 cqp->sq.pa);
596 cqp->sq.va = NULL;
597 kfree(cqp->scratch_array);
598 cqp->scratch_array = NULL;
599 kfree(cqp->cqp_requests);
600 cqp->cqp_requests = NULL;
601 }
602
irdma_destroy_virt_aeq(struct irdma_pci_f * rf)603 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf)
604 {
605 struct irdma_aeq *aeq = &rf->aeq;
606 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
607 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
608
609 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt);
610 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
611 vfree(aeq->mem.va);
612 }
613
614 /**
615 * irdma_destroy_aeq - destroy aeq
616 * @rf: RDMA PCI function
617 *
618 * Issue a destroy aeq request and
619 * free the resources associated with the aeq
620 * The function is called during driver unload
621 */
irdma_destroy_aeq(struct irdma_pci_f * rf)622 static void irdma_destroy_aeq(struct irdma_pci_f *rf)
623 {
624 struct irdma_sc_dev *dev = &rf->sc_dev;
625 struct irdma_aeq *aeq = &rf->aeq;
626 int status = -EBUSY;
627
628 if (!rf->msix_shared) {
629 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false);
630 irdma_destroy_irq(rf, rf->iw_msixtbl, rf);
631 }
632 if (rf->reset)
633 goto exit;
634
635 aeq->sc_aeq.size = 0;
636 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY);
637 if (status)
638 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status);
639
640 exit:
641 if (aeq->virtual_map) {
642 irdma_destroy_virt_aeq(rf);
643 } else {
644 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
645 aeq->mem.pa);
646 aeq->mem.va = NULL;
647 }
648 }
649
650 /**
651 * irdma_destroy_ceq - destroy ceq
652 * @rf: RDMA PCI function
653 * @iwceq: ceq to be destroyed
654 *
655 * Issue a destroy ceq request and
656 * free the resources associated with the ceq
657 */
irdma_destroy_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq)658 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
659 {
660 struct irdma_sc_dev *dev = &rf->sc_dev;
661 int status;
662
663 if (rf->reset)
664 goto exit;
665
666 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1);
667 if (status) {
668 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status);
669 goto exit;
670 }
671
672 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq);
673 if (status)
674 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n",
675 status);
676 exit:
677 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va,
678 iwceq->mem.pa);
679 iwceq->mem.va = NULL;
680 }
681
682 /**
683 * irdma_del_ceq_0 - destroy ceq 0
684 * @rf: RDMA PCI function
685 *
686 * Disable the ceq 0 interrupt and destroy the ceq 0
687 */
irdma_del_ceq_0(struct irdma_pci_f * rf)688 static void irdma_del_ceq_0(struct irdma_pci_f *rf)
689 {
690 struct irdma_ceq *iwceq = rf->ceqlist;
691 struct irdma_msix_vector *msix_vec;
692
693 if (rf->msix_shared) {
694 msix_vec = &rf->iw_msixtbl[0];
695 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
696 msix_vec->ceq_id,
697 msix_vec->idx, false);
698 irdma_destroy_irq(rf, msix_vec, rf);
699 } else {
700 msix_vec = &rf->iw_msixtbl[1];
701 irdma_destroy_irq(rf, msix_vec, iwceq);
702 }
703
704 irdma_destroy_ceq(rf, iwceq);
705 rf->sc_dev.ceq_valid = false;
706 rf->ceqs_count = 0;
707 }
708
709 /**
710 * irdma_del_ceqs - destroy all ceq's except CEQ 0
711 * @rf: RDMA PCI function
712 *
713 * Go through all of the device ceq's, except 0, and for each
714 * ceq disable the ceq interrupt and destroy the ceq
715 */
irdma_del_ceqs(struct irdma_pci_f * rf)716 static void irdma_del_ceqs(struct irdma_pci_f *rf)
717 {
718 struct irdma_ceq *iwceq = &rf->ceqlist[1];
719 struct irdma_msix_vector *msix_vec;
720 u32 i = 0;
721
722 if (rf->msix_shared)
723 msix_vec = &rf->iw_msixtbl[1];
724 else
725 msix_vec = &rf->iw_msixtbl[2];
726
727 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) {
728 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id,
729 msix_vec->idx, false);
730 irdma_destroy_irq(rf, msix_vec, iwceq);
731 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
732 IRDMA_OP_CEQ_DESTROY);
733 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size,
734 iwceq->mem.va, iwceq->mem.pa);
735 iwceq->mem.va = NULL;
736 }
737 rf->ceqs_count = 1;
738 }
739
740 /**
741 * irdma_destroy_ccq - destroy control cq
742 * @rf: RDMA PCI function
743 *
744 * Issue destroy ccq request and
745 * free the resources associated with the ccq
746 */
irdma_destroy_ccq(struct irdma_pci_f * rf)747 static void irdma_destroy_ccq(struct irdma_pci_f *rf)
748 {
749 struct irdma_sc_dev *dev = &rf->sc_dev;
750 struct irdma_ccq *ccq = &rf->ccq;
751 int status = 0;
752
753 if (rf->cqp_cmpl_wq)
754 destroy_workqueue(rf->cqp_cmpl_wq);
755
756 if (!rf->reset)
757 status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
758 if (status)
759 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status);
760 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va,
761 ccq->mem_cq.pa);
762 ccq->mem_cq.va = NULL;
763 }
764
765 /**
766 * irdma_close_hmc_objects_type - delete hmc objects of a given type
767 * @dev: iwarp device
768 * @obj_type: the hmc object type to be deleted
769 * @hmc_info: host memory info struct
770 * @privileged: permission to close HMC objects
771 * @reset: true if called before reset
772 */
irdma_close_hmc_objects_type(struct irdma_sc_dev * dev,enum irdma_hmc_rsrc_type obj_type,struct irdma_hmc_info * hmc_info,bool privileged,bool reset)773 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev,
774 enum irdma_hmc_rsrc_type obj_type,
775 struct irdma_hmc_info *hmc_info,
776 bool privileged, bool reset)
777 {
778 struct irdma_hmc_del_obj_info info = {};
779
780 info.hmc_info = hmc_info;
781 info.rsrc_type = obj_type;
782 info.count = hmc_info->hmc_obj[obj_type].cnt;
783 info.privileged = privileged;
784 if (irdma_sc_del_hmc_obj(dev, &info, reset))
785 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n",
786 obj_type);
787 }
788
789 /**
790 * irdma_del_hmc_objects - remove all device hmc objects
791 * @dev: iwarp device
792 * @hmc_info: hmc_info to free
793 * @privileged: permission to delete HMC objects
794 * @reset: true if called before reset
795 * @vers: hardware version
796 */
irdma_del_hmc_objects(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,bool privileged,bool reset,enum irdma_vers vers)797 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev,
798 struct irdma_hmc_info *hmc_info, bool privileged,
799 bool reset, enum irdma_vers vers)
800 {
801 unsigned int i;
802
803 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
804 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
805 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
806 hmc_info, privileged, reset);
807 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
808 break;
809 }
810 }
811
812 /**
813 * irdma_create_hmc_obj_type - create hmc object of a given type
814 * @dev: hardware control device structure
815 * @info: information for the hmc object to create
816 */
irdma_create_hmc_obj_type(struct irdma_sc_dev * dev,struct irdma_hmc_create_obj_info * info)817 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
818 struct irdma_hmc_create_obj_info *info)
819 {
820 return irdma_sc_create_hmc_obj(dev, info);
821 }
822
823 /**
824 * irdma_create_hmc_objs - create all hmc objects for the device
825 * @rf: RDMA PCI function
826 * @privileged: permission to create HMC objects
827 * @vers: HW version
828 *
829 * Create the device hmc objects and allocate hmc pages
830 * Return 0 if successful, otherwise clean up and return error
831 */
irdma_create_hmc_objs(struct irdma_pci_f * rf,bool privileged,enum irdma_vers vers)832 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
833 enum irdma_vers vers)
834 {
835 struct irdma_sc_dev *dev = &rf->sc_dev;
836 struct irdma_hmc_create_obj_info info = {};
837 int i, status = 0;
838
839 info.hmc_info = dev->hmc_info;
840 info.privileged = privileged;
841 info.entry_type = rf->sd_type;
842
843 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
844 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE)
845 continue;
846 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) {
847 info.rsrc_type = iw_hmc_obj_types[i];
848 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
849 info.add_sd_cnt = 0;
850 status = irdma_create_hmc_obj_type(dev, &info);
851 if (status) {
852 ibdev_dbg(to_ibdev(dev),
853 "ERR: create obj type %d status = %d\n",
854 iw_hmc_obj_types[i], status);
855 break;
856 }
857 }
858 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
859 break;
860 }
861
862 if (!status)
863 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id,
864 true, true);
865
866 while (i) {
867 i--;
868 /* destroy the hmc objects of a given type */
869 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
870 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
871 dev->hmc_info, privileged,
872 false);
873 }
874
875 return status;
876 }
877
878 /**
879 * irdma_obj_aligned_mem - get aligned memory from device allocated memory
880 * @rf: RDMA PCI function
881 * @memptr: points to the memory addresses
882 * @size: size of memory needed
883 * @mask: mask for the aligned memory
884 *
885 * Get aligned memory of the requested size and
886 * update the memptr to point to the new aligned memory
887 * Return 0 if successful, otherwise return no memory error
888 */
irdma_obj_aligned_mem(struct irdma_pci_f * rf,struct irdma_dma_mem * memptr,u32 size,u32 mask)889 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf,
890 struct irdma_dma_mem *memptr, u32 size,
891 u32 mask)
892 {
893 unsigned long va, newva;
894 unsigned long extra;
895
896 va = (unsigned long)rf->obj_next.va;
897 newva = va;
898 if (mask)
899 newva = ALIGN(va, (unsigned long)mask + 1ULL);
900 extra = newva - va;
901 memptr->va = (u8 *)va + extra;
902 memptr->pa = rf->obj_next.pa + extra;
903 memptr->size = size;
904 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
905 return -ENOMEM;
906
907 rf->obj_next.va = (u8 *)memptr->va + size;
908 rf->obj_next.pa = memptr->pa + size;
909
910 return 0;
911 }
912
913 /**
914 * irdma_create_cqp - create control qp
915 * @rf: RDMA PCI function
916 *
917 * Return 0, if the cqp and all the resources associated with it
918 * are successfully created, otherwise return error
919 */
irdma_create_cqp(struct irdma_pci_f * rf)920 static int irdma_create_cqp(struct irdma_pci_f *rf)
921 {
922 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
923 struct irdma_dma_mem mem;
924 struct irdma_sc_dev *dev = &rf->sc_dev;
925 struct irdma_cqp_init_info cqp_init_info = {};
926 struct irdma_cqp *cqp = &rf->cqp;
927 u16 maj_err, min_err;
928 int i, status;
929
930 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
931 if (!cqp->cqp_requests)
932 return -ENOMEM;
933
934 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
935 if (!cqp->scratch_array) {
936 status = -ENOMEM;
937 goto err_scratch;
938 }
939
940 dev->cqp = &cqp->sc_cqp;
941 dev->cqp->dev = dev;
942 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize,
943 IRDMA_CQP_ALIGNMENT);
944 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size,
945 &cqp->sq.pa, GFP_KERNEL);
946 if (!cqp->sq.va) {
947 status = -ENOMEM;
948 goto err_sq;
949 }
950
951 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
952 IRDMA_HOST_CTX_ALIGNMENT_M);
953 if (status)
954 goto err_ctx;
955
956 dev->cqp->host_ctx_pa = mem.pa;
957 dev->cqp->host_ctx = mem.va;
958 /* populate the cqp init info */
959 cqp_init_info.dev = dev;
960 cqp_init_info.sq_size = sqsize;
961 cqp_init_info.sq = cqp->sq.va;
962 cqp_init_info.sq_pa = cqp->sq.pa;
963 cqp_init_info.host_ctx_pa = mem.pa;
964 cqp_init_info.host_ctx = mem.va;
965 cqp_init_info.hmc_profile = rf->rsrc_profile;
966 cqp_init_info.scratch_array = cqp->scratch_array;
967 cqp_init_info.protocol_used = rf->protocol_used;
968
969 switch (rf->rdma_ver) {
970 case IRDMA_GEN_1:
971 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1;
972 break;
973 case IRDMA_GEN_2:
974 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
975 break;
976 }
977 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info);
978 if (status) {
979 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status);
980 goto err_ctx;
981 }
982
983 spin_lock_init(&cqp->req_lock);
984 spin_lock_init(&cqp->compl_lock);
985
986 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err);
987 if (status) {
988 ibdev_dbg(to_ibdev(dev),
989 "ERR: cqp create failed - status %d maj_err %d min_err %d\n",
990 status, maj_err, min_err);
991 goto err_ctx;
992 }
993
994 INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
995 INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
996
997 /* init the waitqueue of the cqp_requests and add them to the list */
998 for (i = 0; i < sqsize; i++) {
999 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
1000 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
1001 }
1002 init_waitqueue_head(&cqp->remove_wq);
1003 return 0;
1004
1005 err_ctx:
1006 dma_free_coherent(dev->hw->device, cqp->sq.size,
1007 cqp->sq.va, cqp->sq.pa);
1008 cqp->sq.va = NULL;
1009 err_sq:
1010 kfree(cqp->scratch_array);
1011 cqp->scratch_array = NULL;
1012 err_scratch:
1013 kfree(cqp->cqp_requests);
1014 cqp->cqp_requests = NULL;
1015
1016 return status;
1017 }
1018
1019 /**
1020 * irdma_create_ccq - create control cq
1021 * @rf: RDMA PCI function
1022 *
1023 * Return 0, if the ccq and the resources associated with it
1024 * are successfully created, otherwise return error
1025 */
irdma_create_ccq(struct irdma_pci_f * rf)1026 static int irdma_create_ccq(struct irdma_pci_f *rf)
1027 {
1028 struct irdma_sc_dev *dev = &rf->sc_dev;
1029 struct irdma_ccq_init_info info = {};
1030 struct irdma_ccq *ccq = &rf->ccq;
1031 int status;
1032
1033 dev->ccq = &ccq->sc_cq;
1034 dev->ccq->dev = dev;
1035 info.dev = dev;
1036 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area);
1037 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE,
1038 IRDMA_CQ0_ALIGNMENT);
1039 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size,
1040 &ccq->mem_cq.pa, GFP_KERNEL);
1041 if (!ccq->mem_cq.va)
1042 return -ENOMEM;
1043
1044 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
1045 ccq->shadow_area.size,
1046 IRDMA_SHADOWAREA_M);
1047 if (status)
1048 goto exit;
1049
1050 ccq->sc_cq.back_cq = ccq;
1051 /* populate the ccq init info */
1052 info.cq_base = ccq->mem_cq.va;
1053 info.cq_pa = ccq->mem_cq.pa;
1054 info.num_elem = IW_CCQ_SIZE;
1055 info.shadow_area = ccq->shadow_area.va;
1056 info.shadow_area_pa = ccq->shadow_area.pa;
1057 info.ceqe_mask = false;
1058 info.ceq_id_valid = true;
1059 info.shadow_read_threshold = 16;
1060 info.vsi = &rf->default_vsi;
1061 status = irdma_sc_ccq_init(dev->ccq, &info);
1062 if (!status)
1063 status = irdma_sc_ccq_create(dev->ccq, 0, true, true);
1064 exit:
1065 if (status) {
1066 dma_free_coherent(dev->hw->device, ccq->mem_cq.size,
1067 ccq->mem_cq.va, ccq->mem_cq.pa);
1068 ccq->mem_cq.va = NULL;
1069 }
1070
1071 return status;
1072 }
1073
1074 /**
1075 * irdma_alloc_set_mac - set up a mac address table entry
1076 * @iwdev: irdma device
1077 *
1078 * Allocate a mac ip entry and add it to the hw table Return 0
1079 * if successful, otherwise return error
1080 */
irdma_alloc_set_mac(struct irdma_device * iwdev)1081 static int irdma_alloc_set_mac(struct irdma_device *iwdev)
1082 {
1083 int status;
1084
1085 status = irdma_alloc_local_mac_entry(iwdev->rf,
1086 &iwdev->mac_ip_table_idx);
1087 if (!status) {
1088 status = irdma_add_local_mac_entry(iwdev->rf,
1089 (const u8 *)iwdev->netdev->dev_addr,
1090 (u8)iwdev->mac_ip_table_idx);
1091 if (status)
1092 irdma_del_local_mac_entry(iwdev->rf,
1093 (u8)iwdev->mac_ip_table_idx);
1094 }
1095 return status;
1096 }
1097
1098 /**
1099 * irdma_cfg_ceq_vector - set up the msix interrupt vector for
1100 * ceq
1101 * @rf: RDMA PCI function
1102 * @iwceq: ceq associated with the vector
1103 * @ceq_id: the id number of the iwceq
1104 * @msix_vec: interrupt vector information
1105 *
1106 * Allocate interrupt resources and enable irq handling
1107 * Return 0 if successful, otherwise return error
1108 */
irdma_cfg_ceq_vector(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u32 ceq_id,struct irdma_msix_vector * msix_vec)1109 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1110 u32 ceq_id, struct irdma_msix_vector *msix_vec)
1111 {
1112 int status;
1113
1114 if (rf->msix_shared && !ceq_id) {
1115 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1116 status = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1117 "AEQCEQ", rf);
1118 } else {
1119 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc);
1120
1121 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0,
1122 "CEQ", iwceq);
1123 }
1124 cpumask_clear(&msix_vec->mask);
1125 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask);
1126 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask);
1127 if (status) {
1128 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n");
1129 return status;
1130 }
1131
1132 msix_vec->ceq_id = ceq_id;
1133 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true);
1134
1135 return 0;
1136 }
1137
1138 /**
1139 * irdma_cfg_aeq_vector - set up the msix vector for aeq
1140 * @rf: RDMA PCI function
1141 *
1142 * Allocate interrupt resources and enable irq handling
1143 * Return 0 if successful, otherwise return error
1144 */
irdma_cfg_aeq_vector(struct irdma_pci_f * rf)1145 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
1146 {
1147 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
1148 u32 ret = 0;
1149
1150 if (!rf->msix_shared) {
1151 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1152 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1153 "irdma", rf);
1154 }
1155 if (ret) {
1156 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n");
1157 return -EINVAL;
1158 }
1159
1160 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true);
1161
1162 return 0;
1163 }
1164
1165 /**
1166 * irdma_create_ceq - create completion event queue
1167 * @rf: RDMA PCI function
1168 * @iwceq: pointer to the ceq resources to be created
1169 * @ceq_id: the id number of the iwceq
1170 * @vsi: SC vsi struct
1171 *
1172 * Return 0, if the ceq and the resources associated with it
1173 * are successfully created, otherwise return error
1174 */
irdma_create_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u32 ceq_id,struct irdma_sc_vsi * vsi)1175 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1176 u32 ceq_id, struct irdma_sc_vsi *vsi)
1177 {
1178 int status;
1179 struct irdma_ceq_init_info info = {};
1180 struct irdma_sc_dev *dev = &rf->sc_dev;
1181 u32 ceq_size;
1182
1183 info.ceq_id = ceq_id;
1184 iwceq->rf = rf;
1185 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
1186 dev->hw_attrs.max_hw_ceq_size);
1187 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size,
1188 IRDMA_CEQ_ALIGNMENT);
1189 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size,
1190 &iwceq->mem.pa, GFP_KERNEL);
1191 if (!iwceq->mem.va)
1192 return -ENOMEM;
1193
1194 info.ceq_id = ceq_id;
1195 info.ceqe_base = iwceq->mem.va;
1196 info.ceqe_pa = iwceq->mem.pa;
1197 info.elem_cnt = ceq_size;
1198 iwceq->sc_ceq.ceq_id = ceq_id;
1199 info.dev = dev;
1200 info.vsi = vsi;
1201 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info);
1202 if (!status) {
1203 if (dev->ceq_valid)
1204 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
1205 IRDMA_OP_CEQ_CREATE);
1206 else
1207 status = irdma_sc_cceq_create(&iwceq->sc_ceq, 0);
1208 }
1209
1210 if (status) {
1211 dma_free_coherent(dev->hw->device, iwceq->mem.size,
1212 iwceq->mem.va, iwceq->mem.pa);
1213 iwceq->mem.va = NULL;
1214 }
1215
1216 return status;
1217 }
1218
1219 /**
1220 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource
1221 * @rf: RDMA PCI function
1222 *
1223 * Allocate a list for all device completion event queues
1224 * Create the ceq 0 and configure it's msix interrupt vector
1225 * Return 0, if successfully set up, otherwise return error
1226 */
irdma_setup_ceq_0(struct irdma_pci_f * rf)1227 static int irdma_setup_ceq_0(struct irdma_pci_f *rf)
1228 {
1229 struct irdma_ceq *iwceq;
1230 struct irdma_msix_vector *msix_vec;
1231 u32 i;
1232 int status = 0;
1233 u32 num_ceqs;
1234
1235 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1236 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL);
1237 if (!rf->ceqlist) {
1238 status = -ENOMEM;
1239 goto exit;
1240 }
1241
1242 iwceq = &rf->ceqlist[0];
1243 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi);
1244 if (status) {
1245 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n",
1246 status);
1247 goto exit;
1248 }
1249
1250 spin_lock_init(&iwceq->ce_lock);
1251 i = rf->msix_shared ? 0 : 1;
1252 msix_vec = &rf->iw_msixtbl[i];
1253 iwceq->irq = msix_vec->irq;
1254 iwceq->msix_idx = msix_vec->idx;
1255 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec);
1256 if (status) {
1257 irdma_destroy_ceq(rf, iwceq);
1258 goto exit;
1259 }
1260
1261 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1262 rf->ceqs_count++;
1263
1264 exit:
1265 if (status && !rf->ceqs_count) {
1266 kfree(rf->ceqlist);
1267 rf->ceqlist = NULL;
1268 return status;
1269 }
1270 rf->sc_dev.ceq_valid = true;
1271
1272 return 0;
1273 }
1274
1275 /**
1276 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources
1277 * @rf: RDMA PCI function
1278 * @vsi: VSI structure for this CEQ
1279 *
1280 * Allocate a list for all device completion event queues
1281 * Create the ceq's and configure their msix interrupt vectors
1282 * Return 0, if ceqs are successfully set up, otherwise return error
1283 */
irdma_setup_ceqs(struct irdma_pci_f * rf,struct irdma_sc_vsi * vsi)1284 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi)
1285 {
1286 u32 i;
1287 u32 ceq_id;
1288 struct irdma_ceq *iwceq;
1289 struct irdma_msix_vector *msix_vec;
1290 int status;
1291 u32 num_ceqs;
1292
1293 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1294 i = (rf->msix_shared) ? 1 : 2;
1295 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) {
1296 iwceq = &rf->ceqlist[ceq_id];
1297 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi);
1298 if (status) {
1299 ibdev_dbg(&rf->iwdev->ibdev,
1300 "ERR: create ceq status = %d\n", status);
1301 goto del_ceqs;
1302 }
1303 spin_lock_init(&iwceq->ce_lock);
1304 msix_vec = &rf->iw_msixtbl[i];
1305 iwceq->irq = msix_vec->irq;
1306 iwceq->msix_idx = msix_vec->idx;
1307 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec);
1308 if (status) {
1309 irdma_destroy_ceq(rf, iwceq);
1310 goto del_ceqs;
1311 }
1312 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1313 rf->ceqs_count++;
1314 }
1315
1316 return 0;
1317
1318 del_ceqs:
1319 irdma_del_ceqs(rf);
1320
1321 return status;
1322 }
1323
irdma_create_virt_aeq(struct irdma_pci_f * rf,u32 size)1324 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
1325 {
1326 struct irdma_aeq *aeq = &rf->aeq;
1327 dma_addr_t *pg_arr;
1328 u32 pg_cnt;
1329 int status;
1330
1331 if (rf->rdma_ver < IRDMA_GEN_2)
1332 return -EOPNOTSUPP;
1333
1334 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
1335 aeq->mem.va = vzalloc(aeq->mem.size);
1336
1337 if (!aeq->mem.va)
1338 return -ENOMEM;
1339
1340 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
1341 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
1342 if (status) {
1343 vfree(aeq->mem.va);
1344 return status;
1345 }
1346
1347 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
1348 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt);
1349 if (status) {
1350 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
1351 vfree(aeq->mem.va);
1352 return status;
1353 }
1354
1355 return 0;
1356 }
1357
1358 /**
1359 * irdma_create_aeq - create async event queue
1360 * @rf: RDMA PCI function
1361 *
1362 * Return 0, if the aeq and the resources associated with it
1363 * are successfully created, otherwise return error
1364 */
irdma_create_aeq(struct irdma_pci_f * rf)1365 static int irdma_create_aeq(struct irdma_pci_f *rf)
1366 {
1367 struct irdma_aeq_init_info info = {};
1368 struct irdma_sc_dev *dev = &rf->sc_dev;
1369 struct irdma_aeq *aeq = &rf->aeq;
1370 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
1371 u32 aeq_size;
1372 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
1373 int status;
1374
1375 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
1376 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1377 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
1378
1379 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size,
1380 IRDMA_AEQ_ALIGNMENT);
1381 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size,
1382 &aeq->mem.pa,
1383 GFP_KERNEL | __GFP_NOWARN);
1384 if (aeq->mem.va)
1385 goto skip_virt_aeq;
1386
1387 /* physically mapped aeq failed. setup virtual aeq */
1388 status = irdma_create_virt_aeq(rf, aeq_size);
1389 if (status)
1390 return status;
1391
1392 info.virtual_map = true;
1393 aeq->virtual_map = info.virtual_map;
1394 info.pbl_chunk_size = 1;
1395 info.first_pm_pbl_idx = aeq->palloc.level1.idx;
1396
1397 skip_virt_aeq:
1398 info.aeqe_base = aeq->mem.va;
1399 info.aeq_elem_pa = aeq->mem.pa;
1400 info.elem_cnt = aeq_size;
1401 info.dev = dev;
1402 info.msix_idx = rf->iw_msixtbl->idx;
1403 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info);
1404 if (status)
1405 goto err;
1406
1407 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE);
1408 if (status)
1409 goto err;
1410
1411 return 0;
1412
1413 err:
1414 if (aeq->virtual_map) {
1415 irdma_destroy_virt_aeq(rf);
1416 } else {
1417 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
1418 aeq->mem.pa);
1419 aeq->mem.va = NULL;
1420 }
1421
1422 return status;
1423 }
1424
1425 /**
1426 * irdma_setup_aeq - set up the device aeq
1427 * @rf: RDMA PCI function
1428 *
1429 * Create the aeq and configure its msix interrupt vector
1430 * Return 0 if successful, otherwise return error
1431 */
irdma_setup_aeq(struct irdma_pci_f * rf)1432 static int irdma_setup_aeq(struct irdma_pci_f *rf)
1433 {
1434 struct irdma_sc_dev *dev = &rf->sc_dev;
1435 int status;
1436
1437 status = irdma_create_aeq(rf);
1438 if (status)
1439 return status;
1440
1441 status = irdma_cfg_aeq_vector(rf);
1442 if (status) {
1443 irdma_destroy_aeq(rf);
1444 return status;
1445 }
1446
1447 if (!rf->msix_shared)
1448 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx);
1449
1450 return 0;
1451 }
1452
1453 /**
1454 * irdma_initialize_ilq - create iwarp local queue for cm
1455 * @iwdev: irdma device
1456 *
1457 * Return 0 if successful, otherwise return error
1458 */
irdma_initialize_ilq(struct irdma_device * iwdev)1459 static int irdma_initialize_ilq(struct irdma_device *iwdev)
1460 {
1461 struct irdma_puda_rsrc_info info = {};
1462 int status;
1463
1464 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
1465 info.cq_id = 1;
1466 info.qp_id = 1;
1467 info.count = 1;
1468 info.pd_id = 1;
1469 info.abi_ver = IRDMA_ABI_VER;
1470 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1471 info.rq_size = info.sq_size;
1472 info.buf_size = 1024;
1473 info.tx_buf_cnt = 2 * info.sq_size;
1474 info.receive = irdma_receive_ilq;
1475 info.xmit_complete = irdma_free_sqbuf;
1476 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1477 if (status)
1478 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n");
1479
1480 return status;
1481 }
1482
1483 /**
1484 * irdma_initialize_ieq - create iwarp exception queue
1485 * @iwdev: irdma device
1486 *
1487 * Return 0 if successful, otherwise return error
1488 */
irdma_initialize_ieq(struct irdma_device * iwdev)1489 static int irdma_initialize_ieq(struct irdma_device *iwdev)
1490 {
1491 struct irdma_puda_rsrc_info info = {};
1492 int status;
1493
1494 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
1495 info.cq_id = 2;
1496 info.qp_id = iwdev->vsi.exception_lan_q;
1497 info.count = 1;
1498 info.pd_id = 2;
1499 info.abi_ver = IRDMA_ABI_VER;
1500 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1501 info.rq_size = info.sq_size;
1502 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD;
1503 info.tx_buf_cnt = 4096;
1504 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1505 if (status)
1506 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n");
1507
1508 return status;
1509 }
1510
1511 /**
1512 * irdma_reinitialize_ieq - destroy and re-create ieq
1513 * @vsi: VSI structure
1514 */
irdma_reinitialize_ieq(struct irdma_sc_vsi * vsi)1515 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi)
1516 {
1517 struct irdma_device *iwdev = vsi->back_vsi;
1518 struct irdma_pci_f *rf = iwdev->rf;
1519
1520 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false);
1521 if (irdma_initialize_ieq(iwdev)) {
1522 iwdev->rf->reset = true;
1523 rf->gen_ops.request_reset(rf);
1524 }
1525 }
1526
1527 /**
1528 * irdma_hmc_setup - create hmc objects for the device
1529 * @rf: RDMA PCI function
1530 *
1531 * Set up the device private memory space for the number and size of
1532 * the hmc objects and create the objects
1533 * Return 0 if successful, otherwise return error
1534 */
irdma_hmc_setup(struct irdma_pci_f * rf)1535 static int irdma_hmc_setup(struct irdma_pci_f *rf)
1536 {
1537 int status;
1538 u32 qpcnt;
1539
1540 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit;
1541
1542 rf->sd_type = IRDMA_SD_TYPE_DIRECT;
1543 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt);
1544 if (status)
1545 return status;
1546
1547 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver);
1548
1549 return status;
1550 }
1551
1552 /**
1553 * irdma_del_init_mem - deallocate memory resources
1554 * @rf: RDMA PCI function
1555 */
irdma_del_init_mem(struct irdma_pci_f * rf)1556 static void irdma_del_init_mem(struct irdma_pci_f *rf)
1557 {
1558 struct irdma_sc_dev *dev = &rf->sc_dev;
1559
1560 kfree(dev->hmc_info->sd_table.sd_entry);
1561 dev->hmc_info->sd_table.sd_entry = NULL;
1562 kfree(rf->mem_rsrc);
1563 rf->mem_rsrc = NULL;
1564 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1565 rf->obj_mem.pa);
1566 rf->obj_mem.va = NULL;
1567 if (rf->rdma_ver != IRDMA_GEN_1) {
1568 bitmap_free(rf->allocated_ws_nodes);
1569 rf->allocated_ws_nodes = NULL;
1570 }
1571 kfree(rf->ceqlist);
1572 rf->ceqlist = NULL;
1573 kfree(rf->iw_msixtbl);
1574 rf->iw_msixtbl = NULL;
1575 kfree(rf->hmc_info_mem);
1576 rf->hmc_info_mem = NULL;
1577 }
1578
1579 /**
1580 * irdma_initialize_dev - initialize device
1581 * @rf: RDMA PCI function
1582 *
1583 * Allocate memory for the hmc objects and initialize iwdev
1584 * Return 0 if successful, otherwise clean up the resources
1585 * and return error
1586 */
irdma_initialize_dev(struct irdma_pci_f * rf)1587 static int irdma_initialize_dev(struct irdma_pci_f *rf)
1588 {
1589 int status;
1590 struct irdma_sc_dev *dev = &rf->sc_dev;
1591 struct irdma_device_init_info info = {};
1592 struct irdma_dma_mem mem;
1593 u32 size;
1594
1595 size = sizeof(struct irdma_hmc_pble_rsrc) +
1596 sizeof(struct irdma_hmc_info) +
1597 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX);
1598
1599 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1600 if (!rf->hmc_info_mem)
1601 return -ENOMEM;
1602
1603 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
1604 dev->hmc_info = &rf->hw.hmc;
1605 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *)
1606 (rf->pble_rsrc + 1);
1607
1608 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE,
1609 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M);
1610 if (status)
1611 goto error;
1612
1613 info.fpm_query_buf_pa = mem.pa;
1614 info.fpm_query_buf = mem.va;
1615
1616 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE,
1617 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M);
1618 if (status)
1619 goto error;
1620
1621 info.fpm_commit_buf_pa = mem.pa;
1622 info.fpm_commit_buf = mem.va;
1623
1624 info.bar0 = rf->hw.hw_addr;
1625 info.hmc_fn_id = rf->pf_id;
1626 info.hw = &rf->hw;
1627 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info);
1628 if (status)
1629 goto error;
1630
1631 return status;
1632 error:
1633 kfree(rf->hmc_info_mem);
1634 rf->hmc_info_mem = NULL;
1635
1636 return status;
1637 }
1638
1639 /**
1640 * irdma_rt_deinit_hw - clean up the irdma device resources
1641 * @iwdev: irdma device
1642 *
1643 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the
1644 * device queues and free the pble and the hmc objects
1645 */
irdma_rt_deinit_hw(struct irdma_device * iwdev)1646 void irdma_rt_deinit_hw(struct irdma_device *iwdev)
1647 {
1648 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state);
1649
1650 switch (iwdev->init_state) {
1651 case IP_ADDR_REGISTERED:
1652 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1653 irdma_del_local_mac_entry(iwdev->rf,
1654 (u8)iwdev->mac_ip_table_idx);
1655 fallthrough;
1656 case AEQ_CREATED:
1657 case PBLE_CHUNK_MEM:
1658 case CEQS_CREATED:
1659 case IEQ_CREATED:
1660 if (!iwdev->roce_mode)
1661 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ,
1662 iwdev->rf->reset);
1663 fallthrough;
1664 case ILQ_CREATED:
1665 if (!iwdev->roce_mode)
1666 irdma_puda_dele_rsrc(&iwdev->vsi,
1667 IRDMA_PUDA_RSRC_TYPE_ILQ,
1668 iwdev->rf->reset);
1669 break;
1670 default:
1671 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state);
1672 break;
1673 }
1674
1675 irdma_cleanup_cm_core(&iwdev->cm_core);
1676 if (iwdev->vsi.pestat) {
1677 irdma_vsi_stats_free(&iwdev->vsi);
1678 kfree(iwdev->vsi.pestat);
1679 }
1680 if (iwdev->cleanup_wq)
1681 destroy_workqueue(iwdev->cleanup_wq);
1682 }
1683
irdma_setup_init_state(struct irdma_pci_f * rf)1684 static int irdma_setup_init_state(struct irdma_pci_f *rf)
1685 {
1686 int status;
1687
1688 status = irdma_save_msix_info(rf);
1689 if (status)
1690 return status;
1691
1692 rf->hw.device = &rf->pcidev->dev;
1693 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE);
1694 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size,
1695 &rf->obj_mem.pa, GFP_KERNEL);
1696 if (!rf->obj_mem.va) {
1697 status = -ENOMEM;
1698 goto clean_msixtbl;
1699 }
1700
1701 rf->obj_next = rf->obj_mem;
1702 status = irdma_initialize_dev(rf);
1703 if (status)
1704 goto clean_obj_mem;
1705
1706 return 0;
1707
1708 clean_obj_mem:
1709 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1710 rf->obj_mem.pa);
1711 rf->obj_mem.va = NULL;
1712 clean_msixtbl:
1713 kfree(rf->iw_msixtbl);
1714 rf->iw_msixtbl = NULL;
1715 return status;
1716 }
1717
1718 /**
1719 * irdma_get_used_rsrc - determine resources used internally
1720 * @iwdev: irdma device
1721 *
1722 * Called at the end of open to get all internal allocations
1723 */
irdma_get_used_rsrc(struct irdma_device * iwdev)1724 static void irdma_get_used_rsrc(struct irdma_device *iwdev)
1725 {
1726 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds,
1727 iwdev->rf->max_pd);
1728 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps,
1729 iwdev->rf->max_qp);
1730 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,
1731 iwdev->rf->max_cq);
1732 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,
1733 iwdev->rf->max_mr);
1734 }
1735
irdma_ctrl_deinit_hw(struct irdma_pci_f * rf)1736 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf)
1737 {
1738 enum init_completion_state state = rf->init_state;
1739
1740 rf->init_state = INVALID_STATE;
1741 if (rf->rsrc_created) {
1742 irdma_destroy_aeq(rf);
1743 irdma_destroy_pble_prm(rf->pble_rsrc);
1744 irdma_del_ceqs(rf);
1745 rf->rsrc_created = false;
1746 }
1747 switch (state) {
1748 case CEQ0_CREATED:
1749 irdma_del_ceq_0(rf);
1750 fallthrough;
1751 case CCQ_CREATED:
1752 irdma_destroy_ccq(rf);
1753 fallthrough;
1754 case HW_RSRC_INITIALIZED:
1755 case HMC_OBJS_CREATED:
1756 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true,
1757 rf->reset, rf->rdma_ver);
1758 fallthrough;
1759 case CQP_CREATED:
1760 irdma_destroy_cqp(rf);
1761 fallthrough;
1762 case INITIAL_STATE:
1763 irdma_del_init_mem(rf);
1764 break;
1765 case INVALID_STATE:
1766 default:
1767 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state);
1768 break;
1769 }
1770 }
1771
1772 /**
1773 * irdma_rt_init_hw - Initializes runtime portion of HW
1774 * @iwdev: irdma device
1775 * @l2params: qos, tc, mtu info from netdev driver
1776 *
1777 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
1778 * device resource objects.
1779 */
irdma_rt_init_hw(struct irdma_device * iwdev,struct irdma_l2params * l2params)1780 int irdma_rt_init_hw(struct irdma_device *iwdev,
1781 struct irdma_l2params *l2params)
1782 {
1783 struct irdma_pci_f *rf = iwdev->rf;
1784 struct irdma_sc_dev *dev = &rf->sc_dev;
1785 struct irdma_vsi_init_info vsi_info = {};
1786 struct irdma_vsi_stats_info stats_info = {};
1787 int status;
1788
1789 vsi_info.dev = dev;
1790 vsi_info.back_vsi = iwdev;
1791 vsi_info.params = l2params;
1792 vsi_info.pf_data_vsi_num = iwdev->vsi_num;
1793 vsi_info.register_qset = rf->gen_ops.register_qset;
1794 vsi_info.unregister_qset = rf->gen_ops.unregister_qset;
1795 vsi_info.exception_lan_q = 2;
1796 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info);
1797
1798 status = irdma_setup_cm_core(iwdev, rf->rdma_ver);
1799 if (status)
1800 return status;
1801
1802 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1803 if (!stats_info.pestat) {
1804 irdma_cleanup_cm_core(&iwdev->cm_core);
1805 return -ENOMEM;
1806 }
1807 stats_info.fcn_id = dev->hmc_fn_id;
1808 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
1809 if (status) {
1810 irdma_cleanup_cm_core(&iwdev->cm_core);
1811 kfree(stats_info.pestat);
1812 return status;
1813 }
1814
1815 do {
1816 if (!iwdev->roce_mode) {
1817 status = irdma_initialize_ilq(iwdev);
1818 if (status)
1819 break;
1820 iwdev->init_state = ILQ_CREATED;
1821 status = irdma_initialize_ieq(iwdev);
1822 if (status)
1823 break;
1824 iwdev->init_state = IEQ_CREATED;
1825 }
1826 if (!rf->rsrc_created) {
1827 status = irdma_setup_ceqs(rf, &iwdev->vsi);
1828 if (status)
1829 break;
1830
1831 iwdev->init_state = CEQS_CREATED;
1832
1833 status = irdma_hmc_init_pble(&rf->sc_dev,
1834 rf->pble_rsrc);
1835 if (status) {
1836 irdma_del_ceqs(rf);
1837 break;
1838 }
1839
1840 iwdev->init_state = PBLE_CHUNK_MEM;
1841
1842 status = irdma_setup_aeq(rf);
1843 if (status) {
1844 irdma_destroy_pble_prm(rf->pble_rsrc);
1845 irdma_del_ceqs(rf);
1846 break;
1847 }
1848 iwdev->init_state = AEQ_CREATED;
1849 rf->rsrc_created = true;
1850 }
1851
1852 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1853 irdma_alloc_set_mac(iwdev);
1854 irdma_add_ip(iwdev);
1855 iwdev->init_state = IP_ADDR_REGISTERED;
1856
1857 /* handles asynch cleanup tasks - disconnect CM , free qp,
1858 * free cq bufs
1859 */
1860 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
1861 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
1862 if (!iwdev->cleanup_wq)
1863 return -ENOMEM;
1864 irdma_get_used_rsrc(iwdev);
1865 init_waitqueue_head(&iwdev->suspend_wq);
1866
1867 return 0;
1868 } while (0);
1869
1870 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n",
1871 status, iwdev->init_state);
1872 irdma_rt_deinit_hw(iwdev);
1873
1874 return status;
1875 }
1876
1877 /**
1878 * irdma_ctrl_init_hw - Initializes control portion of HW
1879 * @rf: RDMA PCI function
1880 *
1881 * Create admin queues, HMC obejcts and RF resource objects
1882 */
irdma_ctrl_init_hw(struct irdma_pci_f * rf)1883 int irdma_ctrl_init_hw(struct irdma_pci_f *rf)
1884 {
1885 struct irdma_sc_dev *dev = &rf->sc_dev;
1886 int status;
1887 do {
1888 status = irdma_setup_init_state(rf);
1889 if (status)
1890 break;
1891 rf->init_state = INITIAL_STATE;
1892
1893 status = irdma_create_cqp(rf);
1894 if (status)
1895 break;
1896 rf->init_state = CQP_CREATED;
1897
1898 status = irdma_hmc_setup(rf);
1899 if (status)
1900 break;
1901 rf->init_state = HMC_OBJS_CREATED;
1902
1903 status = irdma_initialize_hw_rsrc(rf);
1904 if (status)
1905 break;
1906 rf->init_state = HW_RSRC_INITIALIZED;
1907
1908 status = irdma_create_ccq(rf);
1909 if (status)
1910 break;
1911 rf->init_state = CCQ_CREATED;
1912
1913 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT;
1914 if (rf->rdma_ver != IRDMA_GEN_1) {
1915 status = irdma_get_rdma_features(dev);
1916 if (status)
1917 break;
1918 }
1919
1920 status = irdma_setup_ceq_0(rf);
1921 if (status)
1922 break;
1923 rf->init_state = CEQ0_CREATED;
1924 /* Handles processing of CQP completions */
1925 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq",
1926 WQ_HIGHPRI | WQ_UNBOUND);
1927 if (!rf->cqp_cmpl_wq) {
1928 status = -ENOMEM;
1929 break;
1930 }
1931 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
1932 irdma_sc_ccq_arm(dev->ccq);
1933 return 0;
1934 } while (0);
1935
1936 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n",
1937 rf->init_state, status);
1938 irdma_ctrl_deinit_hw(rf);
1939 return status;
1940 }
1941
1942 /**
1943 * irdma_set_hw_rsrc - set hw memory resources.
1944 * @rf: RDMA PCI function
1945 */
irdma_set_hw_rsrc(struct irdma_pci_f * rf)1946 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf)
1947 {
1948 rf->allocated_qps = (void *)(rf->mem_rsrc +
1949 (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
1950 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];
1951 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];
1952 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];
1953 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];
1954 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
1955 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)];
1956 rf->qp_table = (struct irdma_qp **)
1957 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]);
1958
1959 spin_lock_init(&rf->rsrc_lock);
1960 spin_lock_init(&rf->arp_lock);
1961 spin_lock_init(&rf->qptable_lock);
1962 spin_lock_init(&rf->qh_list_lock);
1963 }
1964
1965 /**
1966 * irdma_calc_mem_rsrc_size - calculate memory resources size.
1967 * @rf: RDMA PCI function
1968 */
irdma_calc_mem_rsrc_size(struct irdma_pci_f * rf)1969 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf)
1970 {
1971 u32 rsrc_size;
1972
1973 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size;
1974 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);
1975 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);
1976 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);
1977 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);
1978 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);
1979 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);
1980 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);
1981 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;
1982
1983 return rsrc_size;
1984 }
1985
1986 /**
1987 * irdma_initialize_hw_rsrc - initialize hw resource tracking array
1988 * @rf: RDMA PCI function
1989 */
irdma_initialize_hw_rsrc(struct irdma_pci_f * rf)1990 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
1991 {
1992 u32 rsrc_size;
1993 u32 mrdrvbits;
1994 u32 ret;
1995
1996 if (rf->rdma_ver != IRDMA_GEN_1) {
1997 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES,
1998 GFP_KERNEL);
1999 if (!rf->allocated_ws_nodes)
2000 return -ENOMEM;
2001
2002 set_bit(0, rf->allocated_ws_nodes);
2003 rf->max_ws_node_id = IRDMA_MAX_WS_NODES;
2004 }
2005 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size;
2006 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;
2007 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;
2008 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
2009 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;
2010 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;
2011 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
2012 rf->max_mcg = rf->max_qp;
2013
2014 rsrc_size = irdma_calc_mem_rsrc_size(rf);
2015 rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL);
2016 if (!rf->mem_rsrc) {
2017 ret = -ENOMEM;
2018 goto mem_rsrc_kzalloc_fail;
2019 }
2020
2021 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
2022
2023 irdma_set_hw_rsrc(rf);
2024
2025 set_bit(0, rf->allocated_mrs);
2026 set_bit(0, rf->allocated_qps);
2027 set_bit(0, rf->allocated_cqs);
2028 set_bit(0, rf->allocated_pds);
2029 set_bit(0, rf->allocated_arps);
2030 set_bit(0, rf->allocated_ahs);
2031 set_bit(0, rf->allocated_mcgs);
2032 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */
2033 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */
2034 set_bit(1, rf->allocated_cqs);
2035 set_bit(1, rf->allocated_pds);
2036 set_bit(2, rf->allocated_cqs);
2037 set_bit(2, rf->allocated_pds);
2038
2039 INIT_LIST_HEAD(&rf->mc_qht_list.list);
2040 /* stag index mask has a minimum of 14 bits */
2041 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
2042 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
2043
2044 return 0;
2045
2046 mem_rsrc_kzalloc_fail:
2047 bitmap_free(rf->allocated_ws_nodes);
2048 rf->allocated_ws_nodes = NULL;
2049
2050 return ret;
2051 }
2052
2053 /**
2054 * irdma_cqp_ce_handler - handle cqp completions
2055 * @rf: RDMA PCI function
2056 * @cq: cq for cqp completions
2057 */
irdma_cqp_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)2058 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
2059 {
2060 struct irdma_cqp_request *cqp_request;
2061 struct irdma_sc_dev *dev = &rf->sc_dev;
2062 u32 cqe_count = 0;
2063 struct irdma_ccq_cqe_info info;
2064 unsigned long flags;
2065 int ret;
2066
2067 do {
2068 memset(&info, 0, sizeof(info));
2069 spin_lock_irqsave(&rf->cqp.compl_lock, flags);
2070 ret = irdma_sc_ccq_get_cqe_info(cq, &info);
2071 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags);
2072 if (ret)
2073 break;
2074
2075 cqp_request = (struct irdma_cqp_request *)
2076 (unsigned long)info.scratch;
2077 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd,
2078 info.maj_err_code,
2079 info.min_err_code))
2080 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
2081 info.op_code, info.maj_err_code, info.min_err_code);
2082 if (cqp_request) {
2083 cqp_request->compl_info.maj_err_code = info.maj_err_code;
2084 cqp_request->compl_info.min_err_code = info.min_err_code;
2085 cqp_request->compl_info.op_ret_val = info.op_ret_val;
2086 cqp_request->compl_info.error = info.error;
2087
2088 if (cqp_request->waiting) {
2089 WRITE_ONCE(cqp_request->request_done, true);
2090 wake_up(&cqp_request->waitq);
2091 irdma_put_cqp_request(&rf->cqp, cqp_request);
2092 } else {
2093 if (cqp_request->callback_fcn)
2094 cqp_request->callback_fcn(cqp_request);
2095 irdma_put_cqp_request(&rf->cqp, cqp_request);
2096 }
2097 }
2098
2099 cqe_count++;
2100 } while (1);
2101
2102 if (cqe_count) {
2103 irdma_process_bh(dev);
2104 irdma_sc_ccq_arm(cq);
2105 }
2106 }
2107
2108 /**
2109 * cqp_compl_worker - Handle cqp completions
2110 * @work: Pointer to work structure
2111 */
cqp_compl_worker(struct work_struct * work)2112 void cqp_compl_worker(struct work_struct *work)
2113 {
2114 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f,
2115 cqp_cmpl_work);
2116 struct irdma_sc_cq *cq = &rf->ccq.sc_cq;
2117
2118 irdma_cqp_ce_handler(rf, cq);
2119 }
2120
2121 /**
2122 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port
2123 * @cm_core: cm's core
2124 * @port: port to identify apbvt entry
2125 */
irdma_lookup_apbvt_entry(struct irdma_cm_core * cm_core,u16 port)2126 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core,
2127 u16 port)
2128 {
2129 struct irdma_apbvt_entry *entry;
2130
2131 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) {
2132 if (entry->port == port) {
2133 entry->use_cnt++;
2134 return entry;
2135 }
2136 }
2137
2138 return NULL;
2139 }
2140
2141 /**
2142 * irdma_next_iw_state - modify qp state
2143 * @iwqp: iwarp qp to modify
2144 * @state: next state for qp
2145 * @del_hash: del hash
2146 * @term: term message
2147 * @termlen: length of term message
2148 */
irdma_next_iw_state(struct irdma_qp * iwqp,u8 state,u8 del_hash,u8 term,u8 termlen)2149 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
2150 u8 termlen)
2151 {
2152 struct irdma_modify_qp_info info = {};
2153
2154 info.next_iwarp_state = state;
2155 info.remove_hash_idx = del_hash;
2156 info.cq_num_valid = true;
2157 info.arp_cache_idx_valid = true;
2158 info.dont_send_term = true;
2159 info.dont_send_fin = true;
2160 info.termlen = termlen;
2161
2162 if (term & IRDMAQP_TERM_SEND_TERM_ONLY)
2163 info.dont_send_term = false;
2164 if (term & IRDMAQP_TERM_SEND_FIN_ONLY)
2165 info.dont_send_fin = false;
2166 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR)
2167 info.reset_tcp_conn = true;
2168 iwqp->hw_iwarp_state = state;
2169 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
2170 iwqp->iwarp_state = info.next_iwarp_state;
2171 }
2172
2173 /**
2174 * irdma_del_local_mac_entry - remove a mac entry from the hw
2175 * table
2176 * @rf: RDMA PCI function
2177 * @idx: the index of the mac ip address to delete
2178 */
irdma_del_local_mac_entry(struct irdma_pci_f * rf,u16 idx)2179 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx)
2180 {
2181 struct irdma_cqp *iwcqp = &rf->cqp;
2182 struct irdma_cqp_request *cqp_request;
2183 struct cqp_cmds_info *cqp_info;
2184
2185 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2186 if (!cqp_request)
2187 return;
2188
2189 cqp_info = &cqp_request->info;
2190 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY;
2191 cqp_info->post_sq = 1;
2192 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp;
2193 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;
2194 cqp_info->in.u.del_local_mac_entry.entry_idx = idx;
2195 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0;
2196
2197 irdma_handle_cqp_op(rf, cqp_request);
2198 irdma_put_cqp_request(iwcqp, cqp_request);
2199 }
2200
2201 /**
2202 * irdma_add_local_mac_entry - add a mac ip address entry to the
2203 * hw table
2204 * @rf: RDMA PCI function
2205 * @mac_addr: pointer to mac address
2206 * @idx: the index of the mac ip address to add
2207 */
irdma_add_local_mac_entry(struct irdma_pci_f * rf,const u8 * mac_addr,u16 idx)2208 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx)
2209 {
2210 struct irdma_local_mac_entry_info *info;
2211 struct irdma_cqp *iwcqp = &rf->cqp;
2212 struct irdma_cqp_request *cqp_request;
2213 struct cqp_cmds_info *cqp_info;
2214 int status;
2215
2216 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2217 if (!cqp_request)
2218 return -ENOMEM;
2219
2220 cqp_info = &cqp_request->info;
2221 cqp_info->post_sq = 1;
2222 info = &cqp_info->in.u.add_local_mac_entry.info;
2223 ether_addr_copy(info->mac_addr, mac_addr);
2224 info->entry_idx = idx;
2225 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2226 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY;
2227 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp;
2228 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2229
2230 status = irdma_handle_cqp_op(rf, cqp_request);
2231 irdma_put_cqp_request(iwcqp, cqp_request);
2232
2233 return status;
2234 }
2235
2236 /**
2237 * irdma_alloc_local_mac_entry - allocate a mac entry
2238 * @rf: RDMA PCI function
2239 * @mac_tbl_idx: the index of the new mac address
2240 *
2241 * Allocate a mac address entry and update the mac_tbl_idx
2242 * to hold the index of the newly created mac address
2243 * Return 0 if successful, otherwise return error
2244 */
irdma_alloc_local_mac_entry(struct irdma_pci_f * rf,u16 * mac_tbl_idx)2245 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx)
2246 {
2247 struct irdma_cqp *iwcqp = &rf->cqp;
2248 struct irdma_cqp_request *cqp_request;
2249 struct cqp_cmds_info *cqp_info;
2250 int status = 0;
2251
2252 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2253 if (!cqp_request)
2254 return -ENOMEM;
2255
2256 cqp_info = &cqp_request->info;
2257 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
2258 cqp_info->post_sq = 1;
2259 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp;
2260 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;
2261 status = irdma_handle_cqp_op(rf, cqp_request);
2262 if (!status)
2263 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val;
2264
2265 irdma_put_cqp_request(iwcqp, cqp_request);
2266
2267 return status;
2268 }
2269
2270 /**
2271 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt
2272 * @iwdev: irdma device
2273 * @accel_local_port: port for apbvt
2274 * @add_port: add ordelete port
2275 */
irdma_cqp_manage_apbvt_cmd(struct irdma_device * iwdev,u16 accel_local_port,bool add_port)2276 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
2277 u16 accel_local_port, bool add_port)
2278 {
2279 struct irdma_apbvt_info *info;
2280 struct irdma_cqp_request *cqp_request;
2281 struct cqp_cmds_info *cqp_info;
2282 int status;
2283
2284 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
2285 if (!cqp_request)
2286 return -ENOMEM;
2287
2288 cqp_info = &cqp_request->info;
2289 info = &cqp_info->in.u.manage_apbvt_entry.info;
2290 memset(info, 0, sizeof(*info));
2291 info->add = add_port;
2292 info->port = accel_local_port;
2293 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY;
2294 cqp_info->post_sq = 1;
2295 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2296 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
2297 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n",
2298 (!add_port) ? "DELETE" : "ADD", accel_local_port);
2299
2300 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2301 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2302
2303 return status;
2304 }
2305
2306 /**
2307 * irdma_add_apbvt - add tcp port to HW apbvt table
2308 * @iwdev: irdma device
2309 * @port: port for apbvt
2310 */
irdma_add_apbvt(struct irdma_device * iwdev,u16 port)2311 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port)
2312 {
2313 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2314 struct irdma_apbvt_entry *entry;
2315 unsigned long flags;
2316
2317 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2318 entry = irdma_lookup_apbvt_entry(cm_core, port);
2319 if (entry) {
2320 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2321 return entry;
2322 }
2323
2324 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2325 if (!entry) {
2326 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2327 return NULL;
2328 }
2329
2330 entry->port = port;
2331 entry->use_cnt = 1;
2332 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port);
2333 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2334
2335 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) {
2336 kfree(entry);
2337 return NULL;
2338 }
2339
2340 return entry;
2341 }
2342
2343 /**
2344 * irdma_del_apbvt - delete tcp port from HW apbvt table
2345 * @iwdev: irdma device
2346 * @entry: apbvt entry object
2347 */
irdma_del_apbvt(struct irdma_device * iwdev,struct irdma_apbvt_entry * entry)2348 void irdma_del_apbvt(struct irdma_device *iwdev,
2349 struct irdma_apbvt_entry *entry)
2350 {
2351 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2352 unsigned long flags;
2353
2354 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2355 if (--entry->use_cnt) {
2356 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2357 return;
2358 }
2359
2360 hash_del(&entry->hlist);
2361 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to
2362 * protect against race where add APBVT CQP can race ahead of the delete
2363 * APBVT for same port.
2364 */
2365 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false);
2366 kfree(entry);
2367 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2368 }
2369
2370 /**
2371 * irdma_manage_arp_cache - manage hw arp cache
2372 * @rf: RDMA PCI function
2373 * @mac_addr: mac address ptr
2374 * @ip_addr: ip addr for arp cache
2375 * @ipv4: flag inicating IPv4
2376 * @action: add, delete or modify
2377 */
irdma_manage_arp_cache(struct irdma_pci_f * rf,const unsigned char * mac_addr,u32 * ip_addr,bool ipv4,u32 action)2378 void irdma_manage_arp_cache(struct irdma_pci_f *rf,
2379 const unsigned char *mac_addr,
2380 u32 *ip_addr, bool ipv4, u32 action)
2381 {
2382 struct irdma_add_arp_cache_entry_info *info;
2383 struct irdma_cqp_request *cqp_request;
2384 struct cqp_cmds_info *cqp_info;
2385 int arp_index;
2386
2387 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action);
2388 if (arp_index == -1)
2389 return;
2390
2391 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
2392 if (!cqp_request)
2393 return;
2394
2395 cqp_info = &cqp_request->info;
2396 if (action == IRDMA_ARP_ADD) {
2397 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY;
2398 info = &cqp_info->in.u.add_arp_cache_entry.info;
2399 memset(info, 0, sizeof(*info));
2400 info->arp_index = (u16)arp_index;
2401 info->permanent = true;
2402 ether_addr_copy(info->mac_addr, mac_addr);
2403 cqp_info->in.u.add_arp_cache_entry.scratch =
2404 (uintptr_t)cqp_request;
2405 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2406 } else {
2407 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY;
2408 cqp_info->in.u.del_arp_cache_entry.scratch =
2409 (uintptr_t)cqp_request;
2410 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2411 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
2412 }
2413
2414 cqp_info->post_sq = 1;
2415 irdma_handle_cqp_op(rf, cqp_request);
2416 irdma_put_cqp_request(&rf->cqp, cqp_request);
2417 }
2418
2419 /**
2420 * irdma_send_syn_cqp_callback - do syn/ack after qhash
2421 * @cqp_request: qhash cqp completion
2422 */
irdma_send_syn_cqp_callback(struct irdma_cqp_request * cqp_request)2423 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request)
2424 {
2425 struct irdma_cm_node *cm_node = cqp_request->param;
2426
2427 irdma_send_syn(cm_node, 1);
2428 irdma_rem_ref_cm_node(cm_node);
2429 }
2430
2431 /**
2432 * irdma_manage_qhash - add or modify qhash
2433 * @iwdev: irdma device
2434 * @cminfo: cm info for qhash
2435 * @etype: type (syn or quad)
2436 * @mtype: type of qhash
2437 * @cmnode: cmnode associated with connection
2438 * @wait: wait for completion
2439 */
irdma_manage_qhash(struct irdma_device * iwdev,struct irdma_cm_info * cminfo,enum irdma_quad_entry_type etype,enum irdma_quad_hash_manage_type mtype,void * cmnode,bool wait)2440 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
2441 enum irdma_quad_entry_type etype,
2442 enum irdma_quad_hash_manage_type mtype, void *cmnode,
2443 bool wait)
2444 {
2445 struct irdma_qhash_table_info *info;
2446 struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
2447 struct irdma_cqp_request *cqp_request;
2448 struct cqp_cmds_info *cqp_info;
2449 struct irdma_cm_node *cm_node = cmnode;
2450 int status;
2451
2452 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
2453 if (!cqp_request)
2454 return -ENOMEM;
2455
2456 cqp_info = &cqp_request->info;
2457 info = &cqp_info->in.u.manage_qhash_table_entry.info;
2458 memset(info, 0, sizeof(*info));
2459 info->vsi = &iwdev->vsi;
2460 info->manage = mtype;
2461 info->entry_type = etype;
2462 if (cminfo->vlan_id < VLAN_N_VID) {
2463 info->vlan_valid = true;
2464 info->vlan_id = cminfo->vlan_id;
2465 } else {
2466 info->vlan_valid = false;
2467 }
2468 info->ipv4_valid = cminfo->ipv4;
2469 info->user_pri = cminfo->user_pri;
2470 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
2471 info->qp_num = cminfo->qh_qpid;
2472 info->dest_port = cminfo->loc_port;
2473 info->dest_ip[0] = cminfo->loc_addr[0];
2474 info->dest_ip[1] = cminfo->loc_addr[1];
2475 info->dest_ip[2] = cminfo->loc_addr[2];
2476 info->dest_ip[3] = cminfo->loc_addr[3];
2477 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED ||
2478 etype == IRDMA_QHASH_TYPE_UDP_UNICAST ||
2479 etype == IRDMA_QHASH_TYPE_UDP_MCAST ||
2480 etype == IRDMA_QHASH_TYPE_ROCE_MCAST ||
2481 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) {
2482 info->src_port = cminfo->rem_port;
2483 info->src_ip[0] = cminfo->rem_addr[0];
2484 info->src_ip[1] = cminfo->rem_addr[1];
2485 info->src_ip[2] = cminfo->rem_addr[2];
2486 info->src_ip[3] = cminfo->rem_addr[3];
2487 }
2488 if (cmnode) {
2489 cqp_request->callback_fcn = irdma_send_syn_cqp_callback;
2490 cqp_request->param = cmnode;
2491 if (!wait)
2492 refcount_inc(&cm_node->refcnt);
2493 }
2494 if (info->ipv4_valid)
2495 ibdev_dbg(&iwdev->ibdev,
2496 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n",
2497 (!mtype) ? "DELETE" : "ADD",
2498 __builtin_return_address(0), info->dest_port,
2499 info->src_port, info->dest_ip, info->src_ip,
2500 info->mac_addr, cminfo->vlan_id,
2501 cmnode ? cmnode : NULL);
2502 else
2503 ibdev_dbg(&iwdev->ibdev,
2504 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n",
2505 (!mtype) ? "DELETE" : "ADD",
2506 __builtin_return_address(0), info->dest_port,
2507 info->src_port, info->dest_ip, info->src_ip,
2508 info->mac_addr, cminfo->vlan_id,
2509 cmnode ? cmnode : NULL);
2510
2511 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2512 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
2513 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY;
2514 cqp_info->post_sq = 1;
2515 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2516 if (status && cm_node && !wait)
2517 irdma_rem_ref_cm_node(cm_node);
2518
2519 irdma_put_cqp_request(iwcqp, cqp_request);
2520
2521 return status;
2522 }
2523
2524 /**
2525 * irdma_hw_flush_wqes_callback - Check return code after flush
2526 * @cqp_request: qhash cqp completion
2527 */
irdma_hw_flush_wqes_callback(struct irdma_cqp_request * cqp_request)2528 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request)
2529 {
2530 struct irdma_qp_flush_info *hw_info;
2531 struct irdma_sc_qp *qp;
2532 struct irdma_qp *iwqp;
2533 struct cqp_cmds_info *cqp_info;
2534
2535 cqp_info = &cqp_request->info;
2536 hw_info = &cqp_info->in.u.qp_flush_wqes.info;
2537 qp = cqp_info->in.u.qp_flush_wqes.qp;
2538 iwqp = qp->qp_uk.back_qp;
2539
2540 if (cqp_request->compl_info.maj_err_code)
2541 return;
2542
2543 if (hw_info->rq &&
2544 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2545 cqp_request->compl_info.min_err_code == 0)) {
2546 /* RQ WQE flush was requested but did not happen */
2547 qp->qp_uk.rq_flush_complete = true;
2548 }
2549 if (hw_info->sq &&
2550 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2551 cqp_request->compl_info.min_err_code == 0)) {
2552 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2553 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work",
2554 qp->qp_uk.qp_id);
2555 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2556 }
2557 qp->qp_uk.sq_flush_complete = true;
2558 }
2559 }
2560
2561 /**
2562 * irdma_hw_flush_wqes - flush qp's wqe
2563 * @rf: RDMA PCI function
2564 * @qp: hardware control qp
2565 * @info: info for flush
2566 * @wait: flag wait for completion
2567 */
irdma_hw_flush_wqes(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_qp_flush_info * info,bool wait)2568 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2569 struct irdma_qp_flush_info *info, bool wait)
2570 {
2571 int status;
2572 struct irdma_qp_flush_info *hw_info;
2573 struct irdma_cqp_request *cqp_request;
2574 struct cqp_cmds_info *cqp_info;
2575 struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2576
2577 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2578 if (!cqp_request)
2579 return -ENOMEM;
2580
2581 cqp_info = &cqp_request->info;
2582 if (!wait)
2583 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback;
2584 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
2585 memcpy(hw_info, info, sizeof(*hw_info));
2586 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2587 cqp_info->post_sq = 1;
2588 cqp_info->in.u.qp_flush_wqes.qp = qp;
2589 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
2590 status = irdma_handle_cqp_op(rf, cqp_request);
2591 if (status) {
2592 qp->qp_uk.sq_flush_complete = true;
2593 qp->qp_uk.rq_flush_complete = true;
2594 irdma_put_cqp_request(&rf->cqp, cqp_request);
2595 return status;
2596 }
2597
2598 if (!wait || cqp_request->compl_info.maj_err_code)
2599 goto put_cqp;
2600
2601 if (info->rq) {
2602 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2603 cqp_request->compl_info.min_err_code == 0) {
2604 /* RQ WQE flush was requested but did not happen */
2605 qp->qp_uk.rq_flush_complete = true;
2606 }
2607 }
2608 if (info->sq) {
2609 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2610 cqp_request->compl_info.min_err_code == 0) {
2611 /*
2612 * Handling case where WQE is posted to empty SQ when
2613 * flush has not completed
2614 */
2615 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2616 struct irdma_cqp_request *new_req;
2617
2618 if (!qp->qp_uk.sq_flush_complete)
2619 goto put_cqp;
2620 qp->qp_uk.sq_flush_complete = false;
2621 qp->flush_sq = false;
2622
2623 info->rq = false;
2624 info->sq = true;
2625 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2626 if (!new_req) {
2627 status = -ENOMEM;
2628 goto put_cqp;
2629 }
2630 cqp_info = &new_req->info;
2631 hw_info = &new_req->info.in.u.qp_flush_wqes.info;
2632 memcpy(hw_info, info, sizeof(*hw_info));
2633 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2634 cqp_info->post_sq = 1;
2635 cqp_info->in.u.qp_flush_wqes.qp = qp;
2636 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req;
2637
2638 status = irdma_handle_cqp_op(rf, new_req);
2639 if (new_req->compl_info.maj_err_code ||
2640 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2641 status) {
2642 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d",
2643 iwqp->ibqp.qp_num);
2644 qp->qp_uk.sq_flush_complete = false;
2645 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2646 }
2647 irdma_put_cqp_request(&rf->cqp, new_req);
2648 } else {
2649 /* SQ WQE flush was requested but did not happen */
2650 qp->qp_uk.sq_flush_complete = true;
2651 }
2652 } else {
2653 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring))
2654 qp->qp_uk.sq_flush_complete = true;
2655 }
2656 }
2657
2658 ibdev_dbg(&rf->iwdev->ibdev,
2659 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n",
2660 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state,
2661 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state,
2662 cqp_request->compl_info.maj_err_code,
2663 cqp_request->compl_info.min_err_code);
2664 put_cqp:
2665 irdma_put_cqp_request(&rf->cqp, cqp_request);
2666
2667 return status;
2668 }
2669
2670 /**
2671 * irdma_gen_ae - generate AE
2672 * @rf: RDMA PCI function
2673 * @qp: qp associated with AE
2674 * @info: info for ae
2675 * @wait: wait for completion
2676 */
irdma_gen_ae(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_gen_ae_info * info,bool wait)2677 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2678 struct irdma_gen_ae_info *info, bool wait)
2679 {
2680 struct irdma_gen_ae_info *ae_info;
2681 struct irdma_cqp_request *cqp_request;
2682 struct cqp_cmds_info *cqp_info;
2683
2684 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2685 if (!cqp_request)
2686 return;
2687
2688 cqp_info = &cqp_request->info;
2689 ae_info = &cqp_request->info.in.u.gen_ae.info;
2690 memcpy(ae_info, info, sizeof(*ae_info));
2691 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE;
2692 cqp_info->post_sq = 1;
2693 cqp_info->in.u.gen_ae.qp = qp;
2694 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
2695
2696 irdma_handle_cqp_op(rf, cqp_request);
2697 irdma_put_cqp_request(&rf->cqp, cqp_request);
2698 }
2699
irdma_flush_wqes(struct irdma_qp * iwqp,u32 flush_mask)2700 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask)
2701 {
2702 struct irdma_qp_flush_info info = {};
2703 struct irdma_pci_f *rf = iwqp->iwdev->rf;
2704 u8 flush_code = iwqp->sc_qp.flush_code;
2705
2706 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2707 return;
2708
2709 /* Set flush info fields*/
2710 info.sq = flush_mask & IRDMA_FLUSH_SQ;
2711 info.rq = flush_mask & IRDMA_FLUSH_RQ;
2712
2713 /* Generate userflush errors in CQE */
2714 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2715 info.sq_minor_code = FLUSH_GENERAL_ERR;
2716 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2717 info.rq_minor_code = FLUSH_GENERAL_ERR;
2718 info.userflushcode = true;
2719
2720 if (flush_mask & IRDMA_REFLUSH) {
2721 if (info.sq)
2722 iwqp->sc_qp.flush_sq = false;
2723 if (info.rq)
2724 iwqp->sc_qp.flush_rq = false;
2725 } else {
2726 if (flush_code) {
2727 if (info.sq && iwqp->sc_qp.sq_flush_code)
2728 info.sq_minor_code = flush_code;
2729 if (info.rq && iwqp->sc_qp.rq_flush_code)
2730 info.rq_minor_code = flush_code;
2731 }
2732 if (!iwqp->user_mode)
2733 queue_delayed_work(iwqp->iwdev->cleanup_wq,
2734 &iwqp->dwork_flush,
2735 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
2736 }
2737
2738 /* Issue flush */
2739 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2740 flush_mask & IRDMA_FLUSH_WAIT);
2741 iwqp->flush_issued = true;
2742 }
2743