1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../dmub_srv.h"
27 #include "dmub_dcn20.h"
28 #include "dmub_dcn21.h"
29 #include "dmub_cmd.h"
30 #include "dmub_dcn30.h"
31 #include "dmub_dcn301.h"
32 #include "dmub_dcn302.h"
33 #include "dmub_dcn303.h"
34 #include "dmub_dcn31.h"
35 #include "dmub_dcn314.h"
36 #include "dmub_dcn315.h"
37 #include "dmub_dcn316.h"
38 #include "dmub_dcn32.h"
39 #include "os_types.h"
40 /*
41 * Note: the DMUB service is standalone. No additional headers should be
42 * added below or above this line unless they reside within the DMUB
43 * folder.
44 */
45
46 /* Alignment for framebuffer memory. */
47 #define DMUB_FB_ALIGNMENT (1024 * 1024)
48
49 /* Stack size. */
50 #define DMUB_STACK_SIZE (128 * 1024)
51
52 /* Context size. */
53 #define DMUB_CONTEXT_SIZE (512 * 1024)
54
55 /* Mailbox size : Ring buffers are required for both inbox and outbox */
56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
57
58 /* Default state size if meta is absent. */
59 #define DMUB_FW_STATE_SIZE (64 * 1024)
60
61 /* Default tracebuffer size if meta is absent. */
62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
63
64
65 /* Default scratch mem size. */
66 #define DMUB_SCRATCH_MEM_SIZE (256)
67
68 /* Number of windows in use. */
69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
70 /* Base addresses. */
71
72 #define DMUB_CW0_BASE (0x60000000)
73 #define DMUB_CW1_BASE (0x61000000)
74 #define DMUB_CW3_BASE (0x63000000)
75 #define DMUB_CW4_BASE (0x64000000)
76 #define DMUB_CW5_BASE (0x65000000)
77 #define DMUB_CW6_BASE (0x66000000)
78
79 #define DMUB_REGION5_BASE (0xA0000000)
80
dmub_align(uint32_t val,uint32_t factor)81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
82 {
83 return (val + factor - 1) / factor * factor;
84 }
85
dmub_flush_buffer_mem(const struct dmub_fb * fb)86 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
87 {
88 const uint8_t *base = (const uint8_t *)fb->cpu_addr;
89 uint8_t buf[64];
90 uint32_t pos, end;
91
92 /**
93 * Read 64-byte chunks since we don't want to store a
94 * large temporary buffer for this purpose.
95 */
96 end = fb->size / sizeof(buf) * sizeof(buf);
97
98 for (pos = 0; pos < end; pos += sizeof(buf))
99 dmub_memcpy(buf, base + pos, sizeof(buf));
100
101 /* Read anything leftover into the buffer. */
102 if (end < fb->size)
103 dmub_memcpy(buf, base + pos, fb->size - end);
104 }
105
106 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info_from_blob(const uint8_t * blob,uint32_t blob_size,uint32_t meta_offset)107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
108 {
109 const union dmub_fw_meta *meta;
110
111 if (!blob || !blob_size)
112 return NULL;
113
114 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
115 return NULL;
116
117 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
118 sizeof(union dmub_fw_meta));
119
120 if (meta->info.magic_value != DMUB_FW_META_MAGIC)
121 return NULL;
122
123 return &meta->info;
124 }
125
126 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info(const struct dmub_srv_region_params * params)127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
128 {
129 const struct dmub_fw_meta_info *info = NULL;
130
131 if (params->fw_bss_data && params->bss_data_size) {
132 /* Legacy metadata region. */
133 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
134 params->bss_data_size,
135 DMUB_FW_META_OFFSET);
136 } else if (params->fw_inst_const && params->inst_const_size) {
137 /* Combined metadata region - can be aligned to 16-bytes. */
138 uint32_t i;
139
140 for (i = 0; i < 16; ++i) {
141 info = dmub_get_fw_meta_info_from_blob(
142 params->fw_inst_const, params->inst_const_size, i);
143
144 if (info)
145 break;
146 }
147 }
148
149 return info;
150 }
151
dmub_srv_hw_setup(struct dmub_srv * dmub,enum dmub_asic asic)152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
153 {
154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
155
156 switch (asic) {
157 case DMUB_ASIC_DCN20:
158 case DMUB_ASIC_DCN21:
159 case DMUB_ASIC_DCN30:
160 case DMUB_ASIC_DCN301:
161 case DMUB_ASIC_DCN302:
162 case DMUB_ASIC_DCN303:
163 dmub->regs = &dmub_srv_dcn20_regs;
164
165 funcs->reset = dmub_dcn20_reset;
166 funcs->reset_release = dmub_dcn20_reset_release;
167 funcs->backdoor_load = dmub_dcn20_backdoor_load;
168 funcs->setup_windows = dmub_dcn20_setup_windows;
169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr;
171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
173 funcs->is_supported = dmub_dcn20_is_supported;
174 funcs->is_hw_init = dmub_dcn20_is_hw_init;
175 funcs->set_gpint = dmub_dcn20_set_gpint;
176 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
177 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
178 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
179 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
180 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
181 funcs->get_current_time = dmub_dcn20_get_current_time;
182
183 // Out mailbox register access functions for RN and above
184 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
185 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
186 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
187
188 //outbox0 call stacks
189 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
190 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
191 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
192
193 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
194
195 if (asic == DMUB_ASIC_DCN21) {
196 dmub->regs = &dmub_srv_dcn21_regs;
197
198 funcs->is_phy_init = dmub_dcn21_is_phy_init;
199 }
200 if (asic == DMUB_ASIC_DCN30) {
201 dmub->regs = &dmub_srv_dcn30_regs;
202
203 funcs->backdoor_load = dmub_dcn30_backdoor_load;
204 funcs->setup_windows = dmub_dcn30_setup_windows;
205 }
206 if (asic == DMUB_ASIC_DCN301) {
207 dmub->regs = &dmub_srv_dcn301_regs;
208
209 funcs->backdoor_load = dmub_dcn30_backdoor_load;
210 funcs->setup_windows = dmub_dcn30_setup_windows;
211 }
212 if (asic == DMUB_ASIC_DCN302) {
213 dmub->regs = &dmub_srv_dcn302_regs;
214
215 funcs->backdoor_load = dmub_dcn30_backdoor_load;
216 funcs->setup_windows = dmub_dcn30_setup_windows;
217 }
218 if (asic == DMUB_ASIC_DCN303) {
219 dmub->regs = &dmub_srv_dcn303_regs;
220
221 funcs->backdoor_load = dmub_dcn30_backdoor_load;
222 funcs->setup_windows = dmub_dcn30_setup_windows;
223 }
224 break;
225
226 case DMUB_ASIC_DCN31:
227 case DMUB_ASIC_DCN31B:
228 case DMUB_ASIC_DCN314:
229 case DMUB_ASIC_DCN315:
230 case DMUB_ASIC_DCN316:
231 if (asic == DMUB_ASIC_DCN314) {
232 dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
233 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;
234 } else if (asic == DMUB_ASIC_DCN315) {
235 dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
236 } else if (asic == DMUB_ASIC_DCN316) {
237 dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
238 } else {
239 dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
240 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;
241 }
242 funcs->reset = dmub_dcn31_reset;
243 funcs->reset_release = dmub_dcn31_reset_release;
244 funcs->backdoor_load = dmub_dcn31_backdoor_load;
245 funcs->setup_windows = dmub_dcn31_setup_windows;
246 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
247 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr;
248 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
249 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
250 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
251 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
252 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
253 funcs->is_supported = dmub_dcn31_is_supported;
254 funcs->is_hw_init = dmub_dcn31_is_hw_init;
255 funcs->set_gpint = dmub_dcn31_set_gpint;
256 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
257 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
258 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
259 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
260 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
261 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
262 //outbox0 call stacks
263 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
264 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
265 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
266
267 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
268 funcs->should_detect = dmub_dcn31_should_detect;
269 funcs->get_current_time = dmub_dcn31_get_current_time;
270
271 break;
272
273 case DMUB_ASIC_DCN32:
274 case DMUB_ASIC_DCN321:
275 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
276 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
277 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
278 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
279 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
280 funcs->reset = dmub_dcn32_reset;
281 funcs->reset_release = dmub_dcn32_reset_release;
282 funcs->backdoor_load = dmub_dcn32_backdoor_load;
283 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
284 funcs->setup_windows = dmub_dcn32_setup_windows;
285 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
286 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr;
287 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
288 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
289 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
290 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
291 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
292 funcs->is_supported = dmub_dcn32_is_supported;
293 funcs->is_hw_init = dmub_dcn32_is_hw_init;
294 funcs->set_gpint = dmub_dcn32_set_gpint;
295 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
296 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
297 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
298 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
299 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
300 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
301
302 /* outbox0 call stacks */
303 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
304 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
305 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
306 funcs->get_current_time = dmub_dcn32_get_current_time;
307 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
308
309 break;
310
311 default:
312 return false;
313 }
314
315 return true;
316 }
317
dmub_srv_create(struct dmub_srv * dmub,const struct dmub_srv_create_params * params)318 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
319 const struct dmub_srv_create_params *params)
320 {
321 enum dmub_status status = DMUB_STATUS_OK;
322
323 dmub_memset(dmub, 0, sizeof(*dmub));
324
325 dmub->funcs = params->funcs;
326 dmub->user_ctx = params->user_ctx;
327 dmub->asic = params->asic;
328 dmub->fw_version = params->fw_version;
329 dmub->is_virtual = params->is_virtual;
330
331 /* Setup asic dependent hardware funcs. */
332 if (!dmub_srv_hw_setup(dmub, params->asic)) {
333 status = DMUB_STATUS_INVALID;
334 goto cleanup;
335 }
336
337 /* Override (some) hardware funcs based on user params. */
338 if (params->hw_funcs) {
339 if (params->hw_funcs->emul_get_inbox1_rptr)
340 dmub->hw_funcs.emul_get_inbox1_rptr =
341 params->hw_funcs->emul_get_inbox1_rptr;
342
343 if (params->hw_funcs->emul_set_inbox1_wptr)
344 dmub->hw_funcs.emul_set_inbox1_wptr =
345 params->hw_funcs->emul_set_inbox1_wptr;
346
347 if (params->hw_funcs->is_supported)
348 dmub->hw_funcs.is_supported =
349 params->hw_funcs->is_supported;
350 }
351
352 /* Sanity checks for required hw func pointers. */
353 if (!dmub->hw_funcs.get_inbox1_rptr ||
354 !dmub->hw_funcs.set_inbox1_wptr) {
355 status = DMUB_STATUS_INVALID;
356 goto cleanup;
357 }
358
359 cleanup:
360 if (status == DMUB_STATUS_OK)
361 dmub->sw_init = true;
362 else
363 dmub_srv_destroy(dmub);
364
365 return status;
366 }
367
dmub_srv_destroy(struct dmub_srv * dmub)368 void dmub_srv_destroy(struct dmub_srv *dmub)
369 {
370 dmub_memset(dmub, 0, sizeof(*dmub));
371 }
372
373 enum dmub_status
dmub_srv_calc_region_info(struct dmub_srv * dmub,const struct dmub_srv_region_params * params,struct dmub_srv_region_info * out)374 dmub_srv_calc_region_info(struct dmub_srv *dmub,
375 const struct dmub_srv_region_params *params,
376 struct dmub_srv_region_info *out)
377 {
378 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
379 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
380 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
381 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
382 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
383 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
384 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
385 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
386 const struct dmub_fw_meta_info *fw_info;
387 uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
388 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
389 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
390 uint32_t previous_top = 0;
391 if (!dmub->sw_init)
392 return DMUB_STATUS_INVALID;
393
394 memset(out, 0, sizeof(*out));
395
396 out->num_regions = DMUB_NUM_WINDOWS;
397
398 inst->base = 0x0;
399 inst->top = inst->base + params->inst_const_size;
400
401 data->base = dmub_align(inst->top, 256);
402 data->top = data->base + params->bss_data_size;
403
404 /*
405 * All cache windows below should be aligned to the size
406 * of the DMCUB cache line, 64 bytes.
407 */
408
409 stack->base = dmub_align(data->top, 256);
410 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
411
412 bios->base = dmub_align(stack->top, 256);
413 bios->top = bios->base + params->vbios_size;
414
415 if (params->is_mailbox_in_inbox) {
416 mail->base = 0;
417 mail->top = mail->base + DMUB_MAILBOX_SIZE;
418 previous_top = bios->top;
419 } else {
420 mail->base = dmub_align(bios->top, 256);
421 mail->top = mail->base + DMUB_MAILBOX_SIZE;
422 previous_top = mail->top;
423 }
424
425 fw_info = dmub_get_fw_meta_info(params);
426
427 if (fw_info) {
428 fw_state_size = fw_info->fw_region_size;
429 trace_buffer_size = fw_info->trace_buffer_size;
430
431 /**
432 * If DM didn't fill in a version, then fill it in based on
433 * the firmware meta now that we have it.
434 *
435 * TODO: Make it easier for driver to extract this out to
436 * pass during creation.
437 */
438 if (dmub->fw_version == 0)
439 dmub->fw_version = fw_info->fw_version;
440 }
441
442 trace_buff->base = dmub_align(previous_top, 256);
443 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
444
445 fw_state->base = dmub_align(trace_buff->top, 256);
446 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
447
448 scratch_mem->base = dmub_align(fw_state->top, 256);
449 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
450
451 out->fb_size = dmub_align(scratch_mem->top, 4096);
452
453 if (params->is_mailbox_in_inbox)
454 out->inbox_size = dmub_align(mail->top, 4096);
455
456 return DMUB_STATUS_OK;
457 }
458
dmub_srv_calc_mem_info(struct dmub_srv * dmub,const struct dmub_srv_memory_params * params,struct dmub_srv_fb_info * out)459 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,
460 const struct dmub_srv_memory_params *params,
461 struct dmub_srv_fb_info *out)
462 {
463 uint8_t *cpu_base;
464 uint64_t gpu_base;
465 uint32_t i;
466
467 if (!dmub->sw_init)
468 return DMUB_STATUS_INVALID;
469
470 memset(out, 0, sizeof(*out));
471
472 if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
473 return DMUB_STATUS_INVALID;
474
475 cpu_base = (uint8_t *)params->cpu_fb_addr;
476 gpu_base = params->gpu_fb_addr;
477
478 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
479 const struct dmub_region *reg =
480 ¶ms->region_info->regions[i];
481
482 out->fb[i].cpu_addr = cpu_base + reg->base;
483 out->fb[i].gpu_addr = gpu_base + reg->base;
484
485 if (i == DMUB_WINDOW_4_MAILBOX && params->cpu_inbox_addr != 0) {
486 out->fb[i].cpu_addr = (uint8_t *)params->cpu_inbox_addr + reg->base;
487 out->fb[i].gpu_addr = params->gpu_inbox_addr + reg->base;
488 }
489
490 out->fb[i].size = reg->top - reg->base;
491 }
492
493 out->num_fb = DMUB_NUM_WINDOWS;
494
495 return DMUB_STATUS_OK;
496 }
497
dmub_srv_has_hw_support(struct dmub_srv * dmub,bool * is_supported)498 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
499 bool *is_supported)
500 {
501 *is_supported = false;
502
503 if (!dmub->sw_init)
504 return DMUB_STATUS_INVALID;
505
506 if (dmub->hw_funcs.is_supported)
507 *is_supported = dmub->hw_funcs.is_supported(dmub);
508
509 return DMUB_STATUS_OK;
510 }
511
dmub_srv_is_hw_init(struct dmub_srv * dmub,bool * is_hw_init)512 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
513 {
514 *is_hw_init = false;
515
516 if (!dmub->sw_init)
517 return DMUB_STATUS_INVALID;
518
519 if (!dmub->hw_init)
520 return DMUB_STATUS_OK;
521
522 if (dmub->hw_funcs.is_hw_init)
523 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
524
525 return DMUB_STATUS_OK;
526 }
527
dmub_srv_hw_init(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)528 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
529 const struct dmub_srv_hw_params *params)
530 {
531 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
532 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
533 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
534 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
535 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
536 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
537 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
538 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
539
540 struct dmub_rb_init_params rb_params, outbox0_rb_params;
541 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
542 struct dmub_region inbox1, outbox1, outbox0;
543
544 if (!dmub->sw_init)
545 return DMUB_STATUS_INVALID;
546
547 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
548 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
549 ASSERT(0);
550 return DMUB_STATUS_INVALID;
551 }
552
553 dmub->fb_base = params->fb_base;
554 dmub->fb_offset = params->fb_offset;
555 dmub->psp_version = params->psp_version;
556
557 if (dmub->hw_funcs.reset)
558 dmub->hw_funcs.reset(dmub);
559
560 /* reset the cache of the last wptr as well now that hw is reset */
561 dmub->inbox1_last_wptr = 0;
562
563 cw0.offset.quad_part = inst_fb->gpu_addr;
564 cw0.region.base = DMUB_CW0_BASE;
565 cw0.region.top = cw0.region.base + inst_fb->size - 1;
566
567 cw1.offset.quad_part = stack_fb->gpu_addr;
568 cw1.region.base = DMUB_CW1_BASE;
569 cw1.region.top = cw1.region.base + stack_fb->size - 1;
570
571 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
572 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
573
574 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
575 /**
576 * Read back all the instruction memory so we don't hang the
577 * DMCUB when backdoor loading if the write from x86 hasn't been
578 * flushed yet. This only occurs in backdoor loading.
579 */
580 dmub_flush_buffer_mem(inst_fb);
581
582 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
583 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
584 else
585 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
586 }
587
588 cw2.offset.quad_part = data_fb->gpu_addr;
589 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
590 cw2.region.top = cw2.region.base + data_fb->size;
591
592 cw3.offset.quad_part = bios_fb->gpu_addr;
593 cw3.region.base = DMUB_CW3_BASE;
594 cw3.region.top = cw3.region.base + bios_fb->size;
595
596 cw4.offset.quad_part = mail_fb->gpu_addr;
597 cw4.region.base = DMUB_CW4_BASE;
598 cw4.region.top = cw4.region.base + mail_fb->size;
599
600 /**
601 * Doubled the mailbox region to accomodate inbox and outbox.
602 * Note: Currently, currently total mailbox size is 16KB. It is split
603 * equally into 8KB between inbox and outbox. If this config is
604 * changed, then uncached base address configuration of outbox1
605 * has to be updated in funcs->setup_out_mailbox.
606 */
607 inbox1.base = cw4.region.base;
608 inbox1.top = cw4.region.base + DMUB_RB_SIZE;
609 outbox1.base = inbox1.top;
610 outbox1.top = cw4.region.top;
611
612 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
613 cw5.region.base = DMUB_CW5_BASE;
614 cw5.region.top = cw5.region.base + tracebuff_fb->size;
615
616 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
617 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
618
619 cw6.offset.quad_part = fw_state_fb->gpu_addr;
620 cw6.region.base = DMUB_CW6_BASE;
621 cw6.region.top = cw6.region.base + fw_state_fb->size;
622
623 dmub->fw_state = fw_state_fb->cpu_addr;
624
625 dmub->scratch_mem_fb = *scratch_mem_fb;
626
627 if (dmub->hw_funcs.setup_windows)
628 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
629
630 if (dmub->hw_funcs.setup_outbox0)
631 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
632
633 if (dmub->hw_funcs.setup_mailbox)
634 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
635 if (dmub->hw_funcs.setup_out_mailbox)
636 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
637
638 dmub_memset(&rb_params, 0, sizeof(rb_params));
639 rb_params.ctx = dmub;
640 rb_params.base_address = mail_fb->cpu_addr;
641 rb_params.capacity = DMUB_RB_SIZE;
642 dmub_rb_init(&dmub->inbox1_rb, &rb_params);
643
644 // Initialize outbox1 ring buffer
645 rb_params.ctx = dmub;
646 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
647 rb_params.capacity = DMUB_RB_SIZE;
648 dmub_rb_init(&dmub->outbox1_rb, &rb_params);
649
650 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
651 outbox0_rb_params.ctx = dmub;
652 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
653 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
654 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
655
656 /* Report to DMUB what features are supported by current driver */
657 if (dmub->hw_funcs.enable_dmub_boot_options)
658 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
659
660 if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
661 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
662 params->skip_panel_power_sequence);
663
664 if (dmub->hw_funcs.reset_release)
665 dmub->hw_funcs.reset_release(dmub);
666
667 dmub->hw_init = true;
668
669 return DMUB_STATUS_OK;
670 }
671
dmub_srv_sync_inbox1(struct dmub_srv * dmub)672 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)
673 {
674 if (!dmub->sw_init)
675 return DMUB_STATUS_INVALID;
676
677 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) {
678 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
679 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub);
680
681 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) {
682 return DMUB_STATUS_HW_FAILURE;
683 } else {
684 dmub->inbox1_rb.rptr = rptr;
685 dmub->inbox1_rb.wrpt = wptr;
686 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
687 }
688 }
689
690 return DMUB_STATUS_OK;
691 }
692
dmub_srv_hw_reset(struct dmub_srv * dmub)693 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
694 {
695 if (!dmub->sw_init)
696 return DMUB_STATUS_INVALID;
697
698 if (dmub->hw_funcs.reset)
699 dmub->hw_funcs.reset(dmub);
700
701 /* mailboxes have been reset in hw, so reset the sw state as well */
702 dmub->inbox1_last_wptr = 0;
703 dmub->inbox1_rb.wrpt = 0;
704 dmub->inbox1_rb.rptr = 0;
705 dmub->outbox0_rb.wrpt = 0;
706 dmub->outbox0_rb.rptr = 0;
707 dmub->outbox1_rb.wrpt = 0;
708 dmub->outbox1_rb.rptr = 0;
709
710 dmub->hw_init = false;
711
712 return DMUB_STATUS_OK;
713 }
714
dmub_srv_cmd_queue(struct dmub_srv * dmub,const union dmub_rb_cmd * cmd)715 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
716 const union dmub_rb_cmd *cmd)
717 {
718 if (!dmub->hw_init)
719 return DMUB_STATUS_INVALID;
720
721 if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity ||
722 dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) {
723 return DMUB_STATUS_HW_FAILURE;
724 }
725
726 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
727 return DMUB_STATUS_OK;
728
729 return DMUB_STATUS_QUEUE_FULL;
730 }
731
dmub_srv_cmd_execute(struct dmub_srv * dmub)732 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
733 {
734 struct dmub_rb flush_rb;
735
736 if (!dmub->hw_init)
737 return DMUB_STATUS_INVALID;
738
739 /**
740 * Read back all the queued commands to ensure that they've
741 * been flushed to framebuffer memory. Otherwise DMCUB might
742 * read back stale, fully invalid or partially invalid data.
743 */
744 flush_rb = dmub->inbox1_rb;
745 flush_rb.rptr = dmub->inbox1_last_wptr;
746 dmub_rb_flush_pending(&flush_rb);
747
748 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
749
750 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
751
752 return DMUB_STATUS_OK;
753 }
754
dmub_srv_wait_for_auto_load(struct dmub_srv * dmub,uint32_t timeout_us)755 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
756 uint32_t timeout_us)
757 {
758 uint32_t i;
759
760 if (!dmub->hw_init)
761 return DMUB_STATUS_INVALID;
762
763 for (i = 0; i <= timeout_us; i += 100) {
764 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
765
766 if (status.bits.dal_fw && status.bits.mailbox_rdy)
767 return DMUB_STATUS_OK;
768
769 udelay(100);
770 }
771
772 return DMUB_STATUS_TIMEOUT;
773 }
774
dmub_srv_wait_for_phy_init(struct dmub_srv * dmub,uint32_t timeout_us)775 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
776 uint32_t timeout_us)
777 {
778 uint32_t i = 0;
779
780 if (!dmub->hw_init)
781 return DMUB_STATUS_INVALID;
782
783 if (!dmub->hw_funcs.is_phy_init)
784 return DMUB_STATUS_OK;
785
786 for (i = 0; i <= timeout_us; i += 10) {
787 if (dmub->hw_funcs.is_phy_init(dmub))
788 return DMUB_STATUS_OK;
789
790 udelay(10);
791 }
792
793 return DMUB_STATUS_TIMEOUT;
794 }
795
dmub_srv_wait_for_idle(struct dmub_srv * dmub,uint32_t timeout_us)796 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
797 uint32_t timeout_us)
798 {
799 uint32_t i, rptr;
800
801 if (!dmub->hw_init)
802 return DMUB_STATUS_INVALID;
803
804 for (i = 0; i <= timeout_us; ++i) {
805 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
806
807 if (rptr > dmub->inbox1_rb.capacity)
808 return DMUB_STATUS_HW_FAILURE;
809
810 dmub->inbox1_rb.rptr = rptr;
811
812 if (dmub_rb_empty(&dmub->inbox1_rb))
813 return DMUB_STATUS_OK;
814
815 udelay(1);
816 }
817
818 return DMUB_STATUS_TIMEOUT;
819 }
820
821 enum dmub_status
dmub_srv_send_gpint_command(struct dmub_srv * dmub,enum dmub_gpint_command command_code,uint16_t param,uint32_t timeout_us)822 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
823 enum dmub_gpint_command command_code,
824 uint16_t param, uint32_t timeout_us)
825 {
826 union dmub_gpint_data_register reg;
827 uint32_t i;
828
829 if (!dmub->sw_init)
830 return DMUB_STATUS_INVALID;
831
832 if (!dmub->hw_funcs.set_gpint)
833 return DMUB_STATUS_INVALID;
834
835 if (!dmub->hw_funcs.is_gpint_acked)
836 return DMUB_STATUS_INVALID;
837
838 reg.bits.status = 1;
839 reg.bits.command_code = command_code;
840 reg.bits.param = param;
841
842 dmub->hw_funcs.set_gpint(dmub, reg);
843
844 for (i = 0; i < timeout_us; ++i) {
845 udelay(1);
846
847 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
848 return DMUB_STATUS_OK;
849 }
850
851 return DMUB_STATUS_TIMEOUT;
852 }
853
dmub_srv_get_gpint_response(struct dmub_srv * dmub,uint32_t * response)854 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
855 uint32_t *response)
856 {
857 *response = 0;
858
859 if (!dmub->sw_init)
860 return DMUB_STATUS_INVALID;
861
862 if (!dmub->hw_funcs.get_gpint_response)
863 return DMUB_STATUS_INVALID;
864
865 *response = dmub->hw_funcs.get_gpint_response(dmub);
866
867 return DMUB_STATUS_OK;
868 }
869
dmub_srv_get_gpint_dataout(struct dmub_srv * dmub,uint32_t * dataout)870 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
871 uint32_t *dataout)
872 {
873 *dataout = 0;
874
875 if (!dmub->sw_init)
876 return DMUB_STATUS_INVALID;
877
878 if (!dmub->hw_funcs.get_gpint_dataout)
879 return DMUB_STATUS_INVALID;
880
881 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
882
883 return DMUB_STATUS_OK;
884 }
885
dmub_srv_get_fw_boot_status(struct dmub_srv * dmub,union dmub_fw_boot_status * status)886 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
887 union dmub_fw_boot_status *status)
888 {
889 status->all = 0;
890
891 if (!dmub->sw_init)
892 return DMUB_STATUS_INVALID;
893
894 if (dmub->hw_funcs.get_fw_status)
895 *status = dmub->hw_funcs.get_fw_status(dmub);
896
897 return DMUB_STATUS_OK;
898 }
899
dmub_srv_cmd_with_reply_data(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)900 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
901 union dmub_rb_cmd *cmd)
902 {
903 enum dmub_status status = DMUB_STATUS_OK;
904
905 // Queue command
906 status = dmub_srv_cmd_queue(dmub, cmd);
907
908 if (status != DMUB_STATUS_OK)
909 return status;
910
911 // Execute command
912 status = dmub_srv_cmd_execute(dmub);
913
914 if (status != DMUB_STATUS_OK)
915 return status;
916
917 // Wait for DMUB to process command
918 status = dmub_srv_wait_for_idle(dmub, 100000);
919
920 if (status != DMUB_STATUS_OK)
921 return status;
922
923 // Copy data back from ring buffer into command
924 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
925
926 return status;
927 }
928
dmub_rb_out_trace_buffer_front(struct dmub_rb * rb,void * entry)929 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
930 void *entry)
931 {
932 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
933 uint64_t *dst = (uint64_t *)entry;
934 uint8_t i;
935 uint8_t loop_count;
936
937 if (rb->rptr == rb->wrpt)
938 return false;
939
940 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
941 // copying data
942 for (i = 0; i < loop_count; i++)
943 *dst++ = *src++;
944
945 rb->rptr += sizeof(struct dmcub_trace_buf_entry);
946
947 rb->rptr %= rb->capacity;
948
949 return true;
950 }
951
dmub_srv_get_outbox0_msg(struct dmub_srv * dmub,struct dmcub_trace_buf_entry * entry)952 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
953 {
954 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
955
956 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
957 }
958
dmub_srv_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)959 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
960 {
961 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
962 return false;
963 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
964 return true;
965 }
966
dmub_srv_should_detect(struct dmub_srv * dmub)967 bool dmub_srv_should_detect(struct dmub_srv *dmub)
968 {
969 if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
970 return false;
971
972 return dmub->hw_funcs.should_detect(dmub);
973 }
974
dmub_srv_clear_inbox0_ack(struct dmub_srv * dmub)975 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
976 {
977 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
978 return DMUB_STATUS_INVALID;
979
980 dmub->hw_funcs.clear_inbox0_ack_register(dmub);
981 return DMUB_STATUS_OK;
982 }
983
dmub_srv_wait_for_inbox0_ack(struct dmub_srv * dmub,uint32_t timeout_us)984 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
985 {
986 uint32_t i = 0;
987 uint32_t ack = 0;
988
989 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
990 return DMUB_STATUS_INVALID;
991
992 for (i = 0; i <= timeout_us; i++) {
993 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
994 if (ack)
995 return DMUB_STATUS_OK;
996 udelay(1);
997 }
998 return DMUB_STATUS_TIMEOUT;
999 }
1000
dmub_srv_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)1001 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
1002 union dmub_inbox0_data_register data)
1003 {
1004 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
1005 return DMUB_STATUS_INVALID;
1006
1007 dmub->hw_funcs.send_inbox0_cmd(dmub, data);
1008 return DMUB_STATUS_OK;
1009 }
1010