1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_file.h>
17 #include <drm/drm_probe_helper.h>
18
19 #include "msm_drv.h"
20 #include "dpu_kms.h"
21 #include "dpu_hwio.h"
22 #include "dpu_hw_catalog.h"
23 #include "dpu_hw_intf.h"
24 #include "dpu_hw_ctl.h"
25 #include "dpu_hw_dspp.h"
26 #include "dpu_hw_dsc.h"
27 #include "dpu_hw_merge3d.h"
28 #include "dpu_formats.h"
29 #include "dpu_encoder_phys.h"
30 #include "dpu_crtc.h"
31 #include "dpu_trace.h"
32 #include "dpu_core_irq.h"
33 #include "disp/msm_disp_snapshot.h"
34
35 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
36 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
37
38 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
40
41 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
43
44 /*
45 * Two to anticipate panels that can do cmd/vid dynamic switching
46 * plan is to create all possible physical encoder types, and switch between
47 * them at runtime
48 */
49 #define NUM_PHYS_ENCODER_TYPES 2
50
51 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
52 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
53
54 #define MAX_CHANNELS_PER_ENC 2
55
56 #define IDLE_SHORT_TIMEOUT 1
57
58 #define MAX_HDISPLAY_SPLIT 1080
59
60 /* timeout in frames waiting for frame done */
61 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
62
63 /**
64 * enum dpu_enc_rc_events - events for resource control state machine
65 * @DPU_ENC_RC_EVENT_KICKOFF:
66 * This event happens at NORMAL priority.
67 * Event that signals the start of the transfer. When this event is
68 * received, enable MDP/DSI core clocks. Regardless of the previous
69 * state, the resource should be in ON state at the end of this event.
70 * @DPU_ENC_RC_EVENT_FRAME_DONE:
71 * This event happens at INTERRUPT level.
72 * Event signals the end of the data transfer after the PP FRAME_DONE
73 * event. At the end of this event, a delayed work is scheduled to go to
74 * IDLE_PC state after IDLE_TIMEOUT time.
75 * @DPU_ENC_RC_EVENT_PRE_STOP:
76 * This event happens at NORMAL priority.
77 * This event, when received during the ON state, leave the RC STATE
78 * in the PRE_OFF state. It should be followed by the STOP event as
79 * part of encoder disable.
80 * If received during IDLE or OFF states, it will do nothing.
81 * @DPU_ENC_RC_EVENT_STOP:
82 * This event happens at NORMAL priority.
83 * When this event is received, disable all the MDP/DSI core clocks, and
84 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
85 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
86 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
87 * Resource state should be in OFF at the end of the event.
88 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
89 * This event happens at NORMAL priority from a work item.
90 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
91 * This would disable MDP/DSI core clocks and change the resource state
92 * to IDLE.
93 */
94 enum dpu_enc_rc_events {
95 DPU_ENC_RC_EVENT_KICKOFF = 1,
96 DPU_ENC_RC_EVENT_FRAME_DONE,
97 DPU_ENC_RC_EVENT_PRE_STOP,
98 DPU_ENC_RC_EVENT_STOP,
99 DPU_ENC_RC_EVENT_ENTER_IDLE
100 };
101
102 /*
103 * enum dpu_enc_rc_states - states that the resource control maintains
104 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
105 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
106 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
107 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
108 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
109 */
110 enum dpu_enc_rc_states {
111 DPU_ENC_RC_STATE_OFF,
112 DPU_ENC_RC_STATE_PRE_OFF,
113 DPU_ENC_RC_STATE_ON,
114 DPU_ENC_RC_STATE_IDLE
115 };
116
117 /**
118 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
119 * encoders. Virtual encoder manages one "logical" display. Physical
120 * encoders manage one intf block, tied to a specific panel/sub-panel.
121 * Virtual encoder defers as much as possible to the physical encoders.
122 * Virtual encoder registers itself with the DRM Framework as the encoder.
123 * @base: drm_encoder base class for registration with DRM
124 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
125 * @enabled: True if the encoder is active, protected by enc_lock
126 * @num_phys_encs: Actual number of physical encoders contained.
127 * @phys_encs: Container of physical encoders managed.
128 * @cur_master: Pointer to the current master in this mode. Optimization
129 * Only valid after enable. Cleared as disable.
130 * @cur_slave: As above but for the slave encoder.
131 * @hw_pp: Handle to the pingpong blocks used for the display. No.
132 * pingpong blocks can be different than num_phys_encs.
133 * @hw_dsc: Handle to the DSC blocks used for the display.
134 * @dsc_mask: Bitmask of used DSC blocks.
135 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
136 * for partial update right-only cases, such as pingpong
137 * split where virtual pingpong does not generate IRQs
138 * @crtc: Pointer to the currently assigned crtc. Normally you
139 * would use crtc->state->encoder_mask to determine the
140 * link between encoder/crtc. However in this case we need
141 * to track crtc in the disable() hook which is called
142 * _after_ encoder_mask is cleared.
143 * @connector: If a mode is set, cached pointer to the active connector
144 * @crtc_kickoff_cb: Callback into CRTC that will flush & start
145 * all CTL paths
146 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
147 * @debugfs_root: Debug file system root file node
148 * @enc_lock: Lock around physical encoder
149 * create/destroy/enable/disable
150 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
151 * busy processing current command.
152 * Bit0 = phys_encs[0] etc.
153 * @crtc_frame_event_cb: callback handler for frame event
154 * @crtc_frame_event_cb_data: callback handler private data
155 * @frame_done_timeout_ms: frame done timeout in ms
156 * @frame_done_timer: watchdog timer for frame done event
157 * @vsync_event_timer: vsync timer
158 * @disp_info: local copy of msm_display_info struct
159 * @idle_pc_supported: indicate if idle power collaps is supported
160 * @rc_lock: resource control mutex lock to protect
161 * virt encoder over various state changes
162 * @rc_state: resource controller state
163 * @delayed_off_work: delayed worker to schedule disabling of
164 * clks and resources after IDLE_TIMEOUT time.
165 * @vsync_event_work: worker to handle vsync event for autorefresh
166 * @topology: topology of the display
167 * @idle_timeout: idle timeout duration in milliseconds
168 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
169 */
170 struct dpu_encoder_virt {
171 struct drm_encoder base;
172 spinlock_t enc_spinlock;
173
174 bool enabled;
175
176 unsigned int num_phys_encs;
177 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
178 struct dpu_encoder_phys *cur_master;
179 struct dpu_encoder_phys *cur_slave;
180 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
181 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
182
183 unsigned int dsc_mask;
184
185 bool intfs_swapped;
186
187 struct drm_crtc *crtc;
188 struct drm_connector *connector;
189
190 struct dentry *debugfs_root;
191 struct mutex enc_lock;
192 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
193 void (*crtc_frame_event_cb)(void *, u32 event);
194 void *crtc_frame_event_cb_data;
195
196 atomic_t frame_done_timeout_ms;
197 struct timer_list frame_done_timer;
198 struct timer_list vsync_event_timer;
199
200 struct msm_display_info disp_info;
201
202 bool idle_pc_supported;
203 struct mutex rc_lock;
204 enum dpu_enc_rc_states rc_state;
205 struct delayed_work delayed_off_work;
206 struct kthread_work vsync_event_work;
207 struct msm_display_topology topology;
208
209 u32 idle_timeout;
210
211 bool wide_bus_en;
212
213 /* DSC configuration */
214 struct drm_dsc_config *dsc;
215 };
216
217 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
218
219 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
220 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
221 };
222
223
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)224 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
225 {
226 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
227
228 return dpu_enc->wide_bus_en;
229 }
230
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)231 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
232 {
233 struct dpu_encoder_virt *dpu_enc;
234 int i, num_intf = 0;
235
236 dpu_enc = to_dpu_encoder_virt(drm_enc);
237
238 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
239 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
240
241 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
242 && phys->hw_intf->ops.collect_misr)
243 num_intf++;
244 }
245
246 return num_intf;
247 }
248
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)249 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
250 {
251 struct dpu_encoder_virt *dpu_enc;
252
253 int i;
254
255 dpu_enc = to_dpu_encoder_virt(drm_enc);
256
257 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
258 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
259
260 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
261 continue;
262
263 phys->hw_intf->ops.setup_misr(phys->hw_intf);
264 }
265 }
266
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)267 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
268 {
269 struct dpu_encoder_virt *dpu_enc;
270
271 int i, rc = 0, entries_added = 0;
272
273 if (!drm_enc->crtc) {
274 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
275 return -EINVAL;
276 }
277
278 dpu_enc = to_dpu_encoder_virt(drm_enc);
279
280 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
281 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
282
283 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
284 continue;
285
286 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
287 if (rc)
288 return rc;
289 entries_added++;
290 }
291
292 return entries_added;
293 }
294
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)295 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
296 {
297 struct dpu_hw_dither_cfg dither_cfg = { 0 };
298
299 if (!hw_pp->ops.setup_dither)
300 return;
301
302 switch (bpc) {
303 case 6:
304 dither_cfg.c0_bitdepth = 6;
305 dither_cfg.c1_bitdepth = 6;
306 dither_cfg.c2_bitdepth = 6;
307 dither_cfg.c3_bitdepth = 6;
308 dither_cfg.temporal_en = 0;
309 break;
310 default:
311 hw_pp->ops.setup_dither(hw_pp, NULL);
312 return;
313 }
314
315 memcpy(&dither_cfg.matrix, dither_matrix,
316 sizeof(u32) * DITHER_MATRIX_SZ);
317
318 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
319 }
320
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)321 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
322 {
323 switch (intf_mode) {
324 case INTF_MODE_VIDEO:
325 return "INTF_MODE_VIDEO";
326 case INTF_MODE_CMD:
327 return "INTF_MODE_CMD";
328 case INTF_MODE_WB_BLOCK:
329 return "INTF_MODE_WB_BLOCK";
330 case INTF_MODE_WB_LINE:
331 return "INTF_MODE_WB_LINE";
332 default:
333 return "INTF_MODE_UNKNOWN";
334 }
335 }
336
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)337 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
338 enum dpu_intr_idx intr_idx)
339 {
340 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
341 DRMID(phys_enc->parent),
342 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
343 phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,
344 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
345
346 if (phys_enc->parent_ops->handle_frame_done)
347 phys_enc->parent_ops->handle_frame_done(
348 phys_enc->parent, phys_enc,
349 DPU_ENCODER_FRAME_EVENT_ERROR);
350 }
351
352 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
353 u32 irq_idx, struct dpu_encoder_wait_info *info);
354
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,int irq,void (* func)(void * arg,int irq_idx),struct dpu_encoder_wait_info * wait_info)355 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
356 int irq,
357 void (*func)(void *arg, int irq_idx),
358 struct dpu_encoder_wait_info *wait_info)
359 {
360 u32 irq_status;
361 int ret;
362
363 if (!wait_info) {
364 DPU_ERROR("invalid params\n");
365 return -EINVAL;
366 }
367 /* note: do master / slave checking outside */
368
369 /* return EWOULDBLOCK since we know the wait isn't necessary */
370 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
371 DRM_ERROR("encoder is disabled id=%u, callback=%ps, irq=%d\n",
372 DRMID(phys_enc->parent), func,
373 irq);
374 return -EWOULDBLOCK;
375 }
376
377 if (irq < 0) {
378 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
379 DRMID(phys_enc->parent), func);
380 return 0;
381 }
382
383 DRM_DEBUG_KMS("id=%u, callback=%ps, irq=%d, pp=%d, pending_cnt=%d\n",
384 DRMID(phys_enc->parent), func,
385 irq, phys_enc->hw_pp->idx - PINGPONG_0,
386 atomic_read(wait_info->atomic_cnt));
387
388 ret = dpu_encoder_helper_wait_event_timeout(
389 DRMID(phys_enc->parent),
390 irq,
391 wait_info);
392
393 if (ret <= 0) {
394 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq);
395 if (irq_status) {
396 unsigned long flags;
397
398 DRM_DEBUG_KMS("irq not triggered id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
399 DRMID(phys_enc->parent), func,
400 irq,
401 phys_enc->hw_pp->idx - PINGPONG_0,
402 atomic_read(wait_info->atomic_cnt));
403 local_irq_save(flags);
404 func(phys_enc, irq);
405 local_irq_restore(flags);
406 ret = 0;
407 } else {
408 ret = -ETIMEDOUT;
409 DRM_DEBUG_KMS("irq timeout id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
410 DRMID(phys_enc->parent), func,
411 irq,
412 phys_enc->hw_pp->idx - PINGPONG_0,
413 atomic_read(wait_info->atomic_cnt));
414 }
415 } else {
416 ret = 0;
417 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
418 func, irq,
419 phys_enc->hw_pp->idx - PINGPONG_0,
420 atomic_read(wait_info->atomic_cnt));
421 }
422
423 return ret;
424 }
425
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)426 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
427 {
428 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
429 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
430 return phys ? atomic_read(&phys->vsync_cnt) : 0;
431 }
432
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)433 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
434 {
435 struct dpu_encoder_virt *dpu_enc;
436 struct dpu_encoder_phys *phys;
437 int linecount = 0;
438
439 dpu_enc = to_dpu_encoder_virt(drm_enc);
440 phys = dpu_enc ? dpu_enc->cur_master : NULL;
441
442 if (phys && phys->ops.get_line_count)
443 linecount = phys->ops.get_line_count(phys);
444
445 return linecount;
446 }
447
dpu_encoder_destroy(struct drm_encoder * drm_enc)448 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
449 {
450 struct dpu_encoder_virt *dpu_enc = NULL;
451 int i = 0;
452
453 if (!drm_enc) {
454 DPU_ERROR("invalid encoder\n");
455 return;
456 }
457
458 dpu_enc = to_dpu_encoder_virt(drm_enc);
459 DPU_DEBUG_ENC(dpu_enc, "\n");
460
461 mutex_lock(&dpu_enc->enc_lock);
462
463 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
464 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
465
466 if (phys->ops.destroy) {
467 phys->ops.destroy(phys);
468 --dpu_enc->num_phys_encs;
469 dpu_enc->phys_encs[i] = NULL;
470 }
471 }
472
473 if (dpu_enc->num_phys_encs)
474 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
475 dpu_enc->num_phys_encs);
476 dpu_enc->num_phys_encs = 0;
477 mutex_unlock(&dpu_enc->enc_lock);
478
479 drm_encoder_cleanup(drm_enc);
480 mutex_destroy(&dpu_enc->enc_lock);
481 }
482
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)483 void dpu_encoder_helper_split_config(
484 struct dpu_encoder_phys *phys_enc,
485 enum dpu_intf interface)
486 {
487 struct dpu_encoder_virt *dpu_enc;
488 struct split_pipe_cfg cfg = { 0 };
489 struct dpu_hw_mdp *hw_mdptop;
490 struct msm_display_info *disp_info;
491
492 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
493 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
494 return;
495 }
496
497 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
498 hw_mdptop = phys_enc->hw_mdptop;
499 disp_info = &dpu_enc->disp_info;
500
501 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
502 return;
503
504 /**
505 * disable split modes since encoder will be operating in as the only
506 * encoder, either for the entire use case in the case of, for example,
507 * single DSI, or for this frame in the case of left/right only partial
508 * update.
509 */
510 if (phys_enc->split_role == ENC_ROLE_SOLO) {
511 if (hw_mdptop->ops.setup_split_pipe)
512 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
513 return;
514 }
515
516 cfg.en = true;
517 cfg.mode = phys_enc->intf_mode;
518 cfg.intf = interface;
519
520 if (cfg.en && phys_enc->ops.needs_single_flush &&
521 phys_enc->ops.needs_single_flush(phys_enc))
522 cfg.split_flush_en = true;
523
524 if (phys_enc->split_role == ENC_ROLE_MASTER) {
525 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
526
527 if (hw_mdptop->ops.setup_split_pipe)
528 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
529 }
530 }
531
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)532 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
533 {
534 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
535 int i, intf_count = 0, num_dsc = 0;
536
537 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
538 if (dpu_enc->phys_encs[i])
539 intf_count++;
540
541 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
542 if (dpu_enc->dsc)
543 num_dsc = 2;
544
545 return (num_dsc > 0) && (num_dsc > intf_count);
546 }
547
dpu_encoder_get_topology(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct drm_display_mode * mode)548 static struct msm_display_topology dpu_encoder_get_topology(
549 struct dpu_encoder_virt *dpu_enc,
550 struct dpu_kms *dpu_kms,
551 struct drm_display_mode *mode)
552 {
553 struct msm_display_topology topology = {0};
554 int i, intf_count = 0;
555
556 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
557 if (dpu_enc->phys_encs[i])
558 intf_count++;
559
560 /* Datapath topology selection
561 *
562 * Dual display
563 * 2 LM, 2 INTF ( Split display using 2 interfaces)
564 *
565 * Single display
566 * 1 LM, 1 INTF
567 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
568 *
569 * Adding color blocks only to primary interface if available in
570 * sufficient number
571 */
572 if (intf_count == 2)
573 topology.num_lm = 2;
574 else if (!dpu_kms->catalog->caps->has_3d_merge)
575 topology.num_lm = 1;
576 else
577 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
578
579 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
580 if (dpu_kms->catalog->dspp &&
581 (dpu_kms->catalog->dspp_count >= topology.num_lm))
582 topology.num_dspp = topology.num_lm;
583 }
584
585 topology.num_enc = 0;
586 topology.num_intf = intf_count;
587
588 if (dpu_enc->dsc) {
589 /* In case of Display Stream Compression (DSC), we would use
590 * 2 encoders, 2 layer mixers and 1 interface
591 * this is power optimal and can drive up to (including) 4k
592 * screens
593 */
594 topology.num_enc = 2;
595 topology.num_dsc = 2;
596 topology.num_intf = 1;
597 topology.num_lm = 2;
598 }
599
600 return topology;
601 }
602
dpu_encoder_virt_atomic_check(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)603 static int dpu_encoder_virt_atomic_check(
604 struct drm_encoder *drm_enc,
605 struct drm_crtc_state *crtc_state,
606 struct drm_connector_state *conn_state)
607 {
608 struct dpu_encoder_virt *dpu_enc;
609 struct msm_drm_private *priv;
610 struct dpu_kms *dpu_kms;
611 struct drm_display_mode *adj_mode;
612 struct msm_display_topology topology;
613 struct dpu_global_state *global_state;
614 int i = 0;
615 int ret = 0;
616
617 if (!drm_enc || !crtc_state || !conn_state) {
618 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
619 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
620 return -EINVAL;
621 }
622
623 dpu_enc = to_dpu_encoder_virt(drm_enc);
624 DPU_DEBUG_ENC(dpu_enc, "\n");
625
626 priv = drm_enc->dev->dev_private;
627 dpu_kms = to_dpu_kms(priv->kms);
628 adj_mode = &crtc_state->adjusted_mode;
629 global_state = dpu_kms_get_global_state(crtc_state->state);
630 if (IS_ERR(global_state))
631 return PTR_ERR(global_state);
632
633 trace_dpu_enc_atomic_check(DRMID(drm_enc));
634
635 /* perform atomic check on the first physical encoder (master) */
636 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
637 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
638
639 if (phys->ops.atomic_check)
640 ret = phys->ops.atomic_check(phys, crtc_state,
641 conn_state);
642 if (ret) {
643 DPU_ERROR_ENC(dpu_enc,
644 "mode unsupported, phys idx %d\n", i);
645 break;
646 }
647 }
648
649 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
650
651 /* Reserve dynamic resources now. */
652 if (!ret) {
653 /*
654 * Release and Allocate resources on every modeset
655 * Dont allocate when active is false.
656 */
657 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
658 dpu_rm_release(global_state, drm_enc);
659
660 if (!crtc_state->active_changed || crtc_state->enable)
661 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
662 drm_enc, crtc_state, topology);
663 }
664 }
665
666 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
667
668 return ret;
669 }
670
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)671 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
672 struct msm_display_info *disp_info)
673 {
674 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
675 struct msm_drm_private *priv;
676 struct dpu_kms *dpu_kms;
677 struct dpu_hw_mdp *hw_mdptop;
678 struct drm_encoder *drm_enc;
679 int i;
680
681 if (!dpu_enc || !disp_info) {
682 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
683 dpu_enc != NULL, disp_info != NULL);
684 return;
685 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
686 DPU_ERROR("invalid num phys enc %d/%d\n",
687 dpu_enc->num_phys_encs,
688 (int) ARRAY_SIZE(dpu_enc->hw_pp));
689 return;
690 }
691
692 drm_enc = &dpu_enc->base;
693 /* this pointers are checked in virt_enable_helper */
694 priv = drm_enc->dev->dev_private;
695
696 dpu_kms = to_dpu_kms(priv->kms);
697 hw_mdptop = dpu_kms->hw_mdp;
698 if (!hw_mdptop) {
699 DPU_ERROR("invalid mdptop\n");
700 return;
701 }
702
703 if (hw_mdptop->ops.setup_vsync_source &&
704 disp_info->is_cmd_mode) {
705 for (i = 0; i < dpu_enc->num_phys_encs; i++)
706 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
707
708 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
709 if (disp_info->is_te_using_watchdog_timer)
710 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
711 else
712 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
713
714 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
715 }
716 }
717
_dpu_encoder_irq_control(struct drm_encoder * drm_enc,bool enable)718 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
719 {
720 struct dpu_encoder_virt *dpu_enc;
721 int i;
722
723 if (!drm_enc) {
724 DPU_ERROR("invalid encoder\n");
725 return;
726 }
727
728 dpu_enc = to_dpu_encoder_virt(drm_enc);
729
730 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
731 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
732 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
733
734 if (phys->ops.irq_control)
735 phys->ops.irq_control(phys, enable);
736 }
737
738 }
739
_dpu_encoder_resource_control_helper(struct drm_encoder * drm_enc,bool enable)740 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
741 bool enable)
742 {
743 struct msm_drm_private *priv;
744 struct dpu_kms *dpu_kms;
745 struct dpu_encoder_virt *dpu_enc;
746
747 dpu_enc = to_dpu_encoder_virt(drm_enc);
748 priv = drm_enc->dev->dev_private;
749 dpu_kms = to_dpu_kms(priv->kms);
750
751 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
752
753 if (!dpu_enc->cur_master) {
754 DPU_ERROR("encoder master not set\n");
755 return;
756 }
757
758 if (enable) {
759 /* enable DPU core clks */
760 pm_runtime_get_sync(&dpu_kms->pdev->dev);
761
762 /* enable all the irq */
763 _dpu_encoder_irq_control(drm_enc, true);
764
765 } else {
766 /* disable all the irq */
767 _dpu_encoder_irq_control(drm_enc, false);
768
769 /* disable DPU core clks */
770 pm_runtime_put_sync(&dpu_kms->pdev->dev);
771 }
772
773 }
774
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)775 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
776 u32 sw_event)
777 {
778 struct dpu_encoder_virt *dpu_enc;
779 struct msm_drm_private *priv;
780 bool is_vid_mode = false;
781
782 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
783 DPU_ERROR("invalid parameters\n");
784 return -EINVAL;
785 }
786 dpu_enc = to_dpu_encoder_virt(drm_enc);
787 priv = drm_enc->dev->dev_private;
788 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
789
790 /*
791 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
792 * events and return early for other events (ie wb display).
793 */
794 if (!dpu_enc->idle_pc_supported &&
795 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
796 sw_event != DPU_ENC_RC_EVENT_STOP &&
797 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
798 return 0;
799
800 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
801 dpu_enc->rc_state, "begin");
802
803 switch (sw_event) {
804 case DPU_ENC_RC_EVENT_KICKOFF:
805 /* cancel delayed off work, if any */
806 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
807 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
808 sw_event);
809
810 mutex_lock(&dpu_enc->rc_lock);
811
812 /* return if the resource control is already in ON state */
813 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
814 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
815 DRMID(drm_enc), sw_event);
816 mutex_unlock(&dpu_enc->rc_lock);
817 return 0;
818 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
819 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
820 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
821 DRMID(drm_enc), sw_event,
822 dpu_enc->rc_state);
823 mutex_unlock(&dpu_enc->rc_lock);
824 return -EINVAL;
825 }
826
827 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
828 _dpu_encoder_irq_control(drm_enc, true);
829 else
830 _dpu_encoder_resource_control_helper(drm_enc, true);
831
832 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
833
834 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
835 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
836 "kickoff");
837
838 mutex_unlock(&dpu_enc->rc_lock);
839 break;
840
841 case DPU_ENC_RC_EVENT_FRAME_DONE:
842 /*
843 * mutex lock is not used as this event happens at interrupt
844 * context. And locking is not required as, the other events
845 * like KICKOFF and STOP does a wait-for-idle before executing
846 * the resource_control
847 */
848 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
849 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
850 DRMID(drm_enc), sw_event,
851 dpu_enc->rc_state);
852 return -EINVAL;
853 }
854
855 /*
856 * schedule off work item only when there are no
857 * frames pending
858 */
859 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
860 DRM_DEBUG_KMS("id:%d skip schedule work\n",
861 DRMID(drm_enc));
862 return 0;
863 }
864
865 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
866 msecs_to_jiffies(dpu_enc->idle_timeout));
867
868 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
869 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
870 "frame done");
871 break;
872
873 case DPU_ENC_RC_EVENT_PRE_STOP:
874 /* cancel delayed off work, if any */
875 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
876 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
877 sw_event);
878
879 mutex_lock(&dpu_enc->rc_lock);
880
881 if (is_vid_mode &&
882 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
883 _dpu_encoder_irq_control(drm_enc, true);
884 }
885 /* skip if is already OFF or IDLE, resources are off already */
886 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
887 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
888 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
889 DRMID(drm_enc), sw_event,
890 dpu_enc->rc_state);
891 mutex_unlock(&dpu_enc->rc_lock);
892 return 0;
893 }
894
895 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
896
897 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
898 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
899 "pre stop");
900
901 mutex_unlock(&dpu_enc->rc_lock);
902 break;
903
904 case DPU_ENC_RC_EVENT_STOP:
905 mutex_lock(&dpu_enc->rc_lock);
906
907 /* return if the resource control is already in OFF state */
908 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
909 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
910 DRMID(drm_enc), sw_event);
911 mutex_unlock(&dpu_enc->rc_lock);
912 return 0;
913 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
914 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
915 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
916 mutex_unlock(&dpu_enc->rc_lock);
917 return -EINVAL;
918 }
919
920 /**
921 * expect to arrive here only if in either idle state or pre-off
922 * and in IDLE state the resources are already disabled
923 */
924 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
925 _dpu_encoder_resource_control_helper(drm_enc, false);
926
927 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
928
929 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
930 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
931 "stop");
932
933 mutex_unlock(&dpu_enc->rc_lock);
934 break;
935
936 case DPU_ENC_RC_EVENT_ENTER_IDLE:
937 mutex_lock(&dpu_enc->rc_lock);
938
939 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
940 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
941 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
942 mutex_unlock(&dpu_enc->rc_lock);
943 return 0;
944 }
945
946 /*
947 * if we are in ON but a frame was just kicked off,
948 * ignore the IDLE event, it's probably a stale timer event
949 */
950 if (dpu_enc->frame_busy_mask[0]) {
951 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
952 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
953 mutex_unlock(&dpu_enc->rc_lock);
954 return 0;
955 }
956
957 if (is_vid_mode)
958 _dpu_encoder_irq_control(drm_enc, false);
959 else
960 _dpu_encoder_resource_control_helper(drm_enc, false);
961
962 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
963
964 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
965 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
966 "idle");
967
968 mutex_unlock(&dpu_enc->rc_lock);
969 break;
970
971 default:
972 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
973 sw_event);
974 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
975 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
976 "error");
977 break;
978 }
979
980 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
981 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
982 "end");
983 return 0;
984 }
985
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)986 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
987 struct drm_writeback_job *job)
988 {
989 struct dpu_encoder_virt *dpu_enc;
990 int i;
991
992 dpu_enc = to_dpu_encoder_virt(drm_enc);
993
994 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
995 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
996
997 if (phys->ops.prepare_wb_job)
998 phys->ops.prepare_wb_job(phys, job);
999
1000 }
1001 }
1002
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1003 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1004 struct drm_writeback_job *job)
1005 {
1006 struct dpu_encoder_virt *dpu_enc;
1007 int i;
1008
1009 dpu_enc = to_dpu_encoder_virt(drm_enc);
1010
1011 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1012 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1013
1014 if (phys->ops.cleanup_wb_job)
1015 phys->ops.cleanup_wb_job(phys, job);
1016
1017 }
1018 }
1019
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1020 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1021 struct drm_crtc_state *crtc_state,
1022 struct drm_connector_state *conn_state)
1023 {
1024 struct dpu_encoder_virt *dpu_enc;
1025 struct msm_drm_private *priv;
1026 struct dpu_kms *dpu_kms;
1027 struct dpu_crtc_state *cstate;
1028 struct dpu_global_state *global_state;
1029 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1030 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1031 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
1032 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
1033 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1034 int num_lm, num_ctl, num_pp, num_dsc;
1035 unsigned int dsc_mask = 0;
1036 int i;
1037
1038 if (!drm_enc) {
1039 DPU_ERROR("invalid encoder\n");
1040 return;
1041 }
1042
1043 dpu_enc = to_dpu_encoder_virt(drm_enc);
1044 DPU_DEBUG_ENC(dpu_enc, "\n");
1045
1046 priv = drm_enc->dev->dev_private;
1047 dpu_kms = to_dpu_kms(priv->kms);
1048
1049 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1050 if (IS_ERR_OR_NULL(global_state)) {
1051 DPU_ERROR("Failed to get global state");
1052 return;
1053 }
1054
1055 trace_dpu_enc_mode_set(DRMID(drm_enc));
1056
1057 /* Query resource that have been reserved in atomic check step. */
1058 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1059 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1060 ARRAY_SIZE(hw_pp));
1061 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1062 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1063 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1064 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1065 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1066 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1067 ARRAY_SIZE(hw_dspp));
1068
1069 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1070 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1071 : NULL;
1072
1073 if (dpu_enc->dsc) {
1074 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1075 drm_enc->base.id, DPU_HW_BLK_DSC,
1076 hw_dsc, ARRAY_SIZE(hw_dsc));
1077 for (i = 0; i < num_dsc; i++) {
1078 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1079 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1080 }
1081 }
1082
1083 dpu_enc->dsc_mask = dsc_mask;
1084
1085 cstate = to_dpu_crtc_state(crtc_state);
1086
1087 for (i = 0; i < num_lm; i++) {
1088 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1089
1090 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1091 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1092 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1093 }
1094
1095 cstate->num_mixers = num_lm;
1096
1097 dpu_enc->connector = conn_state->connector;
1098
1099 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1100 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1101
1102 if (!dpu_enc->hw_pp[i]) {
1103 DPU_ERROR_ENC(dpu_enc,
1104 "no pp block assigned at idx: %d\n", i);
1105 return;
1106 }
1107
1108 if (!hw_ctl[i]) {
1109 DPU_ERROR_ENC(dpu_enc,
1110 "no ctl block assigned at idx: %d\n", i);
1111 return;
1112 }
1113
1114 phys->hw_pp = dpu_enc->hw_pp[i];
1115 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1116
1117 phys->cached_mode = crtc_state->adjusted_mode;
1118 if (phys->ops.atomic_mode_set)
1119 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1120 }
1121 }
1122
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1123 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1124 {
1125 struct dpu_encoder_virt *dpu_enc = NULL;
1126 int i;
1127
1128 if (!drm_enc || !drm_enc->dev) {
1129 DPU_ERROR("invalid parameters\n");
1130 return;
1131 }
1132
1133 dpu_enc = to_dpu_encoder_virt(drm_enc);
1134 if (!dpu_enc || !dpu_enc->cur_master) {
1135 DPU_ERROR("invalid dpu encoder/master\n");
1136 return;
1137 }
1138
1139
1140 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
1141 dpu_enc->cur_master->hw_mdptop &&
1142 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1143 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1144 dpu_enc->cur_master->hw_mdptop);
1145
1146 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1147
1148 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1149 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1150 unsigned bpc = dpu_enc->connector->display_info.bpc;
1151 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1152 if (!dpu_enc->hw_pp[i])
1153 continue;
1154 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1155 }
1156 }
1157 }
1158
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1159 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1160 {
1161 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1162
1163 mutex_lock(&dpu_enc->enc_lock);
1164
1165 if (!dpu_enc->enabled)
1166 goto out;
1167
1168 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1169 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1170 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1171 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1172
1173 _dpu_encoder_virt_enable_helper(drm_enc);
1174
1175 out:
1176 mutex_unlock(&dpu_enc->enc_lock);
1177 }
1178
dpu_encoder_virt_enable(struct drm_encoder * drm_enc)1179 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1180 {
1181 struct dpu_encoder_virt *dpu_enc = NULL;
1182 int ret = 0;
1183 struct drm_display_mode *cur_mode = NULL;
1184
1185 dpu_enc = to_dpu_encoder_virt(drm_enc);
1186
1187 mutex_lock(&dpu_enc->enc_lock);
1188 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1189
1190 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1191 cur_mode->vdisplay);
1192
1193 /* always enable slave encoder before master */
1194 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1195 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1196
1197 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1198 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1199
1200 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1201 if (ret) {
1202 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1203 ret);
1204 goto out;
1205 }
1206
1207 _dpu_encoder_virt_enable_helper(drm_enc);
1208
1209 dpu_enc->enabled = true;
1210
1211 out:
1212 mutex_unlock(&dpu_enc->enc_lock);
1213 }
1214
dpu_encoder_virt_disable(struct drm_encoder * drm_enc)1215 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1216 {
1217 struct dpu_encoder_virt *dpu_enc = NULL;
1218 int i = 0;
1219
1220 dpu_enc = to_dpu_encoder_virt(drm_enc);
1221 DPU_DEBUG_ENC(dpu_enc, "\n");
1222
1223 mutex_lock(&dpu_enc->enc_lock);
1224 dpu_enc->enabled = false;
1225
1226 trace_dpu_enc_disable(DRMID(drm_enc));
1227
1228 /* wait for idle */
1229 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1230
1231 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1232
1233 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1234 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1235
1236 if (phys->ops.disable)
1237 phys->ops.disable(phys);
1238 }
1239
1240
1241 /* after phys waits for frame-done, should be no more frames pending */
1242 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1243 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1244 del_timer_sync(&dpu_enc->frame_done_timer);
1245 }
1246
1247 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1248
1249 dpu_enc->connector = NULL;
1250
1251 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1252
1253 mutex_unlock(&dpu_enc->enc_lock);
1254 }
1255
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,enum dpu_intf_type type,u32 controller_id)1256 static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1257 enum dpu_intf_type type, u32 controller_id)
1258 {
1259 int i = 0;
1260
1261 if (type == INTF_WB)
1262 return INTF_MAX;
1263
1264 for (i = 0; i < catalog->intf_count; i++) {
1265 if (catalog->intf[i].type == type
1266 && catalog->intf[i].controller_id == controller_id) {
1267 return catalog->intf[i].id;
1268 }
1269 }
1270
1271 return INTF_MAX;
1272 }
1273
dpu_encoder_get_wb(const struct dpu_mdss_cfg * catalog,enum dpu_intf_type type,u32 controller_id)1274 static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog,
1275 enum dpu_intf_type type, u32 controller_id)
1276 {
1277 int i = 0;
1278
1279 if (type != INTF_WB)
1280 return WB_MAX;
1281
1282 for (i = 0; i < catalog->wb_count; i++) {
1283 if (catalog->wb[i].id == controller_id)
1284 return catalog->wb[i].id;
1285 }
1286
1287 return WB_MAX;
1288 }
1289
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1290 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1291 struct dpu_encoder_phys *phy_enc)
1292 {
1293 struct dpu_encoder_virt *dpu_enc = NULL;
1294 unsigned long lock_flags;
1295
1296 if (!drm_enc || !phy_enc)
1297 return;
1298
1299 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1300 dpu_enc = to_dpu_encoder_virt(drm_enc);
1301
1302 atomic_inc(&phy_enc->vsync_cnt);
1303
1304 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1305 if (dpu_enc->crtc)
1306 dpu_crtc_vblank_callback(dpu_enc->crtc);
1307 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1308
1309 DPU_ATRACE_END("encoder_vblank_callback");
1310 }
1311
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1312 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1313 struct dpu_encoder_phys *phy_enc)
1314 {
1315 if (!phy_enc)
1316 return;
1317
1318 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1319 atomic_inc(&phy_enc->underrun_cnt);
1320
1321 /* trigger dump only on the first underrun */
1322 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1323 msm_disp_snapshot_state(drm_enc->dev);
1324
1325 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1326 atomic_read(&phy_enc->underrun_cnt));
1327 DPU_ATRACE_END("encoder_underrun_callback");
1328 }
1329
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1330 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1331 {
1332 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1333 unsigned long lock_flags;
1334
1335 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1336 /* crtc should always be cleared before re-assigning */
1337 WARN_ON(crtc && dpu_enc->crtc);
1338 dpu_enc->crtc = crtc;
1339 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1340 }
1341
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1342 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1343 struct drm_crtc *crtc, bool enable)
1344 {
1345 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1346 unsigned long lock_flags;
1347 int i;
1348
1349 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1350
1351 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1352 if (dpu_enc->crtc != crtc) {
1353 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1354 return;
1355 }
1356 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1357
1358 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1359 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1360
1361 if (phys->ops.control_vblank_irq)
1362 phys->ops.control_vblank_irq(phys, enable);
1363 }
1364 }
1365
dpu_encoder_register_frame_event_callback(struct drm_encoder * drm_enc,void (* frame_event_cb)(void *,u32 event),void * frame_event_cb_data)1366 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1367 void (*frame_event_cb)(void *, u32 event),
1368 void *frame_event_cb_data)
1369 {
1370 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1371 unsigned long lock_flags;
1372 bool enable;
1373
1374 enable = frame_event_cb ? true : false;
1375
1376 if (!drm_enc) {
1377 DPU_ERROR("invalid encoder\n");
1378 return;
1379 }
1380 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1381
1382 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1383 dpu_enc->crtc_frame_event_cb = frame_event_cb;
1384 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1385 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1386 }
1387
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1388 static void dpu_encoder_frame_done_callback(
1389 struct drm_encoder *drm_enc,
1390 struct dpu_encoder_phys *ready_phys, u32 event)
1391 {
1392 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1393 unsigned int i;
1394
1395 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1396 | DPU_ENCODER_FRAME_EVENT_ERROR
1397 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1398
1399 if (!dpu_enc->frame_busy_mask[0]) {
1400 /**
1401 * suppress frame_done without waiter,
1402 * likely autorefresh
1403 */
1404 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1405 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1406 ready_phys->intf_idx, ready_phys->wb_idx);
1407 return;
1408 }
1409
1410 /* One of the physical encoders has become idle */
1411 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1412 if (dpu_enc->phys_encs[i] == ready_phys) {
1413 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1414 dpu_enc->frame_busy_mask[0]);
1415 clear_bit(i, dpu_enc->frame_busy_mask);
1416 }
1417 }
1418
1419 if (!dpu_enc->frame_busy_mask[0]) {
1420 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1421 del_timer(&dpu_enc->frame_done_timer);
1422
1423 dpu_encoder_resource_control(drm_enc,
1424 DPU_ENC_RC_EVENT_FRAME_DONE);
1425
1426 if (dpu_enc->crtc_frame_event_cb)
1427 dpu_enc->crtc_frame_event_cb(
1428 dpu_enc->crtc_frame_event_cb_data,
1429 event);
1430 }
1431 } else {
1432 if (dpu_enc->crtc_frame_event_cb)
1433 dpu_enc->crtc_frame_event_cb(
1434 dpu_enc->crtc_frame_event_cb_data, event);
1435 }
1436 }
1437
dpu_encoder_off_work(struct work_struct * work)1438 static void dpu_encoder_off_work(struct work_struct *work)
1439 {
1440 struct dpu_encoder_virt *dpu_enc = container_of(work,
1441 struct dpu_encoder_virt, delayed_off_work.work);
1442
1443 dpu_encoder_resource_control(&dpu_enc->base,
1444 DPU_ENC_RC_EVENT_ENTER_IDLE);
1445
1446 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1447 DPU_ENCODER_FRAME_EVENT_IDLE);
1448 }
1449
1450 /**
1451 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1452 * @drm_enc: Pointer to drm encoder structure
1453 * @phys: Pointer to physical encoder structure
1454 * @extra_flush_bits: Additional bit mask to include in flush trigger
1455 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1456 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1457 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1458 {
1459 struct dpu_hw_ctl *ctl;
1460 int pending_kickoff_cnt;
1461 u32 ret = UINT_MAX;
1462
1463 if (!phys->hw_pp) {
1464 DPU_ERROR("invalid pingpong hw\n");
1465 return;
1466 }
1467
1468 ctl = phys->hw_ctl;
1469 if (!ctl->ops.trigger_flush) {
1470 DPU_ERROR("missing trigger cb\n");
1471 return;
1472 }
1473
1474 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1475
1476 if (extra_flush_bits && ctl->ops.update_pending_flush)
1477 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1478
1479 ctl->ops.trigger_flush(ctl);
1480
1481 if (ctl->ops.get_pending_flush)
1482 ret = ctl->ops.get_pending_flush(ctl);
1483
1484 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1485 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1486 phys->intf_idx, phys->wb_idx,
1487 pending_kickoff_cnt, ctl->idx,
1488 extra_flush_bits, ret);
1489 }
1490
1491 /**
1492 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1493 * @phys: Pointer to physical encoder structure
1494 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1495 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1496 {
1497 if (!phys) {
1498 DPU_ERROR("invalid argument(s)\n");
1499 return;
1500 }
1501
1502 if (!phys->hw_pp) {
1503 DPU_ERROR("invalid pingpong hw\n");
1504 return;
1505 }
1506
1507 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1508 phys->ops.trigger_start(phys);
1509 }
1510
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1511 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1512 {
1513 struct dpu_hw_ctl *ctl;
1514
1515 ctl = phys_enc->hw_ctl;
1516 if (ctl->ops.trigger_start) {
1517 ctl->ops.trigger_start(ctl);
1518 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1519 }
1520 }
1521
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,u32 irq_idx,struct dpu_encoder_wait_info * info)1522 static int dpu_encoder_helper_wait_event_timeout(
1523 int32_t drm_id,
1524 u32 irq_idx,
1525 struct dpu_encoder_wait_info *info)
1526 {
1527 int rc = 0;
1528 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1529 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1530 s64 time;
1531
1532 do {
1533 rc = wait_event_timeout(*(info->wq),
1534 atomic_read(info->atomic_cnt) == 0, jiffies);
1535 time = ktime_to_ms(ktime_get());
1536
1537 trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1538 expected_time,
1539 atomic_read(info->atomic_cnt));
1540 /* If we timed out, counter is valid and time is less, wait again */
1541 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1542 (time < expected_time));
1543
1544 return rc;
1545 }
1546
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1547 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1548 {
1549 struct dpu_encoder_virt *dpu_enc;
1550 struct dpu_hw_ctl *ctl;
1551 int rc;
1552 struct drm_encoder *drm_enc;
1553
1554 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1555 ctl = phys_enc->hw_ctl;
1556 drm_enc = phys_enc->parent;
1557
1558 if (!ctl->ops.reset)
1559 return;
1560
1561 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1562 ctl->idx);
1563
1564 rc = ctl->ops.reset(ctl);
1565 if (rc) {
1566 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1567 msm_disp_snapshot_state(drm_enc->dev);
1568 }
1569
1570 phys_enc->enable_state = DPU_ENC_ENABLED;
1571 }
1572
1573 /**
1574 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1575 * Iterate through the physical encoders and perform consolidated flush
1576 * and/or control start triggering as needed. This is done in the virtual
1577 * encoder rather than the individual physical ones in order to handle
1578 * use cases that require visibility into multiple physical encoders at
1579 * a time.
1580 * @dpu_enc: Pointer to virtual encoder structure
1581 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1582 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1583 {
1584 struct dpu_hw_ctl *ctl;
1585 uint32_t i, pending_flush;
1586 unsigned long lock_flags;
1587
1588 pending_flush = 0x0;
1589
1590 /* update pending counts and trigger kickoff ctl flush atomically */
1591 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1592
1593 /* don't perform flush/start operations for slave encoders */
1594 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1595 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1596
1597 if (phys->enable_state == DPU_ENC_DISABLED)
1598 continue;
1599
1600 ctl = phys->hw_ctl;
1601
1602 /*
1603 * This is cleared in frame_done worker, which isn't invoked
1604 * for async commits. So don't set this for async, since it'll
1605 * roll over to the next commit.
1606 */
1607 if (phys->split_role != ENC_ROLE_SLAVE)
1608 set_bit(i, dpu_enc->frame_busy_mask);
1609
1610 if (!phys->ops.needs_single_flush ||
1611 !phys->ops.needs_single_flush(phys))
1612 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1613 else if (ctl->ops.get_pending_flush)
1614 pending_flush |= ctl->ops.get_pending_flush(ctl);
1615 }
1616
1617 /* for split flush, combine pending flush masks and send to master */
1618 if (pending_flush && dpu_enc->cur_master) {
1619 _dpu_encoder_trigger_flush(
1620 &dpu_enc->base,
1621 dpu_enc->cur_master,
1622 pending_flush);
1623 }
1624
1625 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1626
1627 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1628 }
1629
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1630 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1631 {
1632 struct dpu_encoder_virt *dpu_enc;
1633 struct dpu_encoder_phys *phys;
1634 unsigned int i;
1635 struct dpu_hw_ctl *ctl;
1636 struct msm_display_info *disp_info;
1637
1638 if (!drm_enc) {
1639 DPU_ERROR("invalid encoder\n");
1640 return;
1641 }
1642 dpu_enc = to_dpu_encoder_virt(drm_enc);
1643 disp_info = &dpu_enc->disp_info;
1644
1645 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1646 phys = dpu_enc->phys_encs[i];
1647
1648 ctl = phys->hw_ctl;
1649 if (ctl->ops.clear_pending_flush)
1650 ctl->ops.clear_pending_flush(ctl);
1651
1652 /* update only for command mode primary ctl */
1653 if ((phys == dpu_enc->cur_master) &&
1654 disp_info->is_cmd_mode
1655 && ctl->ops.trigger_pending)
1656 ctl->ops.trigger_pending(ctl);
1657 }
1658 }
1659
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1660 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1661 struct drm_display_mode *mode)
1662 {
1663 u64 pclk_rate;
1664 u32 pclk_period;
1665 u32 line_time;
1666
1667 /*
1668 * For linetime calculation, only operate on master encoder.
1669 */
1670 if (!dpu_enc->cur_master)
1671 return 0;
1672
1673 if (!dpu_enc->cur_master->ops.get_line_count) {
1674 DPU_ERROR("get_line_count function not defined\n");
1675 return 0;
1676 }
1677
1678 pclk_rate = mode->clock; /* pixel clock in kHz */
1679 if (pclk_rate == 0) {
1680 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1681 return 0;
1682 }
1683
1684 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1685 if (pclk_period == 0) {
1686 DPU_ERROR("pclk period is 0\n");
1687 return 0;
1688 }
1689
1690 /*
1691 * Line time calculation based on Pixel clock and HTOTAL.
1692 * Final unit is in ns.
1693 */
1694 line_time = (pclk_period * mode->htotal) / 1000;
1695 if (line_time == 0) {
1696 DPU_ERROR("line time calculation is 0\n");
1697 return 0;
1698 }
1699
1700 DPU_DEBUG_ENC(dpu_enc,
1701 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1702 pclk_rate, pclk_period, line_time);
1703
1704 return line_time;
1705 }
1706
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1707 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1708 {
1709 struct drm_display_mode *mode;
1710 struct dpu_encoder_virt *dpu_enc;
1711 u32 cur_line;
1712 u32 line_time;
1713 u32 vtotal, time_to_vsync;
1714 ktime_t cur_time;
1715
1716 dpu_enc = to_dpu_encoder_virt(drm_enc);
1717
1718 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1719 DPU_ERROR("crtc/crtc state object is NULL\n");
1720 return -EINVAL;
1721 }
1722 mode = &drm_enc->crtc->state->adjusted_mode;
1723
1724 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1725 if (!line_time)
1726 return -EINVAL;
1727
1728 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1729
1730 vtotal = mode->vtotal;
1731 if (cur_line >= vtotal)
1732 time_to_vsync = line_time * vtotal;
1733 else
1734 time_to_vsync = line_time * (vtotal - cur_line);
1735
1736 if (time_to_vsync == 0) {
1737 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1738 vtotal);
1739 return -EINVAL;
1740 }
1741
1742 cur_time = ktime_get();
1743 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1744
1745 DPU_DEBUG_ENC(dpu_enc,
1746 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1747 cur_line, vtotal, time_to_vsync,
1748 ktime_to_ms(cur_time),
1749 ktime_to_ms(*wakeup_time));
1750 return 0;
1751 }
1752
dpu_encoder_vsync_event_handler(struct timer_list * t)1753 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1754 {
1755 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1756 vsync_event_timer);
1757 struct drm_encoder *drm_enc = &dpu_enc->base;
1758 struct msm_drm_private *priv;
1759 struct msm_drm_thread *event_thread;
1760
1761 if (!drm_enc->dev || !drm_enc->crtc) {
1762 DPU_ERROR("invalid parameters\n");
1763 return;
1764 }
1765
1766 priv = drm_enc->dev->dev_private;
1767
1768 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1769 DPU_ERROR("invalid crtc index\n");
1770 return;
1771 }
1772 event_thread = &priv->event_thread[drm_enc->crtc->index];
1773 if (!event_thread) {
1774 DPU_ERROR("event_thread not found for crtc:%d\n",
1775 drm_enc->crtc->index);
1776 return;
1777 }
1778
1779 del_timer(&dpu_enc->vsync_event_timer);
1780 }
1781
dpu_encoder_vsync_event_work_handler(struct kthread_work * work)1782 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1783 {
1784 struct dpu_encoder_virt *dpu_enc = container_of(work,
1785 struct dpu_encoder_virt, vsync_event_work);
1786 ktime_t wakeup_time;
1787
1788 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1789 return;
1790
1791 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1792 mod_timer(&dpu_enc->vsync_event_timer,
1793 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1794 }
1795
1796 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1797 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1798 u32 enc_ip_width)
1799 {
1800 int ssm_delay, total_pixels, soft_slice_per_enc;
1801
1802 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1803
1804 /*
1805 * minimum number of initial line pixels is a sum of:
1806 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1807 * 91 for 10 bpc) * 3
1808 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1809 * 3. the initial xmit delay
1810 * 4. total pipeline delay through the "lock step" of encoder (47)
1811 * 5. 6 additional pixels as the output of the rate buffer is
1812 * 48 bits wide
1813 */
1814 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1815 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1816 if (soft_slice_per_enc > 1)
1817 total_pixels += (ssm_delay * 3);
1818 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1819 }
1820
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1821 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
1822 struct dpu_hw_pingpong *hw_pp,
1823 struct drm_dsc_config *dsc,
1824 u32 common_mode,
1825 u32 initial_lines)
1826 {
1827 if (hw_dsc->ops.dsc_config)
1828 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1829
1830 if (hw_dsc->ops.dsc_config_thresh)
1831 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1832
1833 if (hw_pp->ops.setup_dsc)
1834 hw_pp->ops.setup_dsc(hw_pp);
1835
1836 if (hw_pp->ops.enable_dsc)
1837 hw_pp->ops.enable_dsc(hw_pp);
1838 }
1839
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)1840 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
1841 struct drm_dsc_config *dsc)
1842 {
1843 /* coding only for 2LM, 2enc, 1 dsc config */
1844 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
1845 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
1846 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
1847 int this_frame_slices;
1848 int intf_ip_w, enc_ip_w;
1849 int dsc_common_mode;
1850 int pic_width;
1851 u32 initial_lines;
1852 int i;
1853
1854 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1855 hw_pp[i] = dpu_enc->hw_pp[i];
1856 hw_dsc[i] = dpu_enc->hw_dsc[i];
1857
1858 if (!hw_pp[i] || !hw_dsc[i]) {
1859 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
1860 return;
1861 }
1862 }
1863
1864 dsc_common_mode = 0;
1865 pic_width = dsc->pic_width;
1866
1867 dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
1868 if (enc_master->intf_mode == INTF_MODE_VIDEO)
1869 dsc_common_mode |= DSC_MODE_VIDEO;
1870
1871 this_frame_slices = pic_width / dsc->slice_width;
1872 intf_ip_w = this_frame_slices * dsc->slice_width;
1873
1874 /*
1875 * dsc merge case: when using 2 encoders for the same stream,
1876 * no. of slices need to be same on both the encoders.
1877 */
1878 enc_ip_w = intf_ip_w / 2;
1879 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
1880
1881 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1882 dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);
1883 }
1884
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)1885 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1886 {
1887 struct dpu_encoder_virt *dpu_enc;
1888 struct dpu_encoder_phys *phys;
1889 bool needs_hw_reset = false;
1890 unsigned int i;
1891
1892 dpu_enc = to_dpu_encoder_virt(drm_enc);
1893
1894 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1895
1896 /* prepare for next kickoff, may include waiting on previous kickoff */
1897 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1898 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1899 phys = dpu_enc->phys_encs[i];
1900 if (phys->ops.prepare_for_kickoff)
1901 phys->ops.prepare_for_kickoff(phys);
1902 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1903 needs_hw_reset = true;
1904 }
1905 DPU_ATRACE_END("enc_prepare_for_kickoff");
1906
1907 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1908
1909 /* if any phys needs reset, reset all phys, in-order */
1910 if (needs_hw_reset) {
1911 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1912 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1913 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1914 }
1915 }
1916
1917 if (dpu_enc->dsc)
1918 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
1919 }
1920
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)1921 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
1922 {
1923 struct dpu_encoder_virt *dpu_enc;
1924 unsigned int i;
1925 struct dpu_encoder_phys *phys;
1926
1927 dpu_enc = to_dpu_encoder_virt(drm_enc);
1928
1929 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1930 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1931 phys = dpu_enc->phys_encs[i];
1932 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
1933 DPU_DEBUG("invalid FB not kicking off\n");
1934 return false;
1935 }
1936 }
1937 }
1938
1939 return true;
1940 }
1941
dpu_encoder_kickoff(struct drm_encoder * drm_enc)1942 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1943 {
1944 struct dpu_encoder_virt *dpu_enc;
1945 struct dpu_encoder_phys *phys;
1946 ktime_t wakeup_time;
1947 unsigned long timeout_ms;
1948 unsigned int i;
1949
1950 DPU_ATRACE_BEGIN("encoder_kickoff");
1951 dpu_enc = to_dpu_encoder_virt(drm_enc);
1952
1953 trace_dpu_enc_kickoff(DRMID(drm_enc));
1954
1955 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1956 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1957
1958 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1959 mod_timer(&dpu_enc->frame_done_timer,
1960 jiffies + msecs_to_jiffies(timeout_ms));
1961
1962 /* All phys encs are ready to go, trigger the kickoff */
1963 _dpu_encoder_kickoff_phys(dpu_enc);
1964
1965 /* allow phys encs to handle any post-kickoff business */
1966 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1967 phys = dpu_enc->phys_encs[i];
1968 if (phys->ops.handle_post_kickoff)
1969 phys->ops.handle_post_kickoff(phys);
1970 }
1971
1972 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1973 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1974 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1975 ktime_to_ms(wakeup_time));
1976 mod_timer(&dpu_enc->vsync_event_timer,
1977 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1978 }
1979
1980 DPU_ATRACE_END("encoder_kickoff");
1981 }
1982
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)1983 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
1984 {
1985 struct dpu_hw_mixer_cfg mixer;
1986 int i, num_lm;
1987 struct dpu_global_state *global_state;
1988 struct dpu_hw_blk *hw_lm[2];
1989 struct dpu_hw_mixer *hw_mixer[2];
1990 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
1991
1992 memset(&mixer, 0, sizeof(mixer));
1993
1994 /* reset all mixers for this encoder */
1995 if (phys_enc->hw_ctl->ops.clear_all_blendstages)
1996 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
1997
1998 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
1999
2000 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
2001 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
2002
2003 for (i = 0; i < num_lm; i++) {
2004 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2005 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer)
2006 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2007
2008 /* clear all blendstages */
2009 if (phys_enc->hw_ctl->ops.setup_blendstage)
2010 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2011 }
2012 }
2013
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2014 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2015 {
2016 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2017 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2018 int i;
2019 struct dpu_encoder_virt *dpu_enc;
2020
2021 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2022
2023 phys_enc->hw_ctl->ops.reset(ctl);
2024
2025 dpu_encoder_helper_reset_mixers(phys_enc);
2026
2027 /*
2028 * TODO: move the once-only operation like CTL flush/trigger
2029 * into dpu_encoder_virt_disable() and all operations which need
2030 * to be done per phys encoder into the phys_disable() op.
2031 */
2032 if (phys_enc->hw_wb) {
2033 /* disable the PP block */
2034 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2035 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, false,
2036 phys_enc->hw_pp->idx);
2037
2038 /* mark WB flush as pending */
2039 if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
2040 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2041 } else {
2042 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2043 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2044 phys_enc->hw_intf->ops.bind_pingpong_blk(
2045 dpu_enc->phys_encs[i]->hw_intf, false,
2046 dpu_enc->phys_encs[i]->hw_pp->idx);
2047
2048 /* mark INTF flush as pending */
2049 if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
2050 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
2051 dpu_enc->phys_encs[i]->hw_intf->idx);
2052 }
2053 }
2054
2055 /* reset the merge 3D HW block */
2056 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2057 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2058 BLEND_3D_NONE);
2059 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
2060 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2061 phys_enc->hw_pp->merge_3d->idx);
2062 }
2063
2064 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2065 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2066
2067 if (phys_enc->hw_intf)
2068 intf_cfg.intf = phys_enc->hw_intf->idx;
2069 if (phys_enc->hw_wb)
2070 intf_cfg.wb = phys_enc->hw_wb->idx;
2071
2072 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2073 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2074
2075 if (ctl->ops.reset_intf_cfg)
2076 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2077
2078 ctl->ops.trigger_flush(ctl);
2079 ctl->ops.trigger_start(ctl);
2080 ctl->ops.clear_pending_flush(ctl);
2081 }
2082
dpu_encoder_prepare_commit(struct drm_encoder * drm_enc)2083 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
2084 {
2085 struct dpu_encoder_virt *dpu_enc;
2086 struct dpu_encoder_phys *phys;
2087 int i;
2088
2089 if (!drm_enc) {
2090 DPU_ERROR("invalid encoder\n");
2091 return;
2092 }
2093 dpu_enc = to_dpu_encoder_virt(drm_enc);
2094
2095 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2096 phys = dpu_enc->phys_encs[i];
2097 if (phys->ops.prepare_commit)
2098 phys->ops.prepare_commit(phys);
2099 }
2100 }
2101
2102 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2103 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2104 {
2105 struct dpu_encoder_virt *dpu_enc = s->private;
2106 int i;
2107
2108 mutex_lock(&dpu_enc->enc_lock);
2109 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2110 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2111
2112 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d ",
2113 phys->intf_idx - INTF_0, phys->wb_idx - WB_0,
2114 atomic_read(&phys->vsync_cnt),
2115 atomic_read(&phys->underrun_cnt));
2116
2117 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2118 }
2119 mutex_unlock(&dpu_enc->enc_lock);
2120
2121 return 0;
2122 }
2123
2124 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2125
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2126 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2127 {
2128 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2129 int i;
2130
2131 char name[DPU_NAME_SIZE];
2132
2133 if (!drm_enc->dev) {
2134 DPU_ERROR("invalid encoder or kms\n");
2135 return -EINVAL;
2136 }
2137
2138 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
2139
2140 /* create overall sub-directory for the encoder */
2141 dpu_enc->debugfs_root = debugfs_create_dir(name,
2142 drm_enc->dev->primary->debugfs_root);
2143
2144 /* don't error check these */
2145 debugfs_create_file("status", 0600,
2146 dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
2147
2148 for (i = 0; i < dpu_enc->num_phys_encs; i++)
2149 if (dpu_enc->phys_encs[i]->ops.late_register)
2150 dpu_enc->phys_encs[i]->ops.late_register(
2151 dpu_enc->phys_encs[i],
2152 dpu_enc->debugfs_root);
2153
2154 return 0;
2155 }
2156 #else
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2157 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2158 {
2159 return 0;
2160 }
2161 #endif
2162
dpu_encoder_late_register(struct drm_encoder * encoder)2163 static int dpu_encoder_late_register(struct drm_encoder *encoder)
2164 {
2165 return _dpu_encoder_init_debugfs(encoder);
2166 }
2167
dpu_encoder_early_unregister(struct drm_encoder * encoder)2168 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
2169 {
2170 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2171
2172 debugfs_remove_recursive(dpu_enc->debugfs_root);
2173 }
2174
dpu_encoder_virt_add_phys_encs(struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2175 static int dpu_encoder_virt_add_phys_encs(
2176 struct msm_display_info *disp_info,
2177 struct dpu_encoder_virt *dpu_enc,
2178 struct dpu_enc_phys_init_params *params)
2179 {
2180 struct dpu_encoder_phys *enc = NULL;
2181
2182 DPU_DEBUG_ENC(dpu_enc, "\n");
2183
2184 /*
2185 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2186 * in this function, check up-front.
2187 */
2188 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2189 ARRAY_SIZE(dpu_enc->phys_encs)) {
2190 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2191 dpu_enc->num_phys_encs);
2192 return -EINVAL;
2193 }
2194
2195
2196 if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
2197 enc = dpu_encoder_phys_wb_init(params);
2198
2199 if (IS_ERR(enc)) {
2200 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2201 PTR_ERR(enc));
2202 return PTR_ERR(enc);
2203 }
2204
2205 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2206 ++dpu_enc->num_phys_encs;
2207 } else if (disp_info->is_cmd_mode) {
2208 enc = dpu_encoder_phys_cmd_init(params);
2209
2210 if (IS_ERR(enc)) {
2211 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2212 PTR_ERR(enc));
2213 return PTR_ERR(enc);
2214 }
2215
2216 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2217 ++dpu_enc->num_phys_encs;
2218 } else {
2219 enc = dpu_encoder_phys_vid_init(params);
2220
2221 if (IS_ERR(enc)) {
2222 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2223 PTR_ERR(enc));
2224 return PTR_ERR(enc);
2225 }
2226
2227 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2228 ++dpu_enc->num_phys_encs;
2229 }
2230
2231 if (params->split_role == ENC_ROLE_SLAVE)
2232 dpu_enc->cur_slave = enc;
2233 else
2234 dpu_enc->cur_master = enc;
2235
2236 return 0;
2237 }
2238
2239 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2240 .handle_vblank_virt = dpu_encoder_vblank_callback,
2241 .handle_underrun_virt = dpu_encoder_underrun_callback,
2242 .handle_frame_done = dpu_encoder_frame_done_callback,
2243 };
2244
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2245 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2246 struct dpu_kms *dpu_kms,
2247 struct msm_display_info *disp_info)
2248 {
2249 int ret = 0;
2250 int i = 0;
2251 enum dpu_intf_type intf_type = INTF_NONE;
2252 struct dpu_enc_phys_init_params phys_params;
2253
2254 if (!dpu_enc) {
2255 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2256 return -EINVAL;
2257 }
2258
2259 dpu_enc->cur_master = NULL;
2260
2261 memset(&phys_params, 0, sizeof(phys_params));
2262 phys_params.dpu_kms = dpu_kms;
2263 phys_params.parent = &dpu_enc->base;
2264 phys_params.parent_ops = &dpu_encoder_parent_ops;
2265 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2266
2267 switch (disp_info->intf_type) {
2268 case DRM_MODE_ENCODER_DSI:
2269 intf_type = INTF_DSI;
2270 break;
2271 case DRM_MODE_ENCODER_TMDS:
2272 intf_type = INTF_DP;
2273 break;
2274 case DRM_MODE_ENCODER_VIRTUAL:
2275 intf_type = INTF_WB;
2276 break;
2277 }
2278
2279 WARN_ON(disp_info->num_of_h_tiles < 1);
2280
2281 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2282
2283 if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL)
2284 dpu_enc->idle_pc_supported =
2285 dpu_kms->catalog->caps->has_idle_pc;
2286
2287 dpu_enc->dsc = disp_info->dsc;
2288
2289 mutex_lock(&dpu_enc->enc_lock);
2290 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2291 /*
2292 * Left-most tile is at index 0, content is controller id
2293 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2294 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2295 */
2296 u32 controller_id = disp_info->h_tile_instance[i];
2297
2298 if (disp_info->num_of_h_tiles > 1) {
2299 if (i == 0)
2300 phys_params.split_role = ENC_ROLE_MASTER;
2301 else
2302 phys_params.split_role = ENC_ROLE_SLAVE;
2303 } else {
2304 phys_params.split_role = ENC_ROLE_SOLO;
2305 }
2306
2307 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2308 i, controller_id, phys_params.split_role);
2309
2310 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2311 intf_type,
2312 controller_id);
2313
2314 phys_params.wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,
2315 intf_type, controller_id);
2316 /*
2317 * The phys_params might represent either an INTF or a WB unit, but not
2318 * both of them at the same time.
2319 */
2320 if ((phys_params.intf_idx == INTF_MAX) &&
2321 (phys_params.wb_idx == WB_MAX)) {
2322 DPU_ERROR_ENC(dpu_enc, "could not get intf or wb: type %d, id %d\n",
2323 intf_type, controller_id);
2324 ret = -EINVAL;
2325 }
2326
2327 if ((phys_params.intf_idx != INTF_MAX) &&
2328 (phys_params.wb_idx != WB_MAX)) {
2329 DPU_ERROR_ENC(dpu_enc, "both intf and wb present: type %d, id %d\n",
2330 intf_type, controller_id);
2331 ret = -EINVAL;
2332 }
2333
2334 if (!ret) {
2335 ret = dpu_encoder_virt_add_phys_encs(disp_info,
2336 dpu_enc, &phys_params);
2337 if (ret)
2338 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2339 }
2340 }
2341
2342 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2343 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2344 atomic_set(&phys->vsync_cnt, 0);
2345 atomic_set(&phys->underrun_cnt, 0);
2346
2347 if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
2348 phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
2349
2350 if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
2351 phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
2352
2353 if (!phys->hw_intf && !phys->hw_wb) {
2354 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2355 ret = -EINVAL;
2356 }
2357
2358 if (phys->hw_intf && phys->hw_wb) {
2359 DPU_ERROR_ENC(dpu_enc,
2360 "invalid phys both intf and wb block at idx: %d\n", i);
2361 ret = -EINVAL;
2362 }
2363 }
2364
2365 mutex_unlock(&dpu_enc->enc_lock);
2366
2367 return ret;
2368 }
2369
dpu_encoder_frame_done_timeout(struct timer_list * t)2370 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2371 {
2372 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2373 frame_done_timer);
2374 struct drm_encoder *drm_enc = &dpu_enc->base;
2375 u32 event;
2376
2377 if (!drm_enc->dev) {
2378 DPU_ERROR("invalid parameters\n");
2379 return;
2380 }
2381
2382 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2383 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2384 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2385 return;
2386 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2387 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2388 return;
2389 }
2390
2391 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2392
2393 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2394 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2395 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2396 }
2397
2398 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2399 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2400 .disable = dpu_encoder_virt_disable,
2401 .enable = dpu_encoder_virt_enable,
2402 .atomic_check = dpu_encoder_virt_atomic_check,
2403 };
2404
2405 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2406 .destroy = dpu_encoder_destroy,
2407 .late_register = dpu_encoder_late_register,
2408 .early_unregister = dpu_encoder_early_unregister,
2409 };
2410
dpu_encoder_setup(struct drm_device * dev,struct drm_encoder * enc,struct msm_display_info * disp_info)2411 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2412 struct msm_display_info *disp_info)
2413 {
2414 struct msm_drm_private *priv = dev->dev_private;
2415 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2416 struct drm_encoder *drm_enc = NULL;
2417 struct dpu_encoder_virt *dpu_enc = NULL;
2418 int ret = 0;
2419
2420 dpu_enc = to_dpu_encoder_virt(enc);
2421
2422 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2423 if (ret)
2424 goto fail;
2425
2426 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2427 timer_setup(&dpu_enc->frame_done_timer,
2428 dpu_encoder_frame_done_timeout, 0);
2429
2430 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2431 timer_setup(&dpu_enc->vsync_event_timer,
2432 dpu_encoder_vsync_event_handler,
2433 0);
2434 else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
2435 dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
2436 priv->dp[disp_info->h_tile_instance[0]]);
2437
2438 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2439 dpu_encoder_off_work);
2440 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2441
2442 kthread_init_work(&dpu_enc->vsync_event_work,
2443 dpu_encoder_vsync_event_work_handler);
2444
2445 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2446
2447 DPU_DEBUG_ENC(dpu_enc, "created\n");
2448
2449 return ret;
2450
2451 fail:
2452 DPU_ERROR("failed to create encoder\n");
2453 if (drm_enc)
2454 dpu_encoder_destroy(drm_enc);
2455
2456 return ret;
2457
2458
2459 }
2460
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode)2461 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2462 int drm_enc_mode)
2463 {
2464 struct dpu_encoder_virt *dpu_enc = NULL;
2465 int rc = 0;
2466
2467 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2468 if (!dpu_enc)
2469 return ERR_PTR(-ENOMEM);
2470
2471
2472 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2473 drm_enc_mode, NULL);
2474 if (rc) {
2475 devm_kfree(dev->dev, dpu_enc);
2476 return ERR_PTR(rc);
2477 }
2478
2479 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2480
2481 spin_lock_init(&dpu_enc->enc_spinlock);
2482 dpu_enc->enabled = false;
2483 mutex_init(&dpu_enc->enc_lock);
2484 mutex_init(&dpu_enc->rc_lock);
2485
2486 return &dpu_enc->base;
2487 }
2488
dpu_encoder_wait_for_event(struct drm_encoder * drm_enc,enum msm_event_wait event)2489 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2490 enum msm_event_wait event)
2491 {
2492 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2493 struct dpu_encoder_virt *dpu_enc = NULL;
2494 int i, ret = 0;
2495
2496 if (!drm_enc) {
2497 DPU_ERROR("invalid encoder\n");
2498 return -EINVAL;
2499 }
2500 dpu_enc = to_dpu_encoder_virt(drm_enc);
2501 DPU_DEBUG_ENC(dpu_enc, "\n");
2502
2503 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2504 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2505
2506 switch (event) {
2507 case MSM_ENC_COMMIT_DONE:
2508 fn_wait = phys->ops.wait_for_commit_done;
2509 break;
2510 case MSM_ENC_TX_COMPLETE:
2511 fn_wait = phys->ops.wait_for_tx_complete;
2512 break;
2513 case MSM_ENC_VBLANK:
2514 fn_wait = phys->ops.wait_for_vblank;
2515 break;
2516 default:
2517 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2518 event);
2519 return -EINVAL;
2520 }
2521
2522 if (fn_wait) {
2523 DPU_ATRACE_BEGIN("wait_for_completion_event");
2524 ret = fn_wait(phys);
2525 DPU_ATRACE_END("wait_for_completion_event");
2526 if (ret)
2527 return ret;
2528 }
2529 }
2530
2531 return ret;
2532 }
2533
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2534 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2535 {
2536 struct dpu_encoder_virt *dpu_enc = NULL;
2537
2538 if (!encoder) {
2539 DPU_ERROR("invalid encoder\n");
2540 return INTF_MODE_NONE;
2541 }
2542 dpu_enc = to_dpu_encoder_virt(encoder);
2543
2544 if (dpu_enc->cur_master)
2545 return dpu_enc->cur_master->intf_mode;
2546
2547 if (dpu_enc->num_phys_encs)
2548 return dpu_enc->phys_encs[0]->intf_mode;
2549
2550 return INTF_MODE_NONE;
2551 }
2552
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2553 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2554 {
2555 struct drm_encoder *encoder = phys_enc->parent;
2556 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2557
2558 return dpu_enc->dsc_mask;
2559 }
2560