1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020-2022, Linaro Limited
4 */
5
6 #include "dpu_kms.h"
7 #include "dpu_hw_catalog.h"
8 #include "dpu_hwio.h"
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_dsc.h"
11
12 #define DSC_COMMON_MODE 0x000
13 #define DSC_ENC 0x004
14 #define DSC_PICTURE 0x008
15 #define DSC_SLICE 0x00C
16 #define DSC_CHUNK_SIZE 0x010
17 #define DSC_DELAY 0x014
18 #define DSC_SCALE_INITIAL 0x018
19 #define DSC_SCALE_DEC_INTERVAL 0x01C
20 #define DSC_SCALE_INC_INTERVAL 0x020
21 #define DSC_FIRST_LINE_BPG_OFFSET 0x024
22 #define DSC_BPG_OFFSET 0x028
23 #define DSC_DSC_OFFSET 0x02C
24 #define DSC_FLATNESS 0x030
25 #define DSC_RC_MODEL_SIZE 0x034
26 #define DSC_RC 0x038
27 #define DSC_RC_BUF_THRESH 0x03C
28 #define DSC_RANGE_MIN_QP 0x074
29 #define DSC_RANGE_MAX_QP 0x0B0
30 #define DSC_RANGE_BPG_OFFSET 0x0EC
31
dpu_hw_dsc_disable(struct dpu_hw_dsc * dsc)32 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
33 {
34 struct dpu_hw_blk_reg_map *c = &dsc->hw;
35
36 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
37 }
38
dpu_hw_dsc_config(struct dpu_hw_dsc * hw_dsc,struct drm_dsc_config * dsc,u32 mode,u32 initial_lines)39 static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
40 struct drm_dsc_config *dsc,
41 u32 mode,
42 u32 initial_lines)
43 {
44 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
45 u32 data;
46 u32 slice_last_group_size;
47 u32 det_thresh_flatness;
48 bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
49
50 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
51
52 if (is_cmd_mode)
53 initial_lines += 1;
54
55 slice_last_group_size = (dsc->slice_width + 2) % 3;
56
57 data = (initial_lines << 20);
58 data |= (slice_last_group_size << 18);
59 /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
60 data |= (dsc->bits_per_pixel << 8);
61 data |= (dsc->block_pred_enable << 7);
62 data |= (dsc->line_buf_depth << 3);
63 data |= (dsc->simple_422 << 2);
64 data |= (dsc->convert_rgb << 1);
65 data |= dsc->bits_per_component;
66
67 DPU_REG_WRITE(c, DSC_ENC, data);
68
69 data = dsc->pic_width << 16;
70 data |= dsc->pic_height;
71 DPU_REG_WRITE(c, DSC_PICTURE, data);
72
73 data = dsc->slice_width << 16;
74 data |= dsc->slice_height;
75 DPU_REG_WRITE(c, DSC_SLICE, data);
76
77 data = dsc->slice_chunk_size << 16;
78 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
79
80 data = dsc->initial_dec_delay << 16;
81 data |= dsc->initial_xmit_delay;
82 DPU_REG_WRITE(c, DSC_DELAY, data);
83
84 data = dsc->initial_scale_value;
85 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
86
87 data = dsc->scale_decrement_interval;
88 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
89
90 data = dsc->scale_increment_interval;
91 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
92
93 data = dsc->first_line_bpg_offset;
94 DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
95
96 data = dsc->nfl_bpg_offset << 16;
97 data |= dsc->slice_bpg_offset;
98 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
99
100 data = dsc->initial_offset << 16;
101 data |= dsc->final_offset;
102 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
103
104 det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8);
105 data = det_thresh_flatness << 10;
106 data |= dsc->flatness_max_qp << 5;
107 data |= dsc->flatness_min_qp;
108 DPU_REG_WRITE(c, DSC_FLATNESS, data);
109
110 data = dsc->rc_model_size;
111 DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
112
113 data = dsc->rc_tgt_offset_low << 18;
114 data |= dsc->rc_tgt_offset_high << 14;
115 data |= dsc->rc_quant_incr_limit1 << 9;
116 data |= dsc->rc_quant_incr_limit0 << 4;
117 data |= dsc->rc_edge_factor;
118 DPU_REG_WRITE(c, DSC_RC, data);
119 }
120
dpu_hw_dsc_config_thresh(struct dpu_hw_dsc * hw_dsc,struct drm_dsc_config * dsc)121 static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
122 struct drm_dsc_config *dsc)
123 {
124 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params;
125 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
126 u32 off;
127 int i;
128
129 off = DSC_RC_BUF_THRESH;
130 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
131 DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);
132 off += 4;
133 }
134
135 off = DSC_RANGE_MIN_QP;
136 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
137 DPU_REG_WRITE(c, off, rc[i].range_min_qp);
138 off += 4;
139 }
140
141 off = DSC_RANGE_MAX_QP;
142 for (i = 0; i < 15; i++) {
143 DPU_REG_WRITE(c, off, rc[i].range_max_qp);
144 off += 4;
145 }
146
147 off = DSC_RANGE_BPG_OFFSET;
148 for (i = 0; i < 15; i++) {
149 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
150 off += 4;
151 }
152 }
153
_dsc_offset(enum dpu_dsc dsc,const struct dpu_mdss_cfg * m,void __iomem * addr,struct dpu_hw_blk_reg_map * b)154 static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
155 const struct dpu_mdss_cfg *m,
156 void __iomem *addr,
157 struct dpu_hw_blk_reg_map *b)
158 {
159 int i;
160
161 for (i = 0; i < m->dsc_count; i++) {
162 if (dsc == m->dsc[i].id) {
163 b->blk_addr = addr + m->dsc[i].base;
164 b->log_mask = DPU_DBG_MASK_DSC;
165 return &m->dsc[i];
166 }
167 }
168
169 return NULL;
170 }
171
_setup_dsc_ops(struct dpu_hw_dsc_ops * ops,unsigned long cap)172 static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
173 unsigned long cap)
174 {
175 ops->dsc_disable = dpu_hw_dsc_disable;
176 ops->dsc_config = dpu_hw_dsc_config;
177 ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
178 };
179
dpu_hw_dsc_init(enum dpu_dsc idx,void __iomem * addr,const struct dpu_mdss_cfg * m)180 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
181 const struct dpu_mdss_cfg *m)
182 {
183 struct dpu_hw_dsc *c;
184 struct dpu_dsc_cfg *cfg;
185
186 c = kzalloc(sizeof(*c), GFP_KERNEL);
187 if (!c)
188 return ERR_PTR(-ENOMEM);
189
190 cfg = _dsc_offset(idx, m, addr, &c->hw);
191 if (IS_ERR_OR_NULL(cfg)) {
192 kfree(c);
193 return ERR_PTR(-EINVAL);
194 }
195
196 c->idx = idx;
197 c->caps = cfg;
198 _setup_dsc_ops(&c->ops, c->caps->features);
199
200 return c;
201 }
202
dpu_hw_dsc_destroy(struct dpu_hw_dsc * dsc)203 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
204 {
205 kfree(dsc);
206 }
207