1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
39
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
45
46 #include "drm_crtc_internal.h"
47
oui(u8 first,u8 second,u8 third)48 static int oui(u8 first, u8 second, u8 third)
49 {
50 return (first << 16) | (second << 8) | third;
51 }
52
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
56
57 /*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
80 /* Force 8bpc */
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
82 /* Force 12bpc */
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
84 /* Force 6bpc */
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
86 /* Force 10bpc */
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
92
93 #define MICROSOFT_IEEE_OUI 0xca125c
94
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
98 bool preferred;
99 u32 quirks;
100 int modes;
101 };
102
103 #define LEVEL_DMT 0
104 #define LEVEL_GTF 1
105 #define LEVEL_GTF2 2
106 #define LEVEL_CVT 3
107
108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
109 { \
110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
111 product_id), \
112 .quirks = _quirks \
113 }
114
115 static const struct edid_quirk {
116 u32 panel_id;
117 u32 quirks;
118 } edid_quirk_list[] = {
119 /* Acer AL1706 */
120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
121 /* Acer F51 */
122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123
124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
126
127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
129
130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
132
133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
135
136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
138
139 /* Belinea 10 15 55 */
140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
142
143 /* Envision Peripherals, Inc. EN-7100e */
144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
145 /* Envision EN2028 */
146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
147
148 /* Funai Electronics PM36B */
149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
150 EDID_QUIRK_DETAILED_IN_CM),
151
152 /* LG 27GP950 */
153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
154
155 /* LG 27GN950 */
156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
157
158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
160
161 /* LG Philips LCD LP154W01-A5 */
162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
164
165 /* Samsung SyncMaster 205BW. Note: irony */
166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
167 /* Samsung SyncMaster 22[5-6]BW */
168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
170
171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
173
174 /* ViewSonic VA2026w */
175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
176
177 /* Medion MD 30217 PG */
178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
179
180 /* Lenovo G50 */
181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
182
183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
185
186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
188
189 /* Valve Index Headset */
190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
207
208 /* HTC Vive and Vive Pro VR Headsets */
209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
211
212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
217
218 /* Windows Mixed Reality Headsets */
219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
225
226 /* Sony PlayStation VR Headset */
227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
228
229 /* Sensics VR Headsets */
230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
231
232 /* OSVR HDK and HDK2 VR Headsets */
233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
235 };
236
237 /*
238 * Autogenerated from the DMT spec.
239 * This table is copied from xfree86/modes/xf86EdidModes.c.
240 */
241 static const struct drm_display_mode drm_dmt_modes[] = {
242 /* 0x01 - 640x350@85Hz */
243 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 350, 382, 385, 445, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 0x02 - 640x400@85Hz */
247 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
248 736, 832, 0, 400, 401, 404, 445, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x03 - 720x400@85Hz */
251 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
252 828, 936, 0, 400, 401, 404, 446, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x04 - 640x480@60Hz */
255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
256 752, 800, 0, 480, 490, 492, 525, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 0x05 - 640x480@72Hz */
259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
260 704, 832, 0, 480, 489, 492, 520, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x06 - 640x480@75Hz */
263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
264 720, 840, 0, 480, 481, 484, 500, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x07 - 640x480@85Hz */
267 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
268 752, 832, 0, 480, 481, 484, 509, 0,
269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x08 - 800x600@56Hz */
271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
272 896, 1024, 0, 600, 601, 603, 625, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x09 - 800x600@60Hz */
275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
276 968, 1056, 0, 600, 601, 605, 628, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x0a - 800x600@72Hz */
279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
280 976, 1040, 0, 600, 637, 643, 666, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x0b - 800x600@75Hz */
283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
284 896, 1056, 0, 600, 601, 604, 625, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x0c - 800x600@85Hz */
287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
288 896, 1048, 0, 600, 601, 604, 631, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 0x0d - 800x600@120Hz RB */
291 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
292 880, 960, 0, 600, 603, 607, 636, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x0e - 848x480@60Hz */
295 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
296 976, 1088, 0, 480, 486, 494, 517, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x0f - 1024x768@43Hz, interlace */
299 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
300 1208, 1264, 0, 768, 768, 776, 817, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
302 DRM_MODE_FLAG_INTERLACE) },
303 /* 0x10 - 1024x768@60Hz */
304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
305 1184, 1344, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
307 /* 0x11 - 1024x768@70Hz */
308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
309 1184, 1328, 0, 768, 771, 777, 806, 0,
310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x12 - 1024x768@75Hz */
312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
313 1136, 1312, 0, 768, 769, 772, 800, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x13 - 1024x768@85Hz */
316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
317 1168, 1376, 0, 768, 769, 772, 808, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x14 - 1024x768@120Hz RB */
320 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
321 1104, 1184, 0, 768, 771, 775, 813, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
323 /* 0x15 - 1152x864@75Hz */
324 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
325 1344, 1600, 0, 864, 865, 868, 900, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x55 - 1280x720@60Hz */
328 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
329 1430, 1650, 0, 720, 725, 730, 750, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x16 - 1280x768@60Hz RB */
332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
333 1360, 1440, 0, 768, 771, 778, 790, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
335 /* 0x17 - 1280x768@60Hz */
336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
337 1472, 1664, 0, 768, 771, 778, 798, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x18 - 1280x768@75Hz */
340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
341 1488, 1696, 0, 768, 771, 778, 805, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x19 - 1280x768@85Hz */
344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
345 1496, 1712, 0, 768, 771, 778, 809, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
347 /* 0x1a - 1280x768@120Hz RB */
348 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
349 1360, 1440, 0, 768, 771, 778, 813, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x1b - 1280x800@60Hz RB */
352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
353 1360, 1440, 0, 800, 803, 809, 823, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
355 /* 0x1c - 1280x800@60Hz */
356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
357 1480, 1680, 0, 800, 803, 809, 831, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x1d - 1280x800@75Hz */
360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
361 1488, 1696, 0, 800, 803, 809, 838, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x1e - 1280x800@85Hz */
364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
365 1496, 1712, 0, 800, 803, 809, 843, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x1f - 1280x800@120Hz RB */
368 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
369 1360, 1440, 0, 800, 803, 809, 847, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
371 /* 0x20 - 1280x960@60Hz */
372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
373 1488, 1800, 0, 960, 961, 964, 1000, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x21 - 1280x960@85Hz */
376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
377 1504, 1728, 0, 960, 961, 964, 1011, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x22 - 1280x960@120Hz RB */
380 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
381 1360, 1440, 0, 960, 963, 967, 1017, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
383 /* 0x23 - 1280x1024@60Hz */
384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x24 - 1280x1024@75Hz */
388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
389 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x25 - 1280x1024@85Hz */
392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
393 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x26 - 1280x1024@120Hz RB */
396 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
397 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
399 /* 0x27 - 1360x768@60Hz */
400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
401 1536, 1792, 0, 768, 771, 777, 795, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x28 - 1360x768@120Hz RB */
404 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
405 1440, 1520, 0, 768, 771, 776, 813, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
407 /* 0x51 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
409 1579, 1792, 0, 768, 771, 774, 798, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x56 - 1366x768@60Hz */
412 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
413 1436, 1500, 0, 768, 769, 772, 800, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x29 - 1400x1050@60Hz RB */
416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
417 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
419 /* 0x2a - 1400x1050@60Hz */
420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
421 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x2b - 1400x1050@75Hz */
424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
425 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x2c - 1400x1050@85Hz */
428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
429 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x2d - 1400x1050@120Hz RB */
432 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
433 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x2e - 1440x900@60Hz RB */
436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
437 1520, 1600, 0, 900, 903, 909, 926, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
439 /* 0x2f - 1440x900@60Hz */
440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
441 1672, 1904, 0, 900, 903, 909, 934, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x30 - 1440x900@75Hz */
444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
445 1688, 1936, 0, 900, 903, 909, 942, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x31 - 1440x900@85Hz */
448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
449 1696, 1952, 0, 900, 903, 909, 948, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x32 - 1440x900@120Hz RB */
452 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
453 1520, 1600, 0, 900, 903, 909, 953, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x53 - 1600x900@60Hz */
456 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
457 1704, 1800, 0, 900, 901, 904, 1000, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x33 - 1600x1200@60Hz */
460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x34 - 1600x1200@65Hz */
464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x35 - 1600x1200@70Hz */
468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x36 - 1600x1200@75Hz */
472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x37 - 1600x1200@85Hz */
476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
477 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x38 - 1600x1200@120Hz RB */
480 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
481 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x39 - 1680x1050@60Hz RB */
484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
485 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
487 /* 0x3a - 1680x1050@60Hz */
488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
489 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x3b - 1680x1050@75Hz */
492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
493 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x3c - 1680x1050@85Hz */
496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
497 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x3d - 1680x1050@120Hz RB */
500 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
501 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x3e - 1792x1344@60Hz */
504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
505 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x3f - 1792x1344@75Hz */
508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
509 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
510 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
511 /* 0x40 - 1792x1344@120Hz RB */
512 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
513 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
515 /* 0x41 - 1856x1392@60Hz */
516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
517 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x42 - 1856x1392@75Hz */
520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
521 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x43 - 1856x1392@120Hz RB */
524 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
525 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x52 - 1920x1080@60Hz */
528 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
529 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x44 - 1920x1200@60Hz RB */
532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
533 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
535 /* 0x45 - 1920x1200@60Hz */
536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
537 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
539 /* 0x46 - 1920x1200@75Hz */
540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
541 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x47 - 1920x1200@85Hz */
544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
545 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
547 /* 0x48 - 1920x1200@120Hz RB */
548 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
549 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
551 /* 0x49 - 1920x1440@60Hz */
552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
553 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4a - 1920x1440@75Hz */
556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
557 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
559 /* 0x4b - 1920x1440@120Hz RB */
560 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
561 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
563 /* 0x54 - 2048x1152@60Hz */
564 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
565 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
567 /* 0x4c - 2560x1600@60Hz RB */
568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
569 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 /* 0x4d - 2560x1600@60Hz */
572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
573 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
575 /* 0x4e - 2560x1600@75Hz */
576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
579 /* 0x4f - 2560x1600@85Hz */
580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
581 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
583 /* 0x50 - 2560x1600@120Hz RB */
584 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
585 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x57 - 4096x2160@60Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
591 /* 0x58 - 4096x2160@59.94Hz RB */
592 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
593 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
595 };
596
597 /*
598 * These more or less come from the DMT spec. The 720x400 modes are
599 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
600 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
601 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
602 * mode.
603 *
604 * The DMT modes have been fact-checked; the rest are mild guesses.
605 */
606 static const struct drm_display_mode edid_est_modes[] = {
607 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
608 968, 1056, 0, 600, 601, 605, 628, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
611 896, 1024, 0, 600, 601, 603, 625, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
614 720, 840, 0, 480, 481, 484, 500, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
616 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
617 704, 832, 0, 480, 489, 492, 520, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
619 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
620 768, 864, 0, 480, 483, 486, 525, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
622 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
623 752, 800, 0, 480, 490, 492, 525, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
625 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
626 846, 900, 0, 400, 421, 423, 449, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
628 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
629 846, 900, 0, 400, 412, 414, 449, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
631 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
632 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
634 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
635 1136, 1312, 0, 768, 769, 772, 800, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
637 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
638 1184, 1328, 0, 768, 771, 777, 806, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
640 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
641 1184, 1344, 0, 768, 771, 777, 806, 0,
642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
643 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
644 1208, 1264, 0, 768, 768, 776, 817, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
646 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
647 928, 1152, 0, 624, 625, 628, 667, 0,
648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
649 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
650 896, 1056, 0, 600, 601, 604, 625, 0,
651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
652 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
653 976, 1040, 0, 600, 637, 643, 666, 0,
654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
655 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
656 1344, 1600, 0, 864, 865, 868, 900, 0,
657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
658 };
659
660 struct minimode {
661 short w;
662 short h;
663 short r;
664 short rb;
665 };
666
667 static const struct minimode est3_modes[] = {
668 /* byte 6 */
669 { 640, 350, 85, 0 },
670 { 640, 400, 85, 0 },
671 { 720, 400, 85, 0 },
672 { 640, 480, 85, 0 },
673 { 848, 480, 60, 0 },
674 { 800, 600, 85, 0 },
675 { 1024, 768, 85, 0 },
676 { 1152, 864, 75, 0 },
677 /* byte 7 */
678 { 1280, 768, 60, 1 },
679 { 1280, 768, 60, 0 },
680 { 1280, 768, 75, 0 },
681 { 1280, 768, 85, 0 },
682 { 1280, 960, 60, 0 },
683 { 1280, 960, 85, 0 },
684 { 1280, 1024, 60, 0 },
685 { 1280, 1024, 85, 0 },
686 /* byte 8 */
687 { 1360, 768, 60, 0 },
688 { 1440, 900, 60, 1 },
689 { 1440, 900, 60, 0 },
690 { 1440, 900, 75, 0 },
691 { 1440, 900, 85, 0 },
692 { 1400, 1050, 60, 1 },
693 { 1400, 1050, 60, 0 },
694 { 1400, 1050, 75, 0 },
695 /* byte 9 */
696 { 1400, 1050, 85, 0 },
697 { 1680, 1050, 60, 1 },
698 { 1680, 1050, 60, 0 },
699 { 1680, 1050, 75, 0 },
700 { 1680, 1050, 85, 0 },
701 { 1600, 1200, 60, 0 },
702 { 1600, 1200, 65, 0 },
703 { 1600, 1200, 70, 0 },
704 /* byte 10 */
705 { 1600, 1200, 75, 0 },
706 { 1600, 1200, 85, 0 },
707 { 1792, 1344, 60, 0 },
708 { 1792, 1344, 75, 0 },
709 { 1856, 1392, 60, 0 },
710 { 1856, 1392, 75, 0 },
711 { 1920, 1200, 60, 1 },
712 { 1920, 1200, 60, 0 },
713 /* byte 11 */
714 { 1920, 1200, 75, 0 },
715 { 1920, 1200, 85, 0 },
716 { 1920, 1440, 60, 0 },
717 { 1920, 1440, 75, 0 },
718 };
719
720 static const struct minimode extra_modes[] = {
721 { 1024, 576, 60, 0 },
722 { 1366, 768, 60, 0 },
723 { 1600, 900, 60, 0 },
724 { 1680, 945, 60, 0 },
725 { 1920, 1080, 60, 0 },
726 { 2048, 1152, 60, 0 },
727 { 2048, 1536, 60, 0 },
728 };
729
730 /*
731 * From CEA/CTA-861 spec.
732 *
733 * Do not access directly, instead always use cea_mode_for_vic().
734 */
735 static const struct drm_display_mode edid_cea_modes_1[] = {
736 /* 1 - 640x480@60Hz 4:3 */
737 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
738 752, 800, 0, 480, 490, 492, 525, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
741 /* 2 - 720x480@60Hz 4:3 */
742 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
743 798, 858, 0, 480, 489, 495, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 3 - 720x480@60Hz 16:9 */
747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
748 798, 858, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 4 - 1280x720@60Hz 16:9 */
752 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
753 1430, 1650, 0, 720, 725, 730, 750, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 5 - 1920x1080i@60Hz 16:9 */
757 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
758 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
760 DRM_MODE_FLAG_INTERLACE),
761 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 6 - 720(1440)x480i@60Hz 4:3 */
763 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 480, 488, 494, 525, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
767 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
768 /* 7 - 720(1440)x480i@60Hz 16:9 */
769 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
770 801, 858, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
773 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 8 - 720(1440)x240@60Hz 4:3 */
775 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
776 801, 858, 0, 240, 244, 247, 262, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_DBLCLK),
779 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
780 /* 9 - 720(1440)x240@60Hz 16:9 */
781 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
782 801, 858, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_DBLCLK),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
786 /* 10 - 2880x480i@60Hz 4:3 */
787 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 480, 488, 494, 525, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_INTERLACE),
791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 11 - 2880x480i@60Hz 16:9 */
793 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
794 3204, 3432, 0, 480, 488, 494, 525, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_INTERLACE),
797 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 12 - 2880x240@60Hz 4:3 */
799 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
800 3204, 3432, 0, 240, 244, 247, 262, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803 /* 13 - 2880x240@60Hz 16:9 */
804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
805 3204, 3432, 0, 240, 244, 247, 262, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 14 - 1440x480@60Hz 4:3 */
809 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
810 1596, 1716, 0, 480, 489, 495, 525, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
813 /* 15 - 1440x480@60Hz 16:9 */
814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
815 1596, 1716, 0, 480, 489, 495, 525, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 16 - 1920x1080@60Hz 16:9 */
819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
820 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 17 - 720x576@50Hz 4:3 */
824 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
825 796, 864, 0, 576, 581, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 18 - 720x576@50Hz 16:9 */
829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
830 796, 864, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 19 - 1280x720@50Hz 16:9 */
834 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
835 1760, 1980, 0, 720, 725, 730, 750, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 20 - 1920x1080i@50Hz 16:9 */
839 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
840 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
842 DRM_MODE_FLAG_INTERLACE),
843 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
844 /* 21 - 720(1440)x576i@50Hz 4:3 */
845 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 576, 580, 586, 625, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
849 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
850 /* 22 - 720(1440)x576i@50Hz 16:9 */
851 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
852 795, 864, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
855 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
856 /* 23 - 720(1440)x288@50Hz 4:3 */
857 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
858 795, 864, 0, 288, 290, 293, 312, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_DBLCLK),
861 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
862 /* 24 - 720(1440)x288@50Hz 16:9 */
863 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
864 795, 864, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
866 DRM_MODE_FLAG_DBLCLK),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 25 - 2880x576i@50Hz 4:3 */
869 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 576, 580, 586, 625, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
872 DRM_MODE_FLAG_INTERLACE),
873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
874 /* 26 - 2880x576i@50Hz 16:9 */
875 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
876 3180, 3456, 0, 576, 580, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
878 DRM_MODE_FLAG_INTERLACE),
879 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 27 - 2880x288@50Hz 4:3 */
881 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
882 3180, 3456, 0, 288, 290, 293, 312, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885 /* 28 - 2880x288@50Hz 16:9 */
886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
887 3180, 3456, 0, 288, 290, 293, 312, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 29 - 1440x576@50Hz 4:3 */
891 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
892 1592, 1728, 0, 576, 581, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 30 - 1440x576@50Hz 16:9 */
896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
897 1592, 1728, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 31 - 1920x1080@50Hz 16:9 */
901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
902 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 32 - 1920x1080@24Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
907 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 33 - 1920x1080@25Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
912 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 34 - 1920x1080@30Hz 16:9 */
916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
917 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 35 - 2880x480@60Hz 4:3 */
921 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
922 3192, 3432, 0, 480, 489, 495, 525, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
925 /* 36 - 2880x480@60Hz 16:9 */
926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
927 3192, 3432, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 37 - 2880x576@50Hz 4:3 */
931 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
932 3184, 3456, 0, 576, 581, 586, 625, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
935 /* 38 - 2880x576@50Hz 16:9 */
936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
937 3184, 3456, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 39 - 1920x1080i@50Hz 16:9 */
941 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
942 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
944 DRM_MODE_FLAG_INTERLACE),
945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 40 - 1920x1080i@100Hz 16:9 */
947 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
948 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
950 DRM_MODE_FLAG_INTERLACE),
951 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 41 - 1280x720@100Hz 16:9 */
953 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
954 1760, 1980, 0, 720, 725, 730, 750, 0,
955 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 42 - 720x576@100Hz 4:3 */
958 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
959 796, 864, 0, 576, 581, 586, 625, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
962 /* 43 - 720x576@100Hz 16:9 */
963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
964 796, 864, 0, 576, 581, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 44 - 720(1440)x576i@100Hz 4:3 */
968 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
969 795, 864, 0, 576, 580, 586, 625, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
973 /* 45 - 720(1440)x576i@100Hz 16:9 */
974 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
975 795, 864, 0, 576, 580, 586, 625, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
977 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 46 - 1920x1080i@120Hz 16:9 */
980 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
981 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
983 DRM_MODE_FLAG_INTERLACE),
984 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 47 - 1280x720@120Hz 16:9 */
986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
987 1430, 1650, 0, 720, 725, 730, 750, 0,
988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 48 - 720x480@120Hz 4:3 */
991 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
992 798, 858, 0, 480, 489, 495, 525, 0,
993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
995 /* 49 - 720x480@120Hz 16:9 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1000 /* 50 - 720(1440)x480i@120Hz 4:3 */
1001 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1002 801, 858, 0, 480, 488, 494, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1004 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1006 /* 51 - 720(1440)x480i@120Hz 16:9 */
1007 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1008 801, 858, 0, 480, 488, 494, 525, 0,
1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1012 /* 52 - 720x576@200Hz 4:3 */
1013 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1014 796, 864, 0, 576, 581, 586, 625, 0,
1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1017 /* 53 - 720x576@200Hz 16:9 */
1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1019 796, 864, 0, 576, 581, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1022 /* 54 - 720(1440)x576i@200Hz 4:3 */
1023 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1024 795, 864, 0, 576, 580, 586, 625, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1026 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1028 /* 55 - 720(1440)x576i@200Hz 16:9 */
1029 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1030 795, 864, 0, 576, 580, 586, 625, 0,
1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1034 /* 56 - 720x480@240Hz 4:3 */
1035 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1036 798, 858, 0, 480, 489, 495, 525, 0,
1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1039 /* 57 - 720x480@240Hz 16:9 */
1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1041 798, 858, 0, 480, 489, 495, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 58 - 720(1440)x480i@240Hz 4:3 */
1045 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1046 801, 858, 0, 480, 488, 494, 525, 0,
1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1048 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1050 /* 59 - 720(1440)x480i@240Hz 16:9 */
1051 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1052 801, 858, 0, 480, 488, 494, 525, 0,
1053 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1054 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1055 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1056 /* 60 - 1280x720@24Hz 16:9 */
1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1058 3080, 3300, 0, 720, 725, 730, 750, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 61 - 1280x720@25Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1063 3740, 3960, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 62 - 1280x720@30Hz 16:9 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1068 3080, 3300, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 63 - 1920x1080@120Hz 16:9 */
1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1073 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 64 - 1920x1080@100Hz 16:9 */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1078 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081 /* 65 - 1280x720@24Hz 64:27 */
1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1083 3080, 3300, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 66 - 1280x720@25Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1088 3740, 3960, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 67 - 1280x720@30Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1093 3080, 3300, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 68 - 1280x720@50Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1098 1760, 1980, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 69 - 1280x720@60Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1103 1430, 1650, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 70 - 1280x720@100Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1108 1760, 1980, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 71 - 1280x720@120Hz 64:27 */
1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1113 1430, 1650, 0, 720, 725, 730, 750, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 72 - 1920x1080@24Hz 64:27 */
1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1118 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 73 - 1920x1080@25Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1123 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 74 - 1920x1080@30Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1128 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 75 - 1920x1080@50Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1133 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 76 - 1920x1080@60Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1138 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 77 - 1920x1080@100Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1143 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 78 - 1920x1080@120Hz 64:27 */
1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1148 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 79 - 1680x720@24Hz 64:27 */
1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1153 3080, 3300, 0, 720, 725, 730, 750, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 80 - 1680x720@25Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1158 2948, 3168, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 81 - 1680x720@30Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1163 2420, 2640, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 82 - 1680x720@50Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1168 1980, 2200, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 83 - 1680x720@60Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1173 1980, 2200, 0, 720, 725, 730, 750, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 84 - 1680x720@100Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1178 1780, 2000, 0, 720, 725, 730, 825, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 85 - 1680x720@120Hz 64:27 */
1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1183 1780, 2000, 0, 720, 725, 730, 825, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 86 - 2560x1080@24Hz 64:27 */
1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1188 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 87 - 2560x1080@25Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1193 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 88 - 2560x1080@30Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1198 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 89 - 2560x1080@50Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1203 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 90 - 2560x1080@60Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1208 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 91 - 2560x1080@100Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1213 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 92 - 2560x1080@120Hz 64:27 */
1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1218 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 93 - 3840x2160@24Hz 16:9 */
1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1223 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1226 /* 94 - 3840x2160@25Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1228 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 95 - 3840x2160@30Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1233 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 96 - 3840x2160@50Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1238 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 97 - 3840x2160@60Hz 16:9 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1243 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1246 /* 98 - 4096x2160@24Hz 256:135 */
1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1248 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1251 /* 99 - 4096x2160@25Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1253 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 100 - 4096x2160@30Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1258 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 101 - 4096x2160@50Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1263 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 102 - 4096x2160@60Hz 256:135 */
1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1268 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1271 /* 103 - 3840x2160@24Hz 64:27 */
1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1273 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1276 /* 104 - 3840x2160@25Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1278 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 105 - 3840x2160@30Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1283 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 106 - 3840x2160@50Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1288 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 107 - 3840x2160@60Hz 64:27 */
1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1293 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296 /* 108 - 1280x720@48Hz 16:9 */
1297 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1298 2280, 2500, 0, 720, 725, 730, 750, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1301 /* 109 - 1280x720@48Hz 64:27 */
1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1303 2280, 2500, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1306 /* 110 - 1680x720@48Hz 64:27 */
1307 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1308 2530, 2750, 0, 720, 725, 730, 750, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311 /* 111 - 1920x1080@48Hz 16:9 */
1312 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1313 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1316 /* 112 - 1920x1080@48Hz 64:27 */
1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1321 /* 113 - 2560x1080@48Hz 64:27 */
1322 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1323 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1326 /* 114 - 3840x2160@48Hz 16:9 */
1327 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1328 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1331 /* 115 - 4096x2160@48Hz 256:135 */
1332 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1336 /* 116 - 3840x2160@48Hz 64:27 */
1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1341 /* 117 - 3840x2160@100Hz 16:9 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1343 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1346 /* 118 - 3840x2160@120Hz 16:9 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1348 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1351 /* 119 - 3840x2160@100Hz 64:27 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1353 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1356 /* 120 - 3840x2160@120Hz 64:27 */
1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1358 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 121 - 5120x2160@24Hz 64:27 */
1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1363 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 122 - 5120x2160@25Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1368 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 123 - 5120x2160@30Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1373 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 124 - 5120x2160@48Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1378 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 125 - 5120x2160@50Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1383 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 126 - 5120x2160@60Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 127 - 5120x2160@100Hz 64:27 */
1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1393 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1396 };
1397
1398 /*
1399 * From CEA/CTA-861 spec.
1400 *
1401 * Do not access directly, instead always use cea_mode_for_vic().
1402 */
1403 static const struct drm_display_mode edid_cea_modes_193[] = {
1404 /* 193 - 5120x2160@120Hz 64:27 */
1405 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1406 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1408 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1409 /* 194 - 7680x4320@24Hz 16:9 */
1410 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1411 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1414 /* 195 - 7680x4320@25Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1416 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 196 - 7680x4320@30Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1421 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 197 - 7680x4320@48Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1426 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 198 - 7680x4320@50Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1431 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 199 - 7680x4320@60Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1436 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 200 - 7680x4320@100Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1441 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 201 - 7680x4320@120Hz 16:9 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1446 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449 /* 202 - 7680x4320@24Hz 64:27 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1451 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1454 /* 203 - 7680x4320@25Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1456 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 204 - 7680x4320@30Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1461 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 205 - 7680x4320@48Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1466 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 206 - 7680x4320@50Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1471 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 207 - 7680x4320@60Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1476 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 208 - 7680x4320@100Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1481 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 209 - 7680x4320@120Hz 64:27 */
1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1486 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 210 - 10240x4320@24Hz 64:27 */
1490 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1491 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 211 - 10240x4320@25Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1496 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 212 - 10240x4320@30Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1501 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 213 - 10240x4320@48Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1506 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 214 - 10240x4320@50Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1511 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 215 - 10240x4320@60Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1516 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 216 - 10240x4320@100Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1521 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 217 - 10240x4320@120Hz 64:27 */
1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1526 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529 /* 218 - 4096x2160@100Hz 256:135 */
1530 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1531 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1534 /* 219 - 4096x2160@120Hz 256:135 */
1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1536 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1539 };
1540
1541 /*
1542 * HDMI 1.4 4k modes. Index using the VIC.
1543 */
1544 static const struct drm_display_mode edid_4k_modes[] = {
1545 /* 0 - dummy, VICs start at 1 */
1546 { },
1547 /* 1 - 3840x2160@30Hz */
1548 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1549 3840, 4016, 4104, 4400, 0,
1550 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1553 /* 2 - 3840x2160@25Hz */
1554 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1555 3840, 4896, 4984, 5280, 0,
1556 2160, 2168, 2178, 2250, 0,
1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1558 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1559 /* 3 - 3840x2160@24Hz */
1560 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1561 3840, 5116, 5204, 5500, 0,
1562 2160, 2168, 2178, 2250, 0,
1563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1564 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1565 /* 4 - 4096x2160@24Hz (SMPTE) */
1566 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1567 4096, 5116, 5204, 5500, 0,
1568 2160, 2168, 2178, 2250, 0,
1569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1570 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1571 };
1572
1573 /*** DDC fetch and block validation ***/
1574
1575 /*
1576 * The opaque EDID type, internal to drm_edid.c.
1577 */
1578 struct drm_edid {
1579 /* Size allocated for edid */
1580 size_t size;
1581 const struct edid *edid;
1582 };
1583
version_greater(const struct drm_edid * drm_edid,u8 version,u8 revision)1584 static bool version_greater(const struct drm_edid *drm_edid,
1585 u8 version, u8 revision)
1586 {
1587 const struct edid *edid = drm_edid->edid;
1588
1589 return edid->version > version ||
1590 (edid->version == version && edid->revision > revision);
1591 }
1592
1593 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1594
edid_hfeeodb_block_count(const struct edid * edid)1595 static int edid_hfeeodb_block_count(const struct edid *edid)
1596 {
1597 int eeodb = edid_hfeeodb_extension_block_count(edid);
1598
1599 return eeodb ? eeodb + 1 : 0;
1600 }
1601
edid_extension_block_count(const struct edid * edid)1602 static int edid_extension_block_count(const struct edid *edid)
1603 {
1604 return edid->extensions;
1605 }
1606
edid_block_count(const struct edid * edid)1607 static int edid_block_count(const struct edid *edid)
1608 {
1609 return edid_extension_block_count(edid) + 1;
1610 }
1611
edid_size_by_blocks(int num_blocks)1612 static int edid_size_by_blocks(int num_blocks)
1613 {
1614 return num_blocks * EDID_LENGTH;
1615 }
1616
edid_size(const struct edid * edid)1617 static int edid_size(const struct edid *edid)
1618 {
1619 return edid_size_by_blocks(edid_block_count(edid));
1620 }
1621
edid_block_data(const struct edid * edid,int index)1622 static const void *edid_block_data(const struct edid *edid, int index)
1623 {
1624 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1625
1626 return edid + index;
1627 }
1628
edid_extension_block_data(const struct edid * edid,int index)1629 static const void *edid_extension_block_data(const struct edid *edid, int index)
1630 {
1631 return edid_block_data(edid, index + 1);
1632 }
1633
drm_edid_block_count(const struct drm_edid * drm_edid)1634 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1635 {
1636 int num_blocks;
1637
1638 /* Starting point */
1639 num_blocks = edid_block_count(drm_edid->edid);
1640
1641 /* HF-EEODB override */
1642 if (drm_edid->size >= edid_size_by_blocks(2)) {
1643 int eeodb;
1644
1645 /*
1646 * Note: HF-EEODB may specify a smaller extension count than the
1647 * regular one. Unlike in buffer allocation, here we can use it.
1648 */
1649 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1650 if (eeodb)
1651 num_blocks = eeodb;
1652 }
1653
1654 /* Limit by allocated size */
1655 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1656
1657 return num_blocks;
1658 }
1659
drm_edid_extension_block_count(const struct drm_edid * drm_edid)1660 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1661 {
1662 return drm_edid_block_count(drm_edid) - 1;
1663 }
1664
drm_edid_block_data(const struct drm_edid * drm_edid,int index)1665 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1666 {
1667 return edid_block_data(drm_edid->edid, index);
1668 }
1669
drm_edid_extension_block_data(const struct drm_edid * drm_edid,int index)1670 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1671 int index)
1672 {
1673 return edid_extension_block_data(drm_edid->edid, index);
1674 }
1675
1676 /*
1677 * Initializer helper for legacy interfaces, where we have no choice but to
1678 * trust edid size. Not for general purpose use.
1679 */
drm_edid_legacy_init(struct drm_edid * drm_edid,const struct edid * edid)1680 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1681 const struct edid *edid)
1682 {
1683 if (!edid)
1684 return NULL;
1685
1686 memset(drm_edid, 0, sizeof(*drm_edid));
1687
1688 drm_edid->edid = edid;
1689 drm_edid->size = edid_size(edid);
1690
1691 return drm_edid;
1692 }
1693
1694 /*
1695 * EDID base and extension block iterator.
1696 *
1697 * struct drm_edid_iter iter;
1698 * const u8 *block;
1699 *
1700 * drm_edid_iter_begin(drm_edid, &iter);
1701 * drm_edid_iter_for_each(block, &iter) {
1702 * // do stuff with block
1703 * }
1704 * drm_edid_iter_end(&iter);
1705 */
1706 struct drm_edid_iter {
1707 const struct drm_edid *drm_edid;
1708
1709 /* Current block index. */
1710 int index;
1711 };
1712
drm_edid_iter_begin(const struct drm_edid * drm_edid,struct drm_edid_iter * iter)1713 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1714 struct drm_edid_iter *iter)
1715 {
1716 memset(iter, 0, sizeof(*iter));
1717
1718 iter->drm_edid = drm_edid;
1719 }
1720
__drm_edid_iter_next(struct drm_edid_iter * iter)1721 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1722 {
1723 const void *block = NULL;
1724
1725 if (!iter->drm_edid)
1726 return NULL;
1727
1728 if (iter->index < drm_edid_block_count(iter->drm_edid))
1729 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1730
1731 return block;
1732 }
1733
1734 #define drm_edid_iter_for_each(__block, __iter) \
1735 while (((__block) = __drm_edid_iter_next(__iter)))
1736
drm_edid_iter_end(struct drm_edid_iter * iter)1737 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1738 {
1739 memset(iter, 0, sizeof(*iter));
1740 }
1741
1742 static const u8 edid_header[] = {
1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1744 };
1745
edid_header_fix(void * edid)1746 static void edid_header_fix(void *edid)
1747 {
1748 memcpy(edid, edid_header, sizeof(edid_header));
1749 }
1750
1751 /**
1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1753 * @_edid: pointer to raw base EDID block
1754 *
1755 * Sanity check the header of the base EDID block.
1756 *
1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1758 */
drm_edid_header_is_valid(const void * _edid)1759 int drm_edid_header_is_valid(const void *_edid)
1760 {
1761 const struct edid *edid = _edid;
1762 int i, score = 0;
1763
1764 for (i = 0; i < sizeof(edid_header); i++) {
1765 if (edid->header[i] == edid_header[i])
1766 score++;
1767 }
1768
1769 return score;
1770 }
1771 EXPORT_SYMBOL(drm_edid_header_is_valid);
1772
1773 static int edid_fixup __read_mostly = 6;
1774 module_param_named(edid_fixup, edid_fixup, int, 0400);
1775 MODULE_PARM_DESC(edid_fixup,
1776 "Minimum number of valid EDID header bytes (0-8, default 6)");
1777
edid_block_compute_checksum(const void * _block)1778 static int edid_block_compute_checksum(const void *_block)
1779 {
1780 const u8 *block = _block;
1781 int i;
1782 u8 csum = 0, crc = 0;
1783
1784 for (i = 0; i < EDID_LENGTH - 1; i++)
1785 csum += block[i];
1786
1787 crc = 0x100 - csum;
1788
1789 return crc;
1790 }
1791
edid_block_get_checksum(const void * _block)1792 static int edid_block_get_checksum(const void *_block)
1793 {
1794 const struct edid *block = _block;
1795
1796 return block->checksum;
1797 }
1798
edid_block_tag(const void * _block)1799 static int edid_block_tag(const void *_block)
1800 {
1801 const u8 *block = _block;
1802
1803 return block[0];
1804 }
1805
edid_block_is_zero(const void * edid)1806 static bool edid_block_is_zero(const void *edid)
1807 {
1808 return !memchr_inv(edid, 0, EDID_LENGTH);
1809 }
1810
1811 /**
1812 * drm_edid_are_equal - compare two edid blobs.
1813 * @edid1: pointer to first blob
1814 * @edid2: pointer to second blob
1815 * This helper can be used during probing to determine if
1816 * edid had changed.
1817 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1818 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1819 {
1820 int edid1_len, edid2_len;
1821 bool edid1_present = edid1 != NULL;
1822 bool edid2_present = edid2 != NULL;
1823
1824 if (edid1_present != edid2_present)
1825 return false;
1826
1827 if (edid1) {
1828 edid1_len = edid_size(edid1);
1829 edid2_len = edid_size(edid2);
1830
1831 if (edid1_len != edid2_len)
1832 return false;
1833
1834 if (memcmp(edid1, edid2, edid1_len))
1835 return false;
1836 }
1837
1838 return true;
1839 }
1840 EXPORT_SYMBOL(drm_edid_are_equal);
1841
1842 enum edid_block_status {
1843 EDID_BLOCK_OK = 0,
1844 EDID_BLOCK_READ_FAIL,
1845 EDID_BLOCK_NULL,
1846 EDID_BLOCK_ZERO,
1847 EDID_BLOCK_HEADER_CORRUPT,
1848 EDID_BLOCK_HEADER_REPAIR,
1849 EDID_BLOCK_HEADER_FIXED,
1850 EDID_BLOCK_CHECKSUM,
1851 EDID_BLOCK_VERSION,
1852 };
1853
edid_block_check(const void * _block,bool is_base_block)1854 static enum edid_block_status edid_block_check(const void *_block,
1855 bool is_base_block)
1856 {
1857 const struct edid *block = _block;
1858
1859 if (!block)
1860 return EDID_BLOCK_NULL;
1861
1862 if (is_base_block) {
1863 int score = drm_edid_header_is_valid(block);
1864
1865 if (score < clamp(edid_fixup, 0, 8)) {
1866 if (edid_block_is_zero(block))
1867 return EDID_BLOCK_ZERO;
1868 else
1869 return EDID_BLOCK_HEADER_CORRUPT;
1870 }
1871
1872 if (score < 8)
1873 return EDID_BLOCK_HEADER_REPAIR;
1874 }
1875
1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1877 if (edid_block_is_zero(block))
1878 return EDID_BLOCK_ZERO;
1879 else
1880 return EDID_BLOCK_CHECKSUM;
1881 }
1882
1883 if (is_base_block) {
1884 if (block->version != 1)
1885 return EDID_BLOCK_VERSION;
1886 }
1887
1888 return EDID_BLOCK_OK;
1889 }
1890
edid_block_status_valid(enum edid_block_status status,int tag)1891 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1892 {
1893 return status == EDID_BLOCK_OK ||
1894 status == EDID_BLOCK_HEADER_FIXED ||
1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1896 }
1897
edid_block_valid(const void * block,bool base)1898 static bool edid_block_valid(const void *block, bool base)
1899 {
1900 return edid_block_status_valid(edid_block_check(block, base),
1901 edid_block_tag(block));
1902 }
1903
edid_block_status_print(enum edid_block_status status,const struct edid * block,int block_num)1904 static void edid_block_status_print(enum edid_block_status status,
1905 const struct edid *block,
1906 int block_num)
1907 {
1908 switch (status) {
1909 case EDID_BLOCK_OK:
1910 break;
1911 case EDID_BLOCK_READ_FAIL:
1912 pr_debug("EDID block %d read failed\n", block_num);
1913 break;
1914 case EDID_BLOCK_NULL:
1915 pr_debug("EDID block %d pointer is NULL\n", block_num);
1916 break;
1917 case EDID_BLOCK_ZERO:
1918 pr_notice("EDID block %d is all zeroes\n", block_num);
1919 break;
1920 case EDID_BLOCK_HEADER_CORRUPT:
1921 pr_notice("EDID has corrupt header\n");
1922 break;
1923 case EDID_BLOCK_HEADER_REPAIR:
1924 pr_debug("EDID corrupt header needs repair\n");
1925 break;
1926 case EDID_BLOCK_HEADER_FIXED:
1927 pr_debug("EDID corrupt header fixed\n");
1928 break;
1929 case EDID_BLOCK_CHECKSUM:
1930 if (edid_block_status_valid(status, edid_block_tag(block))) {
1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1932 block_num, edid_block_tag(block),
1933 edid_block_compute_checksum(block));
1934 } else {
1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1936 block_num, edid_block_tag(block),
1937 edid_block_compute_checksum(block));
1938 }
1939 break;
1940 case EDID_BLOCK_VERSION:
1941 pr_notice("EDID has major version %d, instead of 1\n",
1942 block->version);
1943 break;
1944 default:
1945 WARN(1, "EDID block %d unknown edid block status code %d\n",
1946 block_num, status);
1947 break;
1948 }
1949 }
1950
edid_block_dump(const char * level,const void * block,int block_num)1951 static void edid_block_dump(const char *level, const void *block, int block_num)
1952 {
1953 enum edid_block_status status;
1954 char prefix[20];
1955
1956 status = edid_block_check(block, block_num == 0);
1957 if (status == EDID_BLOCK_ZERO)
1958 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1959 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1960 sprintf(prefix, "\t[%02x] BAD ", block_num);
1961 else
1962 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1963
1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1965 block, EDID_LENGTH, false);
1966 }
1967
1968 /**
1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1970 * @_block: pointer to raw EDID block
1971 * @block_num: type of block to validate (0 for base, extension otherwise)
1972 * @print_bad_edid: if true, dump bad EDID blocks to the console
1973 * @edid_corrupt: if true, the header or checksum is invalid
1974 *
1975 * Validate a base or extension EDID block and optionally dump bad blocks to
1976 * the console.
1977 *
1978 * Return: True if the block is valid, false otherwise.
1979 */
drm_edid_block_valid(u8 * _block,int block_num,bool print_bad_edid,bool * edid_corrupt)1980 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1981 bool *edid_corrupt)
1982 {
1983 struct edid *block = (struct edid *)_block;
1984 enum edid_block_status status;
1985 bool is_base_block = block_num == 0;
1986 bool valid;
1987
1988 if (WARN_ON(!block))
1989 return false;
1990
1991 status = edid_block_check(block, is_base_block);
1992 if (status == EDID_BLOCK_HEADER_REPAIR) {
1993 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1994 edid_header_fix(block);
1995
1996 /* Retry with fixed header, update status if that worked. */
1997 status = edid_block_check(block, is_base_block);
1998 if (status == EDID_BLOCK_OK)
1999 status = EDID_BLOCK_HEADER_FIXED;
2000 }
2001
2002 if (edid_corrupt) {
2003 /*
2004 * Unknown major version isn't corrupt but we can't use it. Only
2005 * the base block can reset edid_corrupt to false.
2006 */
2007 if (is_base_block &&
2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2009 *edid_corrupt = false;
2010 else if (status != EDID_BLOCK_OK)
2011 *edid_corrupt = true;
2012 }
2013
2014 edid_block_status_print(status, block, block_num);
2015
2016 /* Determine whether we can use this block with this status. */
2017 valid = edid_block_status_valid(status, edid_block_tag(block));
2018
2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2020 pr_notice("Raw EDID:\n");
2021 edid_block_dump(KERN_NOTICE, block, block_num);
2022 }
2023
2024 return valid;
2025 }
2026 EXPORT_SYMBOL(drm_edid_block_valid);
2027
2028 /**
2029 * drm_edid_is_valid - sanity check EDID data
2030 * @edid: EDID data
2031 *
2032 * Sanity-check an entire EDID record (including extensions)
2033 *
2034 * Return: True if the EDID data is valid, false otherwise.
2035 */
drm_edid_is_valid(struct edid * edid)2036 bool drm_edid_is_valid(struct edid *edid)
2037 {
2038 int i;
2039
2040 if (!edid)
2041 return false;
2042
2043 for (i = 0; i < edid_block_count(edid); i++) {
2044 void *block = (void *)edid_block_data(edid, i);
2045
2046 if (!drm_edid_block_valid(block, i, true, NULL))
2047 return false;
2048 }
2049
2050 return true;
2051 }
2052 EXPORT_SYMBOL(drm_edid_is_valid);
2053
edid_filter_invalid_blocks(struct edid * edid,size_t * alloc_size)2054 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2055 size_t *alloc_size)
2056 {
2057 struct edid *new;
2058 int i, valid_blocks = 0;
2059
2060 /*
2061 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2062 * back to regular extension count here. We don't want to start
2063 * modifying the HF-EEODB extension too.
2064 */
2065 for (i = 0; i < edid_block_count(edid); i++) {
2066 const void *src_block = edid_block_data(edid, i);
2067
2068 if (edid_block_valid(src_block, i == 0)) {
2069 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2070
2071 memmove(dst_block, src_block, EDID_LENGTH);
2072 valid_blocks++;
2073 }
2074 }
2075
2076 /* We already trusted the base block to be valid here... */
2077 if (WARN_ON(!valid_blocks)) {
2078 kfree(edid);
2079 return NULL;
2080 }
2081
2082 edid->extensions = valid_blocks - 1;
2083 edid->checksum = edid_block_compute_checksum(edid);
2084
2085 *alloc_size = edid_size_by_blocks(valid_blocks);
2086
2087 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2088 if (!new)
2089 kfree(edid);
2090
2091 return new;
2092 }
2093
2094 #define DDC_SEGMENT_ADDR 0x30
2095 /**
2096 * drm_do_probe_ddc_edid() - get EDID information via I2C
2097 * @data: I2C device adapter
2098 * @buf: EDID data buffer to be filled
2099 * @block: 128 byte EDID block to start fetching from
2100 * @len: EDID data buffer length to fetch
2101 *
2102 * Try to fetch EDID information by calling I2C driver functions.
2103 *
2104 * Return: 0 on success or -1 on failure.
2105 */
2106 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)2107 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2108 {
2109 struct i2c_adapter *adapter = data;
2110 unsigned char start = block * EDID_LENGTH;
2111 unsigned char segment = block >> 1;
2112 unsigned char xfers = segment ? 3 : 2;
2113 int ret, retries = 5;
2114
2115 /*
2116 * The core I2C driver will automatically retry the transfer if the
2117 * adapter reports EAGAIN. However, we find that bit-banging transfers
2118 * are susceptible to errors under a heavily loaded machine and
2119 * generate spurious NAKs and timeouts. Retrying the transfer
2120 * of the individual block a few times seems to overcome this.
2121 */
2122 do {
2123 struct i2c_msg msgs[] = {
2124 {
2125 .addr = DDC_SEGMENT_ADDR,
2126 .flags = 0,
2127 .len = 1,
2128 .buf = &segment,
2129 }, {
2130 .addr = DDC_ADDR,
2131 .flags = 0,
2132 .len = 1,
2133 .buf = &start,
2134 }, {
2135 .addr = DDC_ADDR,
2136 .flags = I2C_M_RD,
2137 .len = len,
2138 .buf = buf,
2139 }
2140 };
2141
2142 /*
2143 * Avoid sending the segment addr to not upset non-compliant
2144 * DDC monitors.
2145 */
2146 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2147
2148 if (ret == -ENXIO) {
2149 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2150 adapter->name);
2151 break;
2152 }
2153 } while (ret != xfers && --retries);
2154
2155 return ret == xfers ? 0 : -1;
2156 }
2157
connector_bad_edid(struct drm_connector * connector,const struct edid * edid,int num_blocks)2158 static void connector_bad_edid(struct drm_connector *connector,
2159 const struct edid *edid, int num_blocks)
2160 {
2161 int i;
2162 u8 last_block;
2163
2164 /*
2165 * 0x7e in the EDID is the number of extension blocks. The EDID
2166 * is 1 (base block) + num_ext_blocks big. That means we can think
2167 * of 0x7e in the EDID of the _index_ of the last block in the
2168 * combined chunk of memory.
2169 */
2170 last_block = edid->extensions;
2171
2172 /* Calculate real checksum for the last edid extension block data */
2173 if (last_block < num_blocks)
2174 connector->real_edid_checksum =
2175 edid_block_compute_checksum(edid + last_block);
2176
2177 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2178 return;
2179
2180 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2181 for (i = 0; i < num_blocks; i++)
2182 edid_block_dump(KERN_DEBUG, edid + i, i);
2183 }
2184
2185 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector,size_t * alloc_size)2186 static struct edid *drm_get_override_edid(struct drm_connector *connector,
2187 size_t *alloc_size)
2188 {
2189 struct edid *override = NULL;
2190
2191 if (connector->override_edid)
2192 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2193
2194 if (!override)
2195 override = drm_load_edid_firmware(connector);
2196
2197 /* FIXME: Get alloc size from deeper down the stack */
2198 if (!IS_ERR_OR_NULL(override) && alloc_size)
2199 *alloc_size = edid_size(override);
2200
2201 return IS_ERR(override) ? NULL : override;
2202 }
2203
2204 /* For debugfs edid_override implementation */
drm_edid_override_set(struct drm_connector * connector,const void * edid,size_t size)2205 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2206 size_t size)
2207 {
2208 int ret;
2209
2210 if (size < EDID_LENGTH || edid_size(edid) > size)
2211 return -EINVAL;
2212
2213 connector->override_edid = false;
2214
2215 ret = drm_connector_update_edid_property(connector, edid);
2216 if (!ret)
2217 connector->override_edid = true;
2218
2219 return ret;
2220 }
2221
2222 /* For debugfs edid_override implementation */
drm_edid_override_reset(struct drm_connector * connector)2223 int drm_edid_override_reset(struct drm_connector *connector)
2224 {
2225 connector->override_edid = false;
2226
2227 return drm_connector_update_edid_property(connector, NULL);
2228 }
2229
2230 /**
2231 * drm_add_override_edid_modes - add modes from override/firmware EDID
2232 * @connector: connector we're probing
2233 *
2234 * Add modes from the override/firmware EDID, if available. Only to be used from
2235 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2236 * failed during drm_get_edid() and caused the override/firmware EDID to be
2237 * skipped.
2238 *
2239 * Return: The number of modes added or 0 if we couldn't find any.
2240 */
drm_add_override_edid_modes(struct drm_connector * connector)2241 int drm_add_override_edid_modes(struct drm_connector *connector)
2242 {
2243 struct edid *override;
2244 int num_modes = 0;
2245
2246 override = drm_get_override_edid(connector, NULL);
2247 if (override) {
2248 drm_connector_update_edid_property(connector, override);
2249 num_modes = drm_add_edid_modes(connector, override);
2250 kfree(override);
2251
2252 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2253 connector->base.id, connector->name, num_modes);
2254 }
2255
2256 return num_modes;
2257 }
2258 EXPORT_SYMBOL(drm_add_override_edid_modes);
2259
2260 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2261
edid_block_read(void * block,unsigned int block_num,read_block_fn read_block,void * context)2262 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2263 read_block_fn read_block,
2264 void *context)
2265 {
2266 enum edid_block_status status;
2267 bool is_base_block = block_num == 0;
2268 int try;
2269
2270 for (try = 0; try < 4; try++) {
2271 if (read_block(context, block, block_num, EDID_LENGTH))
2272 return EDID_BLOCK_READ_FAIL;
2273
2274 status = edid_block_check(block, is_base_block);
2275 if (status == EDID_BLOCK_HEADER_REPAIR) {
2276 edid_header_fix(block);
2277
2278 /* Retry with fixed header, update status if that worked. */
2279 status = edid_block_check(block, is_base_block);
2280 if (status == EDID_BLOCK_OK)
2281 status = EDID_BLOCK_HEADER_FIXED;
2282 }
2283
2284 if (edid_block_status_valid(status, edid_block_tag(block)))
2285 break;
2286
2287 /* Fail early for unrepairable base block all zeros. */
2288 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2289 break;
2290 }
2291
2292 return status;
2293 }
2294
_drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context,size_t * size)2295 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2296 read_block_fn read_block, void *context,
2297 size_t *size)
2298 {
2299 enum edid_block_status status;
2300 int i, num_blocks, invalid_blocks = 0;
2301 struct edid *edid, *new;
2302 size_t alloc_size = EDID_LENGTH;
2303
2304 edid = drm_get_override_edid(connector, &alloc_size);
2305 if (edid)
2306 goto ok;
2307
2308 edid = kmalloc(alloc_size, GFP_KERNEL);
2309 if (!edid)
2310 return NULL;
2311
2312 status = edid_block_read(edid, 0, read_block, context);
2313
2314 edid_block_status_print(status, edid, 0);
2315
2316 if (status == EDID_BLOCK_READ_FAIL)
2317 goto fail;
2318
2319 /* FIXME: Clarify what a corrupt EDID actually means. */
2320 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2321 connector->edid_corrupt = false;
2322 else
2323 connector->edid_corrupt = true;
2324
2325 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2326 if (status == EDID_BLOCK_ZERO)
2327 connector->null_edid_counter++;
2328
2329 connector_bad_edid(connector, edid, 1);
2330 goto fail;
2331 }
2332
2333 if (!edid_extension_block_count(edid))
2334 goto ok;
2335
2336 alloc_size = edid_size(edid);
2337 new = krealloc(edid, alloc_size, GFP_KERNEL);
2338 if (!new)
2339 goto fail;
2340 edid = new;
2341
2342 num_blocks = edid_block_count(edid);
2343 for (i = 1; i < num_blocks; i++) {
2344 void *block = (void *)edid_block_data(edid, i);
2345
2346 status = edid_block_read(block, i, read_block, context);
2347
2348 edid_block_status_print(status, block, i);
2349
2350 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2351 if (status == EDID_BLOCK_READ_FAIL)
2352 goto fail;
2353 invalid_blocks++;
2354 } else if (i == 1) {
2355 /*
2356 * If the first EDID extension is a CTA extension, and
2357 * the first Data Block is HF-EEODB, override the
2358 * extension block count.
2359 *
2360 * Note: HF-EEODB could specify a smaller extension
2361 * count too, but we can't risk allocating a smaller
2362 * amount.
2363 */
2364 int eeodb = edid_hfeeodb_block_count(edid);
2365
2366 if (eeodb > num_blocks) {
2367 num_blocks = eeodb;
2368 alloc_size = edid_size_by_blocks(num_blocks);
2369 new = krealloc(edid, alloc_size, GFP_KERNEL);
2370 if (!new)
2371 goto fail;
2372 edid = new;
2373 }
2374 }
2375 }
2376
2377 if (invalid_blocks) {
2378 connector_bad_edid(connector, edid, num_blocks);
2379
2380 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2381 }
2382
2383 ok:
2384 if (size)
2385 *size = alloc_size;
2386
2387 return edid;
2388
2389 fail:
2390 kfree(edid);
2391 return NULL;
2392 }
2393
2394 /**
2395 * drm_do_get_edid - get EDID data using a custom EDID block read function
2396 * @connector: connector we're probing
2397 * @read_block: EDID block read function
2398 * @context: private data passed to the block read function
2399 *
2400 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2401 * exposes a different interface to read EDID blocks this function can be used
2402 * to get EDID data using a custom block read function.
2403 *
2404 * As in the general case the DDC bus is accessible by the kernel at the I2C
2405 * level, drivers must make all reasonable efforts to expose it as an I2C
2406 * adapter and use drm_get_edid() instead of abusing this function.
2407 *
2408 * The EDID may be overridden using debugfs override_edid or firmware EDID
2409 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2410 * order. Having either of them bypasses actual EDID reads.
2411 *
2412 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2413 */
drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context)2414 struct edid *drm_do_get_edid(struct drm_connector *connector,
2415 read_block_fn read_block,
2416 void *context)
2417 {
2418 return _drm_do_get_edid(connector, read_block, context, NULL);
2419 }
2420 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2421
2422 /**
2423 * drm_edid_raw - Get a pointer to the raw EDID data.
2424 * @drm_edid: drm_edid container
2425 *
2426 * Get a pointer to the raw EDID data.
2427 *
2428 * This is for transition only. Avoid using this like the plague.
2429 *
2430 * Return: Pointer to raw EDID data.
2431 */
drm_edid_raw(const struct drm_edid * drm_edid)2432 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2433 {
2434 if (!drm_edid || !drm_edid->size)
2435 return NULL;
2436
2437 /*
2438 * Do not return pointers where relying on EDID extension count would
2439 * lead to buffer overflow.
2440 */
2441 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2442 return NULL;
2443
2444 return drm_edid->edid;
2445 }
2446 EXPORT_SYMBOL(drm_edid_raw);
2447
2448 /* Allocate struct drm_edid container *without* duplicating the edid data */
_drm_edid_alloc(const void * edid,size_t size)2449 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2450 {
2451 struct drm_edid *drm_edid;
2452
2453 if (!edid || !size || size < EDID_LENGTH)
2454 return NULL;
2455
2456 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2457 if (drm_edid) {
2458 drm_edid->edid = edid;
2459 drm_edid->size = size;
2460 }
2461
2462 return drm_edid;
2463 }
2464
2465 /**
2466 * drm_edid_alloc - Allocate a new drm_edid container
2467 * @edid: Pointer to raw EDID data
2468 * @size: Size of memory allocated for EDID
2469 *
2470 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2471 * the actual size that has been allocated for the data. There is no validation
2472 * of the raw EDID data against the size, but at least the EDID base block must
2473 * fit in the buffer.
2474 *
2475 * The returned pointer must be freed using drm_edid_free().
2476 *
2477 * Return: drm_edid container, or NULL on errors
2478 */
drm_edid_alloc(const void * edid,size_t size)2479 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2480 {
2481 const struct drm_edid *drm_edid;
2482
2483 if (!edid || !size || size < EDID_LENGTH)
2484 return NULL;
2485
2486 edid = kmemdup(edid, size, GFP_KERNEL);
2487 if (!edid)
2488 return NULL;
2489
2490 drm_edid = _drm_edid_alloc(edid, size);
2491 if (!drm_edid)
2492 kfree(edid);
2493
2494 return drm_edid;
2495 }
2496 EXPORT_SYMBOL(drm_edid_alloc);
2497
2498 /**
2499 * drm_edid_dup - Duplicate a drm_edid container
2500 * @drm_edid: EDID to duplicate
2501 *
2502 * The returned pointer must be freed using drm_edid_free().
2503 *
2504 * Returns: drm_edid container copy, or NULL on errors
2505 */
drm_edid_dup(const struct drm_edid * drm_edid)2506 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2507 {
2508 if (!drm_edid)
2509 return NULL;
2510
2511 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2512 }
2513 EXPORT_SYMBOL(drm_edid_dup);
2514
2515 /**
2516 * drm_edid_free - Free the drm_edid container
2517 * @drm_edid: EDID to free
2518 */
drm_edid_free(const struct drm_edid * drm_edid)2519 void drm_edid_free(const struct drm_edid *drm_edid)
2520 {
2521 if (!drm_edid)
2522 return;
2523
2524 kfree(drm_edid->edid);
2525 kfree(drm_edid);
2526 }
2527 EXPORT_SYMBOL(drm_edid_free);
2528
2529 /**
2530 * drm_probe_ddc() - probe DDC presence
2531 * @adapter: I2C adapter to probe
2532 *
2533 * Return: True on success, false on failure.
2534 */
2535 bool
drm_probe_ddc(struct i2c_adapter * adapter)2536 drm_probe_ddc(struct i2c_adapter *adapter)
2537 {
2538 unsigned char out;
2539
2540 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2541 }
2542 EXPORT_SYMBOL(drm_probe_ddc);
2543
2544 /**
2545 * drm_get_edid - get EDID data, if available
2546 * @connector: connector we're probing
2547 * @adapter: I2C adapter to use for DDC
2548 *
2549 * Poke the given I2C channel to grab EDID data if possible. If found,
2550 * attach it to the connector.
2551 *
2552 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2553 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2554 struct edid *drm_get_edid(struct drm_connector *connector,
2555 struct i2c_adapter *adapter)
2556 {
2557 struct edid *edid;
2558
2559 if (connector->force == DRM_FORCE_OFF)
2560 return NULL;
2561
2562 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2563 return NULL;
2564
2565 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2566 drm_connector_update_edid_property(connector, edid);
2567 return edid;
2568 }
2569 EXPORT_SYMBOL(drm_get_edid);
2570
2571 /**
2572 * drm_edid_read_custom - Read EDID data using given EDID block read function
2573 * @connector: Connector to use
2574 * @read_block: EDID block read function
2575 * @context: Private data passed to the block read function
2576 *
2577 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2578 * exposes a different interface to read EDID blocks this function can be used
2579 * to get EDID data using a custom block read function.
2580 *
2581 * As in the general case the DDC bus is accessible by the kernel at the I2C
2582 * level, drivers must make all reasonable efforts to expose it as an I2C
2583 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2584 * this function.
2585 *
2586 * The EDID may be overridden using debugfs override_edid or firmware EDID
2587 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2588 * order. Having either of them bypasses actual EDID reads.
2589 *
2590 * The returned pointer must be freed using drm_edid_free().
2591 *
2592 * Return: Pointer to EDID, or NULL if probe/read failed.
2593 */
drm_edid_read_custom(struct drm_connector * connector,read_block_fn read_block,void * context)2594 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2595 read_block_fn read_block,
2596 void *context)
2597 {
2598 const struct drm_edid *drm_edid;
2599 struct edid *edid;
2600 size_t size = 0;
2601
2602 edid = _drm_do_get_edid(connector, read_block, context, &size);
2603 if (!edid)
2604 return NULL;
2605
2606 /* Sanity check for now */
2607 drm_WARN_ON(connector->dev, !size);
2608
2609 drm_edid = _drm_edid_alloc(edid, size);
2610 if (!drm_edid)
2611 kfree(edid);
2612
2613 return drm_edid;
2614 }
2615 EXPORT_SYMBOL(drm_edid_read_custom);
2616
2617 /**
2618 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2619 * @connector: Connector to use
2620 * @adapter: I2C adapter to use for DDC
2621 *
2622 * Read EDID using the given I2C adapter.
2623 *
2624 * The EDID may be overridden using debugfs override_edid or firmware EDID
2625 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2626 * order. Having either of them bypasses actual EDID reads.
2627 *
2628 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2629 * using drm_edid_read() instead of this function.
2630 *
2631 * The returned pointer must be freed using drm_edid_free().
2632 *
2633 * Return: Pointer to EDID, or NULL if probe/read failed.
2634 */
drm_edid_read_ddc(struct drm_connector * connector,struct i2c_adapter * adapter)2635 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2636 struct i2c_adapter *adapter)
2637 {
2638 const struct drm_edid *drm_edid;
2639
2640 if (connector->force == DRM_FORCE_OFF)
2641 return NULL;
2642
2643 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2644 return NULL;
2645
2646 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2647
2648 /* Note: Do *not* call connector updates here. */
2649
2650 return drm_edid;
2651 }
2652 EXPORT_SYMBOL(drm_edid_read_ddc);
2653
2654 /**
2655 * drm_edid_read - Read EDID data using connector's I2C adapter
2656 * @connector: Connector to use
2657 *
2658 * Read EDID using the connector's I2C adapter.
2659 *
2660 * The EDID may be overridden using debugfs override_edid or firmware EDID
2661 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2662 * order. Having either of them bypasses actual EDID reads.
2663 *
2664 * The returned pointer must be freed using drm_edid_free().
2665 *
2666 * Return: Pointer to EDID, or NULL if probe/read failed.
2667 */
drm_edid_read(struct drm_connector * connector)2668 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2669 {
2670 if (drm_WARN_ON(connector->dev, !connector->ddc))
2671 return NULL;
2672
2673 return drm_edid_read_ddc(connector, connector->ddc);
2674 }
2675 EXPORT_SYMBOL(drm_edid_read);
2676
edid_extract_panel_id(const struct edid * edid)2677 static u32 edid_extract_panel_id(const struct edid *edid)
2678 {
2679 /*
2680 * We represent the ID as a 32-bit number so it can easily be compared
2681 * with "==".
2682 *
2683 * NOTE that we deal with endianness differently for the top half
2684 * of this ID than for the bottom half. The bottom half (the product
2685 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2686 * that's how everyone seems to interpret it. The top half (the mfg_id)
2687 * gets stored as big endian because that makes
2688 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2689 * to write (it's easier to extract the ASCII). It doesn't really
2690 * matter, though, as long as the number here is unique.
2691 */
2692 return (u32)edid->mfg_id[0] << 24 |
2693 (u32)edid->mfg_id[1] << 16 |
2694 (u32)EDID_PRODUCT_ID(edid);
2695 }
2696
2697 /**
2698 * drm_edid_get_panel_id - Get a panel's ID through DDC
2699 * @adapter: I2C adapter to use for DDC
2700 *
2701 * This function reads the first block of the EDID of a panel and (assuming
2702 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2703 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2704 * supposed to be different for each different modem of panel.
2705 *
2706 * This function is intended to be used during early probing on devices where
2707 * more than one panel might be present. Because of its intended use it must
2708 * assume that the EDID of the panel is correct, at least as far as the ID
2709 * is concerned (in other words, we don't process any overrides here).
2710 *
2711 * NOTE: it's expected that this function and drm_do_get_edid() will both
2712 * be read the EDID, but there is no caching between them. Since we're only
2713 * reading the first block, hopefully this extra overhead won't be too big.
2714 *
2715 * Return: A 32-bit ID that should be different for each make/model of panel.
2716 * See the functions drm_edid_encode_panel_id() and
2717 * drm_edid_decode_panel_id() for some details on the structure of this
2718 * ID.
2719 */
2720
drm_edid_get_panel_id(struct i2c_adapter * adapter)2721 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2722 {
2723 enum edid_block_status status;
2724 void *base_block;
2725 u32 panel_id = 0;
2726
2727 /*
2728 * There are no manufacturer IDs of 0, so if there is a problem reading
2729 * the EDID then we'll just return 0.
2730 */
2731
2732 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2733 if (!base_block)
2734 return 0;
2735
2736 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2737
2738 edid_block_status_print(status, base_block, 0);
2739
2740 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2741 panel_id = edid_extract_panel_id(base_block);
2742
2743 kfree(base_block);
2744
2745 return panel_id;
2746 }
2747 EXPORT_SYMBOL(drm_edid_get_panel_id);
2748
2749 /**
2750 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2751 * @connector: connector we're probing
2752 * @adapter: I2C adapter to use for DDC
2753 *
2754 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2755 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2756 * switch DDC to the GPU which is retrieving EDID.
2757 *
2758 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2759 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2760 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2761 struct i2c_adapter *adapter)
2762 {
2763 struct drm_device *dev = connector->dev;
2764 struct pci_dev *pdev = to_pci_dev(dev->dev);
2765 struct edid *edid;
2766
2767 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2768 return NULL;
2769
2770 vga_switcheroo_lock_ddc(pdev);
2771 edid = drm_get_edid(connector, adapter);
2772 vga_switcheroo_unlock_ddc(pdev);
2773
2774 return edid;
2775 }
2776 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2777
2778 /**
2779 * drm_edid_duplicate - duplicate an EDID and the extensions
2780 * @edid: EDID to duplicate
2781 *
2782 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2783 */
drm_edid_duplicate(const struct edid * edid)2784 struct edid *drm_edid_duplicate(const struct edid *edid)
2785 {
2786 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2787 }
2788 EXPORT_SYMBOL(drm_edid_duplicate);
2789
2790 /*** EDID parsing ***/
2791
2792 /**
2793 * edid_get_quirks - return quirk flags for a given EDID
2794 * @drm_edid: EDID to process
2795 *
2796 * This tells subsequent routines what fixes they need to apply.
2797 */
edid_get_quirks(const struct drm_edid * drm_edid)2798 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2799 {
2800 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2801 const struct edid_quirk *quirk;
2802 int i;
2803
2804 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2805 quirk = &edid_quirk_list[i];
2806 if (quirk->panel_id == panel_id)
2807 return quirk->quirks;
2808 }
2809
2810 return 0;
2811 }
2812
2813 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2814 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2815
2816 /*
2817 * Walk the mode list for connector, clearing the preferred status on existing
2818 * modes and setting it anew for the right mode ala quirks.
2819 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2820 static void edid_fixup_preferred(struct drm_connector *connector,
2821 u32 quirks)
2822 {
2823 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2824 int target_refresh = 0;
2825 int cur_vrefresh, preferred_vrefresh;
2826
2827 if (list_empty(&connector->probed_modes))
2828 return;
2829
2830 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2831 target_refresh = 60;
2832 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2833 target_refresh = 75;
2834
2835 preferred_mode = list_first_entry(&connector->probed_modes,
2836 struct drm_display_mode, head);
2837
2838 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2839 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2840
2841 if (cur_mode == preferred_mode)
2842 continue;
2843
2844 /* Largest mode is preferred */
2845 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2846 preferred_mode = cur_mode;
2847
2848 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2849 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2850 /* At a given size, try to get closest to target refresh */
2851 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2852 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2853 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2854 preferred_mode = cur_mode;
2855 }
2856 }
2857
2858 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2859 }
2860
2861 static bool
mode_is_rb(const struct drm_display_mode * mode)2862 mode_is_rb(const struct drm_display_mode *mode)
2863 {
2864 return (mode->htotal - mode->hdisplay == 160) &&
2865 (mode->hsync_end - mode->hdisplay == 80) &&
2866 (mode->hsync_end - mode->hsync_start == 32) &&
2867 (mode->vsync_start - mode->vdisplay == 3);
2868 }
2869
2870 /*
2871 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2872 * @dev: Device to duplicate against
2873 * @hsize: Mode width
2874 * @vsize: Mode height
2875 * @fresh: Mode refresh rate
2876 * @rb: Mode reduced-blanking-ness
2877 *
2878 * Walk the DMT mode list looking for a match for the given parameters.
2879 *
2880 * Return: A newly allocated copy of the mode, or NULL if not found.
2881 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2882 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2883 int hsize, int vsize, int fresh,
2884 bool rb)
2885 {
2886 int i;
2887
2888 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2889 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2890
2891 if (hsize != ptr->hdisplay)
2892 continue;
2893 if (vsize != ptr->vdisplay)
2894 continue;
2895 if (fresh != drm_mode_vrefresh(ptr))
2896 continue;
2897 if (rb != mode_is_rb(ptr))
2898 continue;
2899
2900 return drm_mode_duplicate(dev, ptr);
2901 }
2902
2903 return NULL;
2904 }
2905 EXPORT_SYMBOL(drm_mode_find_dmt);
2906
is_display_descriptor(const struct detailed_timing * descriptor,u8 type)2907 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2908 {
2909 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2910 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2911 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2912
2913 return descriptor->pixel_clock == 0 &&
2914 descriptor->data.other_data.pad1 == 0 &&
2915 descriptor->data.other_data.type == type;
2916 }
2917
is_detailed_timing_descriptor(const struct detailed_timing * descriptor)2918 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2919 {
2920 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2921
2922 return descriptor->pixel_clock != 0;
2923 }
2924
2925 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2926
2927 static void
cea_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)2928 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2929 {
2930 int i, n;
2931 u8 d = ext[0x02];
2932 const u8 *det_base = ext + d;
2933
2934 if (d < 4 || d > 127)
2935 return;
2936
2937 n = (127 - d) / 18;
2938 for (i = 0; i < n; i++)
2939 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2940 }
2941
2942 static void
vtb_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)2943 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2944 {
2945 unsigned int i, n = min((int)ext[0x02], 6);
2946 const u8 *det_base = ext + 5;
2947
2948 if (ext[0x01] != 1)
2949 return; /* unknown version */
2950
2951 for (i = 0; i < n; i++)
2952 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2953 }
2954
drm_for_each_detailed_block(const struct drm_edid * drm_edid,detailed_cb * cb,void * closure)2955 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2956 detailed_cb *cb, void *closure)
2957 {
2958 struct drm_edid_iter edid_iter;
2959 const u8 *ext;
2960 int i;
2961
2962 if (!drm_edid)
2963 return;
2964
2965 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2966 cb(&drm_edid->edid->detailed_timings[i], closure);
2967
2968 drm_edid_iter_begin(drm_edid, &edid_iter);
2969 drm_edid_iter_for_each(ext, &edid_iter) {
2970 switch (*ext) {
2971 case CEA_EXT:
2972 cea_for_each_detailed_block(ext, cb, closure);
2973 break;
2974 case VTB_EXT:
2975 vtb_for_each_detailed_block(ext, cb, closure);
2976 break;
2977 default:
2978 break;
2979 }
2980 }
2981 drm_edid_iter_end(&edid_iter);
2982 }
2983
2984 static void
is_rb(const struct detailed_timing * descriptor,void * data)2985 is_rb(const struct detailed_timing *descriptor, void *data)
2986 {
2987 bool *res = data;
2988
2989 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2990 return;
2991
2992 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2993 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2994
2995 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2996 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2997 *res = true;
2998 }
2999
3000 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3001 static bool
drm_monitor_supports_rb(const struct drm_edid * drm_edid)3002 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3003 {
3004 if (drm_edid->edid->revision >= 4) {
3005 bool ret = false;
3006
3007 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3008 return ret;
3009 }
3010
3011 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3012 }
3013
3014 static void
find_gtf2(const struct detailed_timing * descriptor,void * data)3015 find_gtf2(const struct detailed_timing *descriptor, void *data)
3016 {
3017 const struct detailed_timing **res = data;
3018
3019 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3020 return;
3021
3022 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3023
3024 if (descriptor->data.other_data.data.range.flags == 0x02)
3025 *res = descriptor;
3026 }
3027
3028 /* Secondary GTF curve kicks in above some break frequency */
3029 static int
drm_gtf2_hbreak(const struct drm_edid * drm_edid)3030 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3031 {
3032 const struct detailed_timing *descriptor = NULL;
3033
3034 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3035
3036 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3037
3038 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3039 }
3040
3041 static int
drm_gtf2_2c(const struct drm_edid * drm_edid)3042 drm_gtf2_2c(const struct drm_edid *drm_edid)
3043 {
3044 const struct detailed_timing *descriptor = NULL;
3045
3046 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3047
3048 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3049
3050 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3051 }
3052
3053 static int
drm_gtf2_m(const struct drm_edid * drm_edid)3054 drm_gtf2_m(const struct drm_edid *drm_edid)
3055 {
3056 const struct detailed_timing *descriptor = NULL;
3057
3058 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3059
3060 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3061
3062 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3063 }
3064
3065 static int
drm_gtf2_k(const struct drm_edid * drm_edid)3066 drm_gtf2_k(const struct drm_edid *drm_edid)
3067 {
3068 const struct detailed_timing *descriptor = NULL;
3069
3070 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3071
3072 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3073
3074 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3075 }
3076
3077 static int
drm_gtf2_2j(const struct drm_edid * drm_edid)3078 drm_gtf2_2j(const struct drm_edid *drm_edid)
3079 {
3080 const struct detailed_timing *descriptor = NULL;
3081
3082 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3083
3084 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3085
3086 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3087 }
3088
3089 /* Get standard timing level (CVT/GTF/DMT). */
standard_timing_level(const struct drm_edid * drm_edid)3090 static int standard_timing_level(const struct drm_edid *drm_edid)
3091 {
3092 const struct edid *edid = drm_edid->edid;
3093
3094 if (edid->revision >= 2) {
3095 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
3096 return LEVEL_CVT;
3097 if (drm_gtf2_hbreak(drm_edid))
3098 return LEVEL_GTF2;
3099 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3100 return LEVEL_GTF;
3101 }
3102 return LEVEL_DMT;
3103 }
3104
3105 /*
3106 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3107 * monitors fill with ascii space (0x20) instead.
3108 */
3109 static int
bad_std_timing(u8 a,u8 b)3110 bad_std_timing(u8 a, u8 b)
3111 {
3112 return (a == 0x00 && b == 0x00) ||
3113 (a == 0x01 && b == 0x01) ||
3114 (a == 0x20 && b == 0x20);
3115 }
3116
drm_mode_hsync(const struct drm_display_mode * mode)3117 static int drm_mode_hsync(const struct drm_display_mode *mode)
3118 {
3119 if (mode->htotal <= 0)
3120 return 0;
3121
3122 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3123 }
3124
3125 /*
3126 * Take the standard timing params (in this case width, aspect, and refresh)
3127 * and convert them into a real mode using CVT/GTF/DMT.
3128 */
drm_mode_std(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct std_timing * t)3129 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3130 const struct drm_edid *drm_edid,
3131 const struct std_timing *t)
3132 {
3133 struct drm_device *dev = connector->dev;
3134 struct drm_display_mode *m, *mode = NULL;
3135 int hsize, vsize;
3136 int vrefresh_rate;
3137 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3138 >> EDID_TIMING_ASPECT_SHIFT;
3139 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3140 >> EDID_TIMING_VFREQ_SHIFT;
3141 int timing_level = standard_timing_level(drm_edid);
3142
3143 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3144 return NULL;
3145
3146 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3147 hsize = t->hsize * 8 + 248;
3148 /* vrefresh_rate = vfreq + 60 */
3149 vrefresh_rate = vfreq + 60;
3150 /* the vdisplay is calculated based on the aspect ratio */
3151 if (aspect_ratio == 0) {
3152 if (drm_edid->edid->revision < 3)
3153 vsize = hsize;
3154 else
3155 vsize = (hsize * 10) / 16;
3156 } else if (aspect_ratio == 1)
3157 vsize = (hsize * 3) / 4;
3158 else if (aspect_ratio == 2)
3159 vsize = (hsize * 4) / 5;
3160 else
3161 vsize = (hsize * 9) / 16;
3162
3163 /* HDTV hack, part 1 */
3164 if (vrefresh_rate == 60 &&
3165 ((hsize == 1360 && vsize == 765) ||
3166 (hsize == 1368 && vsize == 769))) {
3167 hsize = 1366;
3168 vsize = 768;
3169 }
3170
3171 /*
3172 * If this connector already has a mode for this size and refresh
3173 * rate (because it came from detailed or CVT info), use that
3174 * instead. This way we don't have to guess at interlace or
3175 * reduced blanking.
3176 */
3177 list_for_each_entry(m, &connector->probed_modes, head)
3178 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3179 drm_mode_vrefresh(m) == vrefresh_rate)
3180 return NULL;
3181
3182 /* HDTV hack, part 2 */
3183 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3184 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3185 false);
3186 if (!mode)
3187 return NULL;
3188 mode->hdisplay = 1366;
3189 mode->hsync_start = mode->hsync_start - 1;
3190 mode->hsync_end = mode->hsync_end - 1;
3191 return mode;
3192 }
3193
3194 /* check whether it can be found in default mode table */
3195 if (drm_monitor_supports_rb(drm_edid)) {
3196 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3197 true);
3198 if (mode)
3199 return mode;
3200 }
3201 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3202 if (mode)
3203 return mode;
3204
3205 /* okay, generate it */
3206 switch (timing_level) {
3207 case LEVEL_DMT:
3208 break;
3209 case LEVEL_GTF:
3210 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3211 break;
3212 case LEVEL_GTF2:
3213 /*
3214 * This is potentially wrong if there's ever a monitor with
3215 * more than one ranges section, each claiming a different
3216 * secondary GTF curve. Please don't do that.
3217 */
3218 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3219 if (!mode)
3220 return NULL;
3221 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3222 drm_mode_destroy(dev, mode);
3223 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3224 vrefresh_rate, 0, 0,
3225 drm_gtf2_m(drm_edid),
3226 drm_gtf2_2c(drm_edid),
3227 drm_gtf2_k(drm_edid),
3228 drm_gtf2_2j(drm_edid));
3229 }
3230 break;
3231 case LEVEL_CVT:
3232 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3233 false);
3234 break;
3235 }
3236 return mode;
3237 }
3238
3239 /*
3240 * EDID is delightfully ambiguous about how interlaced modes are to be
3241 * encoded. Our internal representation is of frame height, but some
3242 * HDTV detailed timings are encoded as field height.
3243 *
3244 * The format list here is from CEA, in frame size. Technically we
3245 * should be checking refresh rate too. Whatever.
3246 */
3247 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,const struct detailed_pixel_timing * pt)3248 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3249 const struct detailed_pixel_timing *pt)
3250 {
3251 int i;
3252 static const struct {
3253 int w, h;
3254 } cea_interlaced[] = {
3255 { 1920, 1080 },
3256 { 720, 480 },
3257 { 1440, 480 },
3258 { 2880, 480 },
3259 { 720, 576 },
3260 { 1440, 576 },
3261 { 2880, 576 },
3262 };
3263
3264 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3265 return;
3266
3267 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3268 if ((mode->hdisplay == cea_interlaced[i].w) &&
3269 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3270 mode->vdisplay *= 2;
3271 mode->vsync_start *= 2;
3272 mode->vsync_end *= 2;
3273 mode->vtotal *= 2;
3274 mode->vtotal |= 1;
3275 }
3276 }
3277
3278 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3279 }
3280
3281 /*
3282 * Create a new mode from an EDID detailed timing section. An EDID detailed
3283 * timing block contains enough info for us to create and return a new struct
3284 * drm_display_mode.
3285 */
drm_mode_detailed(struct drm_device * dev,const struct drm_edid * drm_edid,const struct detailed_timing * timing,u32 quirks)3286 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
3287 const struct drm_edid *drm_edid,
3288 const struct detailed_timing *timing,
3289 u32 quirks)
3290 {
3291 struct drm_display_mode *mode;
3292 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3293 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3294 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3295 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3296 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3297 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3298 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3299 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3300 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3301
3302 /* ignore tiny modes */
3303 if (hactive < 64 || vactive < 64)
3304 return NULL;
3305
3306 if (pt->misc & DRM_EDID_PT_STEREO) {
3307 DRM_DEBUG_KMS("stereo mode not supported\n");
3308 return NULL;
3309 }
3310 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3311 DRM_DEBUG_KMS("composite sync not supported\n");
3312 }
3313
3314 /* it is incorrect if hsync/vsync width is zero */
3315 if (!hsync_pulse_width || !vsync_pulse_width) {
3316 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3317 "Wrong Hsync/Vsync pulse width\n");
3318 return NULL;
3319 }
3320
3321 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3322 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3323 if (!mode)
3324 return NULL;
3325
3326 goto set_size;
3327 }
3328
3329 mode = drm_mode_create(dev);
3330 if (!mode)
3331 return NULL;
3332
3333 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3334 mode->clock = 1088 * 10;
3335 else
3336 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3337
3338 mode->hdisplay = hactive;
3339 mode->hsync_start = mode->hdisplay + hsync_offset;
3340 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3341 mode->htotal = mode->hdisplay + hblank;
3342
3343 mode->vdisplay = vactive;
3344 mode->vsync_start = mode->vdisplay + vsync_offset;
3345 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3346 mode->vtotal = mode->vdisplay + vblank;
3347
3348 /* Some EDIDs have bogus h/vtotal values */
3349 if (mode->hsync_end > mode->htotal)
3350 mode->htotal = mode->hsync_end + 1;
3351 if (mode->vsync_end > mode->vtotal)
3352 mode->vtotal = mode->vsync_end + 1;
3353
3354 drm_mode_do_interlace_quirk(mode, pt);
3355
3356 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3357 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3358 } else {
3359 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3360 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3361 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3362 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3363 }
3364
3365 set_size:
3366 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3367 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3368
3369 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3370 mode->width_mm *= 10;
3371 mode->height_mm *= 10;
3372 }
3373
3374 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3375 mode->width_mm = drm_edid->edid->width_cm * 10;
3376 mode->height_mm = drm_edid->edid->height_cm * 10;
3377 }
3378
3379 mode->type = DRM_MODE_TYPE_DRIVER;
3380 drm_mode_set_name(mode);
3381
3382 return mode;
3383 }
3384
3385 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3386 mode_in_hsync_range(const struct drm_display_mode *mode,
3387 const struct edid *edid, const u8 *t)
3388 {
3389 int hsync, hmin, hmax;
3390
3391 hmin = t[7];
3392 if (edid->revision >= 4)
3393 hmin += ((t[4] & 0x04) ? 255 : 0);
3394 hmax = t[8];
3395 if (edid->revision >= 4)
3396 hmax += ((t[4] & 0x08) ? 255 : 0);
3397 hsync = drm_mode_hsync(mode);
3398
3399 return (hsync <= hmax && hsync >= hmin);
3400 }
3401
3402 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3403 mode_in_vsync_range(const struct drm_display_mode *mode,
3404 const struct edid *edid, const u8 *t)
3405 {
3406 int vsync, vmin, vmax;
3407
3408 vmin = t[5];
3409 if (edid->revision >= 4)
3410 vmin += ((t[4] & 0x01) ? 255 : 0);
3411 vmax = t[6];
3412 if (edid->revision >= 4)
3413 vmax += ((t[4] & 0x02) ? 255 : 0);
3414 vsync = drm_mode_vrefresh(mode);
3415
3416 return (vsync <= vmax && vsync >= vmin);
3417 }
3418
3419 static u32
range_pixel_clock(const struct edid * edid,const u8 * t)3420 range_pixel_clock(const struct edid *edid, const u8 *t)
3421 {
3422 /* unspecified */
3423 if (t[9] == 0 || t[9] == 255)
3424 return 0;
3425
3426 /* 1.4 with CVT support gives us real precision, yay */
3427 if (edid->revision >= 4 && t[10] == 0x04)
3428 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3429
3430 /* 1.3 is pathetic, so fuzz up a bit */
3431 return t[9] * 10000 + 5001;
3432 }
3433
mode_in_range(const struct drm_display_mode * mode,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3434 static bool mode_in_range(const struct drm_display_mode *mode,
3435 const struct drm_edid *drm_edid,
3436 const struct detailed_timing *timing)
3437 {
3438 const struct edid *edid = drm_edid->edid;
3439 u32 max_clock;
3440 const u8 *t = (const u8 *)timing;
3441
3442 if (!mode_in_hsync_range(mode, edid, t))
3443 return false;
3444
3445 if (!mode_in_vsync_range(mode, edid, t))
3446 return false;
3447
3448 if ((max_clock = range_pixel_clock(edid, t)))
3449 if (mode->clock > max_clock)
3450 return false;
3451
3452 /* 1.4 max horizontal check */
3453 if (edid->revision >= 4 && t[10] == 0x04)
3454 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3455 return false;
3456
3457 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3458 return false;
3459
3460 return true;
3461 }
3462
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)3463 static bool valid_inferred_mode(const struct drm_connector *connector,
3464 const struct drm_display_mode *mode)
3465 {
3466 const struct drm_display_mode *m;
3467 bool ok = false;
3468
3469 list_for_each_entry(m, &connector->probed_modes, head) {
3470 if (mode->hdisplay == m->hdisplay &&
3471 mode->vdisplay == m->vdisplay &&
3472 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3473 return false; /* duplicated */
3474 if (mode->hdisplay <= m->hdisplay &&
3475 mode->vdisplay <= m->vdisplay)
3476 ok = true;
3477 }
3478 return ok;
3479 }
3480
drm_dmt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3481 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3482 const struct drm_edid *drm_edid,
3483 const struct detailed_timing *timing)
3484 {
3485 int i, modes = 0;
3486 struct drm_display_mode *newmode;
3487 struct drm_device *dev = connector->dev;
3488
3489 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3490 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3491 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3492 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3493 if (newmode) {
3494 drm_mode_probed_add(connector, newmode);
3495 modes++;
3496 }
3497 }
3498 }
3499
3500 return modes;
3501 }
3502
3503 /* fix up 1366x768 mode from 1368x768;
3504 * GFT/CVT can't express 1366 width which isn't dividable by 8
3505 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)3506 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3507 {
3508 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3509 mode->hdisplay = 1366;
3510 mode->hsync_start--;
3511 mode->hsync_end--;
3512 drm_mode_set_name(mode);
3513 }
3514 }
3515
drm_gtf_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3516 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3517 const struct drm_edid *drm_edid,
3518 const struct detailed_timing *timing)
3519 {
3520 int i, modes = 0;
3521 struct drm_display_mode *newmode;
3522 struct drm_device *dev = connector->dev;
3523
3524 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3525 const struct minimode *m = &extra_modes[i];
3526
3527 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3528 if (!newmode)
3529 return modes;
3530
3531 drm_mode_fixup_1366x768(newmode);
3532 if (!mode_in_range(newmode, drm_edid, timing) ||
3533 !valid_inferred_mode(connector, newmode)) {
3534 drm_mode_destroy(dev, newmode);
3535 continue;
3536 }
3537
3538 drm_mode_probed_add(connector, newmode);
3539 modes++;
3540 }
3541
3542 return modes;
3543 }
3544
drm_cvt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3545 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3546 const struct drm_edid *drm_edid,
3547 const struct detailed_timing *timing)
3548 {
3549 int i, modes = 0;
3550 struct drm_display_mode *newmode;
3551 struct drm_device *dev = connector->dev;
3552 bool rb = drm_monitor_supports_rb(drm_edid);
3553
3554 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3555 const struct minimode *m = &extra_modes[i];
3556
3557 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3558 if (!newmode)
3559 return modes;
3560
3561 drm_mode_fixup_1366x768(newmode);
3562 if (!mode_in_range(newmode, drm_edid, timing) ||
3563 !valid_inferred_mode(connector, newmode)) {
3564 drm_mode_destroy(dev, newmode);
3565 continue;
3566 }
3567
3568 drm_mode_probed_add(connector, newmode);
3569 modes++;
3570 }
3571
3572 return modes;
3573 }
3574
3575 static void
do_inferred_modes(const struct detailed_timing * timing,void * c)3576 do_inferred_modes(const struct detailed_timing *timing, void *c)
3577 {
3578 struct detailed_mode_closure *closure = c;
3579 const struct detailed_non_pixel *data = &timing->data.other_data;
3580 const struct detailed_data_monitor_range *range = &data->data.range;
3581
3582 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3583 return;
3584
3585 closure->modes += drm_dmt_modes_for_range(closure->connector,
3586 closure->drm_edid,
3587 timing);
3588
3589 if (!version_greater(closure->drm_edid, 1, 1))
3590 return; /* GTF not defined yet */
3591
3592 switch (range->flags) {
3593 case 0x02: /* secondary gtf, XXX could do more */
3594 case 0x00: /* default gtf */
3595 closure->modes += drm_gtf_modes_for_range(closure->connector,
3596 closure->drm_edid,
3597 timing);
3598 break;
3599 case 0x04: /* cvt, only in 1.4+ */
3600 if (!version_greater(closure->drm_edid, 1, 3))
3601 break;
3602
3603 closure->modes += drm_cvt_modes_for_range(closure->connector,
3604 closure->drm_edid,
3605 timing);
3606 break;
3607 case 0x01: /* just the ranges, no formula */
3608 default:
3609 break;
3610 }
3611 }
3612
add_inferred_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3613 static int add_inferred_modes(struct drm_connector *connector,
3614 const struct drm_edid *drm_edid)
3615 {
3616 struct detailed_mode_closure closure = {
3617 .connector = connector,
3618 .drm_edid = drm_edid,
3619 };
3620
3621 if (version_greater(drm_edid, 1, 0))
3622 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3623
3624 return closure.modes;
3625 }
3626
3627 static int
drm_est3_modes(struct drm_connector * connector,const struct detailed_timing * timing)3628 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3629 {
3630 int i, j, m, modes = 0;
3631 struct drm_display_mode *mode;
3632 const u8 *est = ((const u8 *)timing) + 6;
3633
3634 for (i = 0; i < 6; i++) {
3635 for (j = 7; j >= 0; j--) {
3636 m = (i * 8) + (7 - j);
3637 if (m >= ARRAY_SIZE(est3_modes))
3638 break;
3639 if (est[i] & (1 << j)) {
3640 mode = drm_mode_find_dmt(connector->dev,
3641 est3_modes[m].w,
3642 est3_modes[m].h,
3643 est3_modes[m].r,
3644 est3_modes[m].rb);
3645 if (mode) {
3646 drm_mode_probed_add(connector, mode);
3647 modes++;
3648 }
3649 }
3650 }
3651 }
3652
3653 return modes;
3654 }
3655
3656 static void
do_established_modes(const struct detailed_timing * timing,void * c)3657 do_established_modes(const struct detailed_timing *timing, void *c)
3658 {
3659 struct detailed_mode_closure *closure = c;
3660
3661 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3662 return;
3663
3664 closure->modes += drm_est3_modes(closure->connector, timing);
3665 }
3666
3667 /*
3668 * Get established modes from EDID and add them. Each EDID block contains a
3669 * bitmap of the supported "established modes" list (defined above). Tease them
3670 * out and add them to the global modes list.
3671 */
add_established_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3672 static int add_established_modes(struct drm_connector *connector,
3673 const struct drm_edid *drm_edid)
3674 {
3675 struct drm_device *dev = connector->dev;
3676 const struct edid *edid = drm_edid->edid;
3677 unsigned long est_bits = edid->established_timings.t1 |
3678 (edid->established_timings.t2 << 8) |
3679 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3680 int i, modes = 0;
3681 struct detailed_mode_closure closure = {
3682 .connector = connector,
3683 .drm_edid = drm_edid,
3684 };
3685
3686 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3687 if (est_bits & (1<<i)) {
3688 struct drm_display_mode *newmode;
3689
3690 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3691 if (newmode) {
3692 drm_mode_probed_add(connector, newmode);
3693 modes++;
3694 }
3695 }
3696 }
3697
3698 if (version_greater(drm_edid, 1, 0))
3699 drm_for_each_detailed_block(drm_edid, do_established_modes,
3700 &closure);
3701
3702 return modes + closure.modes;
3703 }
3704
3705 static void
do_standard_modes(const struct detailed_timing * timing,void * c)3706 do_standard_modes(const struct detailed_timing *timing, void *c)
3707 {
3708 struct detailed_mode_closure *closure = c;
3709 const struct detailed_non_pixel *data = &timing->data.other_data;
3710 struct drm_connector *connector = closure->connector;
3711 int i;
3712
3713 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3714 return;
3715
3716 for (i = 0; i < 6; i++) {
3717 const struct std_timing *std = &data->data.timings[i];
3718 struct drm_display_mode *newmode;
3719
3720 newmode = drm_mode_std(connector, closure->drm_edid, std);
3721 if (newmode) {
3722 drm_mode_probed_add(connector, newmode);
3723 closure->modes++;
3724 }
3725 }
3726 }
3727
3728 /*
3729 * Get standard modes from EDID and add them. Standard modes can be calculated
3730 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3731 * add them to the list.
3732 */
add_standard_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3733 static int add_standard_modes(struct drm_connector *connector,
3734 const struct drm_edid *drm_edid)
3735 {
3736 int i, modes = 0;
3737 struct detailed_mode_closure closure = {
3738 .connector = connector,
3739 .drm_edid = drm_edid,
3740 };
3741
3742 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3743 struct drm_display_mode *newmode;
3744
3745 newmode = drm_mode_std(connector, drm_edid,
3746 &drm_edid->edid->standard_timings[i]);
3747 if (newmode) {
3748 drm_mode_probed_add(connector, newmode);
3749 modes++;
3750 }
3751 }
3752
3753 if (version_greater(drm_edid, 1, 0))
3754 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3755 &closure);
3756
3757 /* XXX should also look for standard codes in VTB blocks */
3758
3759 return modes + closure.modes;
3760 }
3761
drm_cvt_modes(struct drm_connector * connector,const struct detailed_timing * timing)3762 static int drm_cvt_modes(struct drm_connector *connector,
3763 const struct detailed_timing *timing)
3764 {
3765 int i, j, modes = 0;
3766 struct drm_display_mode *newmode;
3767 struct drm_device *dev = connector->dev;
3768 const struct cvt_timing *cvt;
3769 const int rates[] = { 60, 85, 75, 60, 50 };
3770 const u8 empty[3] = { 0, 0, 0 };
3771
3772 for (i = 0; i < 4; i++) {
3773 int width, height;
3774
3775 cvt = &(timing->data.other_data.data.cvt[i]);
3776
3777 if (!memcmp(cvt->code, empty, 3))
3778 continue;
3779
3780 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3781 switch (cvt->code[1] & 0x0c) {
3782 /* default - because compiler doesn't see that we've enumerated all cases */
3783 default:
3784 case 0x00:
3785 width = height * 4 / 3;
3786 break;
3787 case 0x04:
3788 width = height * 16 / 9;
3789 break;
3790 case 0x08:
3791 width = height * 16 / 10;
3792 break;
3793 case 0x0c:
3794 width = height * 15 / 9;
3795 break;
3796 }
3797
3798 for (j = 1; j < 5; j++) {
3799 if (cvt->code[2] & (1 << j)) {
3800 newmode = drm_cvt_mode(dev, width, height,
3801 rates[j], j == 0,
3802 false, false);
3803 if (newmode) {
3804 drm_mode_probed_add(connector, newmode);
3805 modes++;
3806 }
3807 }
3808 }
3809 }
3810
3811 return modes;
3812 }
3813
3814 static void
do_cvt_mode(const struct detailed_timing * timing,void * c)3815 do_cvt_mode(const struct detailed_timing *timing, void *c)
3816 {
3817 struct detailed_mode_closure *closure = c;
3818
3819 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3820 return;
3821
3822 closure->modes += drm_cvt_modes(closure->connector, timing);
3823 }
3824
3825 static int
add_cvt_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3826 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3827 {
3828 struct detailed_mode_closure closure = {
3829 .connector = connector,
3830 .drm_edid = drm_edid,
3831 };
3832
3833 if (version_greater(drm_edid, 1, 2))
3834 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3835
3836 /* XXX should also look for CVT codes in VTB blocks */
3837
3838 return closure.modes;
3839 }
3840
3841 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3842
3843 static void
do_detailed_mode(const struct detailed_timing * timing,void * c)3844 do_detailed_mode(const struct detailed_timing *timing, void *c)
3845 {
3846 struct detailed_mode_closure *closure = c;
3847 struct drm_display_mode *newmode;
3848
3849 if (!is_detailed_timing_descriptor(timing))
3850 return;
3851
3852 newmode = drm_mode_detailed(closure->connector->dev,
3853 closure->drm_edid, timing,
3854 closure->quirks);
3855 if (!newmode)
3856 return;
3857
3858 if (closure->preferred)
3859 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3860
3861 /*
3862 * Detailed modes are limited to 10kHz pixel clock resolution,
3863 * so fix up anything that looks like CEA/HDMI mode, but the clock
3864 * is just slightly off.
3865 */
3866 fixup_detailed_cea_mode_clock(newmode);
3867
3868 drm_mode_probed_add(closure->connector, newmode);
3869 closure->modes++;
3870 closure->preferred = false;
3871 }
3872
3873 /*
3874 * add_detailed_modes - Add modes from detailed timings
3875 * @connector: attached connector
3876 * @drm_edid: EDID block to scan
3877 * @quirks: quirks to apply
3878 */
add_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid,u32 quirks)3879 static int add_detailed_modes(struct drm_connector *connector,
3880 const struct drm_edid *drm_edid, u32 quirks)
3881 {
3882 struct detailed_mode_closure closure = {
3883 .connector = connector,
3884 .drm_edid = drm_edid,
3885 .preferred = true,
3886 .quirks = quirks,
3887 };
3888
3889 if (closure.preferred && !version_greater(drm_edid, 1, 3))
3890 closure.preferred =
3891 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3892
3893 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
3894
3895 return closure.modes;
3896 }
3897
3898 /* CTA-861-H Table 60 - CTA Tag Codes */
3899 #define CTA_DB_AUDIO 1
3900 #define CTA_DB_VIDEO 2
3901 #define CTA_DB_VENDOR 3
3902 #define CTA_DB_SPEAKER 4
3903 #define CTA_DB_EXTENDED_TAG 7
3904
3905 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3906 #define CTA_EXT_DB_VIDEO_CAP 0
3907 #define CTA_EXT_DB_VENDOR 1
3908 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3909 #define CTA_EXT_DB_420_VIDEO_DATA 14
3910 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3911 #define CTA_EXT_DB_HF_EEODB 0x78
3912 #define CTA_EXT_DB_HF_SCDB 0x79
3913
3914 #define EDID_BASIC_AUDIO (1 << 6)
3915 #define EDID_CEA_YCRCB444 (1 << 5)
3916 #define EDID_CEA_YCRCB422 (1 << 4)
3917 #define EDID_CEA_VCDB_QS (1 << 6)
3918
3919 /*
3920 * Search EDID for CEA extension block.
3921 *
3922 * FIXME: Prefer not returning pointers to raw EDID data.
3923 */
drm_find_edid_extension(const struct drm_edid * drm_edid,int ext_id,int * ext_index)3924 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
3925 int ext_id, int *ext_index)
3926 {
3927 const u8 *edid_ext = NULL;
3928 int i;
3929
3930 /* No EDID or EDID extensions */
3931 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
3932 return NULL;
3933
3934 /* Find CEA extension */
3935 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3936 edid_ext = drm_edid_extension_block_data(drm_edid, i);
3937 if (edid_block_tag(edid_ext) == ext_id)
3938 break;
3939 }
3940
3941 if (i >= drm_edid_extension_block_count(drm_edid))
3942 return NULL;
3943
3944 *ext_index = i + 1;
3945
3946 return edid_ext;
3947 }
3948
3949 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
drm_edid_has_cta_extension(const struct drm_edid * drm_edid)3950 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
3951 {
3952 const struct displayid_block *block;
3953 struct displayid_iter iter;
3954 int ext_index = 0;
3955 bool found = false;
3956
3957 /* Look for a top level CEA extension block */
3958 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
3959 return true;
3960
3961 /* CEA blocks can also be found embedded in a DisplayID block */
3962 displayid_iter_edid_begin(drm_edid, &iter);
3963 displayid_iter_for_each(block, &iter) {
3964 if (block->tag == DATA_BLOCK_CTA) {
3965 found = true;
3966 break;
3967 }
3968 }
3969 displayid_iter_end(&iter);
3970
3971 return found;
3972 }
3973
cea_mode_for_vic(u8 vic)3974 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3975 {
3976 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3977 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3978
3979 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3980 return &edid_cea_modes_1[vic - 1];
3981 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3982 return &edid_cea_modes_193[vic - 193];
3983 return NULL;
3984 }
3985
cea_num_vics(void)3986 static u8 cea_num_vics(void)
3987 {
3988 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3989 }
3990
cea_next_vic(u8 vic)3991 static u8 cea_next_vic(u8 vic)
3992 {
3993 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3994 vic = 193;
3995 return vic;
3996 }
3997
3998 /*
3999 * Calculate the alternate clock for the CEA mode
4000 * (60Hz vs. 59.94Hz etc.)
4001 */
4002 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)4003 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4004 {
4005 unsigned int clock = cea_mode->clock;
4006
4007 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4008 return clock;
4009
4010 /*
4011 * edid_cea_modes contains the 59.94Hz
4012 * variant for 240 and 480 line modes,
4013 * and the 60Hz variant otherwise.
4014 */
4015 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4016 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4017 else
4018 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4019
4020 return clock;
4021 }
4022
4023 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)4024 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4025 {
4026 /*
4027 * For certain VICs the spec allows the vertical
4028 * front porch to vary by one or two lines.
4029 *
4030 * cea_modes[] stores the variant with the shortest
4031 * vertical front porch. We can adjust the mode to
4032 * get the other variants by simply increasing the
4033 * vertical front porch length.
4034 */
4035 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4036 cea_mode_for_vic(9)->vtotal != 262 ||
4037 cea_mode_for_vic(12)->vtotal != 262 ||
4038 cea_mode_for_vic(13)->vtotal != 262 ||
4039 cea_mode_for_vic(23)->vtotal != 312 ||
4040 cea_mode_for_vic(24)->vtotal != 312 ||
4041 cea_mode_for_vic(27)->vtotal != 312 ||
4042 cea_mode_for_vic(28)->vtotal != 312);
4043
4044 if (((vic == 8 || vic == 9 ||
4045 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4046 ((vic == 23 || vic == 24 ||
4047 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4048 mode->vsync_start++;
4049 mode->vsync_end++;
4050 mode->vtotal++;
4051
4052 return true;
4053 }
4054
4055 return false;
4056 }
4057
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4058 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4059 unsigned int clock_tolerance)
4060 {
4061 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4062 u8 vic;
4063
4064 if (!to_match->clock)
4065 return 0;
4066
4067 if (to_match->picture_aspect_ratio)
4068 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4069
4070 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4071 struct drm_display_mode cea_mode;
4072 unsigned int clock1, clock2;
4073
4074 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4075
4076 /* Check both 60Hz and 59.94Hz */
4077 clock1 = cea_mode.clock;
4078 clock2 = cea_mode_alternate_clock(&cea_mode);
4079
4080 if (abs(to_match->clock - clock1) > clock_tolerance &&
4081 abs(to_match->clock - clock2) > clock_tolerance)
4082 continue;
4083
4084 do {
4085 if (drm_mode_match(to_match, &cea_mode, match_flags))
4086 return vic;
4087 } while (cea_mode_alternate_timings(vic, &cea_mode));
4088 }
4089
4090 return 0;
4091 }
4092
4093 /**
4094 * drm_match_cea_mode - look for a CEA mode matching given mode
4095 * @to_match: display mode
4096 *
4097 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4098 * mode.
4099 */
drm_match_cea_mode(const struct drm_display_mode * to_match)4100 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4101 {
4102 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4103 u8 vic;
4104
4105 if (!to_match->clock)
4106 return 0;
4107
4108 if (to_match->picture_aspect_ratio)
4109 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4110
4111 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4112 struct drm_display_mode cea_mode;
4113 unsigned int clock1, clock2;
4114
4115 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4116
4117 /* Check both 60Hz and 59.94Hz */
4118 clock1 = cea_mode.clock;
4119 clock2 = cea_mode_alternate_clock(&cea_mode);
4120
4121 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4122 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4123 continue;
4124
4125 do {
4126 if (drm_mode_match(to_match, &cea_mode, match_flags))
4127 return vic;
4128 } while (cea_mode_alternate_timings(vic, &cea_mode));
4129 }
4130
4131 return 0;
4132 }
4133 EXPORT_SYMBOL(drm_match_cea_mode);
4134
drm_valid_cea_vic(u8 vic)4135 static bool drm_valid_cea_vic(u8 vic)
4136 {
4137 return cea_mode_for_vic(vic) != NULL;
4138 }
4139
drm_get_cea_aspect_ratio(const u8 video_code)4140 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4141 {
4142 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4143
4144 if (mode)
4145 return mode->picture_aspect_ratio;
4146
4147 return HDMI_PICTURE_ASPECT_NONE;
4148 }
4149
drm_get_hdmi_aspect_ratio(const u8 video_code)4150 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4151 {
4152 return edid_4k_modes[video_code].picture_aspect_ratio;
4153 }
4154
4155 /*
4156 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4157 * specific block).
4158 */
4159 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)4160 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4161 {
4162 return cea_mode_alternate_clock(hdmi_mode);
4163 }
4164
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4165 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4166 unsigned int clock_tolerance)
4167 {
4168 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4169 u8 vic;
4170
4171 if (!to_match->clock)
4172 return 0;
4173
4174 if (to_match->picture_aspect_ratio)
4175 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4176
4177 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4178 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4179 unsigned int clock1, clock2;
4180
4181 /* Make sure to also match alternate clocks */
4182 clock1 = hdmi_mode->clock;
4183 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4184
4185 if (abs(to_match->clock - clock1) > clock_tolerance &&
4186 abs(to_match->clock - clock2) > clock_tolerance)
4187 continue;
4188
4189 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4190 return vic;
4191 }
4192
4193 return 0;
4194 }
4195
4196 /*
4197 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4198 * @to_match: display mode
4199 *
4200 * An HDMI mode is one defined in the HDMI vendor specific block.
4201 *
4202 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4203 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)4204 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4205 {
4206 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4207 u8 vic;
4208
4209 if (!to_match->clock)
4210 return 0;
4211
4212 if (to_match->picture_aspect_ratio)
4213 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4214
4215 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4216 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4217 unsigned int clock1, clock2;
4218
4219 /* Make sure to also match alternate clocks */
4220 clock1 = hdmi_mode->clock;
4221 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4222
4223 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4224 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4225 drm_mode_match(to_match, hdmi_mode, match_flags))
4226 return vic;
4227 }
4228 return 0;
4229 }
4230
drm_valid_hdmi_vic(u8 vic)4231 static bool drm_valid_hdmi_vic(u8 vic)
4232 {
4233 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4234 }
4235
add_alternate_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4236 static int add_alternate_cea_modes(struct drm_connector *connector,
4237 const struct drm_edid *drm_edid)
4238 {
4239 struct drm_device *dev = connector->dev;
4240 struct drm_display_mode *mode, *tmp;
4241 LIST_HEAD(list);
4242 int modes = 0;
4243
4244 /* Don't add CTA modes if the CTA extension block is missing */
4245 if (!drm_edid_has_cta_extension(drm_edid))
4246 return 0;
4247
4248 /*
4249 * Go through all probed modes and create a new mode
4250 * with the alternate clock for certain CEA modes.
4251 */
4252 list_for_each_entry(mode, &connector->probed_modes, head) {
4253 const struct drm_display_mode *cea_mode = NULL;
4254 struct drm_display_mode *newmode;
4255 u8 vic = drm_match_cea_mode(mode);
4256 unsigned int clock1, clock2;
4257
4258 if (drm_valid_cea_vic(vic)) {
4259 cea_mode = cea_mode_for_vic(vic);
4260 clock2 = cea_mode_alternate_clock(cea_mode);
4261 } else {
4262 vic = drm_match_hdmi_mode(mode);
4263 if (drm_valid_hdmi_vic(vic)) {
4264 cea_mode = &edid_4k_modes[vic];
4265 clock2 = hdmi_mode_alternate_clock(cea_mode);
4266 }
4267 }
4268
4269 if (!cea_mode)
4270 continue;
4271
4272 clock1 = cea_mode->clock;
4273
4274 if (clock1 == clock2)
4275 continue;
4276
4277 if (mode->clock != clock1 && mode->clock != clock2)
4278 continue;
4279
4280 newmode = drm_mode_duplicate(dev, cea_mode);
4281 if (!newmode)
4282 continue;
4283
4284 /* Carry over the stereo flags */
4285 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4286
4287 /*
4288 * The current mode could be either variant. Make
4289 * sure to pick the "other" clock for the new mode.
4290 */
4291 if (mode->clock != clock1)
4292 newmode->clock = clock1;
4293 else
4294 newmode->clock = clock2;
4295
4296 list_add_tail(&newmode->head, &list);
4297 }
4298
4299 list_for_each_entry_safe(mode, tmp, &list, head) {
4300 list_del(&mode->head);
4301 drm_mode_probed_add(connector, mode);
4302 modes++;
4303 }
4304
4305 return modes;
4306 }
4307
svd_to_vic(u8 svd)4308 static u8 svd_to_vic(u8 svd)
4309 {
4310 /* 0-6 bit vic, 7th bit native mode indicator */
4311 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4312 return svd & 127;
4313
4314 return svd;
4315 }
4316
4317 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)4318 drm_display_mode_from_vic_index(struct drm_connector *connector,
4319 const u8 *video_db, u8 video_len,
4320 u8 video_index)
4321 {
4322 struct drm_device *dev = connector->dev;
4323 struct drm_display_mode *newmode;
4324 u8 vic;
4325
4326 if (video_db == NULL || video_index >= video_len)
4327 return NULL;
4328
4329 /* CEA modes are numbered 1..127 */
4330 vic = svd_to_vic(video_db[video_index]);
4331 if (!drm_valid_cea_vic(vic))
4332 return NULL;
4333
4334 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4335 if (!newmode)
4336 return NULL;
4337
4338 return newmode;
4339 }
4340
4341 /*
4342 * do_y420vdb_modes - Parse YCBCR 420 only modes
4343 * @connector: connector corresponding to the HDMI sink
4344 * @svds: start of the data block of CEA YCBCR 420 VDB
4345 * @len: length of the CEA YCBCR 420 VDB
4346 *
4347 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4348 * which contains modes which can be supported in YCBCR 420
4349 * output format only.
4350 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)4351 static int do_y420vdb_modes(struct drm_connector *connector,
4352 const u8 *svds, u8 svds_len)
4353 {
4354 int modes = 0, i;
4355 struct drm_device *dev = connector->dev;
4356 struct drm_display_info *info = &connector->display_info;
4357 struct drm_hdmi_info *hdmi = &info->hdmi;
4358
4359 for (i = 0; i < svds_len; i++) {
4360 u8 vic = svd_to_vic(svds[i]);
4361 struct drm_display_mode *newmode;
4362
4363 if (!drm_valid_cea_vic(vic))
4364 continue;
4365
4366 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4367 if (!newmode)
4368 break;
4369 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4370 drm_mode_probed_add(connector, newmode);
4371 modes++;
4372 }
4373
4374 if (modes > 0)
4375 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4376 return modes;
4377 }
4378
4379 /*
4380 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4381 * @connector: connector corresponding to the HDMI sink
4382 * @vic: CEA vic for the video mode to be added in the map
4383 *
4384 * Makes an entry for a videomode in the YCBCR 420 bitmap
4385 */
4386 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)4387 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4388 {
4389 u8 vic = svd_to_vic(svd);
4390 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4391
4392 if (!drm_valid_cea_vic(vic))
4393 return;
4394
4395 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4396 }
4397
4398 /**
4399 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4400 * @dev: DRM device
4401 * @video_code: CEA VIC of the mode
4402 *
4403 * Creates a new mode matching the specified CEA VIC.
4404 *
4405 * Returns: A new drm_display_mode on success or NULL on failure
4406 */
4407 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)4408 drm_display_mode_from_cea_vic(struct drm_device *dev,
4409 u8 video_code)
4410 {
4411 const struct drm_display_mode *cea_mode;
4412 struct drm_display_mode *newmode;
4413
4414 cea_mode = cea_mode_for_vic(video_code);
4415 if (!cea_mode)
4416 return NULL;
4417
4418 newmode = drm_mode_duplicate(dev, cea_mode);
4419 if (!newmode)
4420 return NULL;
4421
4422 return newmode;
4423 }
4424 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4425
4426 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)4427 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4428 {
4429 int i, modes = 0;
4430 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4431
4432 for (i = 0; i < len; i++) {
4433 struct drm_display_mode *mode;
4434
4435 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4436 if (mode) {
4437 /*
4438 * YCBCR420 capability block contains a bitmap which
4439 * gives the index of CEA modes from CEA VDB, which
4440 * can support YCBCR 420 sampling output also (apart
4441 * from RGB/YCBCR444 etc).
4442 * For example, if the bit 0 in bitmap is set,
4443 * first mode in VDB can support YCBCR420 output too.
4444 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4445 */
4446 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4447 drm_add_cmdb_modes(connector, db[i]);
4448
4449 drm_mode_probed_add(connector, mode);
4450 modes++;
4451 }
4452 }
4453
4454 return modes;
4455 }
4456
4457 struct stereo_mandatory_mode {
4458 int width, height, vrefresh;
4459 unsigned int flags;
4460 };
4461
4462 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4463 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4464 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4465 { 1920, 1080, 50,
4466 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4467 { 1920, 1080, 60,
4468 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4469 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4470 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4471 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4472 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4473 };
4474
4475 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)4476 stereo_match_mandatory(const struct drm_display_mode *mode,
4477 const struct stereo_mandatory_mode *stereo_mode)
4478 {
4479 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4480
4481 return mode->hdisplay == stereo_mode->width &&
4482 mode->vdisplay == stereo_mode->height &&
4483 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4484 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4485 }
4486
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)4487 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4488 {
4489 struct drm_device *dev = connector->dev;
4490 const struct drm_display_mode *mode;
4491 struct list_head stereo_modes;
4492 int modes = 0, i;
4493
4494 INIT_LIST_HEAD(&stereo_modes);
4495
4496 list_for_each_entry(mode, &connector->probed_modes, head) {
4497 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4498 const struct stereo_mandatory_mode *mandatory;
4499 struct drm_display_mode *new_mode;
4500
4501 if (!stereo_match_mandatory(mode,
4502 &stereo_mandatory_modes[i]))
4503 continue;
4504
4505 mandatory = &stereo_mandatory_modes[i];
4506 new_mode = drm_mode_duplicate(dev, mode);
4507 if (!new_mode)
4508 continue;
4509
4510 new_mode->flags |= mandatory->flags;
4511 list_add_tail(&new_mode->head, &stereo_modes);
4512 modes++;
4513 }
4514 }
4515
4516 list_splice_tail(&stereo_modes, &connector->probed_modes);
4517
4518 return modes;
4519 }
4520
add_hdmi_mode(struct drm_connector * connector,u8 vic)4521 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4522 {
4523 struct drm_device *dev = connector->dev;
4524 struct drm_display_mode *newmode;
4525
4526 if (!drm_valid_hdmi_vic(vic)) {
4527 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4528 return 0;
4529 }
4530
4531 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4532 if (!newmode)
4533 return 0;
4534
4535 drm_mode_probed_add(connector, newmode);
4536
4537 return 1;
4538 }
4539
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)4540 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4541 const u8 *video_db, u8 video_len, u8 video_index)
4542 {
4543 struct drm_display_mode *newmode;
4544 int modes = 0;
4545
4546 if (structure & (1 << 0)) {
4547 newmode = drm_display_mode_from_vic_index(connector, video_db,
4548 video_len,
4549 video_index);
4550 if (newmode) {
4551 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4552 drm_mode_probed_add(connector, newmode);
4553 modes++;
4554 }
4555 }
4556 if (structure & (1 << 6)) {
4557 newmode = drm_display_mode_from_vic_index(connector, video_db,
4558 video_len,
4559 video_index);
4560 if (newmode) {
4561 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4562 drm_mode_probed_add(connector, newmode);
4563 modes++;
4564 }
4565 }
4566 if (structure & (1 << 8)) {
4567 newmode = drm_display_mode_from_vic_index(connector, video_db,
4568 video_len,
4569 video_index);
4570 if (newmode) {
4571 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4572 drm_mode_probed_add(connector, newmode);
4573 modes++;
4574 }
4575 }
4576
4577 return modes;
4578 }
4579
4580 /*
4581 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4582 * @connector: connector corresponding to the HDMI sink
4583 * @db: start of the CEA vendor specific block
4584 * @len: length of the CEA block payload, ie. one can access up to db[len]
4585 *
4586 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4587 * also adds the stereo 3d modes when applicable.
4588 */
4589 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)4590 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4591 const u8 *video_db, u8 video_len)
4592 {
4593 struct drm_display_info *info = &connector->display_info;
4594 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4595 u8 vic_len, hdmi_3d_len = 0;
4596 u16 mask;
4597 u16 structure_all;
4598
4599 if (len < 8)
4600 goto out;
4601
4602 /* no HDMI_Video_Present */
4603 if (!(db[8] & (1 << 5)))
4604 goto out;
4605
4606 /* Latency_Fields_Present */
4607 if (db[8] & (1 << 7))
4608 offset += 2;
4609
4610 /* I_Latency_Fields_Present */
4611 if (db[8] & (1 << 6))
4612 offset += 2;
4613
4614 /* the declared length is not long enough for the 2 first bytes
4615 * of additional video format capabilities */
4616 if (len < (8 + offset + 2))
4617 goto out;
4618
4619 /* 3D_Present */
4620 offset++;
4621 if (db[8 + offset] & (1 << 7)) {
4622 modes += add_hdmi_mandatory_stereo_modes(connector);
4623
4624 /* 3D_Multi_present */
4625 multi_present = (db[8 + offset] & 0x60) >> 5;
4626 }
4627
4628 offset++;
4629 vic_len = db[8 + offset] >> 5;
4630 hdmi_3d_len = db[8 + offset] & 0x1f;
4631
4632 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4633 u8 vic;
4634
4635 vic = db[9 + offset + i];
4636 modes += add_hdmi_mode(connector, vic);
4637 }
4638 offset += 1 + vic_len;
4639
4640 if (multi_present == 1)
4641 multi_len = 2;
4642 else if (multi_present == 2)
4643 multi_len = 4;
4644 else
4645 multi_len = 0;
4646
4647 if (len < (8 + offset + hdmi_3d_len - 1))
4648 goto out;
4649
4650 if (hdmi_3d_len < multi_len)
4651 goto out;
4652
4653 if (multi_present == 1 || multi_present == 2) {
4654 /* 3D_Structure_ALL */
4655 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4656
4657 /* check if 3D_MASK is present */
4658 if (multi_present == 2)
4659 mask = (db[10 + offset] << 8) | db[11 + offset];
4660 else
4661 mask = 0xffff;
4662
4663 for (i = 0; i < 16; i++) {
4664 if (mask & (1 << i))
4665 modes += add_3d_struct_modes(connector,
4666 structure_all,
4667 video_db,
4668 video_len, i);
4669 }
4670 }
4671
4672 offset += multi_len;
4673
4674 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4675 int vic_index;
4676 struct drm_display_mode *newmode = NULL;
4677 unsigned int newflag = 0;
4678 bool detail_present;
4679
4680 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4681
4682 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4683 break;
4684
4685 /* 2D_VIC_order_X */
4686 vic_index = db[8 + offset + i] >> 4;
4687
4688 /* 3D_Structure_X */
4689 switch (db[8 + offset + i] & 0x0f) {
4690 case 0:
4691 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4692 break;
4693 case 6:
4694 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4695 break;
4696 case 8:
4697 /* 3D_Detail_X */
4698 if ((db[9 + offset + i] >> 4) == 1)
4699 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4700 break;
4701 }
4702
4703 if (newflag != 0) {
4704 newmode = drm_display_mode_from_vic_index(connector,
4705 video_db,
4706 video_len,
4707 vic_index);
4708
4709 if (newmode) {
4710 newmode->flags |= newflag;
4711 drm_mode_probed_add(connector, newmode);
4712 modes++;
4713 }
4714 }
4715
4716 if (detail_present)
4717 i++;
4718 }
4719
4720 out:
4721 if (modes > 0)
4722 info->has_hdmi_infoframe = true;
4723 return modes;
4724 }
4725
4726 static int
cea_revision(const u8 * cea)4727 cea_revision(const u8 *cea)
4728 {
4729 /*
4730 * FIXME is this correct for the DispID variant?
4731 * The DispID spec doesn't really specify whether
4732 * this is the revision of the CEA extension or
4733 * the DispID CEA data block. And the only value
4734 * given as an example is 0.
4735 */
4736 return cea[1];
4737 }
4738
4739 /*
4740 * CTA Data Block iterator.
4741 *
4742 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4743 * CTA Data Blocks.
4744 *
4745 * struct cea_db *db:
4746 * struct cea_db_iter iter;
4747 *
4748 * cea_db_iter_edid_begin(edid, &iter);
4749 * cea_db_iter_for_each(db, &iter) {
4750 * // do stuff with db
4751 * }
4752 * cea_db_iter_end(&iter);
4753 */
4754 struct cea_db_iter {
4755 struct drm_edid_iter edid_iter;
4756 struct displayid_iter displayid_iter;
4757
4758 /* Current Data Block Collection. */
4759 const u8 *collection;
4760
4761 /* Current Data Block index in current collection. */
4762 int index;
4763
4764 /* End index in current collection. */
4765 int end;
4766 };
4767
4768 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4769 struct cea_db {
4770 u8 tag_length;
4771 u8 data[];
4772 } __packed;
4773
cea_db_tag(const struct cea_db * db)4774 static int cea_db_tag(const struct cea_db *db)
4775 {
4776 return db->tag_length >> 5;
4777 }
4778
cea_db_payload_len(const void * _db)4779 static int cea_db_payload_len(const void *_db)
4780 {
4781 /* FIXME: Transition to passing struct cea_db * everywhere. */
4782 const struct cea_db *db = _db;
4783
4784 return db->tag_length & 0x1f;
4785 }
4786
cea_db_data(const struct cea_db * db)4787 static const void *cea_db_data(const struct cea_db *db)
4788 {
4789 return db->data;
4790 }
4791
cea_db_is_extended_tag(const struct cea_db * db,int tag)4792 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4793 {
4794 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4795 cea_db_payload_len(db) >= 1 &&
4796 db->data[0] == tag;
4797 }
4798
cea_db_is_vendor(const struct cea_db * db,int vendor_oui)4799 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4800 {
4801 const u8 *data = cea_db_data(db);
4802
4803 return cea_db_tag(db) == CTA_DB_VENDOR &&
4804 cea_db_payload_len(db) >= 3 &&
4805 oui(data[2], data[1], data[0]) == vendor_oui;
4806 }
4807
cea_db_iter_edid_begin(const struct drm_edid * drm_edid,struct cea_db_iter * iter)4808 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4809 struct cea_db_iter *iter)
4810 {
4811 memset(iter, 0, sizeof(*iter));
4812
4813 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4814 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4815 }
4816
4817 static const struct cea_db *
__cea_db_iter_current_block(const struct cea_db_iter * iter)4818 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4819 {
4820 const struct cea_db *db;
4821
4822 if (!iter->collection)
4823 return NULL;
4824
4825 db = (const struct cea_db *)&iter->collection[iter->index];
4826
4827 if (iter->index + sizeof(*db) <= iter->end &&
4828 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4829 return db;
4830
4831 return NULL;
4832 }
4833
4834 /*
4835 * References:
4836 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4837 */
cea_db_collection_size(const u8 * cta)4838 static int cea_db_collection_size(const u8 *cta)
4839 {
4840 u8 d = cta[2];
4841
4842 if (d < 4 || d > 127)
4843 return 0;
4844
4845 return d - 4;
4846 }
4847
4848 /*
4849 * References:
4850 * - VESA E-EDID v1.4
4851 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4852 */
__cea_db_iter_edid_next(struct cea_db_iter * iter)4853 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4854 {
4855 const u8 *ext;
4856
4857 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4858 int size;
4859
4860 /* Only support CTA Extension revision 3+ */
4861 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4862 continue;
4863
4864 size = cea_db_collection_size(ext);
4865 if (!size)
4866 continue;
4867
4868 iter->index = 4;
4869 iter->end = iter->index + size;
4870
4871 return ext;
4872 }
4873
4874 return NULL;
4875 }
4876
4877 /*
4878 * References:
4879 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4880 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4881 *
4882 * Note that the above do not specify any connection between DisplayID Data
4883 * Block revision and CTA Extension versions.
4884 */
__cea_db_iter_displayid_next(struct cea_db_iter * iter)4885 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4886 {
4887 const struct displayid_block *block;
4888
4889 displayid_iter_for_each(block, &iter->displayid_iter) {
4890 if (block->tag != DATA_BLOCK_CTA)
4891 continue;
4892
4893 /*
4894 * The displayid iterator has already verified the block bounds
4895 * in displayid_iter_block().
4896 */
4897 iter->index = sizeof(*block);
4898 iter->end = iter->index + block->num_bytes;
4899
4900 return block;
4901 }
4902
4903 return NULL;
4904 }
4905
__cea_db_iter_next(struct cea_db_iter * iter)4906 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4907 {
4908 const struct cea_db *db;
4909
4910 if (iter->collection) {
4911 /* Current collection should always be valid. */
4912 db = __cea_db_iter_current_block(iter);
4913 if (WARN_ON(!db)) {
4914 iter->collection = NULL;
4915 return NULL;
4916 }
4917
4918 /* Next block in CTA Data Block Collection */
4919 iter->index += sizeof(*db) + cea_db_payload_len(db);
4920
4921 db = __cea_db_iter_current_block(iter);
4922 if (db)
4923 return db;
4924 }
4925
4926 for (;;) {
4927 /*
4928 * Find the next CTA Data Block Collection. First iterate all
4929 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4930 *
4931 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4932 * Extension, it's recommended that DisplayID extensions are
4933 * exposed after all of the CTA Extensions.
4934 */
4935 iter->collection = __cea_db_iter_edid_next(iter);
4936 if (!iter->collection)
4937 iter->collection = __cea_db_iter_displayid_next(iter);
4938
4939 if (!iter->collection)
4940 return NULL;
4941
4942 db = __cea_db_iter_current_block(iter);
4943 if (db)
4944 return db;
4945 }
4946 }
4947
4948 #define cea_db_iter_for_each(__db, __iter) \
4949 while (((__db) = __cea_db_iter_next(__iter)))
4950
cea_db_iter_end(struct cea_db_iter * iter)4951 static void cea_db_iter_end(struct cea_db_iter *iter)
4952 {
4953 displayid_iter_end(&iter->displayid_iter);
4954 drm_edid_iter_end(&iter->edid_iter);
4955
4956 memset(iter, 0, sizeof(*iter));
4957 }
4958
cea_db_is_hdmi_vsdb(const struct cea_db * db)4959 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
4960 {
4961 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4962 cea_db_payload_len(db) >= 5;
4963 }
4964
cea_db_is_hdmi_forum_vsdb(const struct cea_db * db)4965 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
4966 {
4967 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4968 cea_db_payload_len(db) >= 7;
4969 }
4970
cea_db_is_hdmi_forum_eeodb(const void * db)4971 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
4972 {
4973 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
4974 cea_db_payload_len(db) >= 2;
4975 }
4976
cea_db_is_microsoft_vsdb(const struct cea_db * db)4977 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
4978 {
4979 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4980 cea_db_payload_len(db) == 21;
4981 }
4982
cea_db_is_vcdb(const struct cea_db * db)4983 static bool cea_db_is_vcdb(const struct cea_db *db)
4984 {
4985 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4986 cea_db_payload_len(db) == 2;
4987 }
4988
cea_db_is_hdmi_forum_scdb(const struct cea_db * db)4989 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
4990 {
4991 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4992 cea_db_payload_len(db) >= 7;
4993 }
4994
cea_db_is_y420cmdb(const struct cea_db * db)4995 static bool cea_db_is_y420cmdb(const struct cea_db *db)
4996 {
4997 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
4998 }
4999
cea_db_is_y420vdb(const struct cea_db * db)5000 static bool cea_db_is_y420vdb(const struct cea_db *db)
5001 {
5002 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5003 }
5004
cea_db_is_hdmi_hdr_metadata_block(const struct cea_db * db)5005 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5006 {
5007 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5008 cea_db_payload_len(db) >= 3;
5009 }
5010
5011 /*
5012 * Get the HF-EEODB override extension block count from EDID.
5013 *
5014 * The passed in EDID may be partially read, as long as it has at least two
5015 * blocks (base block and one extension block) if EDID extension count is > 0.
5016 *
5017 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5018 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5019 * iterators instead.
5020 *
5021 * References:
5022 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5023 */
edid_hfeeodb_extension_block_count(const struct edid * edid)5024 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5025 {
5026 const u8 *cta;
5027
5028 /* No extensions according to base block, no HF-EEODB. */
5029 if (!edid_extension_block_count(edid))
5030 return 0;
5031
5032 /* HF-EEODB is always in the first EDID extension block only */
5033 cta = edid_extension_block_data(edid, 0);
5034 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5035 return 0;
5036
5037 /* Need to have the data block collection, and at least 3 bytes. */
5038 if (cea_db_collection_size(cta) < 3)
5039 return 0;
5040
5041 /*
5042 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5043 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5044 * through 6 of Block 1 of the E-EDID.
5045 */
5046 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5047 return 0;
5048
5049 return cta[4 + 2];
5050 }
5051
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)5052 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5053 const u8 *db)
5054 {
5055 struct drm_display_info *info = &connector->display_info;
5056 struct drm_hdmi_info *hdmi = &info->hdmi;
5057 u8 map_len = cea_db_payload_len(db) - 1;
5058 u8 count;
5059 u64 map = 0;
5060
5061 if (map_len == 0) {
5062 /* All CEA modes support ycbcr420 sampling also.*/
5063 hdmi->y420_cmdb_map = U64_MAX;
5064 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5065 return;
5066 }
5067
5068 /*
5069 * This map indicates which of the existing CEA block modes
5070 * from VDB can support YCBCR420 output too. So if bit=0 is
5071 * set, first mode from VDB can support YCBCR420 output too.
5072 * We will parse and keep this map, before parsing VDB itself
5073 * to avoid going through the same block again and again.
5074 *
5075 * Spec is not clear about max possible size of this block.
5076 * Clamping max bitmap block size at 8 bytes. Every byte can
5077 * address 8 CEA modes, in this way this map can address
5078 * 8*8 = first 64 SVDs.
5079 */
5080 if (WARN_ON_ONCE(map_len > 8))
5081 map_len = 8;
5082
5083 for (count = 0; count < map_len; count++)
5084 map |= (u64)db[2 + count] << (8 * count);
5085
5086 if (map)
5087 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5088
5089 hdmi->y420_cmdb_map = map;
5090 }
5091
add_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)5092 static int add_cea_modes(struct drm_connector *connector,
5093 const struct drm_edid *drm_edid)
5094 {
5095 const struct cea_db *db;
5096 struct cea_db_iter iter;
5097 const u8 *hdmi = NULL, *video = NULL;
5098 u8 hdmi_len = 0, video_len = 0;
5099 int modes = 0;
5100
5101 cea_db_iter_edid_begin(drm_edid, &iter);
5102 cea_db_iter_for_each(db, &iter) {
5103 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5104 video = cea_db_data(db);
5105 video_len = cea_db_payload_len(db);
5106 modes += do_cea_modes(connector, video, video_len);
5107 } else if (cea_db_is_hdmi_vsdb(db)) {
5108 /* FIXME: Switch to use cea_db_data() */
5109 hdmi = (const u8 *)db;
5110 hdmi_len = cea_db_payload_len(db);
5111 } else if (cea_db_is_y420vdb(db)) {
5112 const u8 *vdb420 = cea_db_data(db) + 1;
5113
5114 /* Add 4:2:0(only) modes present in EDID */
5115 modes += do_y420vdb_modes(connector, vdb420,
5116 cea_db_payload_len(db) - 1);
5117 }
5118 }
5119 cea_db_iter_end(&iter);
5120
5121 /*
5122 * We parse the HDMI VSDB after having added the cea modes as we will be
5123 * patching their flags when the sink supports stereo 3D.
5124 */
5125 if (hdmi)
5126 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5127 video, video_len);
5128
5129 return modes;
5130 }
5131
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)5132 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5133 {
5134 const struct drm_display_mode *cea_mode;
5135 int clock1, clock2, clock;
5136 u8 vic;
5137 const char *type;
5138
5139 /*
5140 * allow 5kHz clock difference either way to account for
5141 * the 10kHz clock resolution limit of detailed timings.
5142 */
5143 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5144 if (drm_valid_cea_vic(vic)) {
5145 type = "CEA";
5146 cea_mode = cea_mode_for_vic(vic);
5147 clock1 = cea_mode->clock;
5148 clock2 = cea_mode_alternate_clock(cea_mode);
5149 } else {
5150 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5151 if (drm_valid_hdmi_vic(vic)) {
5152 type = "HDMI";
5153 cea_mode = &edid_4k_modes[vic];
5154 clock1 = cea_mode->clock;
5155 clock2 = hdmi_mode_alternate_clock(cea_mode);
5156 } else {
5157 return;
5158 }
5159 }
5160
5161 /* pick whichever is closest */
5162 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5163 clock = clock1;
5164 else
5165 clock = clock2;
5166
5167 if (mode->clock == clock)
5168 return;
5169
5170 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5171 type, vic, mode->clock, clock);
5172 mode->clock = clock;
5173 }
5174
drm_calculate_luminance_range(struct drm_connector * connector)5175 static void drm_calculate_luminance_range(struct drm_connector *connector)
5176 {
5177 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5178 struct drm_luminance_range_info *luminance_range =
5179 &connector->display_info.luminance_range;
5180 static const u8 pre_computed_values[] = {
5181 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5182 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5183 };
5184 u32 max_avg, min_cll, max, min, q, r;
5185
5186 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5187 return;
5188
5189 max_avg = hdr_metadata->max_fall;
5190 min_cll = hdr_metadata->min_cll;
5191
5192 /*
5193 * From the specification (CTA-861-G), for calculating the maximum
5194 * luminance we need to use:
5195 * Luminance = 50*2**(CV/32)
5196 * Where CV is a one-byte value.
5197 * For calculating this expression we may need float point precision;
5198 * to avoid this complexity level, we take advantage that CV is divided
5199 * by a constant. From the Euclids division algorithm, we know that CV
5200 * can be written as: CV = 32*q + r. Next, we replace CV in the
5201 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5202 * need to pre-compute the value of r/32. For pre-computing the values
5203 * We just used the following Ruby line:
5204 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5205 * The results of the above expressions can be verified at
5206 * pre_computed_values.
5207 */
5208 q = max_avg >> 5;
5209 r = max_avg % 32;
5210 max = (1 << q) * pre_computed_values[r];
5211
5212 /* min luminance: maxLum * (CV/255)^2 / 100 */
5213 q = DIV_ROUND_CLOSEST(min_cll, 255);
5214 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5215
5216 luminance_range->min_luminance = min;
5217 luminance_range->max_luminance = max;
5218 }
5219
eotf_supported(const u8 * edid_ext)5220 static uint8_t eotf_supported(const u8 *edid_ext)
5221 {
5222 return edid_ext[2] &
5223 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5224 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5225 BIT(HDMI_EOTF_SMPTE_ST2084) |
5226 BIT(HDMI_EOTF_BT_2100_HLG));
5227 }
5228
hdr_metadata_type(const u8 * edid_ext)5229 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5230 {
5231 return edid_ext[3] &
5232 BIT(HDMI_STATIC_METADATA_TYPE1);
5233 }
5234
5235 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)5236 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5237 {
5238 u16 len;
5239
5240 len = cea_db_payload_len(db);
5241
5242 connector->hdr_sink_metadata.hdmi_type1.eotf =
5243 eotf_supported(db);
5244 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5245 hdr_metadata_type(db);
5246
5247 if (len >= 4)
5248 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5249 if (len >= 5)
5250 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5251 if (len >= 6) {
5252 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5253
5254 /* Calculate only when all values are available */
5255 drm_calculate_luminance_range(connector);
5256 }
5257 }
5258
5259 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)5260 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5261 {
5262 u8 len = cea_db_payload_len(db);
5263
5264 if (len >= 6 && (db[6] & (1 << 7)))
5265 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5266 if (len >= 8) {
5267 connector->latency_present[0] = db[8] >> 7;
5268 connector->latency_present[1] = (db[8] >> 6) & 1;
5269 }
5270 if (len >= 9)
5271 connector->video_latency[0] = db[9];
5272 if (len >= 10)
5273 connector->audio_latency[0] = db[10];
5274 if (len >= 11)
5275 connector->video_latency[1] = db[11];
5276 if (len >= 12)
5277 connector->audio_latency[1] = db[12];
5278
5279 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5280 "video latency %d %d, "
5281 "audio latency %d %d\n",
5282 connector->latency_present[0],
5283 connector->latency_present[1],
5284 connector->video_latency[0],
5285 connector->video_latency[1],
5286 connector->audio_latency[0],
5287 connector->audio_latency[1]);
5288 }
5289
5290 static void
monitor_name(const struct detailed_timing * timing,void * data)5291 monitor_name(const struct detailed_timing *timing, void *data)
5292 {
5293 const char **res = data;
5294
5295 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5296 return;
5297
5298 *res = timing->data.other_data.data.str.str;
5299 }
5300
get_monitor_name(const struct drm_edid * drm_edid,char name[13])5301 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5302 {
5303 const char *edid_name = NULL;
5304 int mnl;
5305
5306 if (!drm_edid || !name)
5307 return 0;
5308
5309 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5310 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5311 if (edid_name[mnl] == 0x0a)
5312 break;
5313
5314 name[mnl] = edid_name[mnl];
5315 }
5316
5317 return mnl;
5318 }
5319
5320 /**
5321 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5322 * @edid: monitor EDID information
5323 * @name: pointer to a character array to hold the name of the monitor
5324 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5325 *
5326 */
drm_edid_get_monitor_name(const struct edid * edid,char * name,int bufsize)5327 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5328 {
5329 int name_length = 0;
5330
5331 if (bufsize <= 0)
5332 return;
5333
5334 if (edid) {
5335 char buf[13];
5336 struct drm_edid drm_edid = {
5337 .edid = edid,
5338 .size = edid_size(edid),
5339 };
5340
5341 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5342 memcpy(name, buf, name_length);
5343 }
5344
5345 name[name_length] = '\0';
5346 }
5347 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5348
clear_eld(struct drm_connector * connector)5349 static void clear_eld(struct drm_connector *connector)
5350 {
5351 memset(connector->eld, 0, sizeof(connector->eld));
5352
5353 connector->latency_present[0] = false;
5354 connector->latency_present[1] = false;
5355 connector->video_latency[0] = 0;
5356 connector->audio_latency[0] = 0;
5357 connector->video_latency[1] = 0;
5358 connector->audio_latency[1] = 0;
5359 }
5360
5361 /*
5362 * drm_edid_to_eld - build ELD from EDID
5363 * @connector: connector corresponding to the HDMI/DP sink
5364 * @drm_edid: EDID to parse
5365 *
5366 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5367 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5368 */
drm_edid_to_eld(struct drm_connector * connector,const struct drm_edid * drm_edid)5369 static void drm_edid_to_eld(struct drm_connector *connector,
5370 const struct drm_edid *drm_edid)
5371 {
5372 const struct drm_display_info *info = &connector->display_info;
5373 const struct cea_db *db;
5374 struct cea_db_iter iter;
5375 uint8_t *eld = connector->eld;
5376 int total_sad_count = 0;
5377 int mnl;
5378
5379 clear_eld(connector);
5380
5381 if (!drm_edid)
5382 return;
5383
5384 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5385 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
5386
5387 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5388 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5389
5390 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5391
5392 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5393 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5394 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5395 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5396
5397 cea_db_iter_edid_begin(drm_edid, &iter);
5398 cea_db_iter_for_each(db, &iter) {
5399 const u8 *data = cea_db_data(db);
5400 int len = cea_db_payload_len(db);
5401 int sad_count;
5402
5403 switch (cea_db_tag(db)) {
5404 case CTA_DB_AUDIO:
5405 /* Audio Data Block, contains SADs */
5406 sad_count = min(len / 3, 15 - total_sad_count);
5407 if (sad_count >= 1)
5408 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5409 data, sad_count * 3);
5410 total_sad_count += sad_count;
5411 break;
5412 case CTA_DB_SPEAKER:
5413 /* Speaker Allocation Data Block */
5414 if (len >= 1)
5415 eld[DRM_ELD_SPEAKER] = data[0];
5416 break;
5417 case CTA_DB_VENDOR:
5418 /* HDMI Vendor-Specific Data Block */
5419 if (cea_db_is_hdmi_vsdb(db))
5420 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5421 break;
5422 default:
5423 break;
5424 }
5425 }
5426 cea_db_iter_end(&iter);
5427
5428 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5429
5430 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5431 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5432 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5433 else
5434 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5435
5436 eld[DRM_ELD_BASELINE_ELD_LEN] =
5437 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5438
5439 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
5440 drm_eld_size(eld), total_sad_count);
5441 }
5442
_drm_edid_to_sad(const struct drm_edid * drm_edid,struct cea_sad ** sads)5443 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5444 struct cea_sad **sads)
5445 {
5446 const struct cea_db *db;
5447 struct cea_db_iter iter;
5448 int count = 0;
5449
5450 cea_db_iter_edid_begin(drm_edid, &iter);
5451 cea_db_iter_for_each(db, &iter) {
5452 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5453 int j;
5454
5455 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5456 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5457 if (!*sads)
5458 return -ENOMEM;
5459 for (j = 0; j < count; j++) {
5460 const u8 *sad = &db->data[j * 3];
5461
5462 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5463 (*sads)[j].channels = sad[0] & 0x7;
5464 (*sads)[j].freq = sad[1] & 0x7F;
5465 (*sads)[j].byte2 = sad[2];
5466 }
5467 break;
5468 }
5469 }
5470 cea_db_iter_end(&iter);
5471
5472 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5473
5474 return count;
5475 }
5476
5477 /**
5478 * drm_edid_to_sad - extracts SADs from EDID
5479 * @edid: EDID to parse
5480 * @sads: pointer that will be set to the extracted SADs
5481 *
5482 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5483 *
5484 * Note: The returned pointer needs to be freed using kfree().
5485 *
5486 * Return: The number of found SADs or negative number on error.
5487 */
drm_edid_to_sad(const struct edid * edid,struct cea_sad ** sads)5488 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5489 {
5490 struct drm_edid drm_edid;
5491
5492 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5493 }
5494 EXPORT_SYMBOL(drm_edid_to_sad);
5495
_drm_edid_to_speaker_allocation(const struct drm_edid * drm_edid,u8 ** sadb)5496 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5497 u8 **sadb)
5498 {
5499 const struct cea_db *db;
5500 struct cea_db_iter iter;
5501 int count = 0;
5502
5503 cea_db_iter_edid_begin(drm_edid, &iter);
5504 cea_db_iter_for_each(db, &iter) {
5505 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5506 cea_db_payload_len(db) == 3) {
5507 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5508 GFP_KERNEL);
5509 if (!*sadb)
5510 return -ENOMEM;
5511 count = cea_db_payload_len(db);
5512 break;
5513 }
5514 }
5515 cea_db_iter_end(&iter);
5516
5517 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5518
5519 return count;
5520 }
5521
5522 /**
5523 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5524 * @edid: EDID to parse
5525 * @sadb: pointer to the speaker block
5526 *
5527 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5528 *
5529 * Note: The returned pointer needs to be freed using kfree().
5530 *
5531 * Return: The number of found Speaker Allocation Blocks or negative number on
5532 * error.
5533 */
drm_edid_to_speaker_allocation(const struct edid * edid,u8 ** sadb)5534 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5535 {
5536 struct drm_edid drm_edid;
5537
5538 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5539 sadb);
5540 }
5541 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5542
5543 /**
5544 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5545 * @connector: connector associated with the HDMI/DP sink
5546 * @mode: the display mode
5547 *
5548 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5549 * the sink doesn't support audio or video.
5550 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)5551 int drm_av_sync_delay(struct drm_connector *connector,
5552 const struct drm_display_mode *mode)
5553 {
5554 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5555 int a, v;
5556
5557 if (!connector->latency_present[0])
5558 return 0;
5559 if (!connector->latency_present[1])
5560 i = 0;
5561
5562 a = connector->audio_latency[i];
5563 v = connector->video_latency[i];
5564
5565 /*
5566 * HDMI/DP sink doesn't support audio or video?
5567 */
5568 if (a == 255 || v == 255)
5569 return 0;
5570
5571 /*
5572 * Convert raw EDID values to millisecond.
5573 * Treat unknown latency as 0ms.
5574 */
5575 if (a)
5576 a = min(2 * (a - 1), 500);
5577 if (v)
5578 v = min(2 * (v - 1), 500);
5579
5580 return max(v - a, 0);
5581 }
5582 EXPORT_SYMBOL(drm_av_sync_delay);
5583
_drm_detect_hdmi_monitor(const struct drm_edid * drm_edid)5584 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5585 {
5586 const struct cea_db *db;
5587 struct cea_db_iter iter;
5588 bool hdmi = false;
5589
5590 /*
5591 * Because HDMI identifier is in Vendor Specific Block,
5592 * search it from all data blocks of CEA extension.
5593 */
5594 cea_db_iter_edid_begin(drm_edid, &iter);
5595 cea_db_iter_for_each(db, &iter) {
5596 if (cea_db_is_hdmi_vsdb(db)) {
5597 hdmi = true;
5598 break;
5599 }
5600 }
5601 cea_db_iter_end(&iter);
5602
5603 return hdmi;
5604 }
5605
5606 /**
5607 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5608 * @edid: monitor EDID information
5609 *
5610 * Parse the CEA extension according to CEA-861-B.
5611 *
5612 * Drivers that have added the modes parsed from EDID to drm_display_info
5613 * should use &drm_display_info.is_hdmi instead of calling this function.
5614 *
5615 * Return: True if the monitor is HDMI, false if not or unknown.
5616 */
drm_detect_hdmi_monitor(const struct edid * edid)5617 bool drm_detect_hdmi_monitor(const struct edid *edid)
5618 {
5619 struct drm_edid drm_edid;
5620
5621 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5622 }
5623 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5624
_drm_detect_monitor_audio(const struct drm_edid * drm_edid)5625 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5626 {
5627 struct drm_edid_iter edid_iter;
5628 const struct cea_db *db;
5629 struct cea_db_iter iter;
5630 const u8 *edid_ext;
5631 bool has_audio = false;
5632
5633 drm_edid_iter_begin(drm_edid, &edid_iter);
5634 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5635 if (edid_ext[0] == CEA_EXT) {
5636 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5637 if (has_audio)
5638 break;
5639 }
5640 }
5641 drm_edid_iter_end(&edid_iter);
5642
5643 if (has_audio) {
5644 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5645 goto end;
5646 }
5647
5648 cea_db_iter_edid_begin(drm_edid, &iter);
5649 cea_db_iter_for_each(db, &iter) {
5650 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5651 const u8 *data = cea_db_data(db);
5652 int i;
5653
5654 for (i = 0; i < cea_db_payload_len(db); i += 3)
5655 DRM_DEBUG_KMS("CEA audio format %d\n",
5656 (data[i] >> 3) & 0xf);
5657 has_audio = true;
5658 break;
5659 }
5660 }
5661 cea_db_iter_end(&iter);
5662
5663 end:
5664 return has_audio;
5665 }
5666
5667 /**
5668 * drm_detect_monitor_audio - check monitor audio capability
5669 * @edid: EDID block to scan
5670 *
5671 * Monitor should have CEA extension block.
5672 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5673 * audio' only. If there is any audio extension block and supported
5674 * audio format, assume at least 'basic audio' support, even if 'basic
5675 * audio' is not defined in EDID.
5676 *
5677 * Return: True if the monitor supports audio, false otherwise.
5678 */
drm_detect_monitor_audio(const struct edid * edid)5679 bool drm_detect_monitor_audio(const struct edid *edid)
5680 {
5681 struct drm_edid drm_edid;
5682
5683 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5684 }
5685 EXPORT_SYMBOL(drm_detect_monitor_audio);
5686
5687
5688 /**
5689 * drm_default_rgb_quant_range - default RGB quantization range
5690 * @mode: display mode
5691 *
5692 * Determine the default RGB quantization range for the mode,
5693 * as specified in CEA-861.
5694 *
5695 * Return: The default RGB quantization range for the mode
5696 */
5697 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)5698 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5699 {
5700 /* All CEA modes other than VIC 1 use limited quantization range. */
5701 return drm_match_cea_mode(mode) > 1 ?
5702 HDMI_QUANTIZATION_RANGE_LIMITED :
5703 HDMI_QUANTIZATION_RANGE_FULL;
5704 }
5705 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5706
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)5707 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5708 {
5709 struct drm_display_info *info = &connector->display_info;
5710
5711 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5712
5713 if (db[2] & EDID_CEA_VCDB_QS)
5714 info->rgb_quant_range_selectable = true;
5715 }
5716
5717 static
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)5718 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5719 {
5720 switch (max_frl_rate) {
5721 case 1:
5722 *max_lanes = 3;
5723 *max_rate_per_lane = 3;
5724 break;
5725 case 2:
5726 *max_lanes = 3;
5727 *max_rate_per_lane = 6;
5728 break;
5729 case 3:
5730 *max_lanes = 4;
5731 *max_rate_per_lane = 6;
5732 break;
5733 case 4:
5734 *max_lanes = 4;
5735 *max_rate_per_lane = 8;
5736 break;
5737 case 5:
5738 *max_lanes = 4;
5739 *max_rate_per_lane = 10;
5740 break;
5741 case 6:
5742 *max_lanes = 4;
5743 *max_rate_per_lane = 12;
5744 break;
5745 case 0:
5746 default:
5747 *max_lanes = 0;
5748 *max_rate_per_lane = 0;
5749 }
5750 }
5751
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)5752 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5753 const u8 *db)
5754 {
5755 u8 dc_mask;
5756 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5757
5758 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5759 hdmi->y420_dc_modes = dc_mask;
5760 }
5761
5762 /* Sink Capability Data Structure */
drm_parse_hdmi_forum_scds(struct drm_connector * connector,const u8 * hf_scds)5763 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5764 const u8 *hf_scds)
5765 {
5766 struct drm_display_info *display = &connector->display_info;
5767 struct drm_hdmi_info *hdmi = &display->hdmi;
5768
5769 display->has_hdmi_infoframe = true;
5770
5771 if (hf_scds[6] & 0x80) {
5772 hdmi->scdc.supported = true;
5773 if (hf_scds[6] & 0x40)
5774 hdmi->scdc.read_request = true;
5775 }
5776
5777 /*
5778 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5779 * And as per the spec, three factors confirm this:
5780 * * Availability of a HF-VSDB block in EDID (check)
5781 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5782 * * SCDC support available (let's check)
5783 * Lets check it out.
5784 */
5785
5786 if (hf_scds[5]) {
5787 /* max clock is 5000 KHz times block value */
5788 u32 max_tmds_clock = hf_scds[5] * 5000;
5789 struct drm_scdc *scdc = &hdmi->scdc;
5790
5791 if (max_tmds_clock > 340000) {
5792 display->max_tmds_clock = max_tmds_clock;
5793 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5794 display->max_tmds_clock);
5795 }
5796
5797 if (scdc->supported) {
5798 scdc->scrambling.supported = true;
5799
5800 /* Few sinks support scrambling for clocks < 340M */
5801 if ((hf_scds[6] & 0x8))
5802 scdc->scrambling.low_rates = true;
5803 }
5804 }
5805
5806 if (hf_scds[7]) {
5807 u8 max_frl_rate;
5808 u8 dsc_max_frl_rate;
5809 u8 dsc_max_slices;
5810 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5811
5812 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5813 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5814 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5815 &hdmi->max_frl_rate_per_lane);
5816 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5817
5818 if (hdmi_dsc->v_1p2) {
5819 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5820 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5821
5822 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5823 hdmi_dsc->bpc_supported = 16;
5824 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5825 hdmi_dsc->bpc_supported = 12;
5826 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5827 hdmi_dsc->bpc_supported = 10;
5828 else
5829 /* Supports min 8 BPC if DSC 1.2 is supported*/
5830 hdmi_dsc->bpc_supported = 8;
5831
5832 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5833 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5834 &hdmi_dsc->max_frl_rate_per_lane);
5835 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5836
5837 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5838 switch (dsc_max_slices) {
5839 case 1:
5840 hdmi_dsc->max_slices = 1;
5841 hdmi_dsc->clk_per_slice = 340;
5842 break;
5843 case 2:
5844 hdmi_dsc->max_slices = 2;
5845 hdmi_dsc->clk_per_slice = 340;
5846 break;
5847 case 3:
5848 hdmi_dsc->max_slices = 4;
5849 hdmi_dsc->clk_per_slice = 340;
5850 break;
5851 case 4:
5852 hdmi_dsc->max_slices = 8;
5853 hdmi_dsc->clk_per_slice = 340;
5854 break;
5855 case 5:
5856 hdmi_dsc->max_slices = 8;
5857 hdmi_dsc->clk_per_slice = 400;
5858 break;
5859 case 6:
5860 hdmi_dsc->max_slices = 12;
5861 hdmi_dsc->clk_per_slice = 400;
5862 break;
5863 case 7:
5864 hdmi_dsc->max_slices = 16;
5865 hdmi_dsc->clk_per_slice = 400;
5866 break;
5867 case 0:
5868 default:
5869 hdmi_dsc->max_slices = 0;
5870 hdmi_dsc->clk_per_slice = 0;
5871 }
5872 }
5873 }
5874
5875 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5876 }
5877
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)5878 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5879 const u8 *hdmi)
5880 {
5881 struct drm_display_info *info = &connector->display_info;
5882 unsigned int dc_bpc = 0;
5883
5884 /* HDMI supports at least 8 bpc */
5885 info->bpc = 8;
5886
5887 if (cea_db_payload_len(hdmi) < 6)
5888 return;
5889
5890 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5891 dc_bpc = 10;
5892 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5893 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5894 connector->name);
5895 }
5896
5897 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5898 dc_bpc = 12;
5899 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5900 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5901 connector->name);
5902 }
5903
5904 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5905 dc_bpc = 16;
5906 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5907 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5908 connector->name);
5909 }
5910
5911 if (dc_bpc == 0) {
5912 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5913 connector->name);
5914 return;
5915 }
5916
5917 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5918 connector->name, dc_bpc);
5919 info->bpc = dc_bpc;
5920
5921 /* YCRCB444 is optional according to spec. */
5922 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5923 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5924 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5925 connector->name);
5926 }
5927
5928 /*
5929 * Spec says that if any deep color mode is supported at all,
5930 * then deep color 36 bit must be supported.
5931 */
5932 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5933 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5934 connector->name);
5935 }
5936 }
5937
5938 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)5939 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5940 {
5941 struct drm_display_info *info = &connector->display_info;
5942 u8 len = cea_db_payload_len(db);
5943
5944 info->is_hdmi = true;
5945
5946 if (len >= 6)
5947 info->dvi_dual = db[6] & 1;
5948 if (len >= 7)
5949 info->max_tmds_clock = db[7] * 5000;
5950
5951 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5952 "max TMDS clock %d kHz\n",
5953 info->dvi_dual,
5954 info->max_tmds_clock);
5955
5956 drm_parse_hdmi_deep_color_info(connector, db);
5957 }
5958
5959 /*
5960 * See EDID extension for head-mounted and specialized monitors, specified at:
5961 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5962 */
drm_parse_microsoft_vsdb(struct drm_connector * connector,const u8 * db)5963 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5964 const u8 *db)
5965 {
5966 struct drm_display_info *info = &connector->display_info;
5967 u8 version = db[4];
5968 bool desktop_usage = db[5] & BIT(6);
5969
5970 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5971 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5972 info->non_desktop = true;
5973
5974 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5975 version, db[5]);
5976 }
5977
drm_parse_cea_ext(struct drm_connector * connector,const struct drm_edid * drm_edid)5978 static void drm_parse_cea_ext(struct drm_connector *connector,
5979 const struct drm_edid *drm_edid)
5980 {
5981 struct drm_display_info *info = &connector->display_info;
5982 struct drm_edid_iter edid_iter;
5983 const struct cea_db *db;
5984 struct cea_db_iter iter;
5985 const u8 *edid_ext;
5986
5987 drm_edid_iter_begin(drm_edid, &edid_iter);
5988 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5989 if (edid_ext[0] != CEA_EXT)
5990 continue;
5991
5992 if (!info->cea_rev)
5993 info->cea_rev = edid_ext[1];
5994
5995 if (info->cea_rev != edid_ext[1])
5996 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5997 info->cea_rev, edid_ext[1]);
5998
5999 /* The existence of a CTA extension should imply RGB support */
6000 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6001 if (edid_ext[3] & EDID_CEA_YCRCB444)
6002 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6003 if (edid_ext[3] & EDID_CEA_YCRCB422)
6004 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6005 }
6006 drm_edid_iter_end(&edid_iter);
6007
6008 cea_db_iter_edid_begin(drm_edid, &iter);
6009 cea_db_iter_for_each(db, &iter) {
6010 /* FIXME: convert parsers to use struct cea_db */
6011 const u8 *data = (const u8 *)db;
6012
6013 if (cea_db_is_hdmi_vsdb(db))
6014 drm_parse_hdmi_vsdb_video(connector, data);
6015 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6016 cea_db_is_hdmi_forum_scdb(db))
6017 drm_parse_hdmi_forum_scds(connector, data);
6018 else if (cea_db_is_microsoft_vsdb(db))
6019 drm_parse_microsoft_vsdb(connector, data);
6020 else if (cea_db_is_y420cmdb(db))
6021 drm_parse_y420cmdb_bitmap(connector, data);
6022 else if (cea_db_is_vcdb(db))
6023 drm_parse_vcdb(connector, data);
6024 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6025 drm_parse_hdr_metadata_block(connector, data);
6026 }
6027 cea_db_iter_end(&iter);
6028 }
6029
6030 static
get_monitor_range(const struct detailed_timing * timing,void * c)6031 void get_monitor_range(const struct detailed_timing *timing, void *c)
6032 {
6033 struct detailed_mode_closure *closure = c;
6034 struct drm_display_info *info = &closure->connector->display_info;
6035 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6036 const struct detailed_non_pixel *data = &timing->data.other_data;
6037 const struct detailed_data_monitor_range *range = &data->data.range;
6038 const struct edid *edid = closure->drm_edid->edid;
6039
6040 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6041 return;
6042
6043 /*
6044 * Check for flag range limits only. If flag == 1 then
6045 * no additional timing information provided.
6046 * Default GTF, GTF Secondary curve and CVT are not
6047 * supported
6048 */
6049 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6050 return;
6051
6052 monitor_range->min_vfreq = range->min_vfreq;
6053 monitor_range->max_vfreq = range->max_vfreq;
6054
6055 if (edid->revision >= 4) {
6056 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6057 monitor_range->min_vfreq += 255;
6058 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6059 monitor_range->max_vfreq += 255;
6060 }
6061 }
6062
drm_get_monitor_range(struct drm_connector * connector,const struct drm_edid * drm_edid)6063 static void drm_get_monitor_range(struct drm_connector *connector,
6064 const struct drm_edid *drm_edid)
6065 {
6066 const struct drm_display_info *info = &connector->display_info;
6067 struct detailed_mode_closure closure = {
6068 .connector = connector,
6069 .drm_edid = drm_edid,
6070 };
6071
6072 if (!version_greater(drm_edid, 1, 1))
6073 return;
6074
6075 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6076
6077 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6078 info->monitor_range.min_vfreq,
6079 info->monitor_range.max_vfreq);
6080 }
6081
drm_parse_vesa_mso_data(struct drm_connector * connector,const struct displayid_block * block)6082 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6083 const struct displayid_block *block)
6084 {
6085 struct displayid_vesa_vendor_specific_block *vesa =
6086 (struct displayid_vesa_vendor_specific_block *)block;
6087 struct drm_display_info *info = &connector->display_info;
6088
6089 if (block->num_bytes < 3) {
6090 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
6091 block->num_bytes);
6092 return;
6093 }
6094
6095 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6096 return;
6097
6098 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6099 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
6100 return;
6101 }
6102
6103 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6104 default:
6105 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
6106 fallthrough;
6107 case 0:
6108 info->mso_stream_count = 0;
6109 break;
6110 case 1:
6111 info->mso_stream_count = 2; /* 2 or 4 links */
6112 break;
6113 case 2:
6114 info->mso_stream_count = 4; /* 4 links */
6115 break;
6116 }
6117
6118 if (!info->mso_stream_count) {
6119 info->mso_pixel_overlap = 0;
6120 return;
6121 }
6122
6123 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6124 if (info->mso_pixel_overlap > 8) {
6125 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
6126 info->mso_pixel_overlap);
6127 info->mso_pixel_overlap = 8;
6128 }
6129
6130 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
6131 info->mso_stream_count, info->mso_pixel_overlap);
6132 }
6133
drm_update_mso(struct drm_connector * connector,const struct drm_edid * drm_edid)6134 static void drm_update_mso(struct drm_connector *connector,
6135 const struct drm_edid *drm_edid)
6136 {
6137 const struct displayid_block *block;
6138 struct displayid_iter iter;
6139
6140 displayid_iter_edid_begin(drm_edid, &iter);
6141 displayid_iter_for_each(block, &iter) {
6142 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6143 drm_parse_vesa_mso_data(connector, block);
6144 }
6145 displayid_iter_end(&iter);
6146 }
6147
6148 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6149 * all of the values which would have been set from EDID
6150 */
drm_reset_display_info(struct drm_connector * connector)6151 static void drm_reset_display_info(struct drm_connector *connector)
6152 {
6153 struct drm_display_info *info = &connector->display_info;
6154
6155 info->width_mm = 0;
6156 info->height_mm = 0;
6157
6158 info->bpc = 0;
6159 info->color_formats = 0;
6160 info->cea_rev = 0;
6161 info->max_tmds_clock = 0;
6162 info->dvi_dual = false;
6163 info->is_hdmi = false;
6164 info->has_hdmi_infoframe = false;
6165 info->rgb_quant_range_selectable = false;
6166 memset(&info->hdmi, 0, sizeof(info->hdmi));
6167
6168 info->edid_hdmi_rgb444_dc_modes = 0;
6169 info->edid_hdmi_ycbcr444_dc_modes = 0;
6170
6171 info->non_desktop = 0;
6172 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6173 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6174
6175 info->mso_stream_count = 0;
6176 info->mso_pixel_overlap = 0;
6177 info->max_dsc_bpp = 0;
6178 }
6179
update_display_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6180 static u32 update_display_info(struct drm_connector *connector,
6181 const struct drm_edid *drm_edid)
6182 {
6183 struct drm_display_info *info = &connector->display_info;
6184 const struct edid *edid = drm_edid->edid;
6185
6186 u32 quirks = edid_get_quirks(drm_edid);
6187
6188 drm_reset_display_info(connector);
6189
6190 info->width_mm = edid->width_cm * 10;
6191 info->height_mm = edid->height_cm * 10;
6192
6193 drm_get_monitor_range(connector, drm_edid);
6194
6195 if (edid->revision < 3)
6196 goto out;
6197
6198 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6199 goto out;
6200
6201 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6202 drm_parse_cea_ext(connector, drm_edid);
6203
6204 /*
6205 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6206 *
6207 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6208 * tells us to assume 8 bpc color depth if the EDID doesn't have
6209 * extensions which tell otherwise.
6210 */
6211 if (info->bpc == 0 && edid->revision == 3 &&
6212 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6213 info->bpc = 8;
6214 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6215 connector->name, info->bpc);
6216 }
6217
6218 /* Only defined for 1.4 with digital displays */
6219 if (edid->revision < 4)
6220 goto out;
6221
6222 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6223 case DRM_EDID_DIGITAL_DEPTH_6:
6224 info->bpc = 6;
6225 break;
6226 case DRM_EDID_DIGITAL_DEPTH_8:
6227 info->bpc = 8;
6228 break;
6229 case DRM_EDID_DIGITAL_DEPTH_10:
6230 info->bpc = 10;
6231 break;
6232 case DRM_EDID_DIGITAL_DEPTH_12:
6233 info->bpc = 12;
6234 break;
6235 case DRM_EDID_DIGITAL_DEPTH_14:
6236 info->bpc = 14;
6237 break;
6238 case DRM_EDID_DIGITAL_DEPTH_16:
6239 info->bpc = 16;
6240 break;
6241 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6242 default:
6243 info->bpc = 0;
6244 break;
6245 }
6246
6247 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6248 connector->name, info->bpc);
6249
6250 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6251 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6252 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6253 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6254
6255 drm_update_mso(connector, drm_edid);
6256
6257 out:
6258 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6259 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6260 info->non_desktop ? " (redundant quirk)" : "");
6261 info->non_desktop = true;
6262 }
6263
6264 if (quirks & EDID_QUIRK_CAP_DSC_15BPP)
6265 info->max_dsc_bpp = 15;
6266
6267 return quirks;
6268 }
6269
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings,bool type_7)6270 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6271 struct displayid_detailed_timings_1 *timings,
6272 bool type_7)
6273 {
6274 struct drm_display_mode *mode;
6275 unsigned pixel_clock = (timings->pixel_clock[0] |
6276 (timings->pixel_clock[1] << 8) |
6277 (timings->pixel_clock[2] << 16)) + 1;
6278 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6279 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6280 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6281 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6282 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6283 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6284 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6285 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6286 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6287 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6288
6289 mode = drm_mode_create(dev);
6290 if (!mode)
6291 return NULL;
6292
6293 /* resolution is kHz for type VII, and 10 kHz for type I */
6294 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6295 mode->hdisplay = hactive;
6296 mode->hsync_start = mode->hdisplay + hsync;
6297 mode->hsync_end = mode->hsync_start + hsync_width;
6298 mode->htotal = mode->hdisplay + hblank;
6299
6300 mode->vdisplay = vactive;
6301 mode->vsync_start = mode->vdisplay + vsync;
6302 mode->vsync_end = mode->vsync_start + vsync_width;
6303 mode->vtotal = mode->vdisplay + vblank;
6304
6305 mode->flags = 0;
6306 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6307 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6308 mode->type = DRM_MODE_TYPE_DRIVER;
6309
6310 if (timings->flags & 0x80)
6311 mode->type |= DRM_MODE_TYPE_PREFERRED;
6312 drm_mode_set_name(mode);
6313
6314 return mode;
6315 }
6316
add_displayid_detailed_1_modes(struct drm_connector * connector,const struct displayid_block * block)6317 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6318 const struct displayid_block *block)
6319 {
6320 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6321 int i;
6322 int num_timings;
6323 struct drm_display_mode *newmode;
6324 int num_modes = 0;
6325 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6326 /* blocks must be multiple of 20 bytes length */
6327 if (block->num_bytes % 20)
6328 return 0;
6329
6330 num_timings = block->num_bytes / 20;
6331 for (i = 0; i < num_timings; i++) {
6332 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6333
6334 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6335 if (!newmode)
6336 continue;
6337
6338 drm_mode_probed_add(connector, newmode);
6339 num_modes++;
6340 }
6341 return num_modes;
6342 }
6343
add_displayid_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6344 static int add_displayid_detailed_modes(struct drm_connector *connector,
6345 const struct drm_edid *drm_edid)
6346 {
6347 const struct displayid_block *block;
6348 struct displayid_iter iter;
6349 int num_modes = 0;
6350
6351 displayid_iter_edid_begin(drm_edid, &iter);
6352 displayid_iter_for_each(block, &iter) {
6353 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6354 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6355 num_modes += add_displayid_detailed_1_modes(connector, block);
6356 }
6357 displayid_iter_end(&iter);
6358
6359 return num_modes;
6360 }
6361
_drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6362 static int _drm_edid_connector_update(struct drm_connector *connector,
6363 const struct drm_edid *drm_edid)
6364 {
6365 int num_modes = 0;
6366 u32 quirks;
6367
6368 if (!drm_edid) {
6369 drm_reset_display_info(connector);
6370 clear_eld(connector);
6371 return 0;
6372 }
6373
6374 /*
6375 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6376 * To avoid multiple parsing of same block, lets parse that map
6377 * from sink info, before parsing CEA modes.
6378 */
6379 quirks = update_display_info(connector, drm_edid);
6380
6381 /* Depends on info->cea_rev set by update_display_info() above */
6382 drm_edid_to_eld(connector, drm_edid);
6383
6384 /*
6385 * EDID spec says modes should be preferred in this order:
6386 * - preferred detailed mode
6387 * - other detailed modes from base block
6388 * - detailed modes from extension blocks
6389 * - CVT 3-byte code modes
6390 * - standard timing codes
6391 * - established timing codes
6392 * - modes inferred from GTF or CVT range information
6393 *
6394 * We get this pretty much right.
6395 *
6396 * XXX order for additional mode types in extension blocks?
6397 */
6398 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6399 num_modes += add_cvt_modes(connector, drm_edid);
6400 num_modes += add_standard_modes(connector, drm_edid);
6401 num_modes += add_established_modes(connector, drm_edid);
6402 num_modes += add_cea_modes(connector, drm_edid);
6403 num_modes += add_alternate_cea_modes(connector, drm_edid);
6404 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6405 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
6406 num_modes += add_inferred_modes(connector, drm_edid);
6407
6408 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6409 edid_fixup_preferred(connector, quirks);
6410
6411 if (quirks & EDID_QUIRK_FORCE_6BPC)
6412 connector->display_info.bpc = 6;
6413
6414 if (quirks & EDID_QUIRK_FORCE_8BPC)
6415 connector->display_info.bpc = 8;
6416
6417 if (quirks & EDID_QUIRK_FORCE_10BPC)
6418 connector->display_info.bpc = 10;
6419
6420 if (quirks & EDID_QUIRK_FORCE_12BPC)
6421 connector->display_info.bpc = 12;
6422
6423 return num_modes;
6424 }
6425
6426 static void _drm_update_tile_info(struct drm_connector *connector,
6427 const struct drm_edid *drm_edid);
6428
_drm_edid_connector_property_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6429 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6430 const struct drm_edid *drm_edid)
6431 {
6432 struct drm_device *dev = connector->dev;
6433 int ret;
6434
6435 if (connector->edid_blob_ptr) {
6436 const struct edid *old_edid = connector->edid_blob_ptr->data;
6437
6438 if (old_edid) {
6439 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6440 connector->epoch_counter++;
6441 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6442 connector->base.id, connector->name,
6443 connector->epoch_counter);
6444 }
6445 }
6446 }
6447
6448 ret = drm_property_replace_global_blob(dev,
6449 &connector->edid_blob_ptr,
6450 drm_edid ? drm_edid->size : 0,
6451 drm_edid ? drm_edid->edid : NULL,
6452 &connector->base,
6453 dev->mode_config.edid_property);
6454 if (ret) {
6455 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6456 connector->base.id, connector->name, ret);
6457 goto out;
6458 }
6459
6460 ret = drm_object_property_set_value(&connector->base,
6461 dev->mode_config.non_desktop_property,
6462 connector->display_info.non_desktop);
6463 if (ret) {
6464 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6465 connector->base.id, connector->name, ret);
6466 goto out;
6467 }
6468
6469 ret = drm_connector_set_tile_property(connector);
6470 if (ret) {
6471 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6472 connector->base.id, connector->name, ret);
6473 goto out;
6474 }
6475
6476 out:
6477 return ret;
6478 }
6479
6480 /**
6481 * drm_edid_connector_update - Update connector information from EDID
6482 * @connector: Connector
6483 * @drm_edid: EDID
6484 *
6485 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6486 * properties, etc. from the passed in EDID.
6487 *
6488 * If EDID is NULL, reset the information.
6489 *
6490 * Return: The number of modes added or 0 if we couldn't find any.
6491 */
drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6492 int drm_edid_connector_update(struct drm_connector *connector,
6493 const struct drm_edid *drm_edid)
6494 {
6495 int count;
6496
6497 /*
6498 * FIXME: Reconcile the differences in override_edid handling between
6499 * this and drm_connector_update_edid_property().
6500 *
6501 * If override_edid is set, and the EDID passed in here originates from
6502 * drm_edid_read() and friends, it will be the override EDID, and there
6503 * are no issues. drm_connector_update_edid_property() ignoring requests
6504 * to set the EDID dates back to a time when override EDID was not
6505 * handled at the low level EDID read.
6506 *
6507 * The only way the EDID passed in here can be different from the
6508 * override EDID is when a driver passes in an EDID that does *not*
6509 * originate from drm_edid_read() and friends, or passes in a stale
6510 * cached version. This, in turn, is a question of when an override EDID
6511 * set via debugfs should take effect.
6512 */
6513
6514 count = _drm_edid_connector_update(connector, drm_edid);
6515
6516 _drm_update_tile_info(connector, drm_edid);
6517
6518 /* Note: Ignore errors for now. */
6519 _drm_edid_connector_property_update(connector, drm_edid);
6520
6521 return count;
6522 }
6523 EXPORT_SYMBOL(drm_edid_connector_update);
6524
_drm_connector_update_edid_property(struct drm_connector * connector,const struct drm_edid * drm_edid)6525 static int _drm_connector_update_edid_property(struct drm_connector *connector,
6526 const struct drm_edid *drm_edid)
6527 {
6528 /* ignore requests to set edid when overridden */
6529 if (connector->override_edid)
6530 return 0;
6531
6532 /*
6533 * Set the display info, using edid if available, otherwise resetting
6534 * the values to defaults. This duplicates the work done in
6535 * drm_add_edid_modes, but that function is not consistently called
6536 * before this one in all drivers and the computation is cheap enough
6537 * that it seems better to duplicate it rather than attempt to ensure
6538 * some arbitrary ordering of calls.
6539 */
6540 if (drm_edid)
6541 update_display_info(connector, drm_edid);
6542 else
6543 drm_reset_display_info(connector);
6544
6545 _drm_update_tile_info(connector, drm_edid);
6546
6547 return _drm_edid_connector_property_update(connector, drm_edid);
6548 }
6549
6550 /**
6551 * drm_connector_update_edid_property - update the edid property of a connector
6552 * @connector: drm connector
6553 * @edid: new value of the edid property
6554 *
6555 * This function creates a new blob modeset object and assigns its id to the
6556 * connector's edid property.
6557 * Since we also parse tile information from EDID's displayID block, we also
6558 * set the connector's tile property here. See drm_connector_set_tile_property()
6559 * for more details.
6560 *
6561 * This function is deprecated. Use drm_edid_connector_update() instead.
6562 *
6563 * Returns:
6564 * Zero on success, negative errno on failure.
6565 */
drm_connector_update_edid_property(struct drm_connector * connector,const struct edid * edid)6566 int drm_connector_update_edid_property(struct drm_connector *connector,
6567 const struct edid *edid)
6568 {
6569 struct drm_edid drm_edid;
6570
6571 return _drm_connector_update_edid_property(connector,
6572 drm_edid_legacy_init(&drm_edid, edid));
6573 }
6574 EXPORT_SYMBOL(drm_connector_update_edid_property);
6575
6576 /**
6577 * drm_add_edid_modes - add modes from EDID data, if available
6578 * @connector: connector we're probing
6579 * @edid: EDID data
6580 *
6581 * Add the specified modes to the connector's mode list. Also fills out the
6582 * &drm_display_info structure and ELD in @connector with any information which
6583 * can be derived from the edid.
6584 *
6585 * This function is deprecated. Use drm_edid_connector_update() instead.
6586 *
6587 * Return: The number of modes added or 0 if we couldn't find any.
6588 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)6589 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6590 {
6591 struct drm_edid drm_edid;
6592
6593 if (edid && !drm_edid_is_valid(edid)) {
6594 drm_warn(connector->dev, "%s: EDID invalid.\n",
6595 connector->name);
6596 edid = NULL;
6597 }
6598
6599 return _drm_edid_connector_update(connector,
6600 drm_edid_legacy_init(&drm_edid, edid));
6601 }
6602 EXPORT_SYMBOL(drm_add_edid_modes);
6603
6604 /**
6605 * drm_add_modes_noedid - add modes for the connectors without EDID
6606 * @connector: connector we're probing
6607 * @hdisplay: the horizontal display limit
6608 * @vdisplay: the vertical display limit
6609 *
6610 * Add the specified modes to the connector's mode list. Only when the
6611 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6612 *
6613 * Return: The number of modes added or 0 if we couldn't find any.
6614 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)6615 int drm_add_modes_noedid(struct drm_connector *connector,
6616 int hdisplay, int vdisplay)
6617 {
6618 int i, count, num_modes = 0;
6619 struct drm_display_mode *mode;
6620 struct drm_device *dev = connector->dev;
6621
6622 count = ARRAY_SIZE(drm_dmt_modes);
6623 if (hdisplay < 0)
6624 hdisplay = 0;
6625 if (vdisplay < 0)
6626 vdisplay = 0;
6627
6628 for (i = 0; i < count; i++) {
6629 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6630
6631 if (hdisplay && vdisplay) {
6632 /*
6633 * Only when two are valid, they will be used to check
6634 * whether the mode should be added to the mode list of
6635 * the connector.
6636 */
6637 if (ptr->hdisplay > hdisplay ||
6638 ptr->vdisplay > vdisplay)
6639 continue;
6640 }
6641 if (drm_mode_vrefresh(ptr) > 61)
6642 continue;
6643 mode = drm_mode_duplicate(dev, ptr);
6644 if (mode) {
6645 drm_mode_probed_add(connector, mode);
6646 num_modes++;
6647 }
6648 }
6649 return num_modes;
6650 }
6651 EXPORT_SYMBOL(drm_add_modes_noedid);
6652
6653 /**
6654 * drm_set_preferred_mode - Sets the preferred mode of a connector
6655 * @connector: connector whose mode list should be processed
6656 * @hpref: horizontal resolution of preferred mode
6657 * @vpref: vertical resolution of preferred mode
6658 *
6659 * Marks a mode as preferred if it matches the resolution specified by @hpref
6660 * and @vpref.
6661 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)6662 void drm_set_preferred_mode(struct drm_connector *connector,
6663 int hpref, int vpref)
6664 {
6665 struct drm_display_mode *mode;
6666
6667 list_for_each_entry(mode, &connector->probed_modes, head) {
6668 if (mode->hdisplay == hpref &&
6669 mode->vdisplay == vpref)
6670 mode->type |= DRM_MODE_TYPE_PREFERRED;
6671 }
6672 }
6673 EXPORT_SYMBOL(drm_set_preferred_mode);
6674
is_hdmi2_sink(const struct drm_connector * connector)6675 static bool is_hdmi2_sink(const struct drm_connector *connector)
6676 {
6677 /*
6678 * FIXME: sil-sii8620 doesn't have a connector around when
6679 * we need one, so we have to be prepared for a NULL connector.
6680 */
6681 if (!connector)
6682 return true;
6683
6684 return connector->display_info.hdmi.scdc.supported ||
6685 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6686 }
6687
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)6688 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6689 const struct drm_display_mode *mode)
6690 {
6691 bool has_hdmi_infoframe = connector ?
6692 connector->display_info.has_hdmi_infoframe : false;
6693
6694 if (!has_hdmi_infoframe)
6695 return 0;
6696
6697 /* No HDMI VIC when signalling 3D video format */
6698 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6699 return 0;
6700
6701 return drm_match_hdmi_mode(mode);
6702 }
6703
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)6704 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6705 const struct drm_display_mode *mode)
6706 {
6707 /*
6708 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6709 * we should send its VIC in vendor infoframes, else send the
6710 * VIC in AVI infoframes. Lets check if this mode is present in
6711 * HDMI 1.4b 4K modes
6712 */
6713 if (drm_mode_hdmi_vic(connector, mode))
6714 return 0;
6715
6716 return drm_match_cea_mode(mode);
6717 }
6718
6719 /*
6720 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
6721 * conform to HDMI 1.4.
6722 *
6723 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
6724 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
6725 */
vic_for_avi_infoframe(const struct drm_connector * connector,u8 vic)6726 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
6727 {
6728 if (!is_hdmi2_sink(connector) && vic > 64)
6729 return 0;
6730
6731 return vic;
6732 }
6733
6734 /**
6735 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6736 * data from a DRM display mode
6737 * @frame: HDMI AVI infoframe
6738 * @connector: the connector
6739 * @mode: DRM display mode
6740 *
6741 * Return: 0 on success or a negative error code on failure.
6742 */
6743 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)6744 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6745 const struct drm_connector *connector,
6746 const struct drm_display_mode *mode)
6747 {
6748 enum hdmi_picture_aspect picture_aspect;
6749 u8 vic, hdmi_vic;
6750
6751 if (!frame || !mode)
6752 return -EINVAL;
6753
6754 hdmi_avi_infoframe_init(frame);
6755
6756 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6757 frame->pixel_repeat = 1;
6758
6759 vic = drm_mode_cea_vic(connector, mode);
6760 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6761
6762 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6763
6764 /*
6765 * As some drivers don't support atomic, we can't use connector state.
6766 * So just initialize the frame with default values, just the same way
6767 * as it's done with other properties here.
6768 */
6769 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6770 frame->itc = 0;
6771
6772 /*
6773 * Populate picture aspect ratio from either
6774 * user input (if specified) or from the CEA/HDMI mode lists.
6775 */
6776 picture_aspect = mode->picture_aspect_ratio;
6777 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6778 if (vic)
6779 picture_aspect = drm_get_cea_aspect_ratio(vic);
6780 else if (hdmi_vic)
6781 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6782 }
6783
6784 /*
6785 * The infoframe can't convey anything but none, 4:3
6786 * and 16:9, so if the user has asked for anything else
6787 * we can only satisfy it by specifying the right VIC.
6788 */
6789 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6790 if (vic) {
6791 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6792 return -EINVAL;
6793 } else if (hdmi_vic) {
6794 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6795 return -EINVAL;
6796 } else {
6797 return -EINVAL;
6798 }
6799
6800 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6801 }
6802
6803 frame->video_code = vic_for_avi_infoframe(connector, vic);
6804 frame->picture_aspect = picture_aspect;
6805 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6806 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6807
6808 return 0;
6809 }
6810 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6811
6812 /**
6813 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6814 * quantization range information
6815 * @frame: HDMI AVI infoframe
6816 * @connector: the connector
6817 * @mode: DRM display mode
6818 * @rgb_quant_range: RGB quantization range (Q)
6819 */
6820 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)6821 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6822 const struct drm_connector *connector,
6823 const struct drm_display_mode *mode,
6824 enum hdmi_quantization_range rgb_quant_range)
6825 {
6826 const struct drm_display_info *info = &connector->display_info;
6827
6828 /*
6829 * CEA-861:
6830 * "A Source shall not send a non-zero Q value that does not correspond
6831 * to the default RGB Quantization Range for the transmitted Picture
6832 * unless the Sink indicates support for the Q bit in a Video
6833 * Capabilities Data Block."
6834 *
6835 * HDMI 2.0 recommends sending non-zero Q when it does match the
6836 * default RGB quantization range for the mode, even when QS=0.
6837 */
6838 if (info->rgb_quant_range_selectable ||
6839 rgb_quant_range == drm_default_rgb_quant_range(mode))
6840 frame->quantization_range = rgb_quant_range;
6841 else
6842 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6843
6844 /*
6845 * CEA-861-F:
6846 * "When transmitting any RGB colorimetry, the Source should set the
6847 * YQ-field to match the RGB Quantization Range being transmitted
6848 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6849 * set YQ=1) and the Sink shall ignore the YQ-field."
6850 *
6851 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6852 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6853 * good way to tell which version of CEA-861 the sink supports, so
6854 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6855 * on on CEA-861-F.
6856 */
6857 if (!is_hdmi2_sink(connector) ||
6858 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6859 frame->ycc_quantization_range =
6860 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6861 else
6862 frame->ycc_quantization_range =
6863 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6864 }
6865 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6866
6867 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)6868 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6869 {
6870 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6871
6872 switch (layout) {
6873 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6874 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6875 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6876 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6877 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6878 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6879 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6880 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6881 case DRM_MODE_FLAG_3D_L_DEPTH:
6882 return HDMI_3D_STRUCTURE_L_DEPTH;
6883 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6884 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6885 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6886 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6887 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6888 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6889 default:
6890 return HDMI_3D_STRUCTURE_INVALID;
6891 }
6892 }
6893
6894 /**
6895 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6896 * data from a DRM display mode
6897 * @frame: HDMI vendor infoframe
6898 * @connector: the connector
6899 * @mode: DRM display mode
6900 *
6901 * Note that there's is a need to send HDMI vendor infoframes only when using a
6902 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6903 * function will return -EINVAL, error that can be safely ignored.
6904 *
6905 * Return: 0 on success or a negative error code on failure.
6906 */
6907 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)6908 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6909 const struct drm_connector *connector,
6910 const struct drm_display_mode *mode)
6911 {
6912 /*
6913 * FIXME: sil-sii8620 doesn't have a connector around when
6914 * we need one, so we have to be prepared for a NULL connector.
6915 */
6916 bool has_hdmi_infoframe = connector ?
6917 connector->display_info.has_hdmi_infoframe : false;
6918 int err;
6919
6920 if (!frame || !mode)
6921 return -EINVAL;
6922
6923 if (!has_hdmi_infoframe)
6924 return -EINVAL;
6925
6926 err = hdmi_vendor_infoframe_init(frame);
6927 if (err < 0)
6928 return err;
6929
6930 /*
6931 * Even if it's not absolutely necessary to send the infoframe
6932 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6933 * know that the sink can handle it. This is based on a
6934 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6935 * have trouble realizing that they should switch from 3D to 2D
6936 * mode if the source simply stops sending the infoframe when
6937 * it wants to switch from 3D to 2D.
6938 */
6939 frame->vic = drm_mode_hdmi_vic(connector, mode);
6940 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6941
6942 return 0;
6943 }
6944 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6945
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)6946 static void drm_parse_tiled_block(struct drm_connector *connector,
6947 const struct displayid_block *block)
6948 {
6949 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6950 u16 w, h;
6951 u8 tile_v_loc, tile_h_loc;
6952 u8 num_v_tile, num_h_tile;
6953 struct drm_tile_group *tg;
6954
6955 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6956 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6957
6958 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6959 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6960 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6961 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6962
6963 connector->has_tile = true;
6964 if (tile->tile_cap & 0x80)
6965 connector->tile_is_single_monitor = true;
6966
6967 connector->num_h_tile = num_h_tile + 1;
6968 connector->num_v_tile = num_v_tile + 1;
6969 connector->tile_h_loc = tile_h_loc;
6970 connector->tile_v_loc = tile_v_loc;
6971 connector->tile_h_size = w + 1;
6972 connector->tile_v_size = h + 1;
6973
6974 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6975 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6976 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6977 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6978 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6979
6980 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6981 if (!tg)
6982 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6983 if (!tg)
6984 return;
6985
6986 if (connector->tile_group != tg) {
6987 /* if we haven't got a pointer,
6988 take the reference, drop ref to old tile group */
6989 if (connector->tile_group)
6990 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6991 connector->tile_group = tg;
6992 } else {
6993 /* if same tile group, then release the ref we just took. */
6994 drm_mode_put_tile_group(connector->dev, tg);
6995 }
6996 }
6997
_drm_update_tile_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6998 static void _drm_update_tile_info(struct drm_connector *connector,
6999 const struct drm_edid *drm_edid)
7000 {
7001 const struct displayid_block *block;
7002 struct displayid_iter iter;
7003
7004 connector->has_tile = false;
7005
7006 displayid_iter_edid_begin(drm_edid, &iter);
7007 displayid_iter_for_each(block, &iter) {
7008 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7009 drm_parse_tiled_block(connector, block);
7010 }
7011 displayid_iter_end(&iter);
7012
7013 if (!connector->has_tile && connector->tile_group) {
7014 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7015 connector->tile_group = NULL;
7016 }
7017 }
7018