1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 *
5 * Copyright (c) 2009, Intel Corporation.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/preempt.h>
13 #include <linux/highmem.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18 #include <linux/string.h>
19 #include <linux/of.h>
20
21 #include "spi-dw.h"
22
23 #ifdef CONFIG_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 /* Slave spi_device related */
28 struct dw_spi_chip_data {
29 u32 cr0;
30 u32 rx_sample_dly; /* RX sample delay */
31 };
32
33 #ifdef CONFIG_DEBUG_FS
34
35 #define DW_SPI_DBGFS_REG(_name, _off) \
36 { \
37 .name = _name, \
38 .offset = _off, \
39 }
40
41 static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
42 DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
43 DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
44 DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
45 DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
46 DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
47 DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
48 DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
49 DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
50 DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
51 DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
52 DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
53 DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
54 DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
55 DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
56 DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
57 DW_SPI_DBGFS_REG("RX_SAMPLE_DLY", DW_SPI_RX_SAMPLE_DLY),
58 };
59
dw_spi_debugfs_init(struct dw_spi * dws)60 static int dw_spi_debugfs_init(struct dw_spi *dws)
61 {
62 char name[32];
63
64 snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
65 dws->debugfs = debugfs_create_dir(name, NULL);
66 if (!dws->debugfs)
67 return -ENOMEM;
68
69 dws->regset.regs = dw_spi_dbgfs_regs;
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
71 dws->regset.base = dws->regs;
72 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
73
74 return 0;
75 }
76
dw_spi_debugfs_remove(struct dw_spi * dws)77 static void dw_spi_debugfs_remove(struct dw_spi *dws)
78 {
79 debugfs_remove_recursive(dws->debugfs);
80 }
81
82 #else
dw_spi_debugfs_init(struct dw_spi * dws)83 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
84 {
85 return 0;
86 }
87
dw_spi_debugfs_remove(struct dw_spi * dws)88 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
89 {
90 }
91 #endif /* CONFIG_DEBUG_FS */
92
dw_spi_set_cs(struct spi_device * spi,bool enable)93 void dw_spi_set_cs(struct spi_device *spi, bool enable)
94 {
95 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
96 bool cs_high = !!(spi->mode & SPI_CS_HIGH);
97
98 /*
99 * DW SPI controller demands any native CS being set in order to
100 * proceed with data transfer. So in order to activate the SPI
101 * communications we must set a corresponding bit in the Slave
102 * Enable register no matter whether the SPI core is configured to
103 * support active-high or active-low CS level.
104 */
105 if (cs_high == enable)
106 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
107 else
108 dw_writel(dws, DW_SPI_SER, 0);
109 }
110 EXPORT_SYMBOL_NS_GPL(dw_spi_set_cs, SPI_DW_CORE);
111
112 /* Return the max entries we can fill into tx fifo */
dw_spi_tx_max(struct dw_spi * dws)113 static inline u32 dw_spi_tx_max(struct dw_spi *dws)
114 {
115 u32 tx_room, rxtx_gap;
116
117 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
118
119 /*
120 * Another concern is about the tx/rx mismatch, we
121 * though to use (dws->fifo_len - rxflr - txflr) as
122 * one maximum value for tx, but it doesn't cover the
123 * data which is out of tx/rx fifo and inside the
124 * shift registers. So a control from sw point of
125 * view is taken.
126 */
127 rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
128
129 return min3((u32)dws->tx_len, tx_room, rxtx_gap);
130 }
131
132 /* Return the max entries we should read out of rx fifo */
dw_spi_rx_max(struct dw_spi * dws)133 static inline u32 dw_spi_rx_max(struct dw_spi *dws)
134 {
135 return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR));
136 }
137
dw_writer(struct dw_spi * dws)138 static void dw_writer(struct dw_spi *dws)
139 {
140 u32 max = dw_spi_tx_max(dws);
141 u32 txw = 0;
142
143 while (max--) {
144 if (dws->tx) {
145 if (dws->n_bytes == 1)
146 txw = *(u8 *)(dws->tx);
147 else if (dws->n_bytes == 2)
148 txw = *(u16 *)(dws->tx);
149 else
150 txw = *(u32 *)(dws->tx);
151
152 dws->tx += dws->n_bytes;
153 }
154 dw_write_io_reg(dws, DW_SPI_DR, txw);
155 --dws->tx_len;
156 }
157 }
158
dw_reader(struct dw_spi * dws)159 static void dw_reader(struct dw_spi *dws)
160 {
161 u32 max = dw_spi_rx_max(dws);
162 u32 rxw;
163
164 while (max--) {
165 rxw = dw_read_io_reg(dws, DW_SPI_DR);
166 if (dws->rx) {
167 if (dws->n_bytes == 1)
168 *(u8 *)(dws->rx) = rxw;
169 else if (dws->n_bytes == 2)
170 *(u16 *)(dws->rx) = rxw;
171 else
172 *(u32 *)(dws->rx) = rxw;
173
174 dws->rx += dws->n_bytes;
175 }
176 --dws->rx_len;
177 }
178 }
179
dw_spi_check_status(struct dw_spi * dws,bool raw)180 int dw_spi_check_status(struct dw_spi *dws, bool raw)
181 {
182 u32 irq_status;
183 int ret = 0;
184
185 if (raw)
186 irq_status = dw_readl(dws, DW_SPI_RISR);
187 else
188 irq_status = dw_readl(dws, DW_SPI_ISR);
189
190 if (irq_status & DW_SPI_INT_RXOI) {
191 dev_err(&dws->master->dev, "RX FIFO overflow detected\n");
192 ret = -EIO;
193 }
194
195 if (irq_status & DW_SPI_INT_RXUI) {
196 dev_err(&dws->master->dev, "RX FIFO underflow detected\n");
197 ret = -EIO;
198 }
199
200 if (irq_status & DW_SPI_INT_TXOI) {
201 dev_err(&dws->master->dev, "TX FIFO overflow detected\n");
202 ret = -EIO;
203 }
204
205 /* Generically handle the erroneous situation */
206 if (ret) {
207 dw_spi_reset_chip(dws);
208 if (dws->master->cur_msg)
209 dws->master->cur_msg->status = ret;
210 }
211
212 return ret;
213 }
214 EXPORT_SYMBOL_NS_GPL(dw_spi_check_status, SPI_DW_CORE);
215
dw_spi_transfer_handler(struct dw_spi * dws)216 static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
217 {
218 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
219
220 if (dw_spi_check_status(dws, false)) {
221 spi_finalize_current_transfer(dws->master);
222 return IRQ_HANDLED;
223 }
224
225 /*
226 * Read data from the Rx FIFO every time we've got a chance executing
227 * this method. If there is nothing left to receive, terminate the
228 * procedure. Otherwise adjust the Rx FIFO Threshold level if it's a
229 * final stage of the transfer. By doing so we'll get the next IRQ
230 * right when the leftover incoming data is received.
231 */
232 dw_reader(dws);
233 if (!dws->rx_len) {
234 dw_spi_mask_intr(dws, 0xff);
235 spi_finalize_current_transfer(dws->master);
236 } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
237 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
238 }
239
240 /*
241 * Send data out if Tx FIFO Empty IRQ is received. The IRQ will be
242 * disabled after the data transmission is finished so not to
243 * have the TXE IRQ flood at the final stage of the transfer.
244 */
245 if (irq_status & DW_SPI_INT_TXEI) {
246 dw_writer(dws);
247 if (!dws->tx_len)
248 dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
249 }
250
251 return IRQ_HANDLED;
252 }
253
dw_spi_irq(int irq,void * dev_id)254 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
255 {
256 struct spi_controller *master = dev_id;
257 struct dw_spi *dws = spi_controller_get_devdata(master);
258 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
259
260 if (!irq_status)
261 return IRQ_NONE;
262
263 if (!master->cur_msg) {
264 dw_spi_mask_intr(dws, 0xff);
265 return IRQ_HANDLED;
266 }
267
268 return dws->transfer_handler(dws);
269 }
270
dw_spi_prepare_cr0(struct dw_spi * dws,struct spi_device * spi)271 static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
272 {
273 u32 cr0 = 0;
274
275 if (dw_spi_ip_is(dws, PSSI)) {
276 /* CTRLR0[ 5: 4] Frame Format */
277 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
278
279 /*
280 * SPI mode (SCPOL|SCPH)
281 * CTRLR0[ 6] Serial Clock Phase
282 * CTRLR0[ 7] Serial Clock Polarity
283 */
284 if (spi->mode & SPI_CPOL)
285 cr0 |= DW_PSSI_CTRLR0_SCPOL;
286 if (spi->mode & SPI_CPHA)
287 cr0 |= DW_PSSI_CTRLR0_SCPHA;
288
289 /* CTRLR0[11] Shift Register Loop */
290 if (spi->mode & SPI_LOOP)
291 cr0 |= DW_PSSI_CTRLR0_SRL;
292 } else {
293 /* CTRLR0[ 7: 6] Frame Format */
294 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
295
296 /*
297 * SPI mode (SCPOL|SCPH)
298 * CTRLR0[ 8] Serial Clock Phase
299 * CTRLR0[ 9] Serial Clock Polarity
300 */
301 if (spi->mode & SPI_CPOL)
302 cr0 |= DW_HSSI_CTRLR0_SCPOL;
303 if (spi->mode & SPI_CPHA)
304 cr0 |= DW_HSSI_CTRLR0_SCPHA;
305
306 /* CTRLR0[13] Shift Register Loop */
307 if (spi->mode & SPI_LOOP)
308 cr0 |= DW_HSSI_CTRLR0_SRL;
309
310 /* CTRLR0[31] MST */
311 if (dw_spi_ver_is_ge(dws, HSSI, 102A))
312 cr0 |= DW_HSSI_CTRLR0_MST;
313 }
314
315 return cr0;
316 }
317
dw_spi_update_config(struct dw_spi * dws,struct spi_device * spi,struct dw_spi_cfg * cfg)318 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
319 struct dw_spi_cfg *cfg)
320 {
321 struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
322 u32 cr0 = chip->cr0;
323 u32 speed_hz;
324 u16 clk_div;
325
326 /* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */
327 cr0 |= (cfg->dfs - 1) << dws->dfs_offset;
328
329 if (dw_spi_ip_is(dws, PSSI))
330 /* CTRLR0[ 9:8] Transfer Mode */
331 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode);
332 else
333 /* CTRLR0[11:10] Transfer Mode */
334 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
335
336 dw_writel(dws, DW_SPI_CTRLR0, cr0);
337
338 if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
339 cfg->tmode == DW_SPI_CTRLR0_TMOD_RO)
340 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
341
342 /* Note DW APB SSI clock divider doesn't support odd numbers */
343 clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
344 speed_hz = dws->max_freq / clk_div;
345
346 if (dws->current_freq != speed_hz) {
347 dw_spi_set_clk(dws, clk_div);
348 dws->current_freq = speed_hz;
349 }
350
351 /* Update RX sample delay if required */
352 if (dws->cur_rx_sample_dly != chip->rx_sample_dly) {
353 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly);
354 dws->cur_rx_sample_dly = chip->rx_sample_dly;
355 }
356 }
357 EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, SPI_DW_CORE);
358
dw_spi_irq_setup(struct dw_spi * dws)359 static void dw_spi_irq_setup(struct dw_spi *dws)
360 {
361 u16 level;
362 u8 imask;
363
364 /*
365 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
366 * will be adjusted at the final stage of the IRQ-based SPI transfer
367 * execution so not to lose the leftover of the incoming data.
368 */
369 level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len);
370 dw_writel(dws, DW_SPI_TXFTLR, level);
371 dw_writel(dws, DW_SPI_RXFTLR, level - 1);
372
373 dws->transfer_handler = dw_spi_transfer_handler;
374
375 imask = DW_SPI_INT_TXEI | DW_SPI_INT_TXOI |
376 DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI;
377 dw_spi_umask_intr(dws, imask);
378 }
379
380 /*
381 * The iterative procedure of the poll-based transfer is simple: write as much
382 * as possible to the Tx FIFO, wait until the pending to receive data is ready
383 * to be read, read it from the Rx FIFO and check whether the performed
384 * procedure has been successful.
385 *
386 * Note this method the same way as the IRQ-based transfer won't work well for
387 * the SPI devices connected to the controller with native CS due to the
388 * automatic CS assertion/de-assertion.
389 */
dw_spi_poll_transfer(struct dw_spi * dws,struct spi_transfer * transfer)390 static int dw_spi_poll_transfer(struct dw_spi *dws,
391 struct spi_transfer *transfer)
392 {
393 struct spi_delay delay;
394 u16 nbits;
395 int ret;
396
397 delay.unit = SPI_DELAY_UNIT_SCK;
398 nbits = dws->n_bytes * BITS_PER_BYTE;
399
400 do {
401 dw_writer(dws);
402
403 delay.value = nbits * (dws->rx_len - dws->tx_len);
404 spi_delay_exec(&delay, transfer);
405
406 dw_reader(dws);
407
408 ret = dw_spi_check_status(dws, true);
409 if (ret)
410 return ret;
411 } while (dws->rx_len);
412
413 return 0;
414 }
415
dw_spi_transfer_one(struct spi_controller * master,struct spi_device * spi,struct spi_transfer * transfer)416 static int dw_spi_transfer_one(struct spi_controller *master,
417 struct spi_device *spi,
418 struct spi_transfer *transfer)
419 {
420 struct dw_spi *dws = spi_controller_get_devdata(master);
421 struct dw_spi_cfg cfg = {
422 .tmode = DW_SPI_CTRLR0_TMOD_TR,
423 .dfs = transfer->bits_per_word,
424 .freq = transfer->speed_hz,
425 };
426 int ret;
427
428 dws->dma_mapped = 0;
429 dws->n_bytes =
430 roundup_pow_of_two(DIV_ROUND_UP(transfer->bits_per_word,
431 BITS_PER_BYTE));
432
433 dws->tx = (void *)transfer->tx_buf;
434 dws->tx_len = transfer->len / dws->n_bytes;
435 dws->rx = transfer->rx_buf;
436 dws->rx_len = dws->tx_len;
437
438 /* Ensure the data above is visible for all CPUs */
439 smp_mb();
440
441 dw_spi_enable_chip(dws, 0);
442
443 dw_spi_update_config(dws, spi, &cfg);
444
445 transfer->effective_speed_hz = dws->current_freq;
446
447 /* Check if current transfer is a DMA transaction */
448 if (master->can_dma && master->can_dma(master, spi, transfer))
449 dws->dma_mapped = master->cur_msg_mapped;
450
451 /* For poll mode just disable all interrupts */
452 dw_spi_mask_intr(dws, 0xff);
453
454 if (dws->dma_mapped) {
455 ret = dws->dma_ops->dma_setup(dws, transfer);
456 if (ret)
457 return ret;
458 }
459
460 dw_spi_enable_chip(dws, 1);
461
462 if (dws->dma_mapped)
463 return dws->dma_ops->dma_transfer(dws, transfer);
464 else if (dws->irq == IRQ_NOTCONNECTED)
465 return dw_spi_poll_transfer(dws, transfer);
466
467 dw_spi_irq_setup(dws);
468
469 return 1;
470 }
471
dw_spi_handle_err(struct spi_controller * master,struct spi_message * msg)472 static void dw_spi_handle_err(struct spi_controller *master,
473 struct spi_message *msg)
474 {
475 struct dw_spi *dws = spi_controller_get_devdata(master);
476
477 if (dws->dma_mapped)
478 dws->dma_ops->dma_stop(dws);
479
480 dw_spi_reset_chip(dws);
481 }
482
dw_spi_adjust_mem_op_size(struct spi_mem * mem,struct spi_mem_op * op)483 static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
484 {
485 if (op->data.dir == SPI_MEM_DATA_IN)
486 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1);
487
488 return 0;
489 }
490
dw_spi_supports_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)491 static bool dw_spi_supports_mem_op(struct spi_mem *mem,
492 const struct spi_mem_op *op)
493 {
494 if (op->data.buswidth > 1 || op->addr.buswidth > 1 ||
495 op->dummy.buswidth > 1 || op->cmd.buswidth > 1)
496 return false;
497
498 return spi_mem_default_supports_op(mem, op);
499 }
500
dw_spi_init_mem_buf(struct dw_spi * dws,const struct spi_mem_op * op)501 static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
502 {
503 unsigned int i, j, len;
504 u8 *out;
505
506 /*
507 * Calculate the total length of the EEPROM command transfer and
508 * either use the pre-allocated buffer or create a temporary one.
509 */
510 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
511 if (op->data.dir == SPI_MEM_DATA_OUT)
512 len += op->data.nbytes;
513
514 if (len <= DW_SPI_BUF_SIZE) {
515 out = dws->buf;
516 } else {
517 out = kzalloc(len, GFP_KERNEL);
518 if (!out)
519 return -ENOMEM;
520 }
521
522 /*
523 * Collect the operation code, address and dummy bytes into the single
524 * buffer. If it's a transfer with data to be sent, also copy it into the
525 * single buffer in order to speed the data transmission up.
526 */
527 for (i = 0; i < op->cmd.nbytes; ++i)
528 out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1);
529 for (j = 0; j < op->addr.nbytes; ++i, ++j)
530 out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
531 for (j = 0; j < op->dummy.nbytes; ++i, ++j)
532 out[i] = 0x0;
533
534 if (op->data.dir == SPI_MEM_DATA_OUT)
535 memcpy(&out[i], op->data.buf.out, op->data.nbytes);
536
537 dws->n_bytes = 1;
538 dws->tx = out;
539 dws->tx_len = len;
540 if (op->data.dir == SPI_MEM_DATA_IN) {
541 dws->rx = op->data.buf.in;
542 dws->rx_len = op->data.nbytes;
543 } else {
544 dws->rx = NULL;
545 dws->rx_len = 0;
546 }
547
548 return 0;
549 }
550
dw_spi_free_mem_buf(struct dw_spi * dws)551 static void dw_spi_free_mem_buf(struct dw_spi *dws)
552 {
553 if (dws->tx != dws->buf)
554 kfree(dws->tx);
555 }
556
dw_spi_write_then_read(struct dw_spi * dws,struct spi_device * spi)557 static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
558 {
559 u32 room, entries, sts;
560 unsigned int len;
561 u8 *buf;
562
563 /*
564 * At initial stage we just pre-fill the Tx FIFO in with no rush,
565 * since native CS hasn't been enabled yet and the automatic data
566 * transmission won't start til we do that.
567 */
568 len = min(dws->fifo_len, dws->tx_len);
569 buf = dws->tx;
570 while (len--)
571 dw_write_io_reg(dws, DW_SPI_DR, *buf++);
572
573 /*
574 * After setting any bit in the SER register the transmission will
575 * start automatically. We have to keep up with that procedure
576 * otherwise the CS de-assertion will happen whereupon the memory
577 * operation will be pre-terminated.
578 */
579 len = dws->tx_len - ((void *)buf - dws->tx);
580 dw_spi_set_cs(spi, false);
581 while (len) {
582 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
583 if (!entries) {
584 dev_err(&dws->master->dev, "CS de-assertion on Tx\n");
585 return -EIO;
586 }
587 room = min(dws->fifo_len - entries, len);
588 for (; room; --room, --len)
589 dw_write_io_reg(dws, DW_SPI_DR, *buf++);
590 }
591
592 /*
593 * Data fetching will start automatically if the EEPROM-read mode is
594 * activated. We have to keep up with the incoming data pace to
595 * prevent the Rx FIFO overflow causing the inbound data loss.
596 */
597 len = dws->rx_len;
598 buf = dws->rx;
599 while (len) {
600 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR);
601 if (!entries) {
602 sts = readl_relaxed(dws->regs + DW_SPI_RISR);
603 if (sts & DW_SPI_INT_RXOI) {
604 dev_err(&dws->master->dev, "FIFO overflow on Rx\n");
605 return -EIO;
606 }
607 continue;
608 }
609 entries = min(entries, len);
610 for (; entries; --entries, --len)
611 *buf++ = dw_read_io_reg(dws, DW_SPI_DR);
612 }
613
614 return 0;
615 }
616
dw_spi_ctlr_busy(struct dw_spi * dws)617 static inline bool dw_spi_ctlr_busy(struct dw_spi *dws)
618 {
619 return dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_BUSY;
620 }
621
dw_spi_wait_mem_op_done(struct dw_spi * dws)622 static int dw_spi_wait_mem_op_done(struct dw_spi *dws)
623 {
624 int retry = DW_SPI_WAIT_RETRIES;
625 struct spi_delay delay;
626 unsigned long ns, us;
627 u32 nents;
628
629 nents = dw_readl(dws, DW_SPI_TXFLR);
630 ns = NSEC_PER_SEC / dws->current_freq * nents;
631 ns *= dws->n_bytes * BITS_PER_BYTE;
632 if (ns <= NSEC_PER_USEC) {
633 delay.unit = SPI_DELAY_UNIT_NSECS;
634 delay.value = ns;
635 } else {
636 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
637 delay.unit = SPI_DELAY_UNIT_USECS;
638 delay.value = clamp_val(us, 0, USHRT_MAX);
639 }
640
641 while (dw_spi_ctlr_busy(dws) && retry--)
642 spi_delay_exec(&delay, NULL);
643
644 if (retry < 0) {
645 dev_err(&dws->master->dev, "Mem op hanged up\n");
646 return -EIO;
647 }
648
649 return 0;
650 }
651
dw_spi_stop_mem_op(struct dw_spi * dws,struct spi_device * spi)652 static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
653 {
654 dw_spi_enable_chip(dws, 0);
655 dw_spi_set_cs(spi, true);
656 dw_spi_enable_chip(dws, 1);
657 }
658
659 /*
660 * The SPI memory operation implementation below is the best choice for the
661 * devices, which are selected by the native chip-select lane. It's
662 * specifically developed to workaround the problem with automatic chip-select
663 * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current
664 * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
665 * unavailable.
666 */
dw_spi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)667 static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
668 {
669 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
670 struct dw_spi_cfg cfg;
671 unsigned long flags;
672 int ret;
673
674 /*
675 * Collect the outbound data into a single buffer to speed the
676 * transmission up at least on the initial stage.
677 */
678 ret = dw_spi_init_mem_buf(dws, op);
679 if (ret)
680 return ret;
681
682 /*
683 * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN
684 * operation. Transmit-only mode is suitable for the rest of them.
685 */
686 cfg.dfs = 8;
687 cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);
688 if (op->data.dir == SPI_MEM_DATA_IN) {
689 cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
690 cfg.ndf = op->data.nbytes;
691 } else {
692 cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
693 }
694
695 dw_spi_enable_chip(dws, 0);
696
697 dw_spi_update_config(dws, mem->spi, &cfg);
698
699 dw_spi_mask_intr(dws, 0xff);
700
701 dw_spi_enable_chip(dws, 1);
702
703 /*
704 * DW APB SSI controller has very nasty peculiarities. First originally
705 * (without any vendor-specific modifications) it doesn't provide a
706 * direct way to set and clear the native chip-select signal. Instead
707 * the controller asserts the CS lane if Tx FIFO isn't empty and a
708 * transmission is going on, and automatically de-asserts it back to
709 * the high level if the Tx FIFO doesn't have anything to be pushed
710 * out. Due to that a multi-tasking or heavy IRQs activity might be
711 * fatal, since the transfer procedure preemption may cause the Tx FIFO
712 * getting empty and sudden CS de-assertion, which in the middle of the
713 * transfer will most likely cause the data loss. Secondly the
714 * EEPROM-read or Read-only DW SPI transfer modes imply the incoming
715 * data being automatically pulled in into the Rx FIFO. So if the
716 * driver software is late in fetching the data from the FIFO before
717 * it's overflown, new incoming data will be lost. In order to make
718 * sure the executed memory operations are CS-atomic and to prevent the
719 * Rx FIFO overflow we have to disable the local interrupts so to block
720 * any preemption during the subsequent IO operations.
721 *
722 * Note. At some circumstances disabling IRQs may not help to prevent
723 * the problems described above. The CS de-assertion and Rx FIFO
724 * overflow may still happen due to the relatively slow system bus or
725 * CPU not working fast enough, so the write-then-read algo implemented
726 * here just won't keep up with the SPI bus data transfer. Such
727 * situation is highly platform specific and is supposed to be fixed by
728 * manually restricting the SPI bus frequency using the
729 * dws->max_mem_freq parameter.
730 */
731 local_irq_save(flags);
732 preempt_disable();
733
734 ret = dw_spi_write_then_read(dws, mem->spi);
735
736 local_irq_restore(flags);
737 preempt_enable();
738
739 /*
740 * Wait for the operation being finished and check the controller
741 * status only if there hasn't been any run-time error detected. In the
742 * former case it's just pointless. In the later one to prevent an
743 * additional error message printing since any hw error flag being set
744 * would be due to an error detected on the data transfer.
745 */
746 if (!ret) {
747 ret = dw_spi_wait_mem_op_done(dws);
748 if (!ret)
749 ret = dw_spi_check_status(dws, true);
750 }
751
752 dw_spi_stop_mem_op(dws, mem->spi);
753
754 dw_spi_free_mem_buf(dws);
755
756 return ret;
757 }
758
759 /*
760 * Initialize the default memory operations if a glue layer hasn't specified
761 * custom ones. Direct mapping operations will be preserved anyway since DW SPI
762 * controller doesn't have an embedded dirmap interface. Note the memory
763 * operations implemented in this driver is the best choice only for the DW APB
764 * SSI controller with standard native CS functionality. If a hardware vendor
765 * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
766 * be safer to use the normal SPI-messages-based transfers implementation.
767 */
dw_spi_init_mem_ops(struct dw_spi * dws)768 static void dw_spi_init_mem_ops(struct dw_spi *dws)
769 {
770 if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) &&
771 !dws->set_cs) {
772 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
773 dws->mem_ops.supports_op = dw_spi_supports_mem_op;
774 dws->mem_ops.exec_op = dw_spi_exec_mem_op;
775 if (!dws->max_mem_freq)
776 dws->max_mem_freq = dws->max_freq;
777 }
778 }
779
780 /* This may be called twice for each spi dev */
dw_spi_setup(struct spi_device * spi)781 static int dw_spi_setup(struct spi_device *spi)
782 {
783 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
784 struct dw_spi_chip_data *chip;
785
786 /* Only alloc on first setup */
787 chip = spi_get_ctldata(spi);
788 if (!chip) {
789 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
790 u32 rx_sample_dly_ns;
791
792 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
793 if (!chip)
794 return -ENOMEM;
795 spi_set_ctldata(spi, chip);
796 /* Get specific / default rx-sample-delay */
797 if (device_property_read_u32(&spi->dev,
798 "rx-sample-delay-ns",
799 &rx_sample_dly_ns) != 0)
800 /* Use default controller value */
801 rx_sample_dly_ns = dws->def_rx_sample_dly_ns;
802 chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns,
803 NSEC_PER_SEC /
804 dws->max_freq);
805 }
806
807 /*
808 * Update CR0 data each time the setup callback is invoked since
809 * the device parameters could have been changed, for instance, by
810 * the MMC SPI driver or something else.
811 */
812 chip->cr0 = dw_spi_prepare_cr0(dws, spi);
813
814 return 0;
815 }
816
dw_spi_cleanup(struct spi_device * spi)817 static void dw_spi_cleanup(struct spi_device *spi)
818 {
819 struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
820
821 kfree(chip);
822 spi_set_ctldata(spi, NULL);
823 }
824
825 /* Restart the controller, disable all interrupts, clean rx fifo */
dw_spi_hw_init(struct device * dev,struct dw_spi * dws)826 static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
827 {
828 dw_spi_reset_chip(dws);
829
830 /*
831 * Retrieve the Synopsys component version if it hasn't been specified
832 * by the platform. CoreKit version ID is encoded as a 3-chars ASCII
833 * code enclosed with '*' (typical for the most of Synopsys IP-cores).
834 */
835 if (!dws->ver) {
836 dws->ver = dw_readl(dws, DW_SPI_VERSION);
837
838 dev_dbg(dev, "Synopsys DWC%sSSI v%c.%c%c\n",
839 dw_spi_ip_is(dws, PSSI) ? " APB " : " ",
840 DW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2),
841 DW_SPI_GET_BYTE(dws->ver, 1));
842 }
843
844 /*
845 * Try to detect the FIFO depth if not set by interface driver,
846 * the depth could be from 2 to 256 from HW spec
847 */
848 if (!dws->fifo_len) {
849 u32 fifo;
850
851 for (fifo = 1; fifo < 256; fifo++) {
852 dw_writel(dws, DW_SPI_TXFTLR, fifo);
853 if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
854 break;
855 }
856 dw_writel(dws, DW_SPI_TXFTLR, 0);
857
858 dws->fifo_len = (fifo == 1) ? 0 : fifo;
859 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
860 }
861
862 /*
863 * Detect CTRLR0.DFS field size and offset by testing the lowest bits
864 * writability. Note DWC SSI controller also has the extended DFS, but
865 * with zero offset.
866 */
867 if (dw_spi_ip_is(dws, PSSI)) {
868 u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);
869
870 dw_spi_enable_chip(dws, 0);
871 dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
872 cr0 = dw_readl(dws, DW_SPI_CTRLR0);
873 dw_writel(dws, DW_SPI_CTRLR0, tmp);
874 dw_spi_enable_chip(dws, 1);
875
876 if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) {
877 dws->caps |= DW_SPI_CAP_DFS32;
878 dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);
879 dev_dbg(dev, "Detected 32-bits max data frame size\n");
880 }
881 } else {
882 dws->caps |= DW_SPI_CAP_DFS32;
883 }
884
885 /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
886 if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
887 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
888 }
889
dw_spi_add_host(struct device * dev,struct dw_spi * dws)890 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
891 {
892 struct spi_controller *master;
893 int ret;
894
895 if (!dws)
896 return -EINVAL;
897
898 master = spi_alloc_master(dev, 0);
899 if (!master)
900 return -ENOMEM;
901
902 device_set_node(&master->dev, dev_fwnode(dev));
903
904 dws->master = master;
905 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
906
907 spi_controller_set_devdata(master, dws);
908
909 /* Basic HW init */
910 dw_spi_hw_init(dev, dws);
911
912 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
913 master);
914 if (ret < 0 && ret != -ENOTCONN) {
915 dev_err(dev, "can not get IRQ\n");
916 goto err_free_master;
917 }
918
919 dw_spi_init_mem_ops(dws);
920
921 master->use_gpio_descriptors = true;
922 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
923 if (dws->caps & DW_SPI_CAP_DFS32)
924 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
925 else
926 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
927 master->bus_num = dws->bus_num;
928 master->num_chipselect = dws->num_cs;
929 master->setup = dw_spi_setup;
930 master->cleanup = dw_spi_cleanup;
931 if (dws->set_cs)
932 master->set_cs = dws->set_cs;
933 else
934 master->set_cs = dw_spi_set_cs;
935 master->transfer_one = dw_spi_transfer_one;
936 master->handle_err = dw_spi_handle_err;
937 if (dws->mem_ops.exec_op)
938 master->mem_ops = &dws->mem_ops;
939 master->max_speed_hz = dws->max_freq;
940 master->flags = SPI_MASTER_GPIO_SS;
941 master->auto_runtime_pm = true;
942
943 /* Get default rx sample delay */
944 device_property_read_u32(dev, "rx-sample-delay-ns",
945 &dws->def_rx_sample_dly_ns);
946
947 if (dws->dma_ops && dws->dma_ops->dma_init) {
948 ret = dws->dma_ops->dma_init(dev, dws);
949 if (ret == -EPROBE_DEFER) {
950 goto err_free_irq;
951 } else if (ret) {
952 dev_warn(dev, "DMA init failed\n");
953 } else {
954 master->can_dma = dws->dma_ops->can_dma;
955 master->flags |= SPI_CONTROLLER_MUST_TX;
956 }
957 }
958
959 ret = spi_register_controller(master);
960 if (ret) {
961 dev_err_probe(dev, ret, "problem registering spi master\n");
962 goto err_dma_exit;
963 }
964
965 dw_spi_debugfs_init(dws);
966 return 0;
967
968 err_dma_exit:
969 if (dws->dma_ops && dws->dma_ops->dma_exit)
970 dws->dma_ops->dma_exit(dws);
971 dw_spi_enable_chip(dws, 0);
972 err_free_irq:
973 free_irq(dws->irq, master);
974 err_free_master:
975 spi_controller_put(master);
976 return ret;
977 }
978 EXPORT_SYMBOL_NS_GPL(dw_spi_add_host, SPI_DW_CORE);
979
dw_spi_remove_host(struct dw_spi * dws)980 void dw_spi_remove_host(struct dw_spi *dws)
981 {
982 dw_spi_debugfs_remove(dws);
983
984 spi_unregister_controller(dws->master);
985
986 if (dws->dma_ops && dws->dma_ops->dma_exit)
987 dws->dma_ops->dma_exit(dws);
988
989 dw_spi_shutdown_chip(dws);
990
991 free_irq(dws->irq, dws->master);
992 }
993 EXPORT_SYMBOL_NS_GPL(dw_spi_remove_host, SPI_DW_CORE);
994
dw_spi_suspend_host(struct dw_spi * dws)995 int dw_spi_suspend_host(struct dw_spi *dws)
996 {
997 int ret;
998
999 ret = spi_controller_suspend(dws->master);
1000 if (ret)
1001 return ret;
1002
1003 dw_spi_shutdown_chip(dws);
1004 return 0;
1005 }
1006 EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_host, SPI_DW_CORE);
1007
dw_spi_resume_host(struct dw_spi * dws)1008 int dw_spi_resume_host(struct dw_spi *dws)
1009 {
1010 dw_spi_hw_init(&dws->master->dev, dws);
1011 return spi_controller_resume(dws->master);
1012 }
1013 EXPORT_SYMBOL_NS_GPL(dw_spi_resume_host, SPI_DW_CORE);
1014
1015 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1016 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1017 MODULE_LICENSE("GPL v2");
1018