1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2022 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_sriov.h"
26 #include "ef100_netdev.h"
27 #include "tc.h"
28 #include "mae.h"
29 #include "rx_common.h"
30
31 #define EF100_MAX_VIS 4096
32 #define EF100_NUM_MCDI_BUFFERS 1
33 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
34
35 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
36
37 /* MCDI
38 */
ef100_mcdi_buf(struct efx_nic * efx,u8 bufid,dma_addr_t * dma_addr)39 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
40 {
41 struct ef100_nic_data *nic_data = efx->nic_data;
42
43 if (dma_addr)
44 *dma_addr = nic_data->mcdi_buf.dma_addr +
45 bufid * ALIGN(MCDI_BUF_LEN, 256);
46 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
47 }
48
ef100_get_warm_boot_count(struct efx_nic * efx)49 static int ef100_get_warm_boot_count(struct efx_nic *efx)
50 {
51 efx_dword_t reg;
52
53 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
54
55 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
56 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
57 efx->state = STATE_DISABLED;
58 return -ENETDOWN;
59 } else {
60 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
61 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
62 }
63 }
64
ef100_mcdi_request(struct efx_nic * efx,const efx_dword_t * hdr,size_t hdr_len,const efx_dword_t * sdu,size_t sdu_len)65 static void ef100_mcdi_request(struct efx_nic *efx,
66 const efx_dword_t *hdr, size_t hdr_len,
67 const efx_dword_t *sdu, size_t sdu_len)
68 {
69 dma_addr_t dma_addr;
70 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
71
72 memcpy(pdu, hdr, hdr_len);
73 memcpy(pdu + hdr_len, sdu, sdu_len);
74 wmb();
75
76 /* The hardware provides 'low' and 'high' (doorbell) registers
77 * for passing the 64-bit address of an MCDI request to
78 * firmware. However the dwords are swapped by firmware. The
79 * least significant bits of the doorbell are then 0 for all
80 * MCDI requests due to alignment.
81 */
82 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
83 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
84 }
85
ef100_mcdi_poll_response(struct efx_nic * efx)86 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
87 {
88 const efx_dword_t hdr =
89 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
90
91 rmb();
92 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
93 }
94
ef100_mcdi_read_response(struct efx_nic * efx,efx_dword_t * outbuf,size_t offset,size_t outlen)95 static void ef100_mcdi_read_response(struct efx_nic *efx,
96 efx_dword_t *outbuf, size_t offset,
97 size_t outlen)
98 {
99 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
100
101 memcpy(outbuf, pdu + offset, outlen);
102 }
103
ef100_mcdi_poll_reboot(struct efx_nic * efx)104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
105 {
106 struct ef100_nic_data *nic_data = efx->nic_data;
107 int rc;
108
109 rc = ef100_get_warm_boot_count(efx);
110 if (rc < 0) {
111 /* The firmware is presumably in the process of
112 * rebooting. However, we are supposed to report each
113 * reboot just once, so we must only do that once we
114 * can read and store the updated warm boot count.
115 */
116 return 0;
117 }
118
119 if (rc == nic_data->warm_boot_count)
120 return 0;
121
122 nic_data->warm_boot_count = rc;
123
124 return -EIO;
125 }
126
ef100_mcdi_reboot_detected(struct efx_nic * efx)127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
128 {
129 }
130
131 /* MCDI calls
132 */
ef100_get_mac_address(struct efx_nic * efx,u8 * mac_address)133 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
134 {
135 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
136 size_t outlen;
137 int rc;
138
139 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
140
141 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
142 outbuf, sizeof(outbuf), &outlen);
143 if (rc)
144 return rc;
145 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
146 return -EIO;
147
148 ether_addr_copy(mac_address,
149 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
150 return 0;
151 }
152
efx_ef100_init_datapath_caps(struct efx_nic * efx)153 int efx_ef100_init_datapath_caps(struct efx_nic *efx)
154 {
155 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
156 struct ef100_nic_data *nic_data = efx->nic_data;
157 u8 vi_window_mode;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
167 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps = MCDI_DWORD(outbuf,
174 GET_CAPABILITIES_OUT_FLAGS1);
175 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
176 GET_CAPABILITIES_V2_OUT_FLAGS2);
177 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
178 nic_data->datapath_caps3 = 0;
179 else
180 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
181 GET_CAPABILITIES_V7_OUT_FLAGS3);
182
183 vi_window_mode = MCDI_BYTE(outbuf,
184 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
185 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
186 if (rc)
187 return rc;
188
189 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
190 struct net_device *net_dev = efx->net_dev;
191 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
192 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
193 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
194
195 net_dev->features |= tso;
196 net_dev->hw_features |= tso;
197 net_dev->hw_enc_features |= tso;
198 /* EF100 HW can only offload outer checksums if they are UDP,
199 * so for GRE_CSUM we have to use GSO_PARTIAL.
200 */
201 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
202 }
203 efx->num_mac_stats = MCDI_WORD(outbuf,
204 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
205 netif_dbg(efx, probe, efx->net_dev,
206 "firmware reports num_mac_stats = %u\n",
207 efx->num_mac_stats);
208 return 0;
209 }
210
211 /* Event handling
212 */
ef100_ev_probe(struct efx_channel * channel)213 static int ef100_ev_probe(struct efx_channel *channel)
214 {
215 /* Allocate an extra descriptor for the QMDA status completion entry */
216 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
217 (channel->eventq_mask + 2) *
218 sizeof(efx_qword_t),
219 GFP_KERNEL);
220 }
221
ef100_ev_init(struct efx_channel * channel)222 static int ef100_ev_init(struct efx_channel *channel)
223 {
224 struct ef100_nic_data *nic_data = channel->efx->nic_data;
225
226 /* initial phase is 0 */
227 clear_bit(channel->channel, nic_data->evq_phases);
228
229 return efx_mcdi_ev_init(channel, false, false);
230 }
231
ef100_ev_read_ack(struct efx_channel * channel)232 static void ef100_ev_read_ack(struct efx_channel *channel)
233 {
234 efx_dword_t evq_prime;
235
236 EFX_POPULATE_DWORD_2(evq_prime,
237 ERF_GZ_EVQ_ID, channel->channel,
238 ERF_GZ_IDX, channel->eventq_read_ptr &
239 channel->eventq_mask);
240
241 efx_writed(channel->efx, &evq_prime,
242 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
243 }
244
245 #define EFX_NAPI_MAX_TX 512
246
ef100_ev_process(struct efx_channel * channel,int quota)247 static int ef100_ev_process(struct efx_channel *channel, int quota)
248 {
249 struct efx_nic *efx = channel->efx;
250 struct ef100_nic_data *nic_data;
251 bool evq_phase, old_evq_phase;
252 unsigned int read_ptr;
253 efx_qword_t *p_event;
254 int spent_tx = 0;
255 int spent = 0;
256 bool ev_phase;
257 int ev_type;
258
259 if (unlikely(!channel->enabled))
260 return 0;
261
262 nic_data = efx->nic_data;
263 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
264 old_evq_phase = evq_phase;
265 read_ptr = channel->eventq_read_ptr;
266 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
267
268 while (spent < quota) {
269 p_event = efx_event(channel, read_ptr);
270
271 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
272 if (ev_phase != evq_phase)
273 break;
274
275 netif_vdbg(efx, drv, efx->net_dev,
276 "processing event on %d " EFX_QWORD_FMT "\n",
277 channel->channel, EFX_QWORD_VAL(*p_event));
278
279 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
280
281 switch (ev_type) {
282 case ESE_GZ_EF100_EV_RX_PKTS:
283 efx_ef100_ev_rx(channel, p_event);
284 ++spent;
285 break;
286 case ESE_GZ_EF100_EV_MCDI:
287 efx_mcdi_process_event(channel, p_event);
288 break;
289 case ESE_GZ_EF100_EV_TX_COMPLETION:
290 spent_tx += ef100_ev_tx(channel, p_event);
291 if (spent_tx >= EFX_NAPI_MAX_TX)
292 spent = quota;
293 break;
294 case ESE_GZ_EF100_EV_DRIVER:
295 netif_info(efx, drv, efx->net_dev,
296 "Driver initiated event " EFX_QWORD_FMT "\n",
297 EFX_QWORD_VAL(*p_event));
298 break;
299 default:
300 netif_info(efx, drv, efx->net_dev,
301 "Unhandled event " EFX_QWORD_FMT "\n",
302 EFX_QWORD_VAL(*p_event));
303 }
304
305 ++read_ptr;
306 if ((read_ptr & channel->eventq_mask) == 0)
307 evq_phase = !evq_phase;
308 }
309
310 channel->eventq_read_ptr = read_ptr;
311 if (evq_phase != old_evq_phase)
312 change_bit(channel->channel, nic_data->evq_phases);
313
314 return spent;
315 }
316
ef100_msi_interrupt(int irq,void * dev_id)317 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
318 {
319 struct efx_msi_context *context = dev_id;
320 struct efx_nic *efx = context->efx;
321
322 netif_vdbg(efx, intr, efx->net_dev,
323 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
324
325 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
326 /* Note test interrupts */
327 if (context->index == efx->irq_level)
328 efx->last_irq_cpu = raw_smp_processor_id();
329
330 /* Schedule processing of the channel */
331 efx_schedule_channel_irq(efx->channel[context->index]);
332 }
333
334 return IRQ_HANDLED;
335 }
336
ef100_phy_probe(struct efx_nic * efx)337 int ef100_phy_probe(struct efx_nic *efx)
338 {
339 struct efx_mcdi_phy_data *phy_data;
340 int rc;
341
342 /* Probe for the PHY */
343 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
344 if (!efx->phy_data)
345 return -ENOMEM;
346
347 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
348 if (rc)
349 return rc;
350
351 /* Populate driver and ethtool settings */
352 phy_data = efx->phy_data;
353 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
354 efx->link_advertising);
355 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
356 false);
357
358 /* Default to Autonegotiated flow control if the PHY supports it */
359 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
360 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
361 efx->wanted_fc |= EFX_FC_AUTO;
362 efx_link_set_wanted_fc(efx, efx->wanted_fc);
363
364 /* Push settings to the PHY. Failure is not fatal, the user can try to
365 * fix it using ethtool.
366 */
367 rc = efx_mcdi_port_reconfigure(efx);
368 if (rc && rc != -EPERM)
369 netif_warn(efx, drv, efx->net_dev,
370 "could not initialise PHY settings\n");
371
372 return 0;
373 }
374
ef100_filter_table_probe(struct efx_nic * efx)375 int ef100_filter_table_probe(struct efx_nic *efx)
376 {
377 return efx_mcdi_filter_table_probe(efx, true);
378 }
379
ef100_filter_table_up(struct efx_nic * efx)380 static int ef100_filter_table_up(struct efx_nic *efx)
381 {
382 int rc;
383
384 down_write(&efx->filter_sem);
385 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
386 if (rc)
387 goto fail_unspec;
388
389 rc = efx_mcdi_filter_add_vlan(efx, 0);
390 if (rc)
391 goto fail_vlan0;
392 /* Drop the lock: we've finished altering table existence, and
393 * filter insertion will need to take the lock for read.
394 */
395 up_write(&efx->filter_sem);
396 #ifdef CONFIG_SFC_SRIOV
397 rc = efx_tc_insert_rep_filters(efx);
398 /* Rep filter failure is nonfatal */
399 if (rc)
400 netif_warn(efx, drv, efx->net_dev,
401 "Failed to insert representor filters, rc %d\n",
402 rc);
403 #endif
404 return 0;
405
406 fail_vlan0:
407 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
408 fail_unspec:
409 efx_mcdi_filter_table_down(efx);
410 up_write(&efx->filter_sem);
411 return rc;
412 }
413
ef100_filter_table_down(struct efx_nic * efx)414 static void ef100_filter_table_down(struct efx_nic *efx)
415 {
416 #ifdef CONFIG_SFC_SRIOV
417 efx_tc_remove_rep_filters(efx);
418 #endif
419 down_write(&efx->filter_sem);
420 efx_mcdi_filter_del_vlan(efx, 0);
421 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
422 efx_mcdi_filter_table_down(efx);
423 up_write(&efx->filter_sem);
424 }
425
426 /* Other
427 */
ef100_reconfigure_mac(struct efx_nic * efx,bool mtu_only)428 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
429 {
430 WARN_ON(!mutex_is_locked(&efx->mac_lock));
431
432 efx_mcdi_filter_sync_rx_mode(efx);
433
434 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
435 return efx_mcdi_set_mtu(efx);
436 return efx_mcdi_set_mac(efx);
437 }
438
ef100_map_reset_reason(enum reset_type reason)439 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
440 {
441 if (reason == RESET_TYPE_TX_WATCHDOG)
442 return reason;
443 return RESET_TYPE_DISABLE;
444 }
445
ef100_map_reset_flags(u32 * flags)446 static int ef100_map_reset_flags(u32 *flags)
447 {
448 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
449 if ((*flags & EF100_RESET_PORT)) {
450 *flags &= ~EF100_RESET_PORT;
451 return RESET_TYPE_ALL;
452 }
453 if (*flags & ETH_RESET_MGMT) {
454 *flags &= ~ETH_RESET_MGMT;
455 return RESET_TYPE_DISABLE;
456 }
457
458 return -EINVAL;
459 }
460
ef100_reset(struct efx_nic * efx,enum reset_type reset_type)461 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
462 {
463 int rc;
464
465 dev_close(efx->net_dev);
466
467 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
468 netif_device_attach(efx->net_dev);
469 __clear_bit(reset_type, &efx->reset_pending);
470 rc = dev_open(efx->net_dev, NULL);
471 } else if (reset_type == RESET_TYPE_ALL) {
472 rc = efx_mcdi_reset(efx, reset_type);
473 if (rc)
474 return rc;
475
476 netif_device_attach(efx->net_dev);
477
478 rc = dev_open(efx->net_dev, NULL);
479 } else {
480 rc = 1; /* Leave the device closed */
481 }
482 return rc;
483 }
484
ef100_common_stat_mask(unsigned long * mask)485 static void ef100_common_stat_mask(unsigned long *mask)
486 {
487 __set_bit(EF100_STAT_port_rx_packets, mask);
488 __set_bit(EF100_STAT_port_tx_packets, mask);
489 __set_bit(EF100_STAT_port_rx_bytes, mask);
490 __set_bit(EF100_STAT_port_tx_bytes, mask);
491 __set_bit(EF100_STAT_port_rx_multicast, mask);
492 __set_bit(EF100_STAT_port_rx_bad, mask);
493 __set_bit(EF100_STAT_port_rx_align_error, mask);
494 __set_bit(EF100_STAT_port_rx_overflow, mask);
495 }
496
ef100_ethtool_stat_mask(unsigned long * mask)497 static void ef100_ethtool_stat_mask(unsigned long *mask)
498 {
499 __set_bit(EF100_STAT_port_tx_pause, mask);
500 __set_bit(EF100_STAT_port_tx_unicast, mask);
501 __set_bit(EF100_STAT_port_tx_multicast, mask);
502 __set_bit(EF100_STAT_port_tx_broadcast, mask);
503 __set_bit(EF100_STAT_port_tx_lt64, mask);
504 __set_bit(EF100_STAT_port_tx_64, mask);
505 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
506 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
507 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
508 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
509 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
510 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
511 __set_bit(EF100_STAT_port_rx_good, mask);
512 __set_bit(EF100_STAT_port_rx_pause, mask);
513 __set_bit(EF100_STAT_port_rx_unicast, mask);
514 __set_bit(EF100_STAT_port_rx_broadcast, mask);
515 __set_bit(EF100_STAT_port_rx_lt64, mask);
516 __set_bit(EF100_STAT_port_rx_64, mask);
517 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
518 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
519 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
520 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
521 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
522 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
523 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
524 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
525 __set_bit(EF100_STAT_port_rx_length_error, mask);
526 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
527 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
528 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
529 }
530
531 #define EF100_DMA_STAT(ext_name, mcdi_name) \
532 [EF100_STAT_ ## ext_name] = \
533 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
534
535 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
536 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
537 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
538 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
539 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
540 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
541 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
542 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
543 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
544 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
545 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
546 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
547 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
548 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
549 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
550 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
551 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
552 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
553 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
554 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
555 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
556 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
557 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
558 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
559 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
560 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
561 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
562 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
563 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
564 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
565 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
566 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
567 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
568 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
569 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
570 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
571 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
572 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
573 EFX_GENERIC_SW_STAT(rx_noskb_drops),
574 };
575
ef100_describe_stats(struct efx_nic * efx,u8 * names)576 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
577 {
578 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
579
580 ef100_ethtool_stat_mask(mask);
581 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
582 mask, names);
583 }
584
ef100_update_stats_common(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)585 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
586 struct rtnl_link_stats64 *core_stats)
587 {
588 struct ef100_nic_data *nic_data = efx->nic_data;
589 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
590 size_t stats_count = 0, index;
591 u64 *stats = nic_data->stats;
592
593 ef100_ethtool_stat_mask(mask);
594
595 if (full_stats) {
596 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
597 if (ef100_stat_desc[index].name) {
598 *full_stats++ = stats[index];
599 ++stats_count;
600 }
601 }
602 }
603
604 if (!core_stats)
605 return stats_count;
606
607 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
608 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
609 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
610 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
611 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
612 stats[GENERIC_STAT_rx_nodesc_trunc] +
613 stats[GENERIC_STAT_rx_noskb_drops];
614 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
615 core_stats->rx_length_errors =
616 stats[EF100_STAT_port_rx_gtjumbo] +
617 stats[EF100_STAT_port_rx_length_error];
618 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
619 core_stats->rx_frame_errors =
620 stats[EF100_STAT_port_rx_align_error];
621 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
622 core_stats->rx_errors = (core_stats->rx_length_errors +
623 core_stats->rx_crc_errors +
624 core_stats->rx_frame_errors);
625
626 return stats_count;
627 }
628
ef100_update_stats(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)629 static size_t ef100_update_stats(struct efx_nic *efx,
630 u64 *full_stats,
631 struct rtnl_link_stats64 *core_stats)
632 {
633 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
634 struct ef100_nic_data *nic_data = efx->nic_data;
635 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
636 u64 *stats = nic_data->stats;
637
638 ef100_common_stat_mask(mask);
639 ef100_ethtool_stat_mask(mask);
640
641 if (!mc_stats)
642 return 0;
643
644 efx_nic_copy_stats(efx, mc_stats);
645 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
646 stats, mc_stats, false);
647
648 kfree(mc_stats);
649
650 return ef100_update_stats_common(efx, full_stats, core_stats);
651 }
652
efx_ef100_get_phys_port_id(struct efx_nic * efx,struct netdev_phys_item_id * ppid)653 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
654 struct netdev_phys_item_id *ppid)
655 {
656 struct ef100_nic_data *nic_data = efx->nic_data;
657
658 if (!is_valid_ether_addr(nic_data->port_id))
659 return -EOPNOTSUPP;
660
661 ppid->id_len = ETH_ALEN;
662 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
663
664 return 0;
665 }
666
efx_ef100_irq_test_generate(struct efx_nic * efx)667 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
668 {
669 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
670
671 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
672
673 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
674 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
675 inbuf, sizeof(inbuf), NULL, 0, NULL);
676 }
677
678 #define EFX_EF100_TEST 1
679
efx_ef100_ev_test_generate(struct efx_channel * channel)680 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
681 {
682 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
683 struct efx_nic *efx = channel->efx;
684 efx_qword_t event;
685 int rc;
686
687 EFX_POPULATE_QWORD_2(event,
688 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
689 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
690
691 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
692
693 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
694 * already swapped the data to little-endian order.
695 */
696 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
697 sizeof(efx_qword_t));
698
699 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
700 NULL, 0, NULL);
701 if (rc && (rc != -ENETDOWN))
702 goto fail;
703
704 return;
705
706 fail:
707 WARN_ON(true);
708 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
709 }
710
ef100_check_caps(const struct efx_nic * efx,u8 flag,u32 offset)711 static unsigned int ef100_check_caps(const struct efx_nic *efx,
712 u8 flag, u32 offset)
713 {
714 const struct ef100_nic_data *nic_data = efx->nic_data;
715
716 switch (offset) {
717 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
718 return nic_data->datapath_caps & BIT_ULL(flag);
719 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
720 return nic_data->datapath_caps2 & BIT_ULL(flag);
721 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
722 return nic_data->datapath_caps3 & BIT_ULL(flag);
723 default:
724 return 0;
725 }
726 }
727
efx_ef100_recycle_ring_size(const struct efx_nic * efx)728 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
729 {
730 /* Maximum link speed for Riverhead is 100G */
731 return 10 * EFX_RECYCLE_RING_SIZE_10G;
732 }
733
734 #ifdef CONFIG_SFC_SRIOV
efx_ef100_get_base_mport(struct efx_nic * efx)735 static int efx_ef100_get_base_mport(struct efx_nic *efx)
736 {
737 struct ef100_nic_data *nic_data = efx->nic_data;
738 u32 selector, id;
739 int rc;
740
741 /* Construct mport selector for "physical network port" */
742 efx_mae_mport_wire(efx, &selector);
743 /* Look up actual mport ID */
744 rc = efx_mae_lookup_mport(efx, selector, &id);
745 if (rc)
746 return rc;
747 /* The ID should always fit in 16 bits, because that's how wide the
748 * corresponding fields in the RX prefix & TX override descriptor are
749 */
750 if (id >> 16)
751 netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n",
752 id);
753 nic_data->base_mport = id;
754 nic_data->have_mport = true;
755 return 0;
756 }
757 #endif
758
compare_versions(const char * a,const char * b)759 static int compare_versions(const char *a, const char *b)
760 {
761 int a_major, a_minor, a_point, a_patch;
762 int b_major, b_minor, b_point, b_patch;
763 int a_matched, b_matched;
764
765 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
766 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
767
768 if (a_matched == 4 && b_matched != 4)
769 return +1;
770
771 if (a_matched != 4 && b_matched == 4)
772 return -1;
773
774 if (a_matched != 4 && b_matched != 4)
775 return 0;
776
777 if (a_major != b_major)
778 return a_major - b_major;
779
780 if (a_minor != b_minor)
781 return a_minor - b_minor;
782
783 if (a_point != b_point)
784 return a_point - b_point;
785
786 return a_patch - b_patch;
787 }
788
789 enum ef100_tlv_state_machine {
790 EF100_TLV_TYPE,
791 EF100_TLV_TYPE_CONT,
792 EF100_TLV_LENGTH,
793 EF100_TLV_VALUE
794 };
795
796 struct ef100_tlv_state {
797 enum ef100_tlv_state_machine state;
798 u64 value;
799 u32 value_offset;
800 u16 type;
801 u8 len;
802 };
803
ef100_tlv_feed(struct ef100_tlv_state * state,u8 byte)804 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
805 {
806 switch (state->state) {
807 case EF100_TLV_TYPE:
808 state->type = byte & 0x7f;
809 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
810 : EF100_TLV_LENGTH;
811 /* Clear ready to read in a new entry */
812 state->value = 0;
813 state->value_offset = 0;
814 return 0;
815 case EF100_TLV_TYPE_CONT:
816 state->type |= byte << 7;
817 state->state = EF100_TLV_LENGTH;
818 return 0;
819 case EF100_TLV_LENGTH:
820 state->len = byte;
821 /* We only handle TLVs that fit in a u64 */
822 if (state->len > sizeof(state->value))
823 return -EOPNOTSUPP;
824 /* len may be zero, implying a value of zero */
825 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
826 return 0;
827 case EF100_TLV_VALUE:
828 state->value |= ((u64)byte) << (state->value_offset * 8);
829 state->value_offset++;
830 if (state->value_offset >= state->len)
831 state->state = EF100_TLV_TYPE;
832 return 0;
833 default: /* state machine error, can't happen */
834 WARN_ON_ONCE(1);
835 return -EIO;
836 }
837 }
838
ef100_process_design_param(struct efx_nic * efx,const struct ef100_tlv_state * reader)839 static int ef100_process_design_param(struct efx_nic *efx,
840 const struct ef100_tlv_state *reader)
841 {
842 struct ef100_nic_data *nic_data = efx->nic_data;
843
844 switch (reader->type) {
845 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
846 return 0;
847 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
848 /* Driver doesn't support timestamping yet, so we don't care */
849 return 0;
850 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
851 /* Driver doesn't support unsolicited-event credits yet, so
852 * we don't care
853 */
854 return 0;
855 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
856 /* Driver doesn't manage the NMMU (so we don't care) */
857 return 0;
858 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
859 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
860 * protocol checksum validation
861 */
862 return 0;
863 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
864 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
865 return 0;
866 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
867 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
868 if (!reader->value) {
869 netif_err(efx, probe, efx->net_dev,
870 "TSO_MAX_HDR_NUM_SEGS < 1\n");
871 return -EOPNOTSUPP;
872 }
873 return 0;
874 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
875 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
876 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
877 * EFX_MIN_DMAQ_SIZE, so we just need to check that
878 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
879 * This is very unlikely to fail.
880 */
881 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
882 EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
883 netif_err(efx, probe, efx->net_dev,
884 "%s size granularity is %llu, can't guarantee safety\n",
885 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
886 reader->value);
887 return -EOPNOTSUPP;
888 }
889 return 0;
890 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
891 nic_data->tso_max_payload_len = min_t(u64, reader->value,
892 GSO_LEGACY_MAX_SIZE);
893 netif_set_tso_max_size(efx->net_dev,
894 nic_data->tso_max_payload_len);
895 return 0;
896 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
897 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
898 netif_set_tso_max_segs(efx->net_dev,
899 nic_data->tso_max_payload_num_segs);
900 return 0;
901 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
902 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
903 return 0;
904 case ESE_EF100_DP_GZ_COMPAT:
905 if (reader->value) {
906 netif_err(efx, probe, efx->net_dev,
907 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
908 reader->value);
909 return -EOPNOTSUPP;
910 }
911 return 0;
912 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
913 /* Driver doesn't use mem2mem transfers */
914 return 0;
915 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
916 /* Driver doesn't currently use EVQ_TIMER */
917 return 0;
918 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
919 /* Driver doesn't manage the NMMU (so we don't care) */
920 return 0;
921 case ESE_EF100_DP_GZ_VI_STRIDES:
922 /* We never try to set the VI stride, and we don't rely on
923 * being able to find VIs past VI 0 until after we've learned
924 * the current stride from MC_CMD_GET_CAPABILITIES.
925 * So the value of this shouldn't matter.
926 */
927 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
928 netif_dbg(efx, probe, efx->net_dev,
929 "NIC has other than default VI_STRIDES (mask "
930 "%#llx), early probing might use wrong one\n",
931 reader->value);
932 return 0;
933 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
934 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
935 * care whether it indicates runt or overlength for any given
936 * packet, so we don't care about this parameter.
937 */
938 return 0;
939 default:
940 /* Host interface says "Drivers should ignore design parameters
941 * that they do not recognise."
942 */
943 netif_dbg(efx, probe, efx->net_dev,
944 "Ignoring unrecognised design parameter %u\n",
945 reader->type);
946 return 0;
947 }
948 }
949
ef100_check_design_params(struct efx_nic * efx)950 static int ef100_check_design_params(struct efx_nic *efx)
951 {
952 struct ef100_tlv_state reader = {};
953 u32 total_len, offset = 0;
954 efx_dword_t reg;
955 int rc = 0, i;
956 u32 data;
957
958 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN);
959 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
960 pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len);
961 while (offset < total_len) {
962 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset);
963 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
964 for (i = 0; i < sizeof(data); i++) {
965 rc = ef100_tlv_feed(&reader, data);
966 /* Got a complete value? */
967 if (!rc && reader.state == EF100_TLV_TYPE)
968 rc = ef100_process_design_param(efx, &reader);
969 if (rc)
970 goto out;
971 data >>= 8;
972 offset++;
973 }
974 }
975 /* Check we didn't end halfway through a TLV entry, which could either
976 * mean that the TLV stream is truncated or just that it's corrupted
977 * and our state machine is out of sync.
978 */
979 if (reader.state != EF100_TLV_TYPE) {
980 if (reader.state == EF100_TLV_TYPE_CONT)
981 netif_err(efx, probe, efx->net_dev,
982 "truncated design parameter (incomplete type %u)\n",
983 reader.type);
984 else
985 netif_err(efx, probe, efx->net_dev,
986 "truncated design parameter %u\n",
987 reader.type);
988 rc = -EIO;
989 }
990 out:
991 return rc;
992 }
993
994 /* NIC probe and remove
995 */
ef100_probe_main(struct efx_nic * efx)996 static int ef100_probe_main(struct efx_nic *efx)
997 {
998 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
999 struct ef100_nic_data *nic_data;
1000 char fw_version[32];
1001 u32 priv_mask = 0;
1002 int i, rc;
1003
1004 if (WARN_ON(bar_size == 0))
1005 return -EIO;
1006
1007 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1008 if (!nic_data)
1009 return -ENOMEM;
1010 efx->nic_data = nic_data;
1011 nic_data->efx = efx;
1012 efx->max_vis = EF100_MAX_VIS;
1013
1014 /* Populate design-parameter defaults */
1015 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1016 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1017 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1018 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1019
1020 /* Read design parameters */
1021 rc = ef100_check_design_params(efx);
1022 if (rc) {
1023 pci_err(efx->pci_dev, "Unsupported design parameters\n");
1024 goto fail;
1025 }
1026
1027 /* we assume later that we can copy from this buffer in dwords */
1028 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1029
1030 /* MCDI buffers must be 256 byte aligned. */
1031 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1032 GFP_KERNEL);
1033 if (rc)
1034 goto fail;
1035
1036 /* Get the MC's warm boot count. In case it's rebooting right
1037 * now, be prepared to retry.
1038 */
1039 i = 0;
1040 for (;;) {
1041 rc = ef100_get_warm_boot_count(efx);
1042 if (rc >= 0)
1043 break;
1044 if (++i == 5)
1045 goto fail;
1046 ssleep(1);
1047 }
1048 nic_data->warm_boot_count = rc;
1049
1050 /* In case we're recovering from a crash (kexec), we want to
1051 * cancel any outstanding request by the previous user of this
1052 * function. We send a special message using the least
1053 * significant bits of the 'high' (doorbell) register.
1054 */
1055 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1056
1057 /* Post-IO section. */
1058
1059 rc = efx_mcdi_init(efx);
1060 if (rc)
1061 goto fail;
1062 /* Reset (most) configuration for this function */
1063 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1064 if (rc)
1065 goto fail;
1066 /* Enable event logging */
1067 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1068 if (rc)
1069 goto fail;
1070
1071 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1072 if (rc)
1073 goto fail;
1074
1075 rc = efx_mcdi_port_get_number(efx);
1076 if (rc < 0)
1077 goto fail;
1078 efx->port_num = rc;
1079
1080 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1081 pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version);
1082
1083 rc = efx_mcdi_get_privilege_mask(efx, &priv_mask);
1084 if (rc) /* non-fatal, and priv_mask will still be 0 */
1085 pci_info(efx->pci_dev,
1086 "Failed to get privilege mask from FW, rc %d\n", rc);
1087 nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE);
1088
1089 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1090 pci_info(efx->pci_dev, "Firmware uses old event descriptors\n");
1091 rc = -EINVAL;
1092 goto fail;
1093 }
1094
1095 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1096 pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n");
1097 rc = -EINVAL;
1098 goto fail;
1099 }
1100
1101 return 0;
1102 fail:
1103 return rc;
1104 }
1105
ef100_probe_netdev_pf(struct efx_nic * efx)1106 int ef100_probe_netdev_pf(struct efx_nic *efx)
1107 {
1108 struct ef100_nic_data *nic_data = efx->nic_data;
1109 struct net_device *net_dev = efx->net_dev;
1110 int rc;
1111
1112 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1113 if (rc)
1114 goto fail;
1115 /* Assign MAC address */
1116 eth_hw_addr_set(net_dev, net_dev->perm_addr);
1117 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1118
1119 if (!nic_data->grp_mae)
1120 return 0;
1121
1122 #ifdef CONFIG_SFC_SRIOV
1123 rc = efx_init_struct_tc(efx);
1124 if (rc)
1125 return rc;
1126
1127 rc = efx_ef100_get_base_mport(efx);
1128 if (rc) {
1129 netif_warn(efx, probe, net_dev,
1130 "Failed to probe base mport rc %d; representors will not function\n",
1131 rc);
1132 }
1133
1134 rc = efx_init_tc(efx);
1135 if (rc) {
1136 /* Either we don't have an MAE at all (i.e. legacy v-switching),
1137 * or we do but we failed to probe it. In the latter case, we
1138 * may not have set up default rules, in which case we won't be
1139 * able to pass any traffic. However, we don't fail the probe,
1140 * because the user might need to use the netdevice to apply
1141 * configuration changes to fix whatever's wrong with the MAE.
1142 */
1143 netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n",
1144 rc);
1145 } else {
1146 net_dev->features |= NETIF_F_HW_TC;
1147 efx->fixed_features |= NETIF_F_HW_TC;
1148 }
1149 #endif
1150 return 0;
1151
1152 fail:
1153 return rc;
1154 }
1155
ef100_probe_vf(struct efx_nic * efx)1156 int ef100_probe_vf(struct efx_nic *efx)
1157 {
1158 return ef100_probe_main(efx);
1159 }
1160
ef100_remove(struct efx_nic * efx)1161 void ef100_remove(struct efx_nic *efx)
1162 {
1163 struct ef100_nic_data *nic_data = efx->nic_data;
1164
1165 efx_mcdi_detach(efx);
1166 efx_mcdi_fini(efx);
1167 if (nic_data)
1168 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1169 kfree(nic_data);
1170 efx->nic_data = NULL;
1171 }
1172
1173 /* NIC level access functions
1174 */
1175 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
1176 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
1177 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
1178 NETIF_F_HW_VLAN_CTAG_TX)
1179
1180 const struct efx_nic_type ef100_pf_nic_type = {
1181 .revision = EFX_REV_EF100,
1182 .is_vf = false,
1183 .probe = ef100_probe_main,
1184 .offload_features = EF100_OFFLOAD_FEATURES,
1185 .mcdi_max_ver = 2,
1186 .mcdi_request = ef100_mcdi_request,
1187 .mcdi_poll_response = ef100_mcdi_poll_response,
1188 .mcdi_read_response = ef100_mcdi_read_response,
1189 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1190 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1191 .irq_enable_master = efx_port_dummy_op_void,
1192 .irq_test_generate = efx_ef100_irq_test_generate,
1193 .irq_disable_non_ev = efx_port_dummy_op_void,
1194 .push_irq_moderation = efx_channel_dummy_op_void,
1195 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1196 .map_reset_reason = ef100_map_reset_reason,
1197 .map_reset_flags = ef100_map_reset_flags,
1198 .reset = ef100_reset,
1199
1200 .check_caps = ef100_check_caps,
1201
1202 .ev_probe = ef100_ev_probe,
1203 .ev_init = ef100_ev_init,
1204 .ev_fini = efx_mcdi_ev_fini,
1205 .ev_remove = efx_mcdi_ev_remove,
1206 .irq_handle_msi = ef100_msi_interrupt,
1207 .ev_process = ef100_ev_process,
1208 .ev_read_ack = ef100_ev_read_ack,
1209 .ev_test_generate = efx_ef100_ev_test_generate,
1210 .tx_probe = ef100_tx_probe,
1211 .tx_init = ef100_tx_init,
1212 .tx_write = ef100_tx_write,
1213 .tx_enqueue = ef100_enqueue_skb,
1214 .rx_probe = efx_mcdi_rx_probe,
1215 .rx_init = efx_mcdi_rx_init,
1216 .rx_remove = efx_mcdi_rx_remove,
1217 .rx_write = ef100_rx_write,
1218 .rx_packet = __ef100_rx_packet,
1219 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1220 .fini_dmaq = efx_fini_dmaq,
1221 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1222 .filter_table_probe = ef100_filter_table_up,
1223 .filter_table_restore = efx_mcdi_filter_table_restore,
1224 .filter_table_remove = ef100_filter_table_down,
1225 .filter_insert = efx_mcdi_filter_insert,
1226 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1227 .filter_get_safe = efx_mcdi_filter_get_safe,
1228 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1229 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1230 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1231 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1232 #ifdef CONFIG_RFS_ACCEL
1233 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1234 #endif
1235
1236 .get_phys_port_id = efx_ef100_get_phys_port_id,
1237
1238 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1239 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1240 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1241 .rx_hash_key_size = 40,
1242 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1243 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1244 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
1245 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
1246 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1247 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1248
1249 .reconfigure_mac = ef100_reconfigure_mac,
1250 .reconfigure_port = efx_mcdi_port_reconfigure,
1251 .test_nvram = efx_new_mcdi_nvram_test_all,
1252 .describe_stats = ef100_describe_stats,
1253 .start_stats = efx_mcdi_mac_start_stats,
1254 .update_stats = ef100_update_stats,
1255 .pull_stats = efx_mcdi_mac_pull_stats,
1256 .stop_stats = efx_mcdi_mac_stop_stats,
1257 #ifdef CONFIG_SFC_SRIOV
1258 .sriov_configure = efx_ef100_sriov_configure,
1259 #endif
1260
1261 /* Per-type bar/size configuration not used on ef100. Location of
1262 * registers is defined by extended capabilities.
1263 */
1264 .mem_bar = NULL,
1265 .mem_map_size = NULL,
1266
1267 };
1268
1269 const struct efx_nic_type ef100_vf_nic_type = {
1270 .revision = EFX_REV_EF100,
1271 .is_vf = true,
1272 .probe = ef100_probe_vf,
1273 .offload_features = EF100_OFFLOAD_FEATURES,
1274 .mcdi_max_ver = 2,
1275 .mcdi_request = ef100_mcdi_request,
1276 .mcdi_poll_response = ef100_mcdi_poll_response,
1277 .mcdi_read_response = ef100_mcdi_read_response,
1278 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1279 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1280 .irq_enable_master = efx_port_dummy_op_void,
1281 .irq_test_generate = efx_ef100_irq_test_generate,
1282 .irq_disable_non_ev = efx_port_dummy_op_void,
1283 .push_irq_moderation = efx_channel_dummy_op_void,
1284 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1285 .map_reset_reason = ef100_map_reset_reason,
1286 .map_reset_flags = ef100_map_reset_flags,
1287 .reset = ef100_reset,
1288 .check_caps = ef100_check_caps,
1289 .ev_probe = ef100_ev_probe,
1290 .ev_init = ef100_ev_init,
1291 .ev_fini = efx_mcdi_ev_fini,
1292 .ev_remove = efx_mcdi_ev_remove,
1293 .irq_handle_msi = ef100_msi_interrupt,
1294 .ev_process = ef100_ev_process,
1295 .ev_read_ack = ef100_ev_read_ack,
1296 .ev_test_generate = efx_ef100_ev_test_generate,
1297 .tx_probe = ef100_tx_probe,
1298 .tx_init = ef100_tx_init,
1299 .tx_write = ef100_tx_write,
1300 .tx_enqueue = ef100_enqueue_skb,
1301 .rx_probe = efx_mcdi_rx_probe,
1302 .rx_init = efx_mcdi_rx_init,
1303 .rx_remove = efx_mcdi_rx_remove,
1304 .rx_write = ef100_rx_write,
1305 .rx_packet = __ef100_rx_packet,
1306 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1307 .fini_dmaq = efx_fini_dmaq,
1308 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1309 .filter_table_probe = ef100_filter_table_up,
1310 .filter_table_restore = efx_mcdi_filter_table_restore,
1311 .filter_table_remove = ef100_filter_table_down,
1312 .filter_insert = efx_mcdi_filter_insert,
1313 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1314 .filter_get_safe = efx_mcdi_filter_get_safe,
1315 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1316 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1317 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1318 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1319 #ifdef CONFIG_RFS_ACCEL
1320 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1321 #endif
1322
1323 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1324 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1325 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1326 .rx_hash_key_size = 40,
1327 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1328 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1329 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1330 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1331
1332 .reconfigure_mac = ef100_reconfigure_mac,
1333 .test_nvram = efx_new_mcdi_nvram_test_all,
1334 .describe_stats = ef100_describe_stats,
1335 .start_stats = efx_mcdi_mac_start_stats,
1336 .update_stats = ef100_update_stats,
1337 .pull_stats = efx_mcdi_mac_pull_stats,
1338 .stop_stats = efx_mcdi_mac_stop_stats,
1339
1340 .mem_bar = NULL,
1341 .mem_map_size = NULL,
1342
1343 };
1344