1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2019 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include "net_driver.h"
12 #include "ef100_rx.h"
13 #include "rx_common.h"
14 #include "efx.h"
15 #include "nic_common.h"
16 #include "mcdi_functions.h"
17 #include "ef100_regs.h"
18 #include "ef100_nic.h"
19 #include "io.h"
20
21 /* Get the value of a field in the RX prefix */
22 #define PREFIX_OFFSET_W(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN / 32)
23 #define PREFIX_OFFSET_B(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN % 32)
24 #define PREFIX_WIDTH_MASK(_f) ((1UL << ESF_GZ_RX_PREFIX_ ## _f ## _WIDTH) - 1)
25 #define PREFIX_WORD(_p, _f) le32_to_cpu((__force __le32)(_p)[PREFIX_OFFSET_W(_f)])
26 #define PREFIX_FIELD(_p, _f) ((PREFIX_WORD(_p, _f) >> PREFIX_OFFSET_B(_f)) & \
27 PREFIX_WIDTH_MASK(_f))
28
29 #define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_LBN \
30 (ESF_GZ_RX_PREFIX_CLASS_LBN + ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN)
31 #define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_WIDTH \
32 ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH
33
ef100_rx_buf_hash_valid(const u8 * prefix)34 bool ef100_rx_buf_hash_valid(const u8 *prefix)
35 {
36 return PREFIX_FIELD(prefix, RSS_HASH_VALID);
37 }
38
ef100_has_fcs_error(struct efx_channel * channel,u32 * prefix)39 static bool ef100_has_fcs_error(struct efx_channel *channel, u32 *prefix)
40 {
41 u16 rxclass;
42 u8 l2status;
43
44 rxclass = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, CLASS));
45 l2status = PREFIX_FIELD(&rxclass, HCLASS_L2_STATUS);
46
47 if (likely(l2status == ESE_GZ_RH_HCLASS_L2_STATUS_OK))
48 /* Everything is ok */
49 return false;
50
51 if (l2status == ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR)
52 channel->n_rx_eth_crc_err++;
53 return true;
54 }
55
__ef100_rx_packet(struct efx_channel * channel)56 void __ef100_rx_packet(struct efx_channel *channel)
57 {
58 struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
59 struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue,
60 channel->rx_pkt_index);
61 struct efx_nic *efx = channel->efx;
62 struct ef100_nic_data *nic_data;
63 u8 *eh = efx_rx_buf_va(rx_buf);
64 __wsum csum = 0;
65 u16 ing_port;
66 u32 *prefix;
67
68 prefix = (u32 *)(eh - ESE_GZ_RX_PKT_PREFIX_LEN);
69
70 if (ef100_has_fcs_error(channel, prefix) &&
71 unlikely(!(efx->net_dev->features & NETIF_F_RXALL)))
72 goto out;
73
74 rx_buf->len = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, LENGTH));
75 if (rx_buf->len <= sizeof(struct ethhdr)) {
76 if (net_ratelimit())
77 netif_err(channel->efx, rx_err, channel->efx->net_dev,
78 "RX packet too small (%d)\n", rx_buf->len);
79 ++channel->n_rx_frm_trunc;
80 goto out;
81 }
82
83 ing_port = le16_to_cpu((__force __le16) PREFIX_FIELD(prefix, INGRESS_MPORT));
84
85 nic_data = efx->nic_data;
86
87 if (nic_data->have_mport && ing_port != nic_data->base_mport) {
88 #ifdef CONFIG_SFC_SRIOV
89 struct efx_rep *efv;
90
91 rcu_read_lock();
92 efv = efx_ef100_find_rep_by_mport(efx, ing_port);
93 if (efv) {
94 if (efv->net_dev->flags & IFF_UP)
95 efx_ef100_rep_rx_packet(efv, rx_buf);
96 rcu_read_unlock();
97 /* Representor Rx doesn't care about PF Rx buffer
98 * ownership, it just makes a copy. So, we are done
99 * with the Rx buffer from PF point of view and should
100 * free it.
101 */
102 goto free_rx_buffer;
103 }
104 rcu_read_unlock();
105 #endif
106 if (net_ratelimit())
107 netif_warn(efx, drv, efx->net_dev,
108 "Unrecognised ing_port %04x (base %04x), dropping\n",
109 ing_port, nic_data->base_mport);
110 channel->n_rx_mport_bad++;
111 goto free_rx_buffer;
112 }
113
114 if (likely(efx->net_dev->features & NETIF_F_RXCSUM)) {
115 if (PREFIX_FIELD(prefix, NT_OR_INNER_L3_CLASS) == 1) {
116 ++channel->n_rx_ip_hdr_chksum_err;
117 } else {
118 u16 sum = be16_to_cpu((__force __be16)PREFIX_FIELD(prefix, CSUM_FRAME));
119
120 csum = (__force __wsum) sum;
121 }
122 }
123
124 if (channel->type->receive_skb) {
125 /* no support for special channels yet, so just discard */
126 WARN_ON_ONCE(1);
127 goto free_rx_buffer;
128 }
129
130 efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh, csum);
131 goto out;
132
133 free_rx_buffer:
134 efx_free_rx_buffers(rx_queue, rx_buf, 1);
135 out:
136 channel->rx_pkt_n_frags = 0;
137 }
138
ef100_rx_packet(struct efx_rx_queue * rx_queue,unsigned int index)139 static void ef100_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index)
140 {
141 struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue, index);
142 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
143 struct efx_nic *efx = rx_queue->efx;
144
145 ++rx_queue->rx_packets;
146
147 netif_vdbg(efx, rx_status, efx->net_dev,
148 "RX queue %d received id %x\n",
149 efx_rx_queue_index(rx_queue), index);
150
151 efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
152
153 prefetch(efx_rx_buf_va(rx_buf));
154
155 rx_buf->page_offset += efx->rx_prefix_size;
156
157 efx_recycle_rx_pages(channel, rx_buf, 1);
158
159 efx_rx_flush_packet(channel);
160 channel->rx_pkt_n_frags = 1;
161 channel->rx_pkt_index = index;
162 }
163
efx_ef100_ev_rx(struct efx_channel * channel,const efx_qword_t * p_event)164 void efx_ef100_ev_rx(struct efx_channel *channel, const efx_qword_t *p_event)
165 {
166 struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
167 unsigned int n_packets =
168 EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_NUM_PKT);
169 int i;
170
171 WARN_ON_ONCE(!n_packets);
172 if (n_packets > 1)
173 ++channel->n_rx_merge_events;
174
175 channel->irq_mod_score += 2 * n_packets;
176
177 for (i = 0; i < n_packets; ++i) {
178 ef100_rx_packet(rx_queue,
179 rx_queue->removed_count & rx_queue->ptr_mask);
180 ++rx_queue->removed_count;
181 }
182 }
183
ef100_rx_write(struct efx_rx_queue * rx_queue)184 void ef100_rx_write(struct efx_rx_queue *rx_queue)
185 {
186 struct efx_rx_buffer *rx_buf;
187 unsigned int idx;
188 efx_qword_t *rxd;
189 efx_dword_t rxdb;
190
191 while (rx_queue->notified_count != rx_queue->added_count) {
192 idx = rx_queue->notified_count & rx_queue->ptr_mask;
193 rx_buf = efx_rx_buffer(rx_queue, idx);
194 rxd = efx_rx_desc(rx_queue, idx);
195
196 EFX_POPULATE_QWORD_1(*rxd, ESF_GZ_RX_BUF_ADDR, rx_buf->dma_addr);
197
198 ++rx_queue->notified_count;
199 }
200
201 wmb();
202 EFX_POPULATE_DWORD_1(rxdb, ERF_GZ_RX_RING_PIDX,
203 rx_queue->added_count & rx_queue->ptr_mask);
204 efx_writed_page(rx_queue->efx, &rxdb,
205 ER_GZ_RX_RING_DOORBELL, efx_rx_queue_index(rx_queue));
206 }
207