1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6 #include <linux/android_kabi.h>
7
8 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
9 #define MAX_NR_DEVFNS 256
10
11 #define PCI_FIND_CAP_TTL 48
12
13 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14
15 extern const unsigned char pcie_link_speed[];
16 extern bool pci_early_dump;
17
18 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
19 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20
21 /* Functions internal to the PCI core code */
22
23 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
24 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
25 void pci_cleanup_rom(struct pci_dev *dev);
26 #ifdef CONFIG_DMI
27 extern const struct attribute_group pci_dev_smbios_attr_group;
28 #endif
29
30 enum pci_mmap_api {
31 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
32 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
33 };
34 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
35 enum pci_mmap_api mmap_api);
36
37 bool pci_reset_supported(struct pci_dev *dev);
38 void pci_init_reset_methods(struct pci_dev *dev);
39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
40 int pci_bus_error_reset(struct pci_dev *dev);
41
42 struct pci_cap_saved_data {
43 u16 cap_nr;
44 bool cap_extended;
45 unsigned int size;
46 u32 data[];
47 };
48
49 struct pci_cap_saved_state {
50 struct hlist_node next;
51 struct pci_cap_saved_data cap;
52 };
53
54 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
55 void pci_free_cap_save_buffers(struct pci_dev *dev);
56 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
57 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
58 u16 cap, unsigned int size);
59 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
60 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
61 u16 cap);
62
63 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
64 #define PCI_PM_D3HOT_WAIT 10 /* msec */
65 #define PCI_PM_D3COLD_WAIT 100 /* msec */
66
67 /*
68 * Following exit from Conventional Reset, devices must be ready within 1 sec
69 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 * Reset (PCIe r6.0 sec 5.8).
71 */
72 #define PCI_RESET_WAIT 1000 /* msec */
73 /*
74 * Devices may extend the 1 sec period through Request Retry Status completions
75 * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
76 * ought to be enough for any device to become responsive.
77 */
78 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
79
80 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
81 void pci_refresh_power_state(struct pci_dev *dev);
82 int pci_power_up(struct pci_dev *dev);
83 void pci_disable_enabled_device(struct pci_dev *dev);
84 int pci_finish_runtime_suspend(struct pci_dev *dev);
85 void pcie_clear_device_status(struct pci_dev *dev);
86 void pcie_clear_root_pme_status(struct pci_dev *dev);
87 bool pci_check_pme_status(struct pci_dev *dev);
88 void pci_pme_wakeup_bus(struct pci_bus *bus);
89 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
90 void pci_pme_restore(struct pci_dev *dev);
91 bool pci_dev_need_resume(struct pci_dev *dev);
92 void pci_dev_adjust_pme(struct pci_dev *dev);
93 void pci_dev_complete_resume(struct pci_dev *pci_dev);
94 void pci_config_pm_runtime_get(struct pci_dev *dev);
95 void pci_config_pm_runtime_put(struct pci_dev *dev);
96 void pci_pm_init(struct pci_dev *dev);
97 void pci_ea_init(struct pci_dev *dev);
98 void pci_msi_init(struct pci_dev *dev);
99 void pci_msix_init(struct pci_dev *dev);
100 bool pci_bridge_d3_possible(struct pci_dev *dev);
101 void pci_bridge_d3_update(struct pci_dev *dev);
102 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
103 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
104 int timeout);
105
pci_wakeup_event(struct pci_dev * dev)106 static inline void pci_wakeup_event(struct pci_dev *dev)
107 {
108 /* Wait 100 ms before the system can be put into a sleep state. */
109 pm_wakeup_event(&dev->dev, 100);
110 }
111
pci_has_subordinate(struct pci_dev * pci_dev)112 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
113 {
114 return !!(pci_dev->subordinate);
115 }
116
pci_power_manageable(struct pci_dev * pci_dev)117 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
118 {
119 /*
120 * Currently we allow normal PCI devices and PCI bridges transition
121 * into D3 if their bridge_d3 is set.
122 */
123 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
124 }
125
pcie_downstream_port(const struct pci_dev * dev)126 static inline bool pcie_downstream_port(const struct pci_dev *dev)
127 {
128 int type = pci_pcie_type(dev);
129
130 return type == PCI_EXP_TYPE_ROOT_PORT ||
131 type == PCI_EXP_TYPE_DOWNSTREAM ||
132 type == PCI_EXP_TYPE_PCIE_BRIDGE;
133 }
134
135 void pci_vpd_init(struct pci_dev *dev);
136 void pci_vpd_release(struct pci_dev *dev);
137 extern const struct attribute_group pci_dev_vpd_attr_group;
138
139 /* PCI Virtual Channel */
140 int pci_save_vc_state(struct pci_dev *dev);
141 void pci_restore_vc_state(struct pci_dev *dev);
142 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
143
144 /* PCI /proc functions */
145 #ifdef CONFIG_PROC_FS
146 int pci_proc_attach_device(struct pci_dev *dev);
147 int pci_proc_detach_device(struct pci_dev *dev);
148 int pci_proc_detach_bus(struct pci_bus *bus);
149 #else
pci_proc_attach_device(struct pci_dev * dev)150 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)151 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)152 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
153 #endif
154
155 /* Functions for PCI Hotplug drivers to use */
156 int pci_hp_add_bridge(struct pci_dev *dev);
157
158 #ifdef HAVE_PCI_LEGACY
159 void pci_create_legacy_files(struct pci_bus *bus);
160 void pci_remove_legacy_files(struct pci_bus *bus);
161 #else
pci_create_legacy_files(struct pci_bus * bus)162 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
pci_remove_legacy_files(struct pci_bus * bus)163 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
164 #endif
165
166 /* Lock for read/write access to pci device and bus lists */
167 extern struct rw_semaphore pci_bus_sem;
168 extern struct mutex pci_slot_mutex;
169
170 extern raw_spinlock_t pci_lock;
171
172 extern unsigned int pci_pm_d3hot_delay;
173
174 #ifdef CONFIG_PCI_MSI
175 void pci_no_msi(void);
176 #else
pci_no_msi(void)177 static inline void pci_no_msi(void) { }
178 #endif
179
180 void pci_realloc_get_opt(char *);
181
pci_no_d1d2(struct pci_dev * dev)182 static inline int pci_no_d1d2(struct pci_dev *dev)
183 {
184 unsigned int parent_dstates = 0;
185
186 if (dev->bus->self)
187 parent_dstates = dev->bus->self->no_d1d2;
188 return (dev->no_d1d2 || parent_dstates);
189
190 }
191 extern const struct attribute_group *pci_dev_groups[];
192 extern const struct attribute_group *pcibus_groups[];
193 extern const struct device_type pci_dev_type;
194 extern const struct attribute_group *pci_bus_groups[];
195
196 extern unsigned long pci_hotplug_io_size;
197 extern unsigned long pci_hotplug_mmio_size;
198 extern unsigned long pci_hotplug_mmio_pref_size;
199 extern unsigned long pci_hotplug_bus_size;
200
201 /**
202 * pci_match_one_device - Tell if a PCI device structure has a matching
203 * PCI device id structure
204 * @id: single PCI device id structure to match
205 * @dev: the PCI device structure to match against
206 *
207 * Returns the matching pci_device_id structure or %NULL if there is no match.
208 */
209 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)210 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
211 {
212 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
213 (id->device == PCI_ANY_ID || id->device == dev->device) &&
214 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
215 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
216 !((id->class ^ dev->class) & id->class_mask))
217 return id;
218 return NULL;
219 }
220
221 /* PCI slot sysfs helper code */
222 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
223
224 extern struct kset *pci_slots_kset;
225
226 struct pci_slot_attribute {
227 struct attribute attr;
228 ssize_t (*show)(struct pci_slot *, char *);
229 ssize_t (*store)(struct pci_slot *, const char *, size_t);
230 };
231 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
232
233 enum pci_bar_type {
234 pci_bar_unknown, /* Standard PCI BAR probe */
235 pci_bar_io, /* An I/O port BAR */
236 pci_bar_mem32, /* A 32-bit memory BAR */
237 pci_bar_mem64, /* A 64-bit memory BAR */
238 };
239
240 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
241 void pci_put_host_bridge_device(struct device *dev);
242
243 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
244 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
245 int crs_timeout);
246 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
247 int crs_timeout);
248 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
249
250 int pci_setup_device(struct pci_dev *dev);
251 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
252 struct resource *res, unsigned int reg);
253 void pci_configure_ari(struct pci_dev *dev);
254 void __pci_bus_size_bridges(struct pci_bus *bus,
255 struct list_head *realloc_head);
256 void __pci_bus_assign_resources(const struct pci_bus *bus,
257 struct list_head *realloc_head,
258 struct list_head *fail_head);
259 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
260
261 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
262 void pci_disable_bridge_window(struct pci_dev *dev);
263 struct pci_bus *pci_bus_get(struct pci_bus *bus);
264 void pci_bus_put(struct pci_bus *bus);
265
266 /* PCIe link information from Link Capabilities 2 */
267 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
268 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
269 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
270 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
271 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
272 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
273 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
274 PCI_SPEED_UNKNOWN)
275
276 /* PCIe speed to Mb/s reduced by encoding overhead */
277 #define PCIE_SPEED2MBS_ENC(speed) \
278 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
279 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
280 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
281 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
282 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
283 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
284 0)
285
286 const char *pci_speed_string(enum pci_bus_speed speed);
287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
289 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
290 enum pcie_link_width *width);
291 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
292 void pcie_report_downtraining(struct pci_dev *dev);
293 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
294
295 /* Single Root I/O Virtualization */
296 struct pci_sriov {
297 int pos; /* Capability position */
298 int nres; /* Number of resources */
299 u32 cap; /* SR-IOV Capabilities */
300 u16 ctrl; /* SR-IOV Control */
301 u16 total_VFs; /* Total VFs associated with the PF */
302 u16 initial_VFs; /* Initial VFs associated with the PF */
303 u16 num_VFs; /* Number of VFs available */
304 u16 offset; /* First VF Routing ID offset */
305 u16 stride; /* Following VF stride */
306 u16 vf_device; /* VF device ID */
307 u32 pgsz; /* Page size for BAR alignment */
308 u8 link; /* Function Dependency Link */
309 u8 max_VF_buses; /* Max buses consumed by VFs */
310 u16 driver_max_VFs; /* Max num VFs driver supports */
311 struct pci_dev *dev; /* Lowest numbered PF */
312 struct pci_dev *self; /* This PF */
313 u32 class; /* VF device */
314 u8 hdr_type; /* VF header type */
315 u16 subsystem_vendor; /* VF subsystem vendor */
316 u16 subsystem_device; /* VF subsystem device */
317 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
318 bool drivers_autoprobe; /* Auto probing of VFs by driver */
319
320 ANDROID_KABI_RESERVE(1);
321 ANDROID_KABI_RESERVE(2);
322 ANDROID_KABI_RESERVE(3);
323 ANDROID_KABI_RESERVE(4);
324 };
325
326 /**
327 * pci_dev_set_io_state - Set the new error state if possible.
328 *
329 * @dev: PCI device to set new error_state
330 * @new: the state we want dev to be in
331 *
332 * If the device is experiencing perm_failure, it has to remain in that state.
333 * Any other transition is allowed.
334 *
335 * Returns true if state has been changed to the requested state.
336 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)337 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
338 pci_channel_state_t new)
339 {
340 pci_channel_state_t old;
341
342 switch (new) {
343 case pci_channel_io_perm_failure:
344 xchg(&dev->error_state, pci_channel_io_perm_failure);
345 return true;
346 case pci_channel_io_frozen:
347 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
348 pci_channel_io_frozen);
349 return old != pci_channel_io_perm_failure;
350 case pci_channel_io_normal:
351 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
352 pci_channel_io_normal);
353 return old != pci_channel_io_perm_failure;
354 default:
355 return false;
356 }
357 }
358
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)359 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
360 {
361 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
362
363 return 0;
364 }
365
pci_dev_is_disconnected(const struct pci_dev * dev)366 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
367 {
368 return dev->error_state == pci_channel_io_perm_failure;
369 }
370
371 /* pci_dev priv_flags */
372 #define PCI_DEV_ADDED 0
373 #define PCI_DPC_RECOVERED 1
374 #define PCI_DPC_RECOVERING 2
375
pci_dev_assign_added(struct pci_dev * dev,bool added)376 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
377 {
378 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
379 }
380
pci_dev_is_added(const struct pci_dev * dev)381 static inline bool pci_dev_is_added(const struct pci_dev *dev)
382 {
383 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
384 }
385
386 #ifdef CONFIG_PCIEAER
387 #include <linux/aer.h>
388
389 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
390
391 struct aer_err_info {
392 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
393 int error_dev_num;
394
395 unsigned int id:16;
396
397 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
398 unsigned int __pad1:5;
399 unsigned int multi_error_valid:1;
400
401 unsigned int first_error:5;
402 unsigned int __pad2:2;
403 unsigned int tlp_header_valid:1;
404
405 unsigned int status; /* COR/UNCOR Error Status */
406 unsigned int mask; /* COR/UNCOR Error Mask */
407 struct aer_header_log_regs tlp; /* TLP Header */
408 };
409
410 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
411 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
412 #endif /* CONFIG_PCIEAER */
413
414 #ifdef CONFIG_PCIEPORTBUS
415 /* Cached RCEC Endpoint Association */
416 struct rcec_ea {
417 u8 nextbusn;
418 u8 lastbusn;
419 u32 bitmap;
420 };
421 #endif
422
423 #ifdef CONFIG_PCIE_DPC
424 void pci_save_dpc_state(struct pci_dev *dev);
425 void pci_restore_dpc_state(struct pci_dev *dev);
426 void pci_dpc_init(struct pci_dev *pdev);
427 void dpc_process_error(struct pci_dev *pdev);
428 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
429 bool pci_dpc_recovered(struct pci_dev *pdev);
430 #else
pci_save_dpc_state(struct pci_dev * dev)431 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
pci_restore_dpc_state(struct pci_dev * dev)432 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
pci_dpc_init(struct pci_dev * pdev)433 static inline void pci_dpc_init(struct pci_dev *pdev) {}
pci_dpc_recovered(struct pci_dev * pdev)434 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
435 #endif
436
437 #ifdef CONFIG_PCIEPORTBUS
438 void pci_rcec_init(struct pci_dev *dev);
439 void pci_rcec_exit(struct pci_dev *dev);
440 void pcie_link_rcec(struct pci_dev *rcec);
441 void pcie_walk_rcec(struct pci_dev *rcec,
442 int (*cb)(struct pci_dev *, void *),
443 void *userdata);
444 #else
pci_rcec_init(struct pci_dev * dev)445 static inline void pci_rcec_init(struct pci_dev *dev) {}
pci_rcec_exit(struct pci_dev * dev)446 static inline void pci_rcec_exit(struct pci_dev *dev) {}
pcie_link_rcec(struct pci_dev * rcec)447 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)448 static inline void pcie_walk_rcec(struct pci_dev *rcec,
449 int (*cb)(struct pci_dev *, void *),
450 void *userdata) {}
451 #endif
452
453 #ifdef CONFIG_PCI_ATS
454 /* Address Translation Service */
455 void pci_ats_init(struct pci_dev *dev);
456 void pci_restore_ats_state(struct pci_dev *dev);
457 #else
pci_ats_init(struct pci_dev * d)458 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)459 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
460 #endif /* CONFIG_PCI_ATS */
461
462 #ifdef CONFIG_PCI_PRI
463 void pci_pri_init(struct pci_dev *dev);
464 void pci_restore_pri_state(struct pci_dev *pdev);
465 #else
pci_pri_init(struct pci_dev * dev)466 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)467 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
468 #endif
469
470 #ifdef CONFIG_PCI_PASID
471 void pci_pasid_init(struct pci_dev *dev);
472 void pci_restore_pasid_state(struct pci_dev *pdev);
473 #else
pci_pasid_init(struct pci_dev * dev)474 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)475 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
476 #endif
477
478 #ifdef CONFIG_PCI_IOV
479 int pci_iov_init(struct pci_dev *dev);
480 void pci_iov_release(struct pci_dev *dev);
481 void pci_iov_remove(struct pci_dev *dev);
482 void pci_iov_update_resource(struct pci_dev *dev, int resno);
483 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
484 void pci_restore_iov_state(struct pci_dev *dev);
485 int pci_iov_bus_range(struct pci_bus *bus);
486 extern const struct attribute_group sriov_pf_dev_attr_group;
487 extern const struct attribute_group sriov_vf_dev_attr_group;
488 #else
pci_iov_init(struct pci_dev * dev)489 static inline int pci_iov_init(struct pci_dev *dev)
490 {
491 return -ENODEV;
492 }
pci_iov_release(struct pci_dev * dev)493 static inline void pci_iov_release(struct pci_dev *dev)
494
495 {
496 }
pci_iov_remove(struct pci_dev * dev)497 static inline void pci_iov_remove(struct pci_dev *dev)
498 {
499 }
pci_restore_iov_state(struct pci_dev * dev)500 static inline void pci_restore_iov_state(struct pci_dev *dev)
501 {
502 }
pci_iov_bus_range(struct pci_bus * bus)503 static inline int pci_iov_bus_range(struct pci_bus *bus)
504 {
505 return 0;
506 }
507
508 #endif /* CONFIG_PCI_IOV */
509
510 #ifdef CONFIG_PCIE_PTM
511 void pci_ptm_init(struct pci_dev *dev);
512 void pci_save_ptm_state(struct pci_dev *dev);
513 void pci_restore_ptm_state(struct pci_dev *dev);
514 void pci_suspend_ptm(struct pci_dev *dev);
515 void pci_resume_ptm(struct pci_dev *dev);
516 #else
pci_ptm_init(struct pci_dev * dev)517 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_save_ptm_state(struct pci_dev * dev)518 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)519 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_suspend_ptm(struct pci_dev * dev)520 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
pci_resume_ptm(struct pci_dev * dev)521 static inline void pci_resume_ptm(struct pci_dev *dev) { }
522 #endif
523
524 unsigned long pci_cardbus_resource_alignment(struct resource *);
525
pci_resource_alignment(struct pci_dev * dev,struct resource * res)526 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
527 struct resource *res)
528 {
529 #ifdef CONFIG_PCI_IOV
530 int resno = res - dev->resource;
531
532 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
533 return pci_sriov_resource_alignment(dev, resno);
534 #endif
535 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
536 return pci_cardbus_resource_alignment(res);
537 return resource_alignment(res);
538 }
539
540 void pci_acs_init(struct pci_dev *dev);
541 #ifdef CONFIG_PCI_QUIRKS
542 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
543 int pci_dev_specific_enable_acs(struct pci_dev *dev);
544 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
545 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)546 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
547 u16 acs_flags)
548 {
549 return -ENOTTY;
550 }
pci_dev_specific_enable_acs(struct pci_dev * dev)551 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
552 {
553 return -ENOTTY;
554 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)555 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
556 {
557 return -ENOTTY;
558 }
559 #endif
560
561 /* PCI error reporting and recovery */
562 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
563 pci_channel_state_t state,
564 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
565
566 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
567 #ifdef CONFIG_PCIEASPM
568 void pcie_aspm_init_link_state(struct pci_dev *pdev);
569 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
570 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
571 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
572 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)573 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)574 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev)575 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)576 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
577 #endif
578
579 #ifdef CONFIG_PCIE_ECRC
580 void pcie_set_ecrc_checking(struct pci_dev *dev);
581 void pcie_ecrc_get_policy(char *str);
582 #else
pcie_set_ecrc_checking(struct pci_dev * dev)583 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)584 static inline void pcie_ecrc_get_policy(char *str) { }
585 #endif
586
587 struct pci_dev_reset_methods {
588 u16 vendor;
589 u16 device;
590 int (*reset)(struct pci_dev *dev, bool probe);
591 };
592
593 struct pci_reset_fn_method {
594 int (*reset_fn)(struct pci_dev *pdev, bool probe);
595 char *name;
596 };
597
598 #ifdef CONFIG_PCI_QUIRKS
599 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
600 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)601 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
602 {
603 return -ENOTTY;
604 }
605 #endif
606
607 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
608 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
609 struct resource *res);
610 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)611 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
612 u16 segment, struct resource *res)
613 {
614 return -ENODEV;
615 }
616 #endif
617
618 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
619 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)620 static inline u64 pci_rebar_size_to_bytes(int size)
621 {
622 return 1ULL << (size + 20);
623 }
624
625 struct device_node;
626
627 #ifdef CONFIG_OF
628 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
629 int of_get_pci_domain_nr(struct device_node *node);
630 int of_pci_get_max_link_speed(struct device_node *node);
631 u32 of_pci_get_slot_power_limit(struct device_node *node,
632 u8 *slot_power_limit_value,
633 u8 *slot_power_limit_scale);
634 void pci_set_of_node(struct pci_dev *dev);
635 void pci_release_of_node(struct pci_dev *dev);
636 void pci_set_bus_of_node(struct pci_bus *bus);
637 void pci_release_bus_of_node(struct pci_bus *bus);
638
639 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
640
641 #else
642 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)643 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
644 {
645 return -EINVAL;
646 }
647
648 static inline int
of_get_pci_domain_nr(struct device_node * node)649 of_get_pci_domain_nr(struct device_node *node)
650 {
651 return -1;
652 }
653
654 static inline int
of_pci_get_max_link_speed(struct device_node * node)655 of_pci_get_max_link_speed(struct device_node *node)
656 {
657 return -EINVAL;
658 }
659
660 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)661 of_pci_get_slot_power_limit(struct device_node *node,
662 u8 *slot_power_limit_value,
663 u8 *slot_power_limit_scale)
664 {
665 if (slot_power_limit_value)
666 *slot_power_limit_value = 0;
667 if (slot_power_limit_scale)
668 *slot_power_limit_scale = 0;
669 return 0;
670 }
671
pci_set_of_node(struct pci_dev * dev)672 static inline void pci_set_of_node(struct pci_dev *dev) { }
pci_release_of_node(struct pci_dev * dev)673 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)674 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)675 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
676
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)677 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
678 {
679 return 0;
680 }
681
682 #endif /* CONFIG_OF */
683
684 #ifdef CONFIG_PCIEAER
685 void pci_no_aer(void);
686 void pci_aer_init(struct pci_dev *dev);
687 void pci_aer_exit(struct pci_dev *dev);
688 extern const struct attribute_group aer_stats_attr_group;
689 void pci_aer_clear_fatal_status(struct pci_dev *dev);
690 int pci_aer_clear_status(struct pci_dev *dev);
691 int pci_aer_raw_clear_status(struct pci_dev *dev);
692 #else
pci_no_aer(void)693 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)694 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)695 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)696 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)697 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)698 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
699 #endif
700
701 #ifdef CONFIG_ACPI
702 int pci_acpi_program_hp_params(struct pci_dev *dev);
703 extern const struct attribute_group pci_dev_acpi_attr_group;
704 void pci_set_acpi_fwnode(struct pci_dev *dev);
705 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
706 bool acpi_pci_power_manageable(struct pci_dev *dev);
707 bool acpi_pci_bridge_d3(struct pci_dev *dev);
708 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
709 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
710 void acpi_pci_refresh_power_state(struct pci_dev *dev);
711 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
712 bool acpi_pci_need_resume(struct pci_dev *dev);
713 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
714 #else
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)715 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
716 {
717 return -ENOTTY;
718 }
pci_set_acpi_fwnode(struct pci_dev * dev)719 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
pci_acpi_program_hp_params(struct pci_dev * dev)720 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
721 {
722 return -ENODEV;
723 }
acpi_pci_power_manageable(struct pci_dev * dev)724 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
725 {
726 return false;
727 }
acpi_pci_bridge_d3(struct pci_dev * dev)728 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
729 {
730 return false;
731 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)732 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
733 {
734 return -ENODEV;
735 }
acpi_pci_get_power_state(struct pci_dev * dev)736 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
737 {
738 return PCI_UNKNOWN;
739 }
acpi_pci_refresh_power_state(struct pci_dev * dev)740 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
acpi_pci_wakeup(struct pci_dev * dev,bool enable)741 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
742 {
743 return -ENODEV;
744 }
acpi_pci_need_resume(struct pci_dev * dev)745 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
746 {
747 return false;
748 }
acpi_pci_choose_state(struct pci_dev * pdev)749 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
750 {
751 return PCI_POWER_ERROR;
752 }
753 #endif
754
755 #ifdef CONFIG_PCIEASPM
756 extern const struct attribute_group aspm_ctrl_attr_group;
757 #endif
758
759 extern const struct attribute_group pci_dev_reset_method_attr_group;
760
761 #ifdef CONFIG_X86_INTEL_MID
762 bool pci_use_mid_pm(void);
763 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
764 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
765 #else
pci_use_mid_pm(void)766 static inline bool pci_use_mid_pm(void)
767 {
768 return false;
769 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)770 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
771 {
772 return -ENODEV;
773 }
mid_pci_get_power_state(struct pci_dev * pdev)774 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
775 {
776 return PCI_UNKNOWN;
777 }
778 #endif
779
780 /*
781 * Config Address for PCI Configuration Mechanism #1
782 *
783 * See PCI Local Bus Specification, Revision 3.0,
784 * Section 3.2.2.3.2, Figure 3-2, p. 50.
785 */
786
787 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
788 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
789 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
790
791 #define PCI_CONF1_BUS_MASK 0xff
792 #define PCI_CONF1_DEV_MASK 0x1f
793 #define PCI_CONF1_FUNC_MASK 0x7
794 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
795
796 #define PCI_CONF1_ENABLE BIT(31)
797 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
798 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
799 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
800 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
801
802 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
803 (PCI_CONF1_ENABLE | \
804 PCI_CONF1_BUS(bus) | \
805 PCI_CONF1_DEV(dev) | \
806 PCI_CONF1_FUNC(func) | \
807 PCI_CONF1_REG(reg))
808
809 /*
810 * Extension of PCI Config Address for accessing extended PCIe registers
811 *
812 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
813 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
814 * are used for specifying additional 4 high bits of PCI Express register.
815 */
816
817 #define PCI_CONF1_EXT_REG_SHIFT 16
818 #define PCI_CONF1_EXT_REG_MASK 0xf00
819 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
820
821 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
822 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
823 PCI_CONF1_EXT_REG(reg))
824
825 #endif /* DRIVERS_PCI_H */
826