1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/kernel.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/err.h>
14 #include <linux/fs.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/sysfs.h>
19 #include <linux/stat.h>
20 #include <linux/clk.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-pmu.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/property.h>
33
34 #include <asm/barrier.h>
35 #include <asm/sections.h>
36 #include <asm/sysreg.h>
37 #include <asm/local.h>
38 #include <asm/virt.h>
39
40 #include "coresight-etm4x.h"
41 #include "coresight-etm-perf.h"
42 #include "coresight-etm4x-cfg.h"
43 #include "coresight-self-hosted-trace.h"
44 #include "coresight-syscfg.h"
45
46 static int boot_enable;
47 module_param(boot_enable, int, 0444);
48 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
49
50 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
51 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
52 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
53
54 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
55 module_param(pm_save_enable, int, 0444);
56 MODULE_PARM_DESC(pm_save_enable,
57 "Save/restore state on power down: 1 = never, 2 = self-hosted");
58
59 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
60 static void etm4_set_default_config(struct etmv4_config *config);
61 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
62 struct perf_event *event);
63 static u64 etm4_get_access_type(struct etmv4_config *config);
64
65 static enum cpuhp_state hp_online;
66
67 struct etm4_init_arg {
68 unsigned int pid;
69 struct etmv4_drvdata *drvdata;
70 struct csdev_access *csa;
71 };
72
73 /*
74 * Check if TRCSSPCICRn(i) is implemented for a given instance.
75 *
76 * TRCSSPCICRn is implemented only if :
77 * TRCSSPCICR<n> is present only if all of the following are true:
78 * TRCIDR4.NUMSSCC > n.
79 * TRCIDR4.NUMPC > 0b0000 .
80 * TRCSSCSR<n>.PC == 0b1
81 */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)82 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
83 {
84 return (n < drvdata->nr_ss_cmp) &&
85 drvdata->nr_pe &&
86 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
87 }
88
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)89 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
90 {
91 u64 res = 0;
92
93 switch (offset) {
94 ETM4x_READ_SYSREG_CASES(res)
95 default :
96 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
97 offset);
98 }
99
100 if (!_relaxed)
101 __io_ar(res); /* Imitate the !relaxed I/O helpers */
102
103 return res;
104 }
105
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)106 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
107 {
108 if (!_relaxed)
109 __io_bw(); /* Imitate the !relaxed I/O helpers */
110 if (!_64bit)
111 val &= GENMASK(31, 0);
112
113 switch (offset) {
114 ETM4x_WRITE_SYSREG_CASES(val)
115 default :
116 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
117 offset);
118 }
119 }
120
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)121 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
122 {
123 u64 res = 0;
124
125 switch (offset) {
126 ETE_READ_CASES(res)
127 default :
128 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
129 offset);
130 }
131
132 if (!_relaxed)
133 __io_ar(res); /* Imitate the !relaxed I/O helpers */
134
135 return res;
136 }
137
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)138 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
139 {
140 if (!_relaxed)
141 __io_bw(); /* Imitate the !relaxed I/O helpers */
142 if (!_64bit)
143 val &= GENMASK(31, 0);
144
145 switch (offset) {
146 ETE_WRITE_CASES(val)
147 default :
148 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
149 offset);
150 }
151 }
152
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)153 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
154 struct csdev_access *csa)
155 {
156 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
157
158 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
159 }
160
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)161 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
162 struct csdev_access *csa, u32 val)
163 {
164 val = !!val;
165
166 switch (drvdata->os_lock_model) {
167 case ETM_OSLOCK_PRESENT:
168 etm4x_relaxed_write32(csa, val, TRCOSLAR);
169 break;
170 case ETM_OSLOCK_PE:
171 write_sysreg_s(val, SYS_OSLAR_EL1);
172 break;
173 default:
174 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
175 smp_processor_id(), drvdata->os_lock_model);
176 fallthrough;
177 case ETM_OSLOCK_NI:
178 return;
179 }
180 isb();
181 }
182
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)183 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
184 struct csdev_access *csa)
185 {
186 WARN_ON(drvdata->cpu != smp_processor_id());
187
188 /* Writing 0 to OS Lock unlocks the trace unit registers */
189 etm_write_os_lock(drvdata, csa, 0x0);
190 drvdata->os_unlock = true;
191 }
192
etm4_os_unlock(struct etmv4_drvdata * drvdata)193 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
194 {
195 if (!WARN_ON(!drvdata->csdev))
196 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
197 }
198
etm4_os_lock(struct etmv4_drvdata * drvdata)199 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
200 {
201 if (WARN_ON(!drvdata->csdev))
202 return;
203 /* Writing 0x1 to OS Lock locks the trace registers */
204 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
205 drvdata->os_unlock = false;
206 }
207
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)208 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
209 struct csdev_access *csa)
210 {
211 /* Software Lock is only accessible via memory mapped interface */
212 if (csa->io_mem)
213 CS_LOCK(csa->base);
214 }
215
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)216 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
217 struct csdev_access *csa)
218 {
219 if (csa->io_mem)
220 CS_UNLOCK(csa->base);
221 }
222
etm4_cpu_id(struct coresight_device * csdev)223 static int etm4_cpu_id(struct coresight_device *csdev)
224 {
225 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
226
227 return drvdata->cpu;
228 }
229
etm4_trace_id(struct coresight_device * csdev)230 static int etm4_trace_id(struct coresight_device *csdev)
231 {
232 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
233
234 return drvdata->trcid;
235 }
236
237 struct etm4_enable_arg {
238 struct etmv4_drvdata *drvdata;
239 int rc;
240 };
241
242 /*
243 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
244 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
245 * prohibited state by filtering the Exception levels via TRFCR_EL1.
246 */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)247 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
248 {
249 /* If the CPU doesn't support FEAT_TRF, nothing to do */
250 if (!drvdata->trfcr)
251 return;
252 cpu_prohibit_trace();
253 }
254
255 /*
256 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
257 * as configured by the drvdata->config.mode for the current
258 * session. Even though we have TRCVICTLR bits to filter the
259 * trace in the ELs, it doesn't prevent the ETM from generating
260 * a packet (e.g, TraceInfo) that might contain the addresses from
261 * the excluded levels. Thus we use the additional controls provided
262 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
263 * is generated for the excluded ELs.
264 */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)265 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
266 {
267 u64 trfcr = drvdata->trfcr;
268
269 /* If the CPU doesn't support FEAT_TRF, nothing to do */
270 if (!trfcr)
271 return;
272
273 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
274 trfcr &= ~TRFCR_ELx_ExTRE;
275 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
276 trfcr &= ~TRFCR_ELx_E0TRE;
277
278 write_trfcr(trfcr);
279 }
280
281 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
282
283 #define HISI_HIP08_AMBA_ID 0x000b6d01
284 #define ETM4_AMBA_MASK 0xfffff
285 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
286 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
287 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
288 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
289 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
290
291 struct etm4_arch_features {
292 void (*arch_callback)(bool enable);
293 };
294
etm4_hisi_match_pid(unsigned int id)295 static bool etm4_hisi_match_pid(unsigned int id)
296 {
297 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
298 }
299
etm4_hisi_config_core_commit(bool enable)300 static void etm4_hisi_config_core_commit(bool enable)
301 {
302 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
303 HISI_HIP08_CORE_COMMIT_FULL;
304 u64 val;
305
306 /*
307 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
308 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
309 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
310 * speed(minimun value). So bit 12 and 13 should be cleared together.
311 */
312 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
313 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
314 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
315 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
316 }
317
318 static struct etm4_arch_features etm4_features[] = {
319 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
320 .arch_callback = etm4_hisi_config_core_commit,
321 },
322 {},
323 };
324
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)325 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
326 {
327 struct etm4_arch_features *ftr;
328 int bit;
329
330 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
331 ftr = &etm4_features[bit];
332
333 if (ftr->arch_callback)
334 ftr->arch_callback(true);
335 }
336 }
337
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)338 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
339 {
340 struct etm4_arch_features *ftr;
341 int bit;
342
343 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
344 ftr = &etm4_features[bit];
345
346 if (ftr->arch_callback)
347 ftr->arch_callback(false);
348 }
349 }
350
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)351 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
352 unsigned int id)
353 {
354 if (etm4_hisi_match_pid(id))
355 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
356 }
357 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)358 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
359 {
360 }
361
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)362 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
363 {
364 }
365
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)366 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
367 unsigned int id)
368 {
369 }
370 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
371
etm4_enable_hw(struct etmv4_drvdata * drvdata)372 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
373 {
374 int i, rc;
375 struct etmv4_config *config = &drvdata->config;
376 struct coresight_device *csdev = drvdata->csdev;
377 struct device *etm_dev = &csdev->dev;
378 struct csdev_access *csa = &csdev->access;
379
380
381 etm4_cs_unlock(drvdata, csa);
382 etm4_enable_arch_specific(drvdata);
383
384 etm4_os_unlock(drvdata);
385
386 rc = coresight_claim_device_unlocked(csdev);
387 if (rc)
388 goto done;
389
390 /* Disable the trace unit before programming trace registers */
391 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
392
393 /*
394 * If we use system instructions, we need to synchronize the
395 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
396 * See ARM IHI0064F, section
397 * "4.3.7 Synchronization of register updates"
398 */
399 if (!csa->io_mem)
400 isb();
401
402 /* wait for TRCSTATR.IDLE to go up */
403 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
404 dev_err(etm_dev,
405 "timeout while waiting for Idle Trace Status\n");
406 if (drvdata->nr_pe)
407 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
408 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
409 /* nothing specific implemented */
410 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
411 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
412 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
413 if (drvdata->stallctl)
414 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
415 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
416 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
417 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
418 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
419 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
420 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
421 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
422 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
423 if (drvdata->nr_pe_cmp)
424 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
425 for (i = 0; i < drvdata->nrseqstate - 1; i++)
426 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
427 if (drvdata->nrseqstate) {
428 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
429 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
430 }
431 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
432 for (i = 0; i < drvdata->nr_cntr; i++) {
433 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
434 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
435 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
436 }
437
438 /*
439 * Resource selector pair 0 is always implemented and reserved. As
440 * such start at 2.
441 */
442 for (i = 2; i < drvdata->nr_resource * 2; i++)
443 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
444
445 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
446 /* always clear status bit on restart if using single-shot */
447 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
448 config->ss_status[i] &= ~TRCSSCSRn_STATUS;
449 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
450 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
451 if (etm4x_sspcicrn_present(drvdata, i))
452 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
453 }
454 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
455 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
456 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
457 }
458 for (i = 0; i < drvdata->numcidc; i++)
459 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
460 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
461 if (drvdata->numcidc > 4)
462 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
463
464 for (i = 0; i < drvdata->numvmidc; i++)
465 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
466 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
467 if (drvdata->numvmidc > 4)
468 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
469
470 if (!drvdata->skip_power_up) {
471 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
472
473 /*
474 * Request to keep the trace unit powered and also
475 * emulation of powerdown
476 */
477 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
478 }
479
480 /*
481 * ETE mandates that the TRCRSR is written to before
482 * enabling it.
483 */
484 if (etm4x_is_ete(drvdata))
485 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
486
487 etm4x_allow_trace(drvdata);
488 /* Enable the trace unit */
489 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
490
491 /* Synchronize the register updates for sysreg access */
492 if (!csa->io_mem)
493 isb();
494
495 /* wait for TRCSTATR.IDLE to go back down to '0' */
496 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
497 dev_err(etm_dev,
498 "timeout while waiting for Idle Trace Status\n");
499
500 /*
501 * As recommended by section 4.3.7 ("Synchronization when using the
502 * memory-mapped interface") of ARM IHI 0064D
503 */
504 dsb(sy);
505 isb();
506
507 done:
508 etm4_cs_lock(drvdata, csa);
509
510 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
511 drvdata->cpu, rc);
512 return rc;
513 }
514
etm4_enable_hw_smp_call(void * info)515 static void etm4_enable_hw_smp_call(void *info)
516 {
517 struct etm4_enable_arg *arg = info;
518
519 if (WARN_ON(!arg))
520 return;
521 arg->rc = etm4_enable_hw(arg->drvdata);
522 }
523
524 /*
525 * The goal of function etm4_config_timestamp_event() is to configure a
526 * counter that will tell the tracer to emit a timestamp packet when it
527 * reaches zero. This is done in order to get a more fine grained idea
528 * of when instructions are executed so that they can be correlated
529 * with execution on other CPUs.
530 *
531 * To do this the counter itself is configured to self reload and
532 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
533 * there a resource selector is configured with the counter and the
534 * timestamp control register to use the resource selector to trigger the
535 * event that will insert a timestamp packet in the stream.
536 */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)537 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
538 {
539 int ctridx, ret = -EINVAL;
540 int counter, rselector;
541 u32 val = 0;
542 struct etmv4_config *config = &drvdata->config;
543
544 /* No point in trying if we don't have at least one counter */
545 if (!drvdata->nr_cntr)
546 goto out;
547
548 /* Find a counter that hasn't been initialised */
549 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
550 if (config->cntr_val[ctridx] == 0)
551 break;
552
553 /* All the counters have been configured already, bail out */
554 if (ctridx == drvdata->nr_cntr) {
555 pr_debug("%s: no available counter found\n", __func__);
556 ret = -ENOSPC;
557 goto out;
558 }
559
560 /*
561 * Searching for an available resource selector to use, starting at
562 * '2' since every implementation has at least 2 resource selector.
563 * ETMIDR4 gives the number of resource selector _pairs_,
564 * hence multiply by 2.
565 */
566 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
567 if (!config->res_ctrl[rselector])
568 break;
569
570 if (rselector == drvdata->nr_resource * 2) {
571 pr_debug("%s: no available resource selector found\n",
572 __func__);
573 ret = -ENOSPC;
574 goto out;
575 }
576
577 /* Remember what counter we used */
578 counter = 1 << ctridx;
579
580 /*
581 * Initialise original and reload counter value to the smallest
582 * possible value in order to get as much precision as we can.
583 */
584 config->cntr_val[ctridx] = 1;
585 config->cntrldvr[ctridx] = 1;
586
587 /* Set the trace counter control register */
588 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
589 0x0 << 7 | /* Select single resource selector */
590 0x1; /* Resource selector 1, i.e always true */
591
592 config->cntr_ctrl[ctridx] = val;
593
594 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
595 counter << 0; /* Counter to use */
596
597 config->res_ctrl[rselector] = val;
598
599 val = 0x0 << 7 | /* Select single resource selector */
600 rselector; /* Resource selector */
601
602 config->ts_ctrl = val;
603
604 ret = 0;
605 out:
606 return ret;
607 }
608
etm4_parse_event_config(struct coresight_device * csdev,struct perf_event * event)609 static int etm4_parse_event_config(struct coresight_device *csdev,
610 struct perf_event *event)
611 {
612 int ret = 0;
613 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
614 struct etmv4_config *config = &drvdata->config;
615 struct perf_event_attr *attr = &event->attr;
616 unsigned long cfg_hash;
617 int preset;
618
619 /* Clear configuration from previous run */
620 memset(config, 0, sizeof(struct etmv4_config));
621
622 if (attr->exclude_kernel)
623 config->mode = ETM_MODE_EXCL_KERN;
624
625 if (attr->exclude_user)
626 config->mode = ETM_MODE_EXCL_USER;
627
628 /* Always start from the default config */
629 etm4_set_default_config(config);
630
631 /* Configure filters specified on the perf cmd line, if any. */
632 ret = etm4_set_event_filters(drvdata, event);
633 if (ret)
634 goto out;
635
636 /* Go from generic option to ETMv4 specifics */
637 if (attr->config & BIT(ETM_OPT_CYCACC)) {
638 config->cfg |= TRCCONFIGR_CCI;
639 /* TRM: Must program this for cycacc to work */
640 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
641 }
642 if (attr->config & BIT(ETM_OPT_TS)) {
643 /*
644 * Configure timestamps to be emitted at regular intervals in
645 * order to correlate instructions executed on different CPUs
646 * (CPU-wide trace scenarios).
647 */
648 ret = etm4_config_timestamp_event(drvdata);
649
650 /*
651 * No need to go further if timestamp intervals can't
652 * be configured.
653 */
654 if (ret)
655 goto out;
656
657 /* bit[11], Global timestamp tracing bit */
658 config->cfg |= TRCCONFIGR_TS;
659 }
660
661 /* Only trace contextID when runs in root PID namespace */
662 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
663 task_is_in_init_pid_ns(current))
664 /* bit[6], Context ID tracing bit */
665 config->cfg |= TRCCONFIGR_CID;
666
667 /*
668 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
669 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
670 * kernel is not running in EL2.
671 */
672 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
673 if (!is_kernel_in_hyp_mode()) {
674 ret = -EINVAL;
675 goto out;
676 }
677 /* Only trace virtual contextID when runs in root PID namespace */
678 if (task_is_in_init_pid_ns(current))
679 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
680 }
681
682 /* return stack - enable if selected and supported */
683 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
684 /* bit[12], Return stack enable bit */
685 config->cfg |= TRCCONFIGR_RS;
686
687 /*
688 * Set any selected configuration and preset.
689 *
690 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
691 * in the perf attributes defined in coresight-etm-perf.c.
692 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
693 * A zero configid means no configuration active, preset = 0 means no preset selected.
694 */
695 if (attr->config2 & GENMASK_ULL(63, 32)) {
696 cfg_hash = (u32)(attr->config2 >> 32);
697 preset = attr->config & 0xF;
698 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
699 }
700
701 /* branch broadcast - enable if selected and supported */
702 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
703 if (!drvdata->trcbb) {
704 /*
705 * Missing BB support could cause silent decode errors
706 * so fail to open if it's not supported.
707 */
708 ret = -EINVAL;
709 goto out;
710 } else {
711 config->cfg |= BIT(ETM4_CFG_BIT_BB);
712 }
713 }
714
715 out:
716 return ret;
717 }
718
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event)719 static int etm4_enable_perf(struct coresight_device *csdev,
720 struct perf_event *event)
721 {
722 int ret = 0;
723 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
724
725 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
726 ret = -EINVAL;
727 goto out;
728 }
729
730 /* Configure the tracer based on the session's specifics */
731 ret = etm4_parse_event_config(csdev, event);
732 if (ret)
733 goto out;
734 /* And enable it */
735 ret = etm4_enable_hw(drvdata);
736
737 out:
738 return ret;
739 }
740
etm4_enable_sysfs(struct coresight_device * csdev)741 static int etm4_enable_sysfs(struct coresight_device *csdev)
742 {
743 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
744 struct etm4_enable_arg arg = { };
745 unsigned long cfg_hash;
746 int ret, preset;
747
748 /* enable any config activated by configfs */
749 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
750 if (cfg_hash) {
751 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
752 if (ret)
753 return ret;
754 }
755
756 spin_lock(&drvdata->spinlock);
757
758 /*
759 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
760 * ensures that register writes occur when cpu is powered.
761 */
762 arg.drvdata = drvdata;
763 ret = smp_call_function_single(drvdata->cpu,
764 etm4_enable_hw_smp_call, &arg, 1);
765 if (!ret)
766 ret = arg.rc;
767 if (!ret)
768 drvdata->sticky_enable = true;
769 spin_unlock(&drvdata->spinlock);
770
771 if (!ret)
772 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
773 return ret;
774 }
775
etm4_enable(struct coresight_device * csdev,struct perf_event * event,u32 mode)776 static int etm4_enable(struct coresight_device *csdev,
777 struct perf_event *event, u32 mode)
778 {
779 int ret;
780 u32 val;
781 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
782
783 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
784
785 /* Someone is already using the tracer */
786 if (val)
787 return -EBUSY;
788
789 switch (mode) {
790 case CS_MODE_SYSFS:
791 ret = etm4_enable_sysfs(csdev);
792 break;
793 case CS_MODE_PERF:
794 ret = etm4_enable_perf(csdev, event);
795 break;
796 default:
797 ret = -EINVAL;
798 }
799
800 /* The tracer didn't start */
801 if (ret)
802 local_set(&drvdata->mode, CS_MODE_DISABLED);
803
804 return ret;
805 }
806
etm4_disable_hw(void * info)807 static void etm4_disable_hw(void *info)
808 {
809 u32 control;
810 struct etmv4_drvdata *drvdata = info;
811 struct etmv4_config *config = &drvdata->config;
812 struct coresight_device *csdev = drvdata->csdev;
813 struct device *etm_dev = &csdev->dev;
814 struct csdev_access *csa = &csdev->access;
815 int i;
816
817 etm4_cs_unlock(drvdata, csa);
818 etm4_disable_arch_specific(drvdata);
819
820 if (!drvdata->skip_power_up) {
821 /* power can be removed from the trace unit now */
822 control = etm4x_relaxed_read32(csa, TRCPDCR);
823 control &= ~TRCPDCR_PU;
824 etm4x_relaxed_write32(csa, control, TRCPDCR);
825 }
826
827 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
828
829 /* EN, bit[0] Trace unit enable bit */
830 control &= ~0x1;
831
832 /*
833 * If the CPU supports v8.4 Trace filter Control,
834 * set the ETM to trace prohibited region.
835 */
836 etm4x_prohibit_trace(drvdata);
837 /*
838 * Make sure everything completes before disabling, as recommended
839 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
840 * SSTATUS") of ARM IHI 0064D
841 */
842 dsb(sy);
843 isb();
844 /* Trace synchronization barrier, is a nop if not supported */
845 tsb_csync();
846 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
847
848 /* wait for TRCSTATR.PMSTABLE to go to '1' */
849 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
850 dev_err(etm_dev,
851 "timeout while waiting for PM stable Trace Status\n");
852 /* read the status of the single shot comparators */
853 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
854 config->ss_status[i] =
855 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
856 }
857
858 /* read back the current counter values */
859 for (i = 0; i < drvdata->nr_cntr; i++) {
860 config->cntr_val[i] =
861 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
862 }
863
864 coresight_disclaim_device_unlocked(csdev);
865 etm4_cs_lock(drvdata, csa);
866
867 dev_dbg(&drvdata->csdev->dev,
868 "cpu: %d disable smp call done\n", drvdata->cpu);
869 }
870
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)871 static int etm4_disable_perf(struct coresight_device *csdev,
872 struct perf_event *event)
873 {
874 u32 control;
875 struct etm_filters *filters = event->hw.addr_filters;
876 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
877 struct perf_event_attr *attr = &event->attr;
878
879 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
880 return -EINVAL;
881
882 etm4_disable_hw(drvdata);
883 /*
884 * The config_id occupies bits 63:32 of the config2 perf event attr
885 * field. If this is non-zero then we will have enabled a config.
886 */
887 if (attr->config2 & GENMASK_ULL(63, 32))
888 cscfg_csdev_disable_active_config(csdev);
889
890 /*
891 * Check if the start/stop logic was active when the unit was stopped.
892 * That way we can re-enable the start/stop logic when the process is
893 * scheduled again. Configuration of the start/stop logic happens in
894 * function etm4_set_event_filters().
895 */
896 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
897 /* TRCVICTLR::SSSTATUS, bit[9] */
898 filters->ssstatus = (control & BIT(9));
899
900 return 0;
901 }
902
etm4_disable_sysfs(struct coresight_device * csdev)903 static void etm4_disable_sysfs(struct coresight_device *csdev)
904 {
905 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
906
907 /*
908 * Taking hotplug lock here protects from clocks getting disabled
909 * with tracing being left on (crash scenario) if user disable occurs
910 * after cpu online mask indicates the cpu is offline but before the
911 * DYING hotplug callback is serviced by the ETM driver.
912 */
913 cpus_read_lock();
914 spin_lock(&drvdata->spinlock);
915
916 /*
917 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
918 * ensures that register writes occur when cpu is powered.
919 */
920 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
921
922 spin_unlock(&drvdata->spinlock);
923 cpus_read_unlock();
924
925 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
926 }
927
etm4_disable(struct coresight_device * csdev,struct perf_event * event)928 static void etm4_disable(struct coresight_device *csdev,
929 struct perf_event *event)
930 {
931 u32 mode;
932 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
933
934 /*
935 * For as long as the tracer isn't disabled another entity can't
936 * change its status. As such we can read the status here without
937 * fearing it will change under us.
938 */
939 mode = local_read(&drvdata->mode);
940
941 switch (mode) {
942 case CS_MODE_DISABLED:
943 break;
944 case CS_MODE_SYSFS:
945 etm4_disable_sysfs(csdev);
946 break;
947 case CS_MODE_PERF:
948 etm4_disable_perf(csdev, event);
949 break;
950 }
951
952 if (mode)
953 local_set(&drvdata->mode, CS_MODE_DISABLED);
954 }
955
956 static const struct coresight_ops_source etm4_source_ops = {
957 .cpu_id = etm4_cpu_id,
958 .trace_id = etm4_trace_id,
959 .enable = etm4_enable,
960 .disable = etm4_disable,
961 };
962
963 static const struct coresight_ops etm4_cs_ops = {
964 .source_ops = &etm4_source_ops,
965 };
966
cpu_supports_sysreg_trace(void)967 static inline bool cpu_supports_sysreg_trace(void)
968 {
969 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
970
971 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
972 }
973
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)974 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
975 struct csdev_access *csa)
976 {
977 u32 devarch;
978
979 if (!cpu_supports_sysreg_trace())
980 return false;
981
982 /*
983 * ETMs implementing sysreg access must implement TRCDEVARCH.
984 */
985 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
986 switch (devarch & ETM_DEVARCH_ID_MASK) {
987 case ETM_DEVARCH_ETMv4x_ARCH:
988 *csa = (struct csdev_access) {
989 .io_mem = false,
990 .read = etm4x_sysreg_read,
991 .write = etm4x_sysreg_write,
992 };
993 break;
994 case ETM_DEVARCH_ETE_ARCH:
995 *csa = (struct csdev_access) {
996 .io_mem = false,
997 .read = ete_sysreg_read,
998 .write = ete_sysreg_write,
999 };
1000 break;
1001 default:
1002 return false;
1003 }
1004
1005 drvdata->arch = etm_devarch_to_arch(devarch);
1006 return true;
1007 }
1008
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1009 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1010 struct csdev_access *csa)
1011 {
1012 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1013
1014 /*
1015 * All ETMs must implement TRCDEVARCH to indicate that
1016 * the component is an ETMv4. Even though TRCIDR1 also
1017 * contains the information, it is part of the "Trace"
1018 * register and must be accessed with the OSLK cleared,
1019 * with MMIO. But we cannot touch the OSLK until we are
1020 * sure this is an ETM. So rely only on the TRCDEVARCH.
1021 */
1022 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1023 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1024 return false;
1025 }
1026
1027 drvdata->arch = etm_devarch_to_arch(devarch);
1028 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1029 return true;
1030 }
1031
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1032 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1033 struct csdev_access *csa)
1034 {
1035 /*
1036 * Always choose the memory mapped io, if there is
1037 * a memory map to prevent sysreg access on broken
1038 * systems.
1039 */
1040 if (drvdata->base)
1041 return etm4_init_iomem_access(drvdata, csa);
1042
1043 if (etm4_init_sysreg_access(drvdata, csa))
1044 return true;
1045
1046 return false;
1047 }
1048
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1049 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1050 {
1051 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1052 u64 trfcr;
1053
1054 drvdata->trfcr = 0;
1055 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1056 return;
1057
1058 /*
1059 * If the CPU supports v8.4 SelfHosted Tracing, enable
1060 * tracing at the kernel EL and EL0, forcing to use the
1061 * virtual time as the timestamp.
1062 */
1063 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1064 TRFCR_ELx_ExTRE |
1065 TRFCR_ELx_E0TRE);
1066
1067 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1068 if (is_kernel_in_hyp_mode())
1069 trfcr |= TRFCR_EL2_CX;
1070
1071 drvdata->trfcr = trfcr;
1072 }
1073
etm4_init_arch_data(void * info)1074 static void etm4_init_arch_data(void *info)
1075 {
1076 u32 etmidr0;
1077 u32 etmidr2;
1078 u32 etmidr3;
1079 u32 etmidr4;
1080 u32 etmidr5;
1081 struct etm4_init_arg *init_arg = info;
1082 struct etmv4_drvdata *drvdata;
1083 struct csdev_access *csa;
1084 int i;
1085
1086 drvdata = init_arg->drvdata;
1087 csa = init_arg->csa;
1088
1089 /*
1090 * If we are unable to detect the access mechanism,
1091 * or unable to detect the trace unit type, fail
1092 * early.
1093 */
1094 if (!etm4_init_csdev_access(drvdata, csa))
1095 return;
1096
1097 /* Detect the support for OS Lock before we actually use it */
1098 etm_detect_os_lock(drvdata, csa);
1099
1100 /* Make sure all registers are accessible */
1101 etm4_os_unlock_csa(drvdata, csa);
1102 etm4_cs_unlock(drvdata, csa);
1103
1104 etm4_check_arch_features(drvdata, init_arg->pid);
1105
1106 /* find all capabilities of the tracing unit */
1107 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1108
1109 /* INSTP0, bits[2:1] P0 tracing support field */
1110 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1111 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1112 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1113 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1114 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1115 /* TRCCCI, bit[7] Cycle counting instruction bit */
1116 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1117 /* RETSTACK, bit[9] Return stack bit */
1118 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1119 /* NUMEVENT, bits[11:10] Number of events field */
1120 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1121 /* QSUPP, bits[16:15] Q element support field */
1122 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1123 /* TSSIZE, bits[28:24] Global timestamp size field */
1124 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1125
1126 /* maximum size of resources */
1127 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1128 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1129 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1130 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1131 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1132 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1133 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1134
1135 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1136 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1137 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1138 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1139 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1140 drvdata->config.s_ex_level = drvdata->s_ex_level;
1141 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1142 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1143 /*
1144 * TRCERR, bit[24] whether a trace unit can trace a
1145 * system error exception.
1146 */
1147 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1148 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1149 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1150 /* STALLCTL, bit[26] is stall control implemented? */
1151 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1152 /* SYSSTALL, bit[27] implementation can support stall control? */
1153 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1154 /*
1155 * NUMPROC - the number of PEs available for tracing, 5bits
1156 * = TRCIDR3.bits[13:12]bits[30:28]
1157 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1158 * bits[3:0] = TRCIDR3.bits[30:28]
1159 */
1160 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1161 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1162 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1163 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1164
1165 /* number of resources trace unit supports */
1166 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1167 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1168 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1169 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1170 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1171 /*
1172 * NUMRSPAIR, bits[19:16]
1173 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1174 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1175 * As such add 1 to the value of NUMRSPAIR for a better representation.
1176 *
1177 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1178 * the default TRUE and FALSE resource selectors are omitted.
1179 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1180 */
1181 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1182 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1183 drvdata->nr_resource += 1;
1184 /*
1185 * NUMSSCC, bits[23:20] the number of single-shot
1186 * comparator control for tracing. Read any status regs as these
1187 * also contain RO capability data.
1188 */
1189 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1190 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1191 drvdata->config.ss_status[i] =
1192 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1193 }
1194 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1195 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1196 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1197 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1198
1199 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1200 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1201 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1202 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1203 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1204 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1205 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1206 /*
1207 * LPOVERRIDE, bit[23] implementation supports
1208 * low-power state override
1209 */
1210 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1211 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1212 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1213 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1214 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1215 etm4_cs_lock(drvdata, csa);
1216 cpu_detect_trace_filtering(drvdata);
1217 }
1218
etm4_get_victlr_access_type(struct etmv4_config * config)1219 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1220 {
1221 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1222 }
1223
1224 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1225 static void etm4_set_victlr_access(struct etmv4_config *config)
1226 {
1227 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1228 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1229 }
1230
etm4_set_default_config(struct etmv4_config * config)1231 static void etm4_set_default_config(struct etmv4_config *config)
1232 {
1233 /* disable all events tracing */
1234 config->eventctrl0 = 0x0;
1235 config->eventctrl1 = 0x0;
1236
1237 /* disable stalling */
1238 config->stall_ctrl = 0x0;
1239
1240 /* enable trace synchronization every 4096 bytes, if available */
1241 config->syncfreq = 0xC;
1242
1243 /* disable timestamp event */
1244 config->ts_ctrl = 0x0;
1245
1246 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1247 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1248
1249 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1250 etm4_set_victlr_access(config);
1251 }
1252
etm4_get_ns_access_type(struct etmv4_config * config)1253 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1254 {
1255 u64 access_type = 0;
1256
1257 /*
1258 * EXLEVEL_NS, for NonSecure Exception levels.
1259 * The mask here is a generic value and must be
1260 * shifted to the corresponding field for the registers
1261 */
1262 if (!is_kernel_in_hyp_mode()) {
1263 /* Stay away from hypervisor mode for non-VHE */
1264 access_type = ETM_EXLEVEL_NS_HYP;
1265 if (config->mode & ETM_MODE_EXCL_KERN)
1266 access_type |= ETM_EXLEVEL_NS_OS;
1267 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1268 access_type = ETM_EXLEVEL_NS_HYP;
1269 }
1270
1271 if (config->mode & ETM_MODE_EXCL_USER)
1272 access_type |= ETM_EXLEVEL_NS_APP;
1273
1274 return access_type;
1275 }
1276
1277 /*
1278 * Construct the exception level masks for a given config.
1279 * This must be shifted to the corresponding register field
1280 * for usage.
1281 */
etm4_get_access_type(struct etmv4_config * config)1282 static u64 etm4_get_access_type(struct etmv4_config *config)
1283 {
1284 /* All Secure exception levels are excluded from the trace */
1285 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1286 }
1287
etm4_get_comparator_access_type(struct etmv4_config * config)1288 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1289 {
1290 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1291 }
1292
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1293 static void etm4_set_comparator_filter(struct etmv4_config *config,
1294 u64 start, u64 stop, int comparator)
1295 {
1296 u64 access_type = etm4_get_comparator_access_type(config);
1297
1298 /* First half of default address comparator */
1299 config->addr_val[comparator] = start;
1300 config->addr_acc[comparator] = access_type;
1301 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1302
1303 /* Second half of default address comparator */
1304 config->addr_val[comparator + 1] = stop;
1305 config->addr_acc[comparator + 1] = access_type;
1306 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1307
1308 /*
1309 * Configure the ViewInst function to include this address range
1310 * comparator.
1311 *
1312 * @comparator is divided by two since it is the index in the
1313 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1314 * address range comparator _pairs_.
1315 *
1316 * Therefore:
1317 * index 0 -> compatator pair 0
1318 * index 2 -> comparator pair 1
1319 * index 4 -> comparator pair 2
1320 * ...
1321 * index 14 -> comparator pair 7
1322 */
1323 config->viiectlr |= BIT(comparator / 2);
1324 }
1325
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1326 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1327 u64 address, int comparator,
1328 enum etm_addr_type type)
1329 {
1330 int shift;
1331 u64 access_type = etm4_get_comparator_access_type(config);
1332
1333 /* Configure the comparator */
1334 config->addr_val[comparator] = address;
1335 config->addr_acc[comparator] = access_type;
1336 config->addr_type[comparator] = type;
1337
1338 /*
1339 * Configure ViewInst Start-Stop control register.
1340 * Addresses configured to start tracing go from bit 0 to n-1,
1341 * while those configured to stop tracing from 16 to 16 + n-1.
1342 */
1343 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1344 config->vissctlr |= BIT(shift + comparator);
1345 }
1346
etm4_set_default_filter(struct etmv4_config * config)1347 static void etm4_set_default_filter(struct etmv4_config *config)
1348 {
1349 /* Trace everything 'default' filter achieved by no filtering */
1350 config->viiectlr = 0x0;
1351
1352 /*
1353 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1354 * in the started state
1355 */
1356 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1357 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1358
1359 /* No start-stop filtering for ViewInst */
1360 config->vissctlr = 0x0;
1361 }
1362
etm4_set_default(struct etmv4_config * config)1363 static void etm4_set_default(struct etmv4_config *config)
1364 {
1365 if (WARN_ON_ONCE(!config))
1366 return;
1367
1368 /*
1369 * Make default initialisation trace everything
1370 *
1371 * This is done by a minimum default config sufficient to enable
1372 * full instruction trace - with a default filter for trace all
1373 * achieved by having no filtering.
1374 */
1375 etm4_set_default_config(config);
1376 etm4_set_default_filter(config);
1377 }
1378
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1379 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1380 {
1381 int nr_comparator, index = 0;
1382 struct etmv4_config *config = &drvdata->config;
1383
1384 /*
1385 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1386 * for the total number of comparators.
1387 */
1388 nr_comparator = drvdata->nr_addr_cmp * 2;
1389
1390 /* Go through the tally of comparators looking for a free one. */
1391 while (index < nr_comparator) {
1392 switch (type) {
1393 case ETM_ADDR_TYPE_RANGE:
1394 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1395 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1396 return index;
1397
1398 /* Address range comparators go in pairs */
1399 index += 2;
1400 break;
1401 case ETM_ADDR_TYPE_START:
1402 case ETM_ADDR_TYPE_STOP:
1403 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1404 return index;
1405
1406 /* Start/stop address can have odd indexes */
1407 index += 1;
1408 break;
1409 default:
1410 return -EINVAL;
1411 }
1412 }
1413
1414 /* If we are here all the comparators have been used. */
1415 return -ENOSPC;
1416 }
1417
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1418 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1419 struct perf_event *event)
1420 {
1421 int i, comparator, ret = 0;
1422 u64 address;
1423 struct etmv4_config *config = &drvdata->config;
1424 struct etm_filters *filters = event->hw.addr_filters;
1425
1426 if (!filters)
1427 goto default_filter;
1428
1429 /* Sync events with what Perf got */
1430 perf_event_addr_filters_sync(event);
1431
1432 /*
1433 * If there are no filters to deal with simply go ahead with
1434 * the default filter, i.e the entire address range.
1435 */
1436 if (!filters->nr_filters)
1437 goto default_filter;
1438
1439 for (i = 0; i < filters->nr_filters; i++) {
1440 struct etm_filter *filter = &filters->etm_filter[i];
1441 enum etm_addr_type type = filter->type;
1442
1443 /* See if a comparator is free. */
1444 comparator = etm4_get_next_comparator(drvdata, type);
1445 if (comparator < 0) {
1446 ret = comparator;
1447 goto out;
1448 }
1449
1450 switch (type) {
1451 case ETM_ADDR_TYPE_RANGE:
1452 etm4_set_comparator_filter(config,
1453 filter->start_addr,
1454 filter->stop_addr,
1455 comparator);
1456 /*
1457 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1458 * in the started state
1459 */
1460 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1461
1462 /* No start-stop filtering for ViewInst */
1463 config->vissctlr = 0x0;
1464 break;
1465 case ETM_ADDR_TYPE_START:
1466 case ETM_ADDR_TYPE_STOP:
1467 /* Get the right start or stop address */
1468 address = (type == ETM_ADDR_TYPE_START ?
1469 filter->start_addr :
1470 filter->stop_addr);
1471
1472 /* Configure comparator */
1473 etm4_set_start_stop_filter(config, address,
1474 comparator, type);
1475
1476 /*
1477 * If filters::ssstatus == 1, trace acquisition was
1478 * started but the process was yanked away before the
1479 * the stop address was hit. As such the start/stop
1480 * logic needs to be re-started so that tracing can
1481 * resume where it left.
1482 *
1483 * The start/stop logic status when a process is
1484 * scheduled out is checked in function
1485 * etm4_disable_perf().
1486 */
1487 if (filters->ssstatus)
1488 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1489
1490 /* No include/exclude filtering for ViewInst */
1491 config->viiectlr = 0x0;
1492 break;
1493 default:
1494 ret = -EINVAL;
1495 goto out;
1496 }
1497 }
1498
1499 goto out;
1500
1501
1502 default_filter:
1503 etm4_set_default_filter(config);
1504
1505 out:
1506 return ret;
1507 }
1508
etm4_config_trace_mode(struct etmv4_config * config)1509 void etm4_config_trace_mode(struct etmv4_config *config)
1510 {
1511 u32 mode;
1512
1513 mode = config->mode;
1514 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1515
1516 /* excluding kernel AND user space doesn't make sense */
1517 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1518
1519 /* nothing to do if neither flags are set */
1520 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1521 return;
1522
1523 etm4_set_victlr_access(config);
1524 }
1525
etm4_online_cpu(unsigned int cpu)1526 static int etm4_online_cpu(unsigned int cpu)
1527 {
1528 if (!etmdrvdata[cpu])
1529 return 0;
1530
1531 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1532 coresight_enable(etmdrvdata[cpu]->csdev);
1533 return 0;
1534 }
1535
etm4_starting_cpu(unsigned int cpu)1536 static int etm4_starting_cpu(unsigned int cpu)
1537 {
1538 if (!etmdrvdata[cpu])
1539 return 0;
1540
1541 spin_lock(&etmdrvdata[cpu]->spinlock);
1542 if (!etmdrvdata[cpu]->os_unlock)
1543 etm4_os_unlock(etmdrvdata[cpu]);
1544
1545 if (local_read(&etmdrvdata[cpu]->mode))
1546 etm4_enable_hw(etmdrvdata[cpu]);
1547 spin_unlock(&etmdrvdata[cpu]->spinlock);
1548 return 0;
1549 }
1550
etm4_dying_cpu(unsigned int cpu)1551 static int etm4_dying_cpu(unsigned int cpu)
1552 {
1553 if (!etmdrvdata[cpu])
1554 return 0;
1555
1556 spin_lock(&etmdrvdata[cpu]->spinlock);
1557 if (local_read(&etmdrvdata[cpu]->mode))
1558 etm4_disable_hw(etmdrvdata[cpu]);
1559 spin_unlock(&etmdrvdata[cpu]->spinlock);
1560 return 0;
1561 }
1562
etm4_init_trace_id(struct etmv4_drvdata * drvdata)1563 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1564 {
1565 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1566 }
1567
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1568 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1569 {
1570 int i, ret = 0;
1571 struct etmv4_save_state *state;
1572 struct coresight_device *csdev = drvdata->csdev;
1573 struct csdev_access *csa;
1574 struct device *etm_dev;
1575
1576 if (WARN_ON(!csdev))
1577 return -ENODEV;
1578
1579 etm_dev = &csdev->dev;
1580 csa = &csdev->access;
1581
1582 /*
1583 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1584 * of ARM IHI 0064D
1585 */
1586 dsb(sy);
1587 isb();
1588
1589 etm4_cs_unlock(drvdata, csa);
1590 /* Lock the OS lock to disable trace and external debugger access */
1591 etm4_os_lock(drvdata);
1592
1593 /* wait for TRCSTATR.PMSTABLE to go up */
1594 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1595 dev_err(etm_dev,
1596 "timeout while waiting for PM Stable Status\n");
1597 etm4_os_unlock(drvdata);
1598 ret = -EBUSY;
1599 goto out;
1600 }
1601
1602 state = drvdata->save_state;
1603
1604 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1605 if (drvdata->nr_pe)
1606 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1607 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1608 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1609 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1610 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1611 if (drvdata->stallctl)
1612 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1613 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1614 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1615 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1616 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1617 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1618 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1619
1620 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1621 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1622 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1623 if (drvdata->nr_pe_cmp)
1624 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1625 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1626 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1627 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1628
1629 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1630 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1631
1632 if (drvdata->nrseqstate) {
1633 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1634 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1635 }
1636 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1637
1638 for (i = 0; i < drvdata->nr_cntr; i++) {
1639 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1640 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1641 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1642 }
1643
1644 for (i = 0; i < drvdata->nr_resource * 2; i++)
1645 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1646
1647 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1648 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1649 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1650 if (etm4x_sspcicrn_present(drvdata, i))
1651 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1652 }
1653
1654 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1655 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1656 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1657 }
1658
1659 /*
1660 * Data trace stream is architecturally prohibited for A profile cores
1661 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1662 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1663 * unit") of ARM IHI 0064D.
1664 */
1665
1666 for (i = 0; i < drvdata->numcidc; i++)
1667 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1668
1669 for (i = 0; i < drvdata->numvmidc; i++)
1670 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1671
1672 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1673 if (drvdata->numcidc > 4)
1674 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1675
1676 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1677 if (drvdata->numvmidc > 4)
1678 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1679
1680 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1681
1682 if (!drvdata->skip_power_up)
1683 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1684
1685 /* wait for TRCSTATR.IDLE to go up */
1686 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1687 dev_err(etm_dev,
1688 "timeout while waiting for Idle Trace Status\n");
1689 etm4_os_unlock(drvdata);
1690 ret = -EBUSY;
1691 goto out;
1692 }
1693
1694 drvdata->state_needs_restore = true;
1695
1696 /*
1697 * Power can be removed from the trace unit now. We do this to
1698 * potentially save power on systems that respect the TRCPDCR_PU
1699 * despite requesting software to save/restore state.
1700 */
1701 if (!drvdata->skip_power_up)
1702 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1703 TRCPDCR);
1704 out:
1705 etm4_cs_lock(drvdata, csa);
1706 return ret;
1707 }
1708
etm4_cpu_save(struct etmv4_drvdata * drvdata)1709 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1710 {
1711 int ret = 0;
1712
1713 /* Save the TRFCR irrespective of whether the ETM is ON */
1714 if (drvdata->trfcr)
1715 drvdata->save_trfcr = read_trfcr();
1716 /*
1717 * Save and restore the ETM Trace registers only if
1718 * the ETM is active.
1719 */
1720 if (local_read(&drvdata->mode) && drvdata->save_state)
1721 ret = __etm4_cpu_save(drvdata);
1722 return ret;
1723 }
1724
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1725 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1726 {
1727 int i;
1728 struct etmv4_save_state *state = drvdata->save_state;
1729 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1730 struct csdev_access *csa = &tmp_csa;
1731
1732 etm4_cs_unlock(drvdata, csa);
1733 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1734
1735 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1736 if (drvdata->nr_pe)
1737 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1738 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1739 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1740 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1741 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1742 if (drvdata->stallctl)
1743 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1744 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1745 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1746 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1747 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1748 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1749 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1750
1751 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1752 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1753 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1754 if (drvdata->nr_pe_cmp)
1755 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1756 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1757 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1758 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1759
1760 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1761 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1762
1763 if (drvdata->nrseqstate) {
1764 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1765 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1766 }
1767 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1768
1769 for (i = 0; i < drvdata->nr_cntr; i++) {
1770 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1771 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1772 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1773 }
1774
1775 for (i = 0; i < drvdata->nr_resource * 2; i++)
1776 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1777
1778 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1779 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1780 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1781 if (etm4x_sspcicrn_present(drvdata, i))
1782 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1783 }
1784
1785 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1786 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1787 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1788 }
1789
1790 for (i = 0; i < drvdata->numcidc; i++)
1791 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1792
1793 for (i = 0; i < drvdata->numvmidc; i++)
1794 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1795
1796 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1797 if (drvdata->numcidc > 4)
1798 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1799
1800 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1801 if (drvdata->numvmidc > 4)
1802 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1803
1804 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1805
1806 if (!drvdata->skip_power_up)
1807 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1808
1809 drvdata->state_needs_restore = false;
1810
1811 /*
1812 * As recommended by section 4.3.7 ("Synchronization when using the
1813 * memory-mapped interface") of ARM IHI 0064D
1814 */
1815 dsb(sy);
1816 isb();
1817
1818 /* Unlock the OS lock to re-enable trace and external debug access */
1819 etm4_os_unlock(drvdata);
1820 etm4_cs_lock(drvdata, csa);
1821 }
1822
etm4_cpu_restore(struct etmv4_drvdata * drvdata)1823 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1824 {
1825 if (drvdata->trfcr)
1826 write_trfcr(drvdata->save_trfcr);
1827 if (drvdata->state_needs_restore)
1828 __etm4_cpu_restore(drvdata);
1829 }
1830
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)1831 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1832 void *v)
1833 {
1834 struct etmv4_drvdata *drvdata;
1835 unsigned int cpu = smp_processor_id();
1836
1837 if (!etmdrvdata[cpu])
1838 return NOTIFY_OK;
1839
1840 drvdata = etmdrvdata[cpu];
1841
1842 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1843 return NOTIFY_BAD;
1844
1845 switch (cmd) {
1846 case CPU_PM_ENTER:
1847 if (etm4_cpu_save(drvdata))
1848 return NOTIFY_BAD;
1849 break;
1850 case CPU_PM_EXIT:
1851 case CPU_PM_ENTER_FAILED:
1852 etm4_cpu_restore(drvdata);
1853 break;
1854 default:
1855 return NOTIFY_DONE;
1856 }
1857
1858 return NOTIFY_OK;
1859 }
1860
1861 static struct notifier_block etm4_cpu_pm_nb = {
1862 .notifier_call = etm4_cpu_pm_notify,
1863 };
1864
1865 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)1866 static int __init etm4_pm_setup(void)
1867 {
1868 int ret;
1869
1870 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1871 if (ret)
1872 return ret;
1873
1874 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1875 "arm/coresight4:starting",
1876 etm4_starting_cpu, etm4_dying_cpu);
1877
1878 if (ret)
1879 goto unregister_notifier;
1880
1881 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1882 "arm/coresight4:online",
1883 etm4_online_cpu, NULL);
1884
1885 /* HP dyn state ID returned in ret on success */
1886 if (ret > 0) {
1887 hp_online = ret;
1888 return 0;
1889 }
1890
1891 /* failed dyn state - remove others */
1892 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1893
1894 unregister_notifier:
1895 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1896 return ret;
1897 }
1898
etm4_pm_clear(void)1899 static void etm4_pm_clear(void)
1900 {
1901 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1902 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1903 if (hp_online) {
1904 cpuhp_remove_state_nocalls(hp_online);
1905 hp_online = 0;
1906 }
1907 }
1908
etm4_probe(struct device * dev,void __iomem * base,u32 etm_pid)1909 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1910 {
1911 int ret;
1912 struct coresight_platform_data *pdata = NULL;
1913 struct etmv4_drvdata *drvdata;
1914 struct coresight_desc desc = { 0 };
1915 struct etm4_init_arg init_arg = { 0 };
1916 u8 major, minor;
1917 char *type_name;
1918
1919 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1920 if (!drvdata)
1921 return -ENOMEM;
1922
1923 dev_set_drvdata(dev, drvdata);
1924
1925 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1926 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1927 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1928
1929 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1930 drvdata->save_state = devm_kmalloc(dev,
1931 sizeof(struct etmv4_save_state), GFP_KERNEL);
1932 if (!drvdata->save_state)
1933 return -ENOMEM;
1934 }
1935
1936 drvdata->base = base;
1937
1938 spin_lock_init(&drvdata->spinlock);
1939
1940 drvdata->cpu = coresight_get_cpu(dev);
1941 if (drvdata->cpu < 0)
1942 return drvdata->cpu;
1943
1944 init_arg.drvdata = drvdata;
1945 init_arg.csa = &desc.access;
1946 init_arg.pid = etm_pid;
1947
1948 if (smp_call_function_single(drvdata->cpu,
1949 etm4_init_arch_data, &init_arg, 1))
1950 dev_err(dev, "ETM arch init failed\n");
1951
1952 if (!drvdata->arch)
1953 return -EINVAL;
1954
1955 /* TRCPDCR is not accessible with system instructions. */
1956 if (!desc.access.io_mem ||
1957 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1958 drvdata->skip_power_up = true;
1959
1960 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1961 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1962
1963 if (etm4x_is_ete(drvdata)) {
1964 type_name = "ete";
1965 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1966 major -= 4;
1967 } else {
1968 type_name = "etm";
1969 }
1970
1971 desc.name = devm_kasprintf(dev, GFP_KERNEL,
1972 "%s%d", type_name, drvdata->cpu);
1973 if (!desc.name)
1974 return -ENOMEM;
1975
1976 etm4_init_trace_id(drvdata);
1977 etm4_set_default(&drvdata->config);
1978
1979 pdata = coresight_get_platform_data(dev);
1980 if (IS_ERR(pdata))
1981 return PTR_ERR(pdata);
1982
1983 dev->platform_data = pdata;
1984
1985 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1986 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1987 desc.ops = &etm4_cs_ops;
1988 desc.pdata = pdata;
1989 desc.dev = dev;
1990 desc.groups = coresight_etmv4_groups;
1991 drvdata->csdev = coresight_register(&desc);
1992 if (IS_ERR(drvdata->csdev))
1993 return PTR_ERR(drvdata->csdev);
1994
1995 ret = etm_perf_symlink(drvdata->csdev, true);
1996 if (ret) {
1997 coresight_unregister(drvdata->csdev);
1998 return ret;
1999 }
2000
2001 /* register with config infrastructure & load any current features */
2002 ret = etm4_cscfg_register(drvdata->csdev);
2003 if (ret) {
2004 coresight_unregister(drvdata->csdev);
2005 return ret;
2006 }
2007
2008 etmdrvdata[drvdata->cpu] = drvdata;
2009
2010 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2011 drvdata->cpu, type_name, major, minor);
2012
2013 if (boot_enable) {
2014 coresight_enable(drvdata->csdev);
2015 drvdata->boot_enable = true;
2016 }
2017
2018 return 0;
2019 }
2020
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2021 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2022 {
2023 void __iomem *base;
2024 struct device *dev = &adev->dev;
2025 struct resource *res = &adev->res;
2026 int ret;
2027
2028 /* Validity for the resource is already checked by the AMBA core */
2029 base = devm_ioremap_resource(dev, res);
2030 if (IS_ERR(base))
2031 return PTR_ERR(base);
2032
2033 ret = etm4_probe(dev, base, id->id);
2034 if (!ret)
2035 pm_runtime_put(&adev->dev);
2036
2037 return ret;
2038 }
2039
etm4_probe_platform_dev(struct platform_device * pdev)2040 static int etm4_probe_platform_dev(struct platform_device *pdev)
2041 {
2042 int ret;
2043
2044 pm_runtime_get_noresume(&pdev->dev);
2045 pm_runtime_set_active(&pdev->dev);
2046 pm_runtime_enable(&pdev->dev);
2047
2048 /*
2049 * System register based devices could match the
2050 * HW by reading appropriate registers on the HW
2051 * and thus we could skip the PID.
2052 */
2053 ret = etm4_probe(&pdev->dev, NULL, 0);
2054
2055 pm_runtime_put(&pdev->dev);
2056 return ret;
2057 }
2058
2059 static struct amba_cs_uci_id uci_id_etm4[] = {
2060 {
2061 /* ETMv4 UCI data */
2062 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2063 .devarch_mask = ETM_DEVARCH_ID_MASK,
2064 .devtype = 0x00000013,
2065 }
2066 };
2067
clear_etmdrvdata(void * info)2068 static void clear_etmdrvdata(void *info)
2069 {
2070 int cpu = *(int *)info;
2071
2072 etmdrvdata[cpu] = NULL;
2073 }
2074
etm4_remove_dev(struct etmv4_drvdata * drvdata)2075 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2076 {
2077 etm_perf_symlink(drvdata->csdev, false);
2078 /*
2079 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2080 * and CPU hotplug call backs.
2081 */
2082 cpus_read_lock();
2083 /*
2084 * The readers for etmdrvdata[] are CPU hotplug call backs
2085 * and PM notification call backs. Change etmdrvdata[i] on
2086 * CPU i ensures these call backs has consistent view
2087 * inside one call back function.
2088 */
2089 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2090 etmdrvdata[drvdata->cpu] = NULL;
2091
2092 cpus_read_unlock();
2093
2094 cscfg_unregister_csdev(drvdata->csdev);
2095 coresight_unregister(drvdata->csdev);
2096
2097 }
2098
etm4_remove_amba(struct amba_device * adev)2099 static void etm4_remove_amba(struct amba_device *adev)
2100 {
2101 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2102
2103 if (drvdata)
2104 etm4_remove_dev(drvdata);
2105 }
2106
etm4_remove_platform_dev(struct platform_device * pdev)2107 static int etm4_remove_platform_dev(struct platform_device *pdev)
2108 {
2109 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2110
2111 if (drvdata)
2112 etm4_remove_dev(drvdata);
2113 pm_runtime_disable(&pdev->dev);
2114 return 0;
2115 }
2116
2117 static const struct amba_id etm4_ids[] = {
2118 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2119 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2120 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2121 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2122 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2123 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2124 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2125 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2126 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2127 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2128 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2129 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2130 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2131 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2132 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2133 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2134 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2135 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2136 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2137 {},
2138 };
2139
2140 MODULE_DEVICE_TABLE(amba, etm4_ids);
2141
2142 static struct amba_driver etm4x_amba_driver = {
2143 .drv = {
2144 .name = "coresight-etm4x",
2145 .owner = THIS_MODULE,
2146 .suppress_bind_attrs = true,
2147 },
2148 .probe = etm4_probe_amba,
2149 .remove = etm4_remove_amba,
2150 .id_table = etm4_ids,
2151 };
2152
2153 static const struct of_device_id etm4_sysreg_match[] = {
2154 { .compatible = "arm,coresight-etm4x-sysreg" },
2155 { .compatible = "arm,embedded-trace-extension" },
2156 {}
2157 };
2158
2159 static struct platform_driver etm4_platform_driver = {
2160 .probe = etm4_probe_platform_dev,
2161 .remove = etm4_remove_platform_dev,
2162 .driver = {
2163 .name = "coresight-etm4x",
2164 .of_match_table = etm4_sysreg_match,
2165 .suppress_bind_attrs = true,
2166 },
2167 };
2168
etm4x_init(void)2169 static int __init etm4x_init(void)
2170 {
2171 int ret;
2172
2173 ret = etm4_pm_setup();
2174
2175 /* etm4_pm_setup() does its own cleanup - exit on error */
2176 if (ret)
2177 return ret;
2178
2179 ret = amba_driver_register(&etm4x_amba_driver);
2180 if (ret) {
2181 pr_err("Error registering etm4x AMBA driver\n");
2182 goto clear_pm;
2183 }
2184
2185 ret = platform_driver_register(&etm4_platform_driver);
2186 if (!ret)
2187 return 0;
2188
2189 pr_err("Error registering etm4x platform driver\n");
2190 amba_driver_unregister(&etm4x_amba_driver);
2191
2192 clear_pm:
2193 etm4_pm_clear();
2194 return ret;
2195 }
2196
etm4x_exit(void)2197 static void __exit etm4x_exit(void)
2198 {
2199 amba_driver_unregister(&etm4x_amba_driver);
2200 platform_driver_unregister(&etm4_platform_driver);
2201 etm4_pm_clear();
2202 }
2203
2204 module_init(etm4x_init);
2205 module_exit(etm4x_exit);
2206
2207 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2208 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2209 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2210 MODULE_LICENSE("GPL v2");
2211