1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "hdmi.h"
27 #include "head.h"
28 #include "ior.h"
29
30 #include <nvif/class.h>
31
32 void
g84_sor_hdmi_ctrl(struct nvkm_ior * ior,int head,bool enable,u8 max_ac_packet,u8 rekey,u8 * avi,u8 avi_size,u8 * vendor,u8 vendor_size)33 g84_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
34 u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size)
35 {
36 struct nvkm_device *device = ior->disp->engine.subdev.device;
37 const u32 ctrl = 0x40000000 * enable |
38 0x1f000000 /* ??? */ |
39 max_ac_packet << 16 |
40 rekey;
41 const u32 hoff = head * 0x800;
42 struct packed_hdmi_infoframe avi_infoframe;
43 struct packed_hdmi_infoframe vendor_infoframe;
44
45 pack_hdmi_infoframe(&avi_infoframe, avi, avi_size);
46 pack_hdmi_infoframe(&vendor_infoframe, vendor, vendor_size);
47
48 if (!(ctrl & 0x40000000)) {
49 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);
50 nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000);
51 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
52 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
53 return;
54 }
55
56 /* AVI InfoFrame */
57 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
58 if (avi_size) {
59 nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header);
60 nvkm_wr32(device, 0x61652c + hoff, avi_infoframe.subpack0_low);
61 nvkm_wr32(device, 0x616530 + hoff, avi_infoframe.subpack0_high);
62 nvkm_wr32(device, 0x616534 + hoff, avi_infoframe.subpack1_low);
63 nvkm_wr32(device, 0x616538 + hoff, avi_infoframe.subpack1_high);
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);
65 }
66
67 /* Audio InfoFrame */
68 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
69 nvkm_wr32(device, 0x616508 + hoff, 0x000a0184);
70 nvkm_wr32(device, 0x61650c + hoff, 0x00000071);
71 nvkm_wr32(device, 0x616510 + hoff, 0x00000000);
72 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);
73
74 /* Vendor InfoFrame */
75 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000);
76 if (vendor_size) {
77 nvkm_wr32(device, 0x616544 + hoff, vendor_infoframe.header);
78 nvkm_wr32(device, 0x616548 + hoff, vendor_infoframe.subpack0_low);
79 nvkm_wr32(device, 0x61654c + hoff, vendor_infoframe.subpack0_high);
80 /* Is there a second (or up to fourth?) set of subpack registers here? */
81 /* nvkm_wr32(device, 0x616550 + hoff, vendor_infoframe->subpack1_low); */
82 /* nvkm_wr32(device, 0x616554 + hoff, vendor_infoframe->subpack1_high); */
83 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001);
84 }
85
86 nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
87 nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
88 nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
89
90 /* ??? */
91 nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
92 nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
93 nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
94
95 /* HDMI_CTRL */
96 nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
97 }
98
99 static const struct nvkm_ior_func
100 g84_sor = {
101 .state = nv50_sor_state,
102 .power = nv50_sor_power,
103 .clock = nv50_sor_clock,
104 .hdmi = {
105 .ctrl = g84_sor_hdmi_ctrl,
106 },
107 };
108
109 int
g84_sor_new(struct nvkm_disp * disp,int id)110 g84_sor_new(struct nvkm_disp *disp, int id)
111 {
112 return nvkm_ior_new_(&g84_sor, disp, SOR, id, false);
113 }
114
115 static const struct nvkm_disp_mthd_list
116 g84_disp_ovly_mthd_base = {
117 .mthd = 0x0000,
118 .addr = 0x000000,
119 .data = {
120 { 0x0080, 0x000000 },
121 { 0x0084, 0x6109a0 },
122 { 0x0088, 0x6109c0 },
123 { 0x008c, 0x6109c8 },
124 { 0x0090, 0x6109b4 },
125 { 0x0094, 0x610970 },
126 { 0x00a0, 0x610998 },
127 { 0x00a4, 0x610964 },
128 { 0x00c0, 0x610958 },
129 { 0x00e0, 0x6109a8 },
130 { 0x00e4, 0x6109d0 },
131 { 0x00e8, 0x6109d8 },
132 { 0x0100, 0x61094c },
133 { 0x0104, 0x610984 },
134 { 0x0108, 0x61098c },
135 { 0x0800, 0x6109f8 },
136 { 0x0808, 0x610a08 },
137 { 0x080c, 0x610a10 },
138 { 0x0810, 0x610a00 },
139 {}
140 }
141 };
142
143 static const struct nvkm_disp_chan_mthd
144 g84_disp_ovly_mthd = {
145 .name = "Overlay",
146 .addr = 0x000540,
147 .prev = 0x000004,
148 .data = {
149 { "Global", 1, &g84_disp_ovly_mthd_base },
150 {}
151 }
152 };
153
154 const struct nvkm_disp_chan_user
155 g84_disp_ovly = {
156 .func = &nv50_disp_dmac_func,
157 .ctrl = 3,
158 .user = 3,
159 .mthd = &g84_disp_ovly_mthd,
160 };
161
162 static const struct nvkm_disp_mthd_list
163 g84_disp_base_mthd_base = {
164 .mthd = 0x0000,
165 .addr = 0x000000,
166 .data = {
167 { 0x0080, 0x000000 },
168 { 0x0084, 0x0008c4 },
169 { 0x0088, 0x0008d0 },
170 { 0x008c, 0x0008dc },
171 { 0x0090, 0x0008e4 },
172 { 0x0094, 0x610884 },
173 { 0x00a0, 0x6108a0 },
174 { 0x00a4, 0x610878 },
175 { 0x00c0, 0x61086c },
176 { 0x00c4, 0x610800 },
177 { 0x00c8, 0x61080c },
178 { 0x00cc, 0x610818 },
179 { 0x00e0, 0x610858 },
180 { 0x00e4, 0x610860 },
181 { 0x00e8, 0x6108ac },
182 { 0x00ec, 0x6108b4 },
183 { 0x00fc, 0x610824 },
184 { 0x0100, 0x610894 },
185 { 0x0104, 0x61082c },
186 { 0x0110, 0x6108bc },
187 { 0x0114, 0x61088c },
188 {}
189 }
190 };
191
192 static const struct nvkm_disp_chan_mthd
193 g84_disp_base_mthd = {
194 .name = "Base",
195 .addr = 0x000540,
196 .prev = 0x000004,
197 .data = {
198 { "Global", 1, &g84_disp_base_mthd_base },
199 { "Image", 2, &nv50_disp_base_mthd_image },
200 {}
201 }
202 };
203
204 const struct nvkm_disp_chan_user
205 g84_disp_base = {
206 .func = &nv50_disp_dmac_func,
207 .ctrl = 1,
208 .user = 1,
209 .mthd = &g84_disp_base_mthd,
210 };
211
212 const struct nvkm_disp_mthd_list
213 g84_disp_core_mthd_dac = {
214 .mthd = 0x0080,
215 .addr = 0x000008,
216 .data = {
217 { 0x0400, 0x610b58 },
218 { 0x0404, 0x610bdc },
219 { 0x0420, 0x610bc4 },
220 {}
221 }
222 };
223
224 const struct nvkm_disp_mthd_list
225 g84_disp_core_mthd_head = {
226 .mthd = 0x0400,
227 .addr = 0x000540,
228 .data = {
229 { 0x0800, 0x610ad8 },
230 { 0x0804, 0x610ad0 },
231 { 0x0808, 0x610a48 },
232 { 0x080c, 0x610a78 },
233 { 0x0810, 0x610ac0 },
234 { 0x0814, 0x610af8 },
235 { 0x0818, 0x610b00 },
236 { 0x081c, 0x610ae8 },
237 { 0x0820, 0x610af0 },
238 { 0x0824, 0x610b08 },
239 { 0x0828, 0x610b10 },
240 { 0x082c, 0x610a68 },
241 { 0x0830, 0x610a60 },
242 { 0x0834, 0x000000 },
243 { 0x0838, 0x610a40 },
244 { 0x0840, 0x610a24 },
245 { 0x0844, 0x610a2c },
246 { 0x0848, 0x610aa8 },
247 { 0x084c, 0x610ab0 },
248 { 0x085c, 0x610c5c },
249 { 0x0860, 0x610a84 },
250 { 0x0864, 0x610a90 },
251 { 0x0868, 0x610b18 },
252 { 0x086c, 0x610b20 },
253 { 0x0870, 0x610ac8 },
254 { 0x0874, 0x610a38 },
255 { 0x0878, 0x610c50 },
256 { 0x0880, 0x610a58 },
257 { 0x0884, 0x610a9c },
258 { 0x089c, 0x610c68 },
259 { 0x08a0, 0x610a70 },
260 { 0x08a4, 0x610a50 },
261 { 0x08a8, 0x610ae0 },
262 { 0x08c0, 0x610b28 },
263 { 0x08c4, 0x610b30 },
264 { 0x08c8, 0x610b40 },
265 { 0x08d4, 0x610b38 },
266 { 0x08d8, 0x610b48 },
267 { 0x08dc, 0x610b50 },
268 { 0x0900, 0x610a18 },
269 { 0x0904, 0x610ab8 },
270 { 0x0910, 0x610c70 },
271 { 0x0914, 0x610c78 },
272 {}
273 }
274 };
275
276 const struct nvkm_disp_chan_mthd
277 g84_disp_core_mthd = {
278 .name = "Core",
279 .addr = 0x000000,
280 .prev = 0x000004,
281 .data = {
282 { "Global", 1, &nv50_disp_core_mthd_base },
283 { "DAC", 3, &g84_disp_core_mthd_dac },
284 { "SOR", 2, &nv50_disp_core_mthd_sor },
285 { "PIOR", 3, &nv50_disp_core_mthd_pior },
286 { "HEAD", 2, &g84_disp_core_mthd_head },
287 {}
288 }
289 };
290
291 const struct nvkm_disp_chan_user
292 g84_disp_core = {
293 .func = &nv50_disp_core_func,
294 .ctrl = 0,
295 .user = 0,
296 .mthd = &g84_disp_core_mthd,
297 };
298
299 static const struct nvkm_disp_func
300 g84_disp = {
301 .oneinit = nv50_disp_oneinit,
302 .init = nv50_disp_init,
303 .fini = nv50_disp_fini,
304 .intr = nv50_disp_intr,
305 .super = nv50_disp_super,
306 .uevent = &nv50_disp_chan_uevent,
307 .head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
308 .dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
309 .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
310 .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
311 .root = { 0,0,G82_DISP },
312 .user = {
313 {{0,0,G82_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs },
314 {{0,0,G82_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm },
315 {{0,0,G82_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },
316 {{0,0,G82_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g84_disp_core },
317 {{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },
318 {}
319 },
320 };
321
322 int
g84_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)323 g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
324 struct nvkm_disp **pdisp)
325 {
326 return nvkm_disp_new_(&g84_disp, device, type, inst, pdisp);
327 }
328