1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "changk104.h"
25 #include "cgrp.h"
26
27 #include <core/client.h>
28 #include <core/gpuobj.h>
29 #include <subdev/fb.h>
30 #include <subdev/mmu.h>
31 #include <subdev/timer.h>
32
33 #include <nvif/class.h>
34 #include <nvif/cla06f.h>
35 #include <nvif/unpack.h>
36
37 int
gk104_fifo_gpfifo_kick_locked(struct gk104_fifo_chan * chan)38 gk104_fifo_gpfifo_kick_locked(struct gk104_fifo_chan *chan)
39 {
40 struct gk104_fifo *fifo = chan->fifo;
41 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
42 struct nvkm_device *device = subdev->device;
43 struct nvkm_client *client = chan->base.object.client;
44 struct nvkm_fifo_cgrp *cgrp = chan->cgrp;
45 int ret = 0;
46
47 if (cgrp)
48 nvkm_wr32(device, 0x002634, cgrp->id | 0x01000000);
49 else
50 nvkm_wr32(device, 0x002634, chan->base.chid);
51 if (nvkm_msec(device, 2000,
52 if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
53 break;
54 ) < 0) {
55 nvkm_error(subdev, "%s %d [%s] kick timeout\n",
56 cgrp ? "tsg" : "channel",
57 cgrp ? cgrp->id : chan->base.chid, client->name);
58 nvkm_fifo_recover_chan(&fifo->base, chan->base.chid);
59 ret = -ETIMEDOUT;
60 }
61 return ret;
62 }
63
64 int
gk104_fifo_gpfifo_kick(struct gk104_fifo_chan * chan)65 gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
66 {
67 int ret;
68 mutex_lock(&chan->base.fifo->mutex);
69 ret = gk104_fifo_gpfifo_kick_locked(chan);
70 mutex_unlock(&chan->base.fifo->mutex);
71 return ret;
72 }
73
74 static u32
gk104_fifo_gpfifo_engine_addr(struct nvkm_engine * engine)75 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
76 {
77 switch (engine->subdev.type) {
78 case NVKM_ENGINE_SW :
79 case NVKM_ENGINE_CE : return 0;
80 case NVKM_ENGINE_GR : return 0x0210;
81 case NVKM_ENGINE_SEC : return 0x0220;
82 case NVKM_ENGINE_MSPDEC: return 0x0250;
83 case NVKM_ENGINE_MSPPP : return 0x0260;
84 case NVKM_ENGINE_MSVLD : return 0x0270;
85 case NVKM_ENGINE_VIC : return 0x0280;
86 case NVKM_ENGINE_MSENC : return 0x0290;
87 case NVKM_ENGINE_NVDEC : return 0x02100270;
88 case NVKM_ENGINE_NVENC :
89 if (engine->subdev.inst)
90 return 0x0210;
91 return 0x02100290;
92 default:
93 WARN_ON(1);
94 return 0;
95 }
96 }
97
98 struct gk104_fifo_engn *
gk104_fifo_gpfifo_engine(struct gk104_fifo_chan * chan,struct nvkm_engine * engine)99 gk104_fifo_gpfifo_engine(struct gk104_fifo_chan *chan, struct nvkm_engine *engine)
100 {
101 int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine);
102 if (engi >= 0)
103 return &chan->engn[engi];
104 return NULL;
105 }
106
107 static int
gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,bool suspend)108 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
109 struct nvkm_engine *engine, bool suspend)
110 {
111 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
112 struct nvkm_gpuobj *inst = chan->base.inst;
113 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
114 int ret;
115
116 ret = gk104_fifo_gpfifo_kick(chan);
117 if (ret && suspend)
118 return ret;
119
120 if (offset) {
121 nvkm_kmap(inst);
122 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
123 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
124 if ((offset >>= 16)) {
125 nvkm_wo32(inst, offset + 0x00, 0x00000000);
126 nvkm_wo32(inst, offset + 0x04, 0x00000000);
127 }
128 nvkm_done(inst);
129 }
130
131 return ret;
132 }
133
134 static int
gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)135 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
136 struct nvkm_engine *engine)
137 {
138 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
139 struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
140 struct nvkm_gpuobj *inst = chan->base.inst;
141 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
142
143 if (offset) {
144 u32 datalo = lower_32_bits(engn->vma->addr) | 0x00000004;
145 u32 datahi = upper_32_bits(engn->vma->addr);
146 nvkm_kmap(inst);
147 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
148 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
149 if ((offset >>= 16)) {
150 nvkm_wo32(inst, offset + 0x00, datalo);
151 nvkm_wo32(inst, offset + 0x04, datahi);
152 }
153 nvkm_done(inst);
154 }
155
156 return 0;
157 }
158
159 void
gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)160 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
161 struct nvkm_engine *engine)
162 {
163 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
164 struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
165 nvkm_vmm_put(chan->base.vmm, &engn->vma);
166 nvkm_gpuobj_del(&engn->inst);
167 }
168
169 int
gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,struct nvkm_object * object)170 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
171 struct nvkm_engine *engine,
172 struct nvkm_object *object)
173 {
174 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
175 struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
176 int ret;
177
178 if (!gk104_fifo_gpfifo_engine_addr(engine)) {
179 if (engine->subdev.type != NVKM_ENGINE_CE ||
180 engine->subdev.device->card_type < GV100)
181 return 0;
182 }
183
184 ret = nvkm_object_bind(object, NULL, 0, &engn->inst);
185 if (ret)
186 return ret;
187
188 if (!gk104_fifo_gpfifo_engine_addr(engine))
189 return 0;
190
191 ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma);
192 if (ret)
193 return ret;
194
195 return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0);
196 }
197
198 void
gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan * base)199 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
200 {
201 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
202 struct gk104_fifo *fifo = chan->fifo;
203 struct nvkm_device *device = fifo->base.engine.subdev.device;
204 u32 coff = chan->base.chid * 8;
205
206 if (!list_empty(&chan->head)) {
207 gk104_fifo_runlist_remove(fifo, chan);
208 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
209 gk104_fifo_gpfifo_kick(chan);
210 gk104_fifo_runlist_update(fifo, chan->runl);
211 }
212
213 nvkm_wr32(device, 0x800000 + coff, 0x00000000);
214 }
215
216 void
gk104_fifo_gpfifo_init(struct nvkm_fifo_chan * base)217 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
218 {
219 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
220 struct gk104_fifo *fifo = chan->fifo;
221 struct nvkm_device *device = fifo->base.engine.subdev.device;
222 u32 addr = chan->base.inst->addr >> 12;
223 u32 coff = chan->base.chid * 8;
224
225 nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
226 nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
227
228 if (list_empty(&chan->head) && !chan->killed) {
229 gk104_fifo_runlist_insert(fifo, chan);
230 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
231 gk104_fifo_runlist_update(fifo, chan->runl);
232 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
233 }
234 }
235
236 void *
gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan * base)237 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
238 {
239 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
240 kfree(chan->cgrp);
241 return chan;
242 }
243
244 const struct nvkm_fifo_chan_func
245 gk104_fifo_gpfifo_func = {
246 .dtor = gk104_fifo_gpfifo_dtor,
247 .init = gk104_fifo_gpfifo_init,
248 .fini = gk104_fifo_gpfifo_fini,
249 .ntfy = gf100_fifo_chan_ntfy,
250 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
251 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
252 .engine_init = gk104_fifo_gpfifo_engine_init,
253 .engine_fini = gk104_fifo_gpfifo_engine_fini,
254 };
255
256 static int
gk104_fifo_gpfifo_new_(struct gk104_fifo * fifo,u64 * runlists,u16 * chid,u64 vmm,u64 ioffset,u64 ilength,u64 * inst,bool priv,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)257 gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
258 u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv,
259 const struct nvkm_oclass *oclass,
260 struct nvkm_object **pobject)
261 {
262 struct gk104_fifo_chan *chan;
263 int runlist = ffs(*runlists) -1, ret, i;
264 u64 usermem;
265
266 if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
267 return -EINVAL;
268 *runlists = BIT_ULL(runlist);
269
270 /* Allocate the channel. */
271 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
272 return -ENOMEM;
273 *pobject = &chan->base.object;
274 chan->fifo = fifo;
275 chan->runl = runlist;
276 INIT_LIST_HEAD(&chan->head);
277
278 ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
279 0x1000, 0x1000, true, vmm, 0, fifo->runlist[runlist].engm_sw,
280 1, fifo->user.bar->addr, 0x200,
281 oclass, &chan->base);
282 if (ret)
283 return ret;
284
285 *chid = chan->base.chid;
286 *inst = chan->base.inst->addr;
287
288 /* Hack to support GPUs where even individual channels should be
289 * part of a channel group.
290 */
291 if (fifo->func->cgrp_force) {
292 if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
293 return -ENOMEM;
294 chan->cgrp->id = chan->base.chid;
295 INIT_LIST_HEAD(&chan->cgrp->head);
296 INIT_LIST_HEAD(&chan->cgrp->chan);
297 chan->cgrp->chan_nr = 0;
298 }
299
300 /* Clear channel control registers. */
301 usermem = chan->base.chid * 0x200;
302 ilength = order_base_2(ilength / 8);
303
304 nvkm_kmap(fifo->user.mem);
305 for (i = 0; i < 0x200; i += 4)
306 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
307 nvkm_done(fifo->user.mem);
308 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
309
310 /* RAMFC */
311 nvkm_kmap(chan->base.inst);
312 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
313 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
314 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
315 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
316 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
317 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
318 (ilength << 16));
319 nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
320 nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
321 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
322 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
323 nvkm_wo32(chan->base.inst, 0xe4, priv ? 0x00000020 : 0x00000000);
324 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
325 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
326 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
327 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
328 nvkm_done(chan->base.inst);
329 return 0;
330 }
331
332 int
gk104_fifo_gpfifo_new(struct gk104_fifo * fifo,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)333 gk104_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass,
334 void *data, u32 size, struct nvkm_object **pobject)
335 {
336 struct nvkm_object *parent = oclass->parent;
337 union {
338 struct kepler_channel_gpfifo_a_v0 v0;
339 } *args = data;
340 int ret = -ENOSYS;
341
342 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
343 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
344 nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
345 "ioffset %016llx ilength %08x "
346 "runlist %016llx priv %d\n",
347 args->v0.version, args->v0.vmm, args->v0.ioffset,
348 args->v0.ilength, args->v0.runlist, args->v0.priv);
349 return gk104_fifo_gpfifo_new_(fifo,
350 &args->v0.runlist,
351 &args->v0.chid,
352 args->v0.vmm,
353 args->v0.ioffset,
354 args->v0.ilength,
355 &args->v0.inst,
356 args->v0.priv,
357 oclass, pobject);
358 }
359
360 return ret;
361 }
362