1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "hdmi.h"
27 #include "head.h"
28 #include "ior.h"
29
30 #include <subdev/timer.h>
31
32 #include <nvif/class.h>
33
34 static void
gt215_sor_hda_eld(struct nvkm_ior * ior,int head,u8 * data,u8 size)35 gt215_sor_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size)
36 {
37 struct nvkm_device *device = ior->disp->engine.subdev.device;
38 const u32 soff = ior->id * 0x800;
39 int i;
40
41 for (i = 0; i < size; i++)
42 nvkm_wr32(device, 0x61c440 + soff, (i << 8) | data[i]);
43 for (; i < 0x60; i++)
44 nvkm_wr32(device, 0x61c440 + soff, (i << 8));
45 nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002);
46 }
47
48 static void
gt215_sor_hda_hpd(struct nvkm_ior * ior,int head,bool present)49 gt215_sor_hda_hpd(struct nvkm_ior *ior, int head, bool present)
50 {
51 struct nvkm_device *device = ior->disp->engine.subdev.device;
52 u32 data = 0x80000000;
53 u32 mask = 0x80000001;
54 if (present)
55 data |= 0x00000001;
56 else
57 mask |= 0x00000002;
58 nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data);
59 }
60
61 const struct nvkm_ior_func_hda
62 gt215_sor_hda = {
63 .hpd = gt215_sor_hda_hpd,
64 .eld = gt215_sor_hda_eld,
65 };
66
67 void
gt215_sor_dp_audio(struct nvkm_ior * sor,int head,bool enable)68 gt215_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
69 {
70 struct nvkm_device *device = sor->disp->engine.subdev.device;
71 const u32 soff = nv50_ior_base(sor);
72 const u32 data = 0x80000000 | (0x00000001 * enable);
73 const u32 mask = 0x8000000d;
74
75 nvkm_mask(device, 0x61c1e0 + soff, mask, data);
76 nvkm_msec(device, 2000,
77 if (!(nvkm_rd32(device, 0x61c1e0 + soff) & 0x80000000))
78 break;
79 );
80 }
81
82 static const struct nvkm_ior_func_dp
83 gt215_sor_dp = {
84 .lanes = { 2, 1, 0, 3 },
85 .links = g94_sor_dp_links,
86 .power = g94_sor_dp_power,
87 .pattern = g94_sor_dp_pattern,
88 .drive = g94_sor_dp_drive,
89 .audio = gt215_sor_dp_audio,
90 .audio_sym = g94_sor_dp_audio_sym,
91 .activesym = g94_sor_dp_activesym,
92 .watermark = g94_sor_dp_watermark,
93 };
94
95 void
gt215_sor_hdmi_ctrl(struct nvkm_ior * ior,int head,bool enable,u8 max_ac_packet,u8 rekey,u8 * avi,u8 avi_size,u8 * vendor,u8 vendor_size)96 gt215_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
97 u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size)
98 {
99 struct nvkm_device *device = ior->disp->engine.subdev.device;
100 const u32 ctrl = 0x40000000 * enable |
101 0x1f000000 /* ??? */ |
102 max_ac_packet << 16 |
103 rekey;
104 const u32 soff = nv50_ior_base(ior);
105 struct packed_hdmi_infoframe avi_infoframe;
106 struct packed_hdmi_infoframe vendor_infoframe;
107
108 pack_hdmi_infoframe(&avi_infoframe, avi, avi_size);
109 pack_hdmi_infoframe(&vendor_infoframe, vendor, vendor_size);
110
111 if (!(ctrl & 0x40000000)) {
112 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000);
113 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000);
114 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
115 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
116 return;
117 }
118
119 /* AVI InfoFrame */
120 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
121 if (avi_size) {
122 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header);
123 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low);
124 nvkm_wr32(device, 0x61c530 + soff, avi_infoframe.subpack0_high);
125 nvkm_wr32(device, 0x61c534 + soff, avi_infoframe.subpack1_low);
126 nvkm_wr32(device, 0x61c538 + soff, avi_infoframe.subpack1_high);
127 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001);
128 }
129
130 /* Audio InfoFrame */
131 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
132 nvkm_wr32(device, 0x61c508 + soff, 0x000a0184);
133 nvkm_wr32(device, 0x61c50c + soff, 0x00000071);
134 nvkm_wr32(device, 0x61c510 + soff, 0x00000000);
135 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001);
136
137 /* Vendor InfoFrame */
138 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010000);
139 if (vendor_size) {
140 nvkm_wr32(device, 0x61c544 + soff, vendor_infoframe.header);
141 nvkm_wr32(device, 0x61c548 + soff, vendor_infoframe.subpack0_low);
142 nvkm_wr32(device, 0x61c54c + soff, vendor_infoframe.subpack0_high);
143 /* Is there a second (or up to fourth?) set of subpack registers here? */
144 /* nvkm_wr32(device, 0x61c550 + soff, vendor_infoframe.subpack1_low); */
145 /* nvkm_wr32(device, 0x61c554 + soff, vendor_infoframe.subpack1_high); */
146 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010001);
147 }
148
149 nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
150 nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
151 nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
152
153 /* ??? */
154 nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
155 nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
156 nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
157
158 /* HDMI_CTRL */
159 nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
160 }
161
162 static const struct nvkm_ior_func
163 gt215_sor = {
164 .state = g94_sor_state,
165 .power = nv50_sor_power,
166 .clock = nv50_sor_clock,
167 .hdmi = {
168 .ctrl = gt215_sor_hdmi_ctrl,
169 },
170 .dp = >215_sor_dp,
171 .hda = >215_sor_hda,
172 };
173
174 static int
gt215_sor_new(struct nvkm_disp * disp,int id)175 gt215_sor_new(struct nvkm_disp *disp, int id)
176 {
177 return nvkm_ior_new_(>215_sor, disp, SOR, id, true);
178 }
179
180 static const struct nvkm_disp_func
181 gt215_disp = {
182 .oneinit = nv50_disp_oneinit,
183 .init = nv50_disp_init,
184 .fini = nv50_disp_fini,
185 .intr = nv50_disp_intr,
186 .super = nv50_disp_super,
187 .uevent = &nv50_disp_chan_uevent,
188 .head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
189 .dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
190 .sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
191 .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
192 .root = { 0,0,GT214_DISP },
193 .user = {
194 {{0,0,GT214_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },
195 {{0,0,GT214_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },
196 {{0,0,GT214_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },
197 {{0,0,GT214_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g94_disp_core },
198 {{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },
199 {}
200 },
201 };
202
203 int
gt215_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)204 gt215_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
205 struct nvkm_disp **pdisp)
206 {
207 return nvkm_disp_new_(>215_disp, device, type, inst, pdisp);
208 }
209