1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/aer.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/pkt_cls.h>
23 #include <net/tcp.h>
24 #include <net/vxlan.h>
25 #include <net/geneve.h>
26
27 #include "hnae3.h"
28 #include "hns3_enet.h"
29 /* All hns3 tracepoints are defined by the include below, which
30 * must be included exactly once across the whole kernel with
31 * CREATE_TRACE_POINTS defined
32 */
33 #define CREATE_TRACE_POINTS
34 #include "hns3_trace.h"
35
36 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
37 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
38
39 #define hns3_rl_err(fmt, ...) \
40 do { \
41 if (net_ratelimit()) \
42 netdev_err(fmt, ##__VA_ARGS__); \
43 } while (0)
44
45 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
46
47 static const char hns3_driver_name[] = "hns3";
48 static const char hns3_driver_string[] =
49 "Hisilicon Ethernet Network Driver for Hip08 Family";
50 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
51 static struct hnae3_client client;
52
53 static int debug = -1;
54 module_param(debug, int, 0);
55 MODULE_PARM_DESC(debug, " Network interface message level setting");
56
57 static unsigned int tx_sgl = 1;
58 module_param(tx_sgl, uint, 0600);
59 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
60
61 static bool page_pool_enabled = true;
62 module_param(page_pool_enabled, bool, 0400);
63
64 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
65 sizeof(struct sg_table))
66 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
67 dma_get_cache_alignment())
68
69 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
70 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
71
72 #define HNS3_INNER_VLAN_TAG 1
73 #define HNS3_OUTER_VLAN_TAG 2
74
75 #define HNS3_MIN_TX_LEN 33U
76 #define HNS3_MIN_TUN_PKT_LEN 65U
77
78 /* hns3_pci_tbl - PCI Device ID Table
79 *
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static const struct pci_device_id hns3_pci_tbl[] = {
86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
89 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
102 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
103 /* required last entry */
104 {0,}
105 };
106 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
107
108 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
109 { ptype, \
110 l, \
111 CHECKSUM_##s, \
112 HNS3_L3_TYPE_##t, \
113 1, \
114 h}
115
116 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
117 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
118 PKT_HASH_TYPE_NONE }
119
120 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
121 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
122 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
123 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
124 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
137 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
138 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
139 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
141 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
142 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
143 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
144 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
145 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
146 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
147 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
150 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
151 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
152 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
153 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
154 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
155 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
156 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
158 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
159 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
160 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
161 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
162 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
163 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
164 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
166 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
167 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
232 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
233 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
234 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
235 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
236 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
237 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
238 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
239 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
240 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
241 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
244 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
245 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
246 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
247 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
248 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
249 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
250 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
252 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
253 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
254 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
255 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
256 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
257 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
258 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
260 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
261 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
377 };
378
379 #define HNS3_INVALID_PTYPE \
380 ARRAY_SIZE(hns3_rx_ptype_tbl)
381
hns3_irq_handle(int irq,void * vector)382 static irqreturn_t hns3_irq_handle(int irq, void *vector)
383 {
384 struct hns3_enet_tqp_vector *tqp_vector = vector;
385
386 napi_schedule_irqoff(&tqp_vector->napi);
387 tqp_vector->event_cnt++;
388
389 return IRQ_HANDLED;
390 }
391
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)392 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
393 {
394 struct hns3_enet_tqp_vector *tqp_vectors;
395 unsigned int i;
396
397 for (i = 0; i < priv->vector_num; i++) {
398 tqp_vectors = &priv->tqp_vector[i];
399
400 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
401 continue;
402
403 /* clear the affinity mask */
404 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
405
406 /* release the irq resource */
407 free_irq(tqp_vectors->vector_irq, tqp_vectors);
408 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
409 }
410 }
411
hns3_nic_init_irq(struct hns3_nic_priv * priv)412 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
413 {
414 struct hns3_enet_tqp_vector *tqp_vectors;
415 int txrx_int_idx = 0;
416 int rx_int_idx = 0;
417 int tx_int_idx = 0;
418 unsigned int i;
419 int ret;
420
421 for (i = 0; i < priv->vector_num; i++) {
422 tqp_vectors = &priv->tqp_vector[i];
423
424 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
425 continue;
426
427 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
428 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
429 "%s-%s-%s-%d", hns3_driver_name,
430 pci_name(priv->ae_handle->pdev),
431 "TxRx", txrx_int_idx++);
432 txrx_int_idx++;
433 } else if (tqp_vectors->rx_group.ring) {
434 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
435 "%s-%s-%s-%d", hns3_driver_name,
436 pci_name(priv->ae_handle->pdev),
437 "Rx", rx_int_idx++);
438 } else if (tqp_vectors->tx_group.ring) {
439 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
440 "%s-%s-%s-%d", hns3_driver_name,
441 pci_name(priv->ae_handle->pdev),
442 "Tx", tx_int_idx++);
443 } else {
444 /* Skip this unused q_vector */
445 continue;
446 }
447
448 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
449
450 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
451 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
452 tqp_vectors->name, tqp_vectors);
453 if (ret) {
454 netdev_err(priv->netdev, "request irq(%d) fail\n",
455 tqp_vectors->vector_irq);
456 hns3_nic_uninit_irq(priv);
457 return ret;
458 }
459
460 irq_set_affinity_hint(tqp_vectors->vector_irq,
461 &tqp_vectors->affinity_mask);
462
463 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
464 }
465
466 return 0;
467 }
468
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)469 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
470 u32 mask_en)
471 {
472 writel(mask_en, tqp_vector->mask_addr);
473 }
474
hns3_vector_enable(struct hns3_enet_tqp_vector * tqp_vector)475 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
476 {
477 napi_enable(&tqp_vector->napi);
478 enable_irq(tqp_vector->vector_irq);
479
480 /* enable vector */
481 hns3_mask_vector_irq(tqp_vector, 1);
482 }
483
hns3_vector_disable(struct hns3_enet_tqp_vector * tqp_vector)484 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
485 {
486 /* disable vector */
487 hns3_mask_vector_irq(tqp_vector, 0);
488
489 disable_irq(tqp_vector->vector_irq);
490 napi_disable(&tqp_vector->napi);
491 cancel_work_sync(&tqp_vector->rx_group.dim.work);
492 cancel_work_sync(&tqp_vector->tx_group.dim.work);
493 }
494
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)495 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
496 u32 rl_value)
497 {
498 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
499
500 /* this defines the configuration for RL (Interrupt Rate Limiter).
501 * Rl defines rate of interrupts i.e. number of interrupts-per-second
502 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
503 */
504 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
505 !tqp_vector->rx_group.coal.adapt_enable)
506 /* According to the hardware, the range of rl_reg is
507 * 0-59 and the unit is 4.
508 */
509 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
510
511 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
512 }
513
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)514 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
515 u32 gl_value)
516 {
517 u32 new_val;
518
519 if (tqp_vector->rx_group.coal.unit_1us)
520 new_val = gl_value | HNS3_INT_GL_1US;
521 else
522 new_val = hns3_gl_usec_to_reg(gl_value);
523
524 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
525 }
526
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)527 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
528 u32 gl_value)
529 {
530 u32 new_val;
531
532 if (tqp_vector->tx_group.coal.unit_1us)
533 new_val = gl_value | HNS3_INT_GL_1US;
534 else
535 new_val = hns3_gl_usec_to_reg(gl_value);
536
537 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
538 }
539
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)540 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
541 u32 ql_value)
542 {
543 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
544 }
545
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)546 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
547 u32 ql_value)
548 {
549 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
550 }
551
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)552 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
553 struct hns3_nic_priv *priv)
554 {
555 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
556 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
557 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
558 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
559 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
560
561 tx_coal->adapt_enable = ptx_coal->adapt_enable;
562 rx_coal->adapt_enable = prx_coal->adapt_enable;
563
564 tx_coal->int_gl = ptx_coal->int_gl;
565 rx_coal->int_gl = prx_coal->int_gl;
566
567 rx_coal->flow_level = prx_coal->flow_level;
568 tx_coal->flow_level = ptx_coal->flow_level;
569
570 /* device version above V3(include V3), GL can configure 1us
571 * unit, so uses 1us unit.
572 */
573 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
574 tx_coal->unit_1us = 1;
575 rx_coal->unit_1us = 1;
576 }
577
578 if (ae_dev->dev_specs.int_ql_max) {
579 tx_coal->ql_enable = 1;
580 rx_coal->ql_enable = 1;
581 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
582 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
583 tx_coal->int_ql = ptx_coal->int_ql;
584 rx_coal->int_ql = prx_coal->int_ql;
585 }
586 }
587
588 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)589 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
590 struct hns3_nic_priv *priv)
591 {
592 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
593 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
594 struct hnae3_handle *h = priv->ae_handle;
595
596 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
597 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
598 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
599
600 if (tx_coal->ql_enable)
601 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
602
603 if (rx_coal->ql_enable)
604 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
605 }
606
hns3_nic_set_real_num_queue(struct net_device * netdev)607 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
608 {
609 struct hnae3_handle *h = hns3_get_handle(netdev);
610 struct hnae3_knic_private_info *kinfo = &h->kinfo;
611 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
612 unsigned int queue_size = kinfo->num_tqps;
613 int i, ret;
614
615 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
616 netdev_reset_tc(netdev);
617 } else {
618 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
619 if (ret) {
620 netdev_err(netdev,
621 "netdev_set_num_tc fail, ret=%d!\n", ret);
622 return ret;
623 }
624
625 for (i = 0; i < tc_info->num_tc; i++)
626 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
627 tc_info->tqp_offset[i]);
628 }
629
630 ret = netif_set_real_num_tx_queues(netdev, queue_size);
631 if (ret) {
632 netdev_err(netdev,
633 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
634 return ret;
635 }
636
637 ret = netif_set_real_num_rx_queues(netdev, queue_size);
638 if (ret) {
639 netdev_err(netdev,
640 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
641 return ret;
642 }
643
644 return 0;
645 }
646
hns3_get_max_available_channels(struct hnae3_handle * h)647 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
648 {
649 u16 alloc_tqps, max_rss_size, rss_size;
650
651 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
652 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
653
654 return min_t(u16, rss_size, max_rss_size);
655 }
656
hns3_tqp_enable(struct hnae3_queue * tqp)657 static void hns3_tqp_enable(struct hnae3_queue *tqp)
658 {
659 u32 rcb_reg;
660
661 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
662 rcb_reg |= BIT(HNS3_RING_EN_B);
663 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
664 }
665
hns3_tqp_disable(struct hnae3_queue * tqp)666 static void hns3_tqp_disable(struct hnae3_queue *tqp)
667 {
668 u32 rcb_reg;
669
670 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
671 rcb_reg &= ~BIT(HNS3_RING_EN_B);
672 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
673 }
674
hns3_free_rx_cpu_rmap(struct net_device * netdev)675 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
676 {
677 #ifdef CONFIG_RFS_ACCEL
678 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
679 netdev->rx_cpu_rmap = NULL;
680 #endif
681 }
682
hns3_set_rx_cpu_rmap(struct net_device * netdev)683 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
684 {
685 #ifdef CONFIG_RFS_ACCEL
686 struct hns3_nic_priv *priv = netdev_priv(netdev);
687 struct hns3_enet_tqp_vector *tqp_vector;
688 int i, ret;
689
690 if (!netdev->rx_cpu_rmap) {
691 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
692 if (!netdev->rx_cpu_rmap)
693 return -ENOMEM;
694 }
695
696 for (i = 0; i < priv->vector_num; i++) {
697 tqp_vector = &priv->tqp_vector[i];
698 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
699 tqp_vector->vector_irq);
700 if (ret) {
701 hns3_free_rx_cpu_rmap(netdev);
702 return ret;
703 }
704 }
705 #endif
706 return 0;
707 }
708
hns3_nic_net_up(struct net_device * netdev)709 static int hns3_nic_net_up(struct net_device *netdev)
710 {
711 struct hns3_nic_priv *priv = netdev_priv(netdev);
712 struct hnae3_handle *h = priv->ae_handle;
713 int i, j;
714 int ret;
715
716 ret = hns3_nic_reset_all_ring(h);
717 if (ret)
718 return ret;
719
720 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
721
722 /* enable the vectors */
723 for (i = 0; i < priv->vector_num; i++)
724 hns3_vector_enable(&priv->tqp_vector[i]);
725
726 /* enable rcb */
727 for (j = 0; j < h->kinfo.num_tqps; j++)
728 hns3_tqp_enable(h->kinfo.tqp[j]);
729
730 /* start the ae_dev */
731 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
732 if (ret) {
733 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
734 while (j--)
735 hns3_tqp_disable(h->kinfo.tqp[j]);
736
737 for (j = i - 1; j >= 0; j--)
738 hns3_vector_disable(&priv->tqp_vector[j]);
739 }
740
741 return ret;
742 }
743
hns3_config_xps(struct hns3_nic_priv * priv)744 static void hns3_config_xps(struct hns3_nic_priv *priv)
745 {
746 int i;
747
748 for (i = 0; i < priv->vector_num; i++) {
749 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
750 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
751
752 while (ring) {
753 int ret;
754
755 ret = netif_set_xps_queue(priv->netdev,
756 &tqp_vector->affinity_mask,
757 ring->tqp->tqp_index);
758 if (ret)
759 netdev_warn(priv->netdev,
760 "set xps queue failed: %d", ret);
761
762 ring = ring->next;
763 }
764 }
765 }
766
hns3_nic_net_open(struct net_device * netdev)767 static int hns3_nic_net_open(struct net_device *netdev)
768 {
769 struct hns3_nic_priv *priv = netdev_priv(netdev);
770 struct hnae3_handle *h = hns3_get_handle(netdev);
771 struct hnae3_knic_private_info *kinfo;
772 int i, ret;
773
774 if (hns3_nic_resetting(netdev))
775 return -EBUSY;
776
777 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
778 netdev_warn(netdev, "net open repeatedly!\n");
779 return 0;
780 }
781
782 netif_carrier_off(netdev);
783
784 ret = hns3_nic_set_real_num_queue(netdev);
785 if (ret)
786 return ret;
787
788 ret = hns3_nic_net_up(netdev);
789 if (ret) {
790 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
791 return ret;
792 }
793
794 kinfo = &h->kinfo;
795 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
796 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
797
798 if (h->ae_algo->ops->set_timer_task)
799 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
800
801 hns3_config_xps(priv);
802
803 netif_dbg(h, drv, netdev, "net open\n");
804
805 return 0;
806 }
807
hns3_reset_tx_queue(struct hnae3_handle * h)808 static void hns3_reset_tx_queue(struct hnae3_handle *h)
809 {
810 struct net_device *ndev = h->kinfo.netdev;
811 struct hns3_nic_priv *priv = netdev_priv(ndev);
812 struct netdev_queue *dev_queue;
813 u32 i;
814
815 for (i = 0; i < h->kinfo.num_tqps; i++) {
816 dev_queue = netdev_get_tx_queue(ndev,
817 priv->ring[i].queue_index);
818 netdev_tx_reset_queue(dev_queue);
819 }
820 }
821
hns3_nic_net_down(struct net_device * netdev)822 static void hns3_nic_net_down(struct net_device *netdev)
823 {
824 struct hns3_nic_priv *priv = netdev_priv(netdev);
825 struct hnae3_handle *h = hns3_get_handle(netdev);
826 const struct hnae3_ae_ops *ops;
827 int i;
828
829 /* disable vectors */
830 for (i = 0; i < priv->vector_num; i++)
831 hns3_vector_disable(&priv->tqp_vector[i]);
832
833 /* disable rcb */
834 for (i = 0; i < h->kinfo.num_tqps; i++)
835 hns3_tqp_disable(h->kinfo.tqp[i]);
836
837 /* stop ae_dev */
838 ops = priv->ae_handle->ae_algo->ops;
839 if (ops->stop)
840 ops->stop(priv->ae_handle);
841
842 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
843 * during reset process, because driver may not be able
844 * to disable the ring through firmware when downing the netdev.
845 */
846 if (!hns3_nic_resetting(netdev))
847 hns3_clear_all_ring(priv->ae_handle, false);
848
849 hns3_reset_tx_queue(priv->ae_handle);
850 }
851
hns3_nic_net_stop(struct net_device * netdev)852 static int hns3_nic_net_stop(struct net_device *netdev)
853 {
854 struct hns3_nic_priv *priv = netdev_priv(netdev);
855 struct hnae3_handle *h = hns3_get_handle(netdev);
856
857 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
858 return 0;
859
860 netif_dbg(h, drv, netdev, "net stop\n");
861
862 if (h->ae_algo->ops->set_timer_task)
863 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
864
865 netif_carrier_off(netdev);
866 netif_tx_disable(netdev);
867
868 hns3_nic_net_down(netdev);
869
870 return 0;
871 }
872
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)873 static int hns3_nic_uc_sync(struct net_device *netdev,
874 const unsigned char *addr)
875 {
876 struct hnae3_handle *h = hns3_get_handle(netdev);
877
878 if (h->ae_algo->ops->add_uc_addr)
879 return h->ae_algo->ops->add_uc_addr(h, addr);
880
881 return 0;
882 }
883
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)884 static int hns3_nic_uc_unsync(struct net_device *netdev,
885 const unsigned char *addr)
886 {
887 struct hnae3_handle *h = hns3_get_handle(netdev);
888
889 /* need ignore the request of removing device address, because
890 * we store the device address and other addresses of uc list
891 * in the function's mac filter list.
892 */
893 if (ether_addr_equal(addr, netdev->dev_addr))
894 return 0;
895
896 if (h->ae_algo->ops->rm_uc_addr)
897 return h->ae_algo->ops->rm_uc_addr(h, addr);
898
899 return 0;
900 }
901
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)902 static int hns3_nic_mc_sync(struct net_device *netdev,
903 const unsigned char *addr)
904 {
905 struct hnae3_handle *h = hns3_get_handle(netdev);
906
907 if (h->ae_algo->ops->add_mc_addr)
908 return h->ae_algo->ops->add_mc_addr(h, addr);
909
910 return 0;
911 }
912
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)913 static int hns3_nic_mc_unsync(struct net_device *netdev,
914 const unsigned char *addr)
915 {
916 struct hnae3_handle *h = hns3_get_handle(netdev);
917
918 if (h->ae_algo->ops->rm_mc_addr)
919 return h->ae_algo->ops->rm_mc_addr(h, addr);
920
921 return 0;
922 }
923
hns3_get_netdev_flags(struct net_device * netdev)924 static u8 hns3_get_netdev_flags(struct net_device *netdev)
925 {
926 u8 flags = 0;
927
928 if (netdev->flags & IFF_PROMISC)
929 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
930 else if (netdev->flags & IFF_ALLMULTI)
931 flags = HNAE3_USER_MPE;
932
933 return flags;
934 }
935
hns3_nic_set_rx_mode(struct net_device * netdev)936 static void hns3_nic_set_rx_mode(struct net_device *netdev)
937 {
938 struct hnae3_handle *h = hns3_get_handle(netdev);
939 u8 new_flags;
940
941 new_flags = hns3_get_netdev_flags(netdev);
942
943 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
944 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
945
946 /* User mode Promisc mode enable and vlan filtering is disabled to
947 * let all packets in.
948 */
949 h->netdev_flags = new_flags;
950 hns3_request_update_promisc_mode(h);
951 }
952
hns3_request_update_promisc_mode(struct hnae3_handle * handle)953 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
954 {
955 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
956
957 if (ops->request_update_promisc_mode)
958 ops->request_update_promisc_mode(handle);
959 }
960
hns3_tx_spare_space(struct hns3_enet_ring * ring)961 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
962 {
963 struct hns3_tx_spare *tx_spare = ring->tx_spare;
964 u32 ntc, ntu;
965
966 /* This smp_load_acquire() pairs with smp_store_release() in
967 * hns3_tx_spare_update() called in tx desc cleaning process.
968 */
969 ntc = smp_load_acquire(&tx_spare->last_to_clean);
970 ntu = tx_spare->next_to_use;
971
972 if (ntc > ntu)
973 return ntc - ntu - 1;
974
975 /* The free tx buffer is divided into two part, so pick the
976 * larger one.
977 */
978 return max(ntc, tx_spare->len - ntu) - 1;
979 }
980
hns3_tx_spare_update(struct hns3_enet_ring * ring)981 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
982 {
983 struct hns3_tx_spare *tx_spare = ring->tx_spare;
984
985 if (!tx_spare ||
986 tx_spare->last_to_clean == tx_spare->next_to_clean)
987 return;
988
989 /* This smp_store_release() pairs with smp_load_acquire() in
990 * hns3_tx_spare_space() called in xmit process.
991 */
992 smp_store_release(&tx_spare->last_to_clean,
993 tx_spare->next_to_clean);
994 }
995
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)996 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
997 struct sk_buff *skb,
998 u32 space)
999 {
1000 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1001 skb_headlen(skb);
1002
1003 if (len > ring->tx_copybreak)
1004 return false;
1005
1006 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1007 hns3_ring_stats_update(ring, tx_spare_full);
1008 return false;
1009 }
1010
1011 return true;
1012 }
1013
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1014 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1015 struct sk_buff *skb,
1016 u32 space)
1017 {
1018 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1019 (!skb_has_frag_list(skb) &&
1020 skb_shinfo(skb)->nr_frags < tx_sgl))
1021 return false;
1022
1023 if (space < HNS3_MAX_SGL_SIZE) {
1024 hns3_ring_stats_update(ring, tx_spare_full);
1025 return false;
1026 }
1027
1028 return true;
1029 }
1030
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1031 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1032 {
1033 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1034 struct hns3_tx_spare *tx_spare;
1035 struct page *page;
1036 dma_addr_t dma;
1037 int order;
1038
1039 if (!alloc_size)
1040 return;
1041
1042 order = get_order(alloc_size);
1043 if (order >= MAX_ORDER) {
1044 if (net_ratelimit())
1045 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1046 return;
1047 }
1048
1049 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1050 GFP_KERNEL);
1051 if (!tx_spare) {
1052 /* The driver still work without the tx spare buffer */
1053 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1054 goto devm_kzalloc_error;
1055 }
1056
1057 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1058 GFP_KERNEL, order);
1059 if (!page) {
1060 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1061 goto alloc_pages_error;
1062 }
1063
1064 dma = dma_map_page(ring_to_dev(ring), page, 0,
1065 PAGE_SIZE << order, DMA_TO_DEVICE);
1066 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1067 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1068 goto dma_mapping_error;
1069 }
1070
1071 tx_spare->dma = dma;
1072 tx_spare->buf = page_address(page);
1073 tx_spare->len = PAGE_SIZE << order;
1074 ring->tx_spare = tx_spare;
1075 return;
1076
1077 dma_mapping_error:
1078 put_page(page);
1079 alloc_pages_error:
1080 devm_kfree(ring_to_dev(ring), tx_spare);
1081 devm_kzalloc_error:
1082 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1083 }
1084
1085 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1086 * before calling below function to allocate tx buffer.
1087 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1088 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1089 unsigned int size, dma_addr_t *dma,
1090 u32 *cb_len)
1091 {
1092 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1093 u32 ntu = tx_spare->next_to_use;
1094
1095 size = ALIGN(size, dma_get_cache_alignment());
1096 *cb_len = size;
1097
1098 /* Tx spare buffer wraps back here because the end of
1099 * freed tx buffer is not enough.
1100 */
1101 if (ntu + size > tx_spare->len) {
1102 *cb_len += (tx_spare->len - ntu);
1103 ntu = 0;
1104 }
1105
1106 tx_spare->next_to_use = ntu + size;
1107 if (tx_spare->next_to_use == tx_spare->len)
1108 tx_spare->next_to_use = 0;
1109
1110 *dma = tx_spare->dma + ntu;
1111
1112 return tx_spare->buf + ntu;
1113 }
1114
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1115 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1116 {
1117 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1118
1119 if (len > tx_spare->next_to_use) {
1120 len -= tx_spare->next_to_use;
1121 tx_spare->next_to_use = tx_spare->len - len;
1122 } else {
1123 tx_spare->next_to_use -= len;
1124 }
1125 }
1126
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1127 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1128 struct hns3_desc_cb *cb)
1129 {
1130 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1131 u32 ntc = tx_spare->next_to_clean;
1132 u32 len = cb->length;
1133
1134 tx_spare->next_to_clean += len;
1135
1136 if (tx_spare->next_to_clean >= tx_spare->len) {
1137 tx_spare->next_to_clean -= tx_spare->len;
1138
1139 if (tx_spare->next_to_clean) {
1140 ntc = 0;
1141 len = tx_spare->next_to_clean;
1142 }
1143 }
1144
1145 /* This tx spare buffer is only really reclaimed after calling
1146 * hns3_tx_spare_update(), so it is still safe to use the info in
1147 * the tx buffer to do the dma sync or sg unmapping after
1148 * tx_spare->next_to_clean is moved forword.
1149 */
1150 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1151 dma_addr_t dma = tx_spare->dma + ntc;
1152
1153 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1154 DMA_TO_DEVICE);
1155 } else {
1156 struct sg_table *sgt = tx_spare->buf + ntc;
1157
1158 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1159 DMA_TO_DEVICE);
1160 }
1161 }
1162
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1163 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1164 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1165 {
1166 u32 l4_offset, hdr_len;
1167 union l3_hdr_info l3;
1168 union l4_hdr_info l4;
1169 u32 l4_paylen;
1170 int ret;
1171
1172 if (!skb_is_gso(skb))
1173 return 0;
1174
1175 ret = skb_cow_head(skb, 0);
1176 if (unlikely(ret < 0))
1177 return ret;
1178
1179 l3.hdr = skb_network_header(skb);
1180 l4.hdr = skb_transport_header(skb);
1181
1182 /* Software should clear the IPv4's checksum field when tso is
1183 * needed.
1184 */
1185 if (l3.v4->version == 4)
1186 l3.v4->check = 0;
1187
1188 /* tunnel packet */
1189 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1190 SKB_GSO_GRE_CSUM |
1191 SKB_GSO_UDP_TUNNEL |
1192 SKB_GSO_UDP_TUNNEL_CSUM)) {
1193 /* reset l3&l4 pointers from outer to inner headers */
1194 l3.hdr = skb_inner_network_header(skb);
1195 l4.hdr = skb_inner_transport_header(skb);
1196
1197 /* Software should clear the IPv4's checksum field when
1198 * tso is needed.
1199 */
1200 if (l3.v4->version == 4)
1201 l3.v4->check = 0;
1202 }
1203
1204 /* normal or tunnel packet */
1205 l4_offset = l4.hdr - skb->data;
1206
1207 /* remove payload length from inner pseudo checksum when tso */
1208 l4_paylen = skb->len - l4_offset;
1209
1210 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1211 hdr_len = sizeof(*l4.udp) + l4_offset;
1212 csum_replace_by_diff(&l4.udp->check,
1213 (__force __wsum)htonl(l4_paylen));
1214 } else {
1215 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1216 csum_replace_by_diff(&l4.tcp->check,
1217 (__force __wsum)htonl(l4_paylen));
1218 }
1219
1220 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1221
1222 /* find the txbd field values */
1223 *paylen_fdop_ol4cs = skb->len - hdr_len;
1224 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1225
1226 /* offload outer UDP header checksum */
1227 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1228 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1229
1230 /* get MSS for TSO */
1231 *mss = skb_shinfo(skb)->gso_size;
1232
1233 trace_hns3_tso(skb);
1234
1235 return 0;
1236 }
1237
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1238 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1239 u8 *il4_proto)
1240 {
1241 union l3_hdr_info l3;
1242 unsigned char *l4_hdr;
1243 unsigned char *exthdr;
1244 u8 l4_proto_tmp;
1245 __be16 frag_off;
1246
1247 /* find outer header point */
1248 l3.hdr = skb_network_header(skb);
1249 l4_hdr = skb_transport_header(skb);
1250
1251 if (skb->protocol == htons(ETH_P_IPV6)) {
1252 exthdr = l3.hdr + sizeof(*l3.v6);
1253 l4_proto_tmp = l3.v6->nexthdr;
1254 if (l4_hdr != exthdr)
1255 ipv6_skip_exthdr(skb, exthdr - skb->data,
1256 &l4_proto_tmp, &frag_off);
1257 } else if (skb->protocol == htons(ETH_P_IP)) {
1258 l4_proto_tmp = l3.v4->protocol;
1259 } else {
1260 return -EINVAL;
1261 }
1262
1263 *ol4_proto = l4_proto_tmp;
1264
1265 /* tunnel packet */
1266 if (!skb->encapsulation) {
1267 *il4_proto = 0;
1268 return 0;
1269 }
1270
1271 /* find inner header point */
1272 l3.hdr = skb_inner_network_header(skb);
1273 l4_hdr = skb_inner_transport_header(skb);
1274
1275 if (l3.v6->version == 6) {
1276 exthdr = l3.hdr + sizeof(*l3.v6);
1277 l4_proto_tmp = l3.v6->nexthdr;
1278 if (l4_hdr != exthdr)
1279 ipv6_skip_exthdr(skb, exthdr - skb->data,
1280 &l4_proto_tmp, &frag_off);
1281 } else if (l3.v4->version == 4) {
1282 l4_proto_tmp = l3.v4->protocol;
1283 }
1284
1285 *il4_proto = l4_proto_tmp;
1286
1287 return 0;
1288 }
1289
1290 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1291 * and it is udp packet, which has a dest port as the IANA assigned.
1292 * the hardware is expected to do the checksum offload, but the
1293 * hardware will not do the checksum offload when udp dest port is
1294 * 4789, 4790 or 6081.
1295 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1296 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1297 {
1298 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1299 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1300 union l4_hdr_info l4;
1301
1302 /* device version above V3(include V3), the hardware can
1303 * do this checksum offload.
1304 */
1305 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1306 return false;
1307
1308 l4.hdr = skb_transport_header(skb);
1309
1310 if (!(!skb->encapsulation &&
1311 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1312 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1313 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1314 return false;
1315
1316 return true;
1317 }
1318
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1319 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1320 u32 *ol_type_vlan_len_msec)
1321 {
1322 u32 l2_len, l3_len, l4_len;
1323 unsigned char *il2_hdr;
1324 union l3_hdr_info l3;
1325 union l4_hdr_info l4;
1326
1327 l3.hdr = skb_network_header(skb);
1328 l4.hdr = skb_transport_header(skb);
1329
1330 /* compute OL2 header size, defined in 2 Bytes */
1331 l2_len = l3.hdr - skb->data;
1332 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1333
1334 /* compute OL3 header size, defined in 4 Bytes */
1335 l3_len = l4.hdr - l3.hdr;
1336 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1337
1338 il2_hdr = skb_inner_mac_header(skb);
1339 /* compute OL4 header size, defined in 4 Bytes */
1340 l4_len = il2_hdr - l4.hdr;
1341 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1342
1343 /* define outer network header type */
1344 if (skb->protocol == htons(ETH_P_IP)) {
1345 if (skb_is_gso(skb))
1346 hns3_set_field(*ol_type_vlan_len_msec,
1347 HNS3_TXD_OL3T_S,
1348 HNS3_OL3T_IPV4_CSUM);
1349 else
1350 hns3_set_field(*ol_type_vlan_len_msec,
1351 HNS3_TXD_OL3T_S,
1352 HNS3_OL3T_IPV4_NO_CSUM);
1353 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1354 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1355 HNS3_OL3T_IPV6);
1356 }
1357
1358 if (ol4_proto == IPPROTO_UDP)
1359 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1360 HNS3_TUN_MAC_IN_UDP);
1361 else if (ol4_proto == IPPROTO_GRE)
1362 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1363 HNS3_TUN_NVGRE);
1364 }
1365
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1366 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1367 u32 *type_cs_vlan_tso)
1368 {
1369 if (l3.v4->version == 4) {
1370 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1371 HNS3_L3T_IPV4);
1372
1373 /* the stack computes the IP header already, the only time we
1374 * need the hardware to recompute it is in the case of TSO.
1375 */
1376 if (skb_is_gso(skb))
1377 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1378 } else if (l3.v6->version == 6) {
1379 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1380 HNS3_L3T_IPV6);
1381 }
1382 }
1383
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1384 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1385 u32 l4_proto, u32 *type_cs_vlan_tso)
1386 {
1387 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1388 switch (l4_proto) {
1389 case IPPROTO_TCP:
1390 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1392 HNS3_L4T_TCP);
1393 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1394 l4.tcp->doff);
1395 break;
1396 case IPPROTO_UDP:
1397 if (hns3_tunnel_csum_bug(skb)) {
1398 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1399
1400 return ret ? ret : skb_checksum_help(skb);
1401 }
1402
1403 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1405 HNS3_L4T_UDP);
1406 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1407 (sizeof(struct udphdr) >> 2));
1408 break;
1409 case IPPROTO_SCTP:
1410 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1412 HNS3_L4T_SCTP);
1413 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1414 (sizeof(struct sctphdr) >> 2));
1415 break;
1416 default:
1417 /* drop the skb tunnel packet if hardware don't support,
1418 * because hardware can't calculate csum when TSO.
1419 */
1420 if (skb_is_gso(skb))
1421 return -EDOM;
1422
1423 /* the stack computes the IP header already,
1424 * driver calculate l4 checksum when not TSO.
1425 */
1426 return skb_checksum_help(skb);
1427 }
1428
1429 return 0;
1430 }
1431
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1432 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1433 u8 il4_proto, u32 *type_cs_vlan_tso,
1434 u32 *ol_type_vlan_len_msec)
1435 {
1436 unsigned char *l2_hdr = skb->data;
1437 u32 l4_proto = ol4_proto;
1438 union l4_hdr_info l4;
1439 union l3_hdr_info l3;
1440 u32 l2_len, l3_len;
1441
1442 l4.hdr = skb_transport_header(skb);
1443 l3.hdr = skb_network_header(skb);
1444
1445 /* handle encapsulation skb */
1446 if (skb->encapsulation) {
1447 /* If this is a not UDP/GRE encapsulation skb */
1448 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1449 /* drop the skb tunnel packet if hardware don't support,
1450 * because hardware can't calculate csum when TSO.
1451 */
1452 if (skb_is_gso(skb))
1453 return -EDOM;
1454
1455 /* the stack computes the IP header already,
1456 * driver calculate l4 checksum when not TSO.
1457 */
1458 return skb_checksum_help(skb);
1459 }
1460
1461 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1462
1463 /* switch to inner header */
1464 l2_hdr = skb_inner_mac_header(skb);
1465 l3.hdr = skb_inner_network_header(skb);
1466 l4.hdr = skb_inner_transport_header(skb);
1467 l4_proto = il4_proto;
1468 }
1469
1470 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1471
1472 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1473 l2_len = l3.hdr - l2_hdr;
1474 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1475
1476 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1477 l3_len = l4.hdr - l3.hdr;
1478 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1479
1480 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1481 }
1482
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1483 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1484 struct sk_buff *skb)
1485 {
1486 struct hnae3_handle *handle = tx_ring->tqp->handle;
1487 struct hnae3_ae_dev *ae_dev;
1488 struct vlan_ethhdr *vhdr;
1489 int rc;
1490
1491 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1492 skb_vlan_tag_present(skb)))
1493 return 0;
1494
1495 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1496 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1497 * will cause RAS error.
1498 */
1499 ae_dev = pci_get_drvdata(handle->pdev);
1500 if (unlikely(skb_vlan_tagged_multi(skb) &&
1501 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1502 handle->port_base_vlan_state ==
1503 HNAE3_PORT_BASE_VLAN_ENABLE))
1504 return -EINVAL;
1505
1506 if (skb->protocol == htons(ETH_P_8021Q) &&
1507 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1508 /* When HW VLAN acceleration is turned off, and the stack
1509 * sets the protocol to 802.1q, the driver just need to
1510 * set the protocol to the encapsulated ethertype.
1511 */
1512 skb->protocol = vlan_get_protocol(skb);
1513 return 0;
1514 }
1515
1516 if (skb_vlan_tag_present(skb)) {
1517 /* Based on hw strategy, use out_vtag in two layer tag case,
1518 * and use inner_vtag in one tag case.
1519 */
1520 if (skb->protocol == htons(ETH_P_8021Q) &&
1521 handle->port_base_vlan_state ==
1522 HNAE3_PORT_BASE_VLAN_DISABLE)
1523 rc = HNS3_OUTER_VLAN_TAG;
1524 else
1525 rc = HNS3_INNER_VLAN_TAG;
1526
1527 skb->protocol = vlan_get_protocol(skb);
1528 return rc;
1529 }
1530
1531 rc = skb_cow_head(skb, 0);
1532 if (unlikely(rc < 0))
1533 return rc;
1534
1535 vhdr = skb_vlan_eth_hdr(skb);
1536 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1537 & VLAN_PRIO_MASK);
1538
1539 skb->protocol = vlan_get_protocol(skb);
1540 return 0;
1541 }
1542
1543 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1544 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1545 {
1546 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1547
1548 /* Kindly note, due to backward compatibility of the TX descriptor,
1549 * HW checksum of the non-IP packets and GSO packets is handled at
1550 * different place in the following code
1551 */
1552 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1553 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1554 return false;
1555
1556 return true;
1557 }
1558
1559 struct hns3_desc_param {
1560 u32 paylen_ol4cs;
1561 u32 ol_type_vlan_len_msec;
1562 u32 type_cs_vlan_tso;
1563 u16 mss_hw_csum;
1564 u16 inner_vtag;
1565 u16 out_vtag;
1566 };
1567
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1568 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1569 {
1570 pa->paylen_ol4cs = skb->len;
1571 pa->ol_type_vlan_len_msec = 0;
1572 pa->type_cs_vlan_tso = 0;
1573 pa->mss_hw_csum = 0;
1574 pa->inner_vtag = 0;
1575 pa->out_vtag = 0;
1576 }
1577
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1578 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1579 struct sk_buff *skb,
1580 struct hns3_desc_param *param)
1581 {
1582 int ret;
1583
1584 ret = hns3_handle_vtags(ring, skb);
1585 if (unlikely(ret < 0)) {
1586 hns3_ring_stats_update(ring, tx_vlan_err);
1587 return ret;
1588 } else if (ret == HNS3_INNER_VLAN_TAG) {
1589 param->inner_vtag = skb_vlan_tag_get(skb);
1590 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1591 VLAN_PRIO_MASK;
1592 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1593 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1594 param->out_vtag = skb_vlan_tag_get(skb);
1595 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1596 VLAN_PRIO_MASK;
1597 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1598 1);
1599 }
1600 return 0;
1601 }
1602
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1603 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1604 struct sk_buff *skb,
1605 struct hns3_desc_cb *desc_cb,
1606 struct hns3_desc_param *param)
1607 {
1608 u8 ol4_proto, il4_proto;
1609 int ret;
1610
1611 if (hns3_check_hw_tx_csum(skb)) {
1612 /* set checksum start and offset, defined in 2 Bytes */
1613 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1614 skb_checksum_start_offset(skb) >> 1);
1615 hns3_set_field(param->ol_type_vlan_len_msec,
1616 HNS3_TXD_CSUM_OFFSET_S,
1617 skb->csum_offset >> 1);
1618 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1619 return 0;
1620 }
1621
1622 skb_reset_mac_len(skb);
1623
1624 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1625 if (unlikely(ret < 0)) {
1626 hns3_ring_stats_update(ring, tx_l4_proto_err);
1627 return ret;
1628 }
1629
1630 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1631 ¶m->type_cs_vlan_tso,
1632 ¶m->ol_type_vlan_len_msec);
1633 if (unlikely(ret < 0)) {
1634 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1635 return ret;
1636 }
1637
1638 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1639 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1640 if (unlikely(ret < 0)) {
1641 hns3_ring_stats_update(ring, tx_tso_err);
1642 return ret;
1643 }
1644 return 0;
1645 }
1646
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1647 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1648 struct sk_buff *skb, struct hns3_desc *desc,
1649 struct hns3_desc_cb *desc_cb)
1650 {
1651 struct hns3_desc_param param;
1652 int ret;
1653
1654 hns3_init_desc_data(skb, ¶m);
1655 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1656 if (unlikely(ret < 0))
1657 return ret;
1658
1659 desc_cb->send_bytes = skb->len;
1660
1661 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1662 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1663 if (ret)
1664 return ret;
1665 }
1666
1667 /* Set txbd */
1668 desc->tx.ol_type_vlan_len_msec =
1669 cpu_to_le32(param.ol_type_vlan_len_msec);
1670 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1671 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1672 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1673 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1674 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1675
1676 return 0;
1677 }
1678
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1679 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1680 unsigned int size)
1681 {
1682 #define HNS3_LIKELY_BD_NUM 1
1683
1684 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1685 unsigned int frag_buf_num;
1686 int k, sizeoflast;
1687
1688 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1689 desc->addr = cpu_to_le64(dma);
1690 desc->tx.send_size = cpu_to_le16(size);
1691 desc->tx.bdtp_fe_sc_vld_ra_ri =
1692 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1693
1694 trace_hns3_tx_desc(ring, ring->next_to_use);
1695 ring_ptr_move_fw(ring, next_to_use);
1696 return HNS3_LIKELY_BD_NUM;
1697 }
1698
1699 frag_buf_num = hns3_tx_bd_count(size);
1700 sizeoflast = size % HNS3_MAX_BD_SIZE;
1701 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1702
1703 /* When frag size is bigger than hardware limit, split this frag */
1704 for (k = 0; k < frag_buf_num; k++) {
1705 /* now, fill the descriptor */
1706 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1707 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1708 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1709 desc->tx.bdtp_fe_sc_vld_ra_ri =
1710 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1711
1712 trace_hns3_tx_desc(ring, ring->next_to_use);
1713 /* move ring pointer to next */
1714 ring_ptr_move_fw(ring, next_to_use);
1715
1716 desc = &ring->desc[ring->next_to_use];
1717 }
1718
1719 return frag_buf_num;
1720 }
1721
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1722 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1723 unsigned int type)
1724 {
1725 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1726 struct device *dev = ring_to_dev(ring);
1727 unsigned int size;
1728 dma_addr_t dma;
1729
1730 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1731 struct sk_buff *skb = (struct sk_buff *)priv;
1732
1733 size = skb_headlen(skb);
1734 if (!size)
1735 return 0;
1736
1737 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1738 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1739 /* Head data has been filled in hns3_handle_tx_bounce(),
1740 * just return 0 here.
1741 */
1742 return 0;
1743 } else {
1744 skb_frag_t *frag = (skb_frag_t *)priv;
1745
1746 size = skb_frag_size(frag);
1747 if (!size)
1748 return 0;
1749
1750 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1751 }
1752
1753 if (unlikely(dma_mapping_error(dev, dma))) {
1754 hns3_ring_stats_update(ring, sw_err_cnt);
1755 return -ENOMEM;
1756 }
1757
1758 desc_cb->priv = priv;
1759 desc_cb->length = size;
1760 desc_cb->dma = dma;
1761 desc_cb->type = type;
1762
1763 return hns3_fill_desc(ring, dma, size);
1764 }
1765
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1766 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1767 unsigned int bd_num)
1768 {
1769 unsigned int size;
1770 int i;
1771
1772 size = skb_headlen(skb);
1773 while (size > HNS3_MAX_BD_SIZE) {
1774 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1775 size -= HNS3_MAX_BD_SIZE;
1776
1777 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1778 return bd_num;
1779 }
1780
1781 if (size) {
1782 bd_size[bd_num++] = size;
1783 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1784 return bd_num;
1785 }
1786
1787 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1788 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1789 size = skb_frag_size(frag);
1790 if (!size)
1791 continue;
1792
1793 while (size > HNS3_MAX_BD_SIZE) {
1794 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1795 size -= HNS3_MAX_BD_SIZE;
1796
1797 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1798 return bd_num;
1799 }
1800
1801 bd_size[bd_num++] = size;
1802 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1803 return bd_num;
1804 }
1805
1806 return bd_num;
1807 }
1808
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1809 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1810 u8 max_non_tso_bd_num, unsigned int bd_num,
1811 unsigned int recursion_level)
1812 {
1813 #define HNS3_MAX_RECURSION_LEVEL 24
1814
1815 struct sk_buff *frag_skb;
1816
1817 /* If the total len is within the max bd limit */
1818 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1819 !skb_has_frag_list(skb) &&
1820 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1821 return skb_shinfo(skb)->nr_frags + 1U;
1822
1823 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1824 return UINT_MAX;
1825
1826 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1827 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1828 return bd_num;
1829
1830 skb_walk_frags(skb, frag_skb) {
1831 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1832 bd_num, recursion_level + 1);
1833 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1834 return bd_num;
1835 }
1836
1837 return bd_num;
1838 }
1839
hns3_gso_hdr_len(struct sk_buff * skb)1840 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1841 {
1842 if (!skb->encapsulation)
1843 return skb_tcp_all_headers(skb);
1844
1845 return skb_inner_tcp_all_headers(skb);
1846 }
1847
1848 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1849 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1850 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1851 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1852 * than MSS except the last max_non_tso_bd_num - 1 frags.
1853 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1854 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1855 unsigned int bd_num, u8 max_non_tso_bd_num)
1856 {
1857 unsigned int tot_len = 0;
1858 int i;
1859
1860 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1861 tot_len += bd_size[i];
1862
1863 /* ensure the first max_non_tso_bd_num frags is greater than
1864 * mss + header
1865 */
1866 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1867 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1868 return true;
1869
1870 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1871 * than mss except the last one.
1872 */
1873 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1874 tot_len -= bd_size[i];
1875 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1876
1877 if (tot_len < skb_shinfo(skb)->gso_size)
1878 return true;
1879 }
1880
1881 return false;
1882 }
1883
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1884 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1885 {
1886 int i;
1887
1888 for (i = 0; i < MAX_SKB_FRAGS; i++)
1889 size[i] = skb_frag_size(&shinfo->frags[i]);
1890 }
1891
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1892 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1893 struct sk_buff *skb,
1894 unsigned int bd_num)
1895 {
1896 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1897 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1898 */
1899 if (bd_num == UINT_MAX) {
1900 hns3_ring_stats_update(ring, over_max_recursion);
1901 return -ENOMEM;
1902 }
1903
1904 /* The skb->len has exceeded the hw limitation, linearization
1905 * will not help.
1906 */
1907 if (skb->len > HNS3_MAX_TSO_SIZE ||
1908 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1909 hns3_ring_stats_update(ring, hw_limitation);
1910 return -ENOMEM;
1911 }
1912
1913 if (__skb_linearize(skb)) {
1914 hns3_ring_stats_update(ring, sw_err_cnt);
1915 return -ENOMEM;
1916 }
1917
1918 return 0;
1919 }
1920
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1921 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1922 struct net_device *netdev,
1923 struct sk_buff *skb)
1924 {
1925 struct hns3_nic_priv *priv = netdev_priv(netdev);
1926 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1927 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1928 unsigned int bd_num;
1929
1930 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1931 if (unlikely(bd_num > max_non_tso_bd_num)) {
1932 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1933 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1934 max_non_tso_bd_num)) {
1935 trace_hns3_over_max_bd(skb);
1936 goto out;
1937 }
1938
1939 if (hns3_skb_linearize(ring, skb, bd_num))
1940 return -ENOMEM;
1941
1942 bd_num = hns3_tx_bd_count(skb->len);
1943
1944 hns3_ring_stats_update(ring, tx_copy);
1945 }
1946
1947 out:
1948 if (likely(ring_space(ring) >= bd_num))
1949 return bd_num;
1950
1951 netif_stop_subqueue(netdev, ring->queue_index);
1952 smp_mb(); /* Memory barrier before checking ring_space */
1953
1954 /* Start queue in case hns3_clean_tx_ring has just made room
1955 * available and has not seen the queue stopped state performed
1956 * by netif_stop_subqueue above.
1957 */
1958 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1959 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1960 netif_start_subqueue(netdev, ring->queue_index);
1961 return bd_num;
1962 }
1963
1964 hns3_ring_stats_update(ring, tx_busy);
1965
1966 return -EBUSY;
1967 }
1968
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1969 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1970 {
1971 struct device *dev = ring_to_dev(ring);
1972 unsigned int i;
1973
1974 for (i = 0; i < ring->desc_num; i++) {
1975 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1976 struct hns3_desc_cb *desc_cb;
1977
1978 memset(desc, 0, sizeof(*desc));
1979
1980 /* check if this is where we started */
1981 if (ring->next_to_use == next_to_use_orig)
1982 break;
1983
1984 /* rollback one */
1985 ring_ptr_move_bw(ring, next_to_use);
1986
1987 desc_cb = &ring->desc_cb[ring->next_to_use];
1988
1989 if (!desc_cb->dma)
1990 continue;
1991
1992 /* unmap the descriptor dma address */
1993 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1994 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1995 DMA_TO_DEVICE);
1996 else if (desc_cb->type &
1997 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1998 hns3_tx_spare_rollback(ring, desc_cb->length);
1999 else if (desc_cb->length)
2000 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2001 DMA_TO_DEVICE);
2002
2003 desc_cb->length = 0;
2004 desc_cb->dma = 0;
2005 desc_cb->type = DESC_TYPE_UNKNOWN;
2006 }
2007 }
2008
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2009 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2010 struct sk_buff *skb, unsigned int type)
2011 {
2012 struct sk_buff *frag_skb;
2013 int i, ret, bd_num = 0;
2014
2015 ret = hns3_map_and_fill_desc(ring, skb, type);
2016 if (unlikely(ret < 0))
2017 return ret;
2018
2019 bd_num += ret;
2020
2021 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2022 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2023
2024 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2025 if (unlikely(ret < 0))
2026 return ret;
2027
2028 bd_num += ret;
2029 }
2030
2031 skb_walk_frags(skb, frag_skb) {
2032 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2033 DESC_TYPE_FRAGLIST_SKB);
2034 if (unlikely(ret < 0))
2035 return ret;
2036
2037 bd_num += ret;
2038 }
2039
2040 return bd_num;
2041 }
2042
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2043 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2044 {
2045 #define HNS3_BYTES_PER_64BIT 8
2046
2047 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2048 int offset = 0;
2049
2050 /* make sure everything is visible to device before
2051 * excuting tx push or updating doorbell
2052 */
2053 dma_wmb();
2054
2055 do {
2056 int idx = (ring->next_to_use - num + ring->desc_num) %
2057 ring->desc_num;
2058
2059 u64_stats_update_begin(&ring->syncp);
2060 ring->stats.tx_push++;
2061 u64_stats_update_end(&ring->syncp);
2062 memcpy(&desc[offset], &ring->desc[idx],
2063 sizeof(struct hns3_desc));
2064 offset++;
2065 } while (--num);
2066
2067 __iowrite64_copy(ring->tqp->mem_base, desc,
2068 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2069 HNS3_BYTES_PER_64BIT);
2070
2071 io_stop_wc();
2072 }
2073
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2074 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2075 {
2076 #define HNS3_MEM_DOORBELL_OFFSET 64
2077
2078 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2079
2080 /* make sure everything is visible to device before
2081 * excuting tx push or updating doorbell
2082 */
2083 dma_wmb();
2084
2085 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2086 &bd_num, 1);
2087 u64_stats_update_begin(&ring->syncp);
2088 ring->stats.tx_mem_doorbell += ring->pending_buf;
2089 u64_stats_update_end(&ring->syncp);
2090
2091 io_stop_wc();
2092 }
2093
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2094 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2095 bool doorbell)
2096 {
2097 struct net_device *netdev = ring_to_netdev(ring);
2098 struct hns3_nic_priv *priv = netdev_priv(netdev);
2099
2100 /* when tx push is enabled, the packet whose number of BD below
2101 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2102 */
2103 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2104 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2105 /* This smp_store_release() pairs with smp_load_aquire() in
2106 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2107 * is updated.
2108 */
2109 smp_store_release(&ring->last_to_use, ring->next_to_use);
2110 hns3_tx_push_bd(ring, num);
2111 return;
2112 }
2113
2114 ring->pending_buf += num;
2115
2116 if (!doorbell) {
2117 hns3_ring_stats_update(ring, tx_more);
2118 return;
2119 }
2120
2121 /* This smp_store_release() pairs with smp_load_aquire() in
2122 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2123 */
2124 smp_store_release(&ring->last_to_use, ring->next_to_use);
2125
2126 if (ring->tqp->mem_base)
2127 hns3_tx_mem_doorbell(ring);
2128 else
2129 writel(ring->pending_buf,
2130 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2131
2132 ring->pending_buf = 0;
2133 }
2134
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2135 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2136 struct hns3_desc *desc)
2137 {
2138 struct hnae3_handle *h = hns3_get_handle(netdev);
2139
2140 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2141 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2142 return;
2143
2144 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2145 }
2146
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2147 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2148 struct sk_buff *skb)
2149 {
2150 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2151 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2152 unsigned int size = skb_headlen(skb);
2153 dma_addr_t dma;
2154 int bd_num = 0;
2155 u32 cb_len;
2156 void *buf;
2157 int ret;
2158
2159 if (skb->len <= ring->tx_copybreak) {
2160 size = skb->len;
2161 type = DESC_TYPE_BOUNCE_ALL;
2162 }
2163
2164 /* hns3_can_use_tx_bounce() is called to ensure the below
2165 * function can always return the tx buffer.
2166 */
2167 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2168
2169 ret = skb_copy_bits(skb, 0, buf, size);
2170 if (unlikely(ret < 0)) {
2171 hns3_tx_spare_rollback(ring, cb_len);
2172 hns3_ring_stats_update(ring, copy_bits_err);
2173 return ret;
2174 }
2175
2176 desc_cb->priv = skb;
2177 desc_cb->length = cb_len;
2178 desc_cb->dma = dma;
2179 desc_cb->type = type;
2180
2181 bd_num += hns3_fill_desc(ring, dma, size);
2182
2183 if (type == DESC_TYPE_BOUNCE_HEAD) {
2184 ret = hns3_fill_skb_to_desc(ring, skb,
2185 DESC_TYPE_BOUNCE_HEAD);
2186 if (unlikely(ret < 0))
2187 return ret;
2188
2189 bd_num += ret;
2190 }
2191
2192 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2193 DMA_TO_DEVICE);
2194
2195 hns3_ring_stats_update(ring, tx_bounce);
2196
2197 return bd_num;
2198 }
2199
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2200 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2201 struct sk_buff *skb)
2202 {
2203 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2204 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2205 struct sg_table *sgt;
2206 int i, bd_num = 0;
2207 dma_addr_t dma;
2208 u32 cb_len;
2209 int nents;
2210
2211 if (skb_has_frag_list(skb))
2212 nfrag = HNS3_MAX_TSO_BD_NUM;
2213
2214 /* hns3_can_use_tx_sgl() is called to ensure the below
2215 * function can always return the tx buffer.
2216 */
2217 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2218 &dma, &cb_len);
2219
2220 /* scatterlist follows by the sg table */
2221 sgt->sgl = (struct scatterlist *)(sgt + 1);
2222 sg_init_table(sgt->sgl, nfrag);
2223 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2224 if (unlikely(nents < 0)) {
2225 hns3_tx_spare_rollback(ring, cb_len);
2226 hns3_ring_stats_update(ring, skb2sgl_err);
2227 return -ENOMEM;
2228 }
2229
2230 sgt->orig_nents = nents;
2231 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2232 DMA_TO_DEVICE);
2233 if (unlikely(!sgt->nents)) {
2234 hns3_tx_spare_rollback(ring, cb_len);
2235 hns3_ring_stats_update(ring, map_sg_err);
2236 return -ENOMEM;
2237 }
2238
2239 desc_cb->priv = skb;
2240 desc_cb->length = cb_len;
2241 desc_cb->dma = dma;
2242 desc_cb->type = DESC_TYPE_SGL_SKB;
2243
2244 for (i = 0; i < sgt->nents; i++)
2245 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2246 sg_dma_len(sgt->sgl + i));
2247 hns3_ring_stats_update(ring, tx_sgl);
2248
2249 return bd_num;
2250 }
2251
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2252 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2253 struct sk_buff *skb)
2254 {
2255 u32 space;
2256
2257 if (!ring->tx_spare)
2258 goto out;
2259
2260 space = hns3_tx_spare_space(ring);
2261
2262 if (hns3_can_use_tx_sgl(ring, skb, space))
2263 return hns3_handle_tx_sgl(ring, skb);
2264
2265 if (hns3_can_use_tx_bounce(ring, skb, space))
2266 return hns3_handle_tx_bounce(ring, skb);
2267
2268 out:
2269 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2270 }
2271
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2272 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2273 struct sk_buff *skb,
2274 struct hns3_desc_cb *desc_cb,
2275 int next_to_use_head)
2276 {
2277 int ret;
2278
2279 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2280 desc_cb);
2281 if (unlikely(ret < 0))
2282 goto fill_err;
2283
2284 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2285 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2286 * need to be notified to the hw.
2287 */
2288 ret = hns3_handle_desc_filling(ring, skb);
2289 if (likely(ret > 0))
2290 return ret;
2291
2292 fill_err:
2293 hns3_clear_desc(ring, next_to_use_head);
2294 return ret;
2295 }
2296
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2297 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2298 {
2299 struct hns3_nic_priv *priv = netdev_priv(netdev);
2300 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2301 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2302 struct netdev_queue *dev_queue;
2303 int pre_ntu, ret;
2304 bool doorbell;
2305
2306 /* Hardware can only handle short frames above 32 bytes */
2307 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2308 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2309
2310 hns3_ring_stats_update(ring, sw_err_cnt);
2311
2312 return NETDEV_TX_OK;
2313 }
2314
2315 /* Prefetch the data used later */
2316 prefetch(skb->data);
2317
2318 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2319 if (unlikely(ret <= 0)) {
2320 if (ret == -EBUSY) {
2321 hns3_tx_doorbell(ring, 0, true);
2322 return NETDEV_TX_BUSY;
2323 }
2324
2325 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2326 goto out_err_tx_ok;
2327 }
2328
2329 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2330 if (unlikely(ret <= 0))
2331 goto out_err_tx_ok;
2332
2333 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2334 (ring->desc_num - 1);
2335
2336 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2337 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2338
2339 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2340 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2341 trace_hns3_tx_desc(ring, pre_ntu);
2342
2343 skb_tx_timestamp(skb);
2344
2345 /* Complete translate all packets */
2346 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2347 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2348 netdev_xmit_more());
2349 hns3_tx_doorbell(ring, ret, doorbell);
2350
2351 return NETDEV_TX_OK;
2352
2353 out_err_tx_ok:
2354 dev_kfree_skb_any(skb);
2355 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2356 return NETDEV_TX_OK;
2357 }
2358
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2359 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2360 {
2361 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2362 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2363 struct hnae3_handle *h = hns3_get_handle(netdev);
2364 struct sockaddr *mac_addr = p;
2365 int ret;
2366
2367 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2368 return -EADDRNOTAVAIL;
2369
2370 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2371 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2372 netdev_info(netdev, "already using mac address %s\n",
2373 format_mac_addr_sa);
2374 return 0;
2375 }
2376
2377 /* For VF device, if there is a perm_addr, then the user will not
2378 * be allowed to change the address.
2379 */
2380 if (!hns3_is_phys_func(h->pdev) &&
2381 !is_zero_ether_addr(netdev->perm_addr)) {
2382 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2383 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2384 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2385 format_mac_addr_perm, format_mac_addr_sa);
2386 return -EPERM;
2387 }
2388
2389 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2390 if (ret) {
2391 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2392 return ret;
2393 }
2394
2395 eth_hw_addr_set(netdev, mac_addr->sa_data);
2396
2397 return 0;
2398 }
2399
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2400 static int hns3_nic_do_ioctl(struct net_device *netdev,
2401 struct ifreq *ifr, int cmd)
2402 {
2403 struct hnae3_handle *h = hns3_get_handle(netdev);
2404
2405 if (!netif_running(netdev))
2406 return -EINVAL;
2407
2408 if (!h->ae_algo->ops->do_ioctl)
2409 return -EOPNOTSUPP;
2410
2411 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2412 }
2413
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2414 static int hns3_nic_set_features(struct net_device *netdev,
2415 netdev_features_t features)
2416 {
2417 netdev_features_t changed = netdev->features ^ features;
2418 struct hns3_nic_priv *priv = netdev_priv(netdev);
2419 struct hnae3_handle *h = priv->ae_handle;
2420 bool enable;
2421 int ret;
2422
2423 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2424 enable = !!(features & NETIF_F_GRO_HW);
2425 ret = h->ae_algo->ops->set_gro_en(h, enable);
2426 if (ret)
2427 return ret;
2428 }
2429
2430 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2431 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2432 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2433 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2434 if (ret)
2435 return ret;
2436 }
2437
2438 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2439 enable = !!(features & NETIF_F_NTUPLE);
2440 h->ae_algo->ops->enable_fd(h, enable);
2441 }
2442
2443 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2444 h->ae_algo->ops->cls_flower_active(h)) {
2445 netdev_err(netdev,
2446 "there are offloaded TC filters active, cannot disable HW TC offload");
2447 return -EINVAL;
2448 }
2449
2450 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2451 h->ae_algo->ops->enable_vlan_filter) {
2452 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2453 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2454 if (ret)
2455 return ret;
2456 }
2457
2458 netdev->features = features;
2459 return 0;
2460 }
2461
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2462 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2463 struct net_device *dev,
2464 netdev_features_t features)
2465 {
2466 #define HNS3_MAX_HDR_LEN 480U
2467 #define HNS3_MAX_L4_HDR_LEN 60U
2468
2469 size_t len;
2470
2471 if (skb->ip_summed != CHECKSUM_PARTIAL)
2472 return features;
2473
2474 if (skb->encapsulation)
2475 len = skb_inner_transport_header(skb) - skb->data;
2476 else
2477 len = skb_transport_header(skb) - skb->data;
2478
2479 /* Assume L4 is 60 byte as TCP is the only protocol with a
2480 * a flexible value, and it's max len is 60 bytes.
2481 */
2482 len += HNS3_MAX_L4_HDR_LEN;
2483
2484 /* Hardware only supports checksum on the skb with a max header
2485 * len of 480 bytes.
2486 */
2487 if (len > HNS3_MAX_HDR_LEN)
2488 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2489
2490 return features;
2491 }
2492
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2493 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2494 struct hns3_enet_ring *ring, bool is_tx)
2495 {
2496 unsigned int start;
2497
2498 do {
2499 start = u64_stats_fetch_begin_irq(&ring->syncp);
2500 if (is_tx) {
2501 stats->tx_bytes += ring->stats.tx_bytes;
2502 stats->tx_packets += ring->stats.tx_pkts;
2503 stats->tx_dropped += ring->stats.sw_err_cnt;
2504 stats->tx_dropped += ring->stats.tx_vlan_err;
2505 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2506 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2507 stats->tx_dropped += ring->stats.tx_tso_err;
2508 stats->tx_dropped += ring->stats.over_max_recursion;
2509 stats->tx_dropped += ring->stats.hw_limitation;
2510 stats->tx_dropped += ring->stats.copy_bits_err;
2511 stats->tx_dropped += ring->stats.skb2sgl_err;
2512 stats->tx_dropped += ring->stats.map_sg_err;
2513 stats->tx_errors += ring->stats.sw_err_cnt;
2514 stats->tx_errors += ring->stats.tx_vlan_err;
2515 stats->tx_errors += ring->stats.tx_l4_proto_err;
2516 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2517 stats->tx_errors += ring->stats.tx_tso_err;
2518 stats->tx_errors += ring->stats.over_max_recursion;
2519 stats->tx_errors += ring->stats.hw_limitation;
2520 stats->tx_errors += ring->stats.copy_bits_err;
2521 stats->tx_errors += ring->stats.skb2sgl_err;
2522 stats->tx_errors += ring->stats.map_sg_err;
2523 } else {
2524 stats->rx_bytes += ring->stats.rx_bytes;
2525 stats->rx_packets += ring->stats.rx_pkts;
2526 stats->rx_dropped += ring->stats.l2_err;
2527 stats->rx_errors += ring->stats.l2_err;
2528 stats->rx_errors += ring->stats.l3l4_csum_err;
2529 stats->rx_crc_errors += ring->stats.l2_err;
2530 stats->multicast += ring->stats.rx_multicast;
2531 stats->rx_length_errors += ring->stats.err_pkt_len;
2532 }
2533 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2534 }
2535
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2536 static void hns3_nic_get_stats64(struct net_device *netdev,
2537 struct rtnl_link_stats64 *stats)
2538 {
2539 struct hns3_nic_priv *priv = netdev_priv(netdev);
2540 int queue_num = priv->ae_handle->kinfo.num_tqps;
2541 struct hnae3_handle *handle = priv->ae_handle;
2542 struct rtnl_link_stats64 ring_total_stats;
2543 struct hns3_enet_ring *ring;
2544 unsigned int idx;
2545
2546 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2547 return;
2548
2549 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2550
2551 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2552 for (idx = 0; idx < queue_num; idx++) {
2553 /* fetch the tx stats */
2554 ring = &priv->ring[idx];
2555 hns3_fetch_stats(&ring_total_stats, ring, true);
2556
2557 /* fetch the rx stats */
2558 ring = &priv->ring[idx + queue_num];
2559 hns3_fetch_stats(&ring_total_stats, ring, false);
2560 }
2561
2562 stats->tx_bytes = ring_total_stats.tx_bytes;
2563 stats->tx_packets = ring_total_stats.tx_packets;
2564 stats->rx_bytes = ring_total_stats.rx_bytes;
2565 stats->rx_packets = ring_total_stats.rx_packets;
2566
2567 stats->rx_errors = ring_total_stats.rx_errors;
2568 stats->multicast = ring_total_stats.multicast;
2569 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2570 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2571 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2572
2573 stats->tx_errors = ring_total_stats.tx_errors;
2574 stats->rx_dropped = ring_total_stats.rx_dropped;
2575 stats->tx_dropped = ring_total_stats.tx_dropped;
2576 stats->collisions = netdev->stats.collisions;
2577 stats->rx_over_errors = netdev->stats.rx_over_errors;
2578 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2579 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2580 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2581 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2582 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2583 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2584 stats->tx_window_errors = netdev->stats.tx_window_errors;
2585 stats->rx_compressed = netdev->stats.rx_compressed;
2586 stats->tx_compressed = netdev->stats.tx_compressed;
2587 }
2588
hns3_setup_tc(struct net_device * netdev,void * type_data)2589 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2590 {
2591 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2592 struct hnae3_knic_private_info *kinfo;
2593 u8 tc = mqprio_qopt->qopt.num_tc;
2594 u16 mode = mqprio_qopt->mode;
2595 u8 hw = mqprio_qopt->qopt.hw;
2596 struct hnae3_handle *h;
2597
2598 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2599 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2600 return -EOPNOTSUPP;
2601
2602 if (tc > HNAE3_MAX_TC)
2603 return -EINVAL;
2604
2605 if (!netdev)
2606 return -EINVAL;
2607
2608 h = hns3_get_handle(netdev);
2609 kinfo = &h->kinfo;
2610
2611 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2612
2613 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2614 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2615 }
2616
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2617 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2618 struct flow_cls_offload *flow)
2619 {
2620 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2621 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2622
2623 switch (flow->command) {
2624 case FLOW_CLS_REPLACE:
2625 if (h->ae_algo->ops->add_cls_flower)
2626 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2627 break;
2628 case FLOW_CLS_DESTROY:
2629 if (h->ae_algo->ops->del_cls_flower)
2630 return h->ae_algo->ops->del_cls_flower(h, flow);
2631 break;
2632 default:
2633 break;
2634 }
2635
2636 return -EOPNOTSUPP;
2637 }
2638
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2639 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2640 void *cb_priv)
2641 {
2642 struct hns3_nic_priv *priv = cb_priv;
2643
2644 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2645 return -EOPNOTSUPP;
2646
2647 switch (type) {
2648 case TC_SETUP_CLSFLOWER:
2649 return hns3_setup_tc_cls_flower(priv, type_data);
2650 default:
2651 return -EOPNOTSUPP;
2652 }
2653 }
2654
2655 static LIST_HEAD(hns3_block_cb_list);
2656
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2657 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2658 void *type_data)
2659 {
2660 struct hns3_nic_priv *priv = netdev_priv(dev);
2661 int ret;
2662
2663 switch (type) {
2664 case TC_SETUP_QDISC_MQPRIO:
2665 ret = hns3_setup_tc(dev, type_data);
2666 break;
2667 case TC_SETUP_BLOCK:
2668 ret = flow_block_cb_setup_simple(type_data,
2669 &hns3_block_cb_list,
2670 hns3_setup_tc_block_cb,
2671 priv, priv, true);
2672 break;
2673 default:
2674 return -EOPNOTSUPP;
2675 }
2676
2677 return ret;
2678 }
2679
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2680 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2681 __be16 proto, u16 vid)
2682 {
2683 struct hnae3_handle *h = hns3_get_handle(netdev);
2684 int ret = -EIO;
2685
2686 if (h->ae_algo->ops->set_vlan_filter)
2687 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2688
2689 return ret;
2690 }
2691
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2692 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2693 __be16 proto, u16 vid)
2694 {
2695 struct hnae3_handle *h = hns3_get_handle(netdev);
2696 int ret = -EIO;
2697
2698 if (h->ae_algo->ops->set_vlan_filter)
2699 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2700
2701 return ret;
2702 }
2703
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2704 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2705 u8 qos, __be16 vlan_proto)
2706 {
2707 struct hnae3_handle *h = hns3_get_handle(netdev);
2708 int ret = -EIO;
2709
2710 netif_dbg(h, drv, netdev,
2711 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2712 vf, vlan, qos, ntohs(vlan_proto));
2713
2714 if (h->ae_algo->ops->set_vf_vlan_filter)
2715 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2716 qos, vlan_proto);
2717
2718 return ret;
2719 }
2720
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2721 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2722 {
2723 struct hnae3_handle *handle = hns3_get_handle(netdev);
2724
2725 if (hns3_nic_resetting(netdev))
2726 return -EBUSY;
2727
2728 if (!handle->ae_algo->ops->set_vf_spoofchk)
2729 return -EOPNOTSUPP;
2730
2731 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2732 }
2733
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2734 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2735 {
2736 struct hnae3_handle *handle = hns3_get_handle(netdev);
2737
2738 if (!handle->ae_algo->ops->set_vf_trust)
2739 return -EOPNOTSUPP;
2740
2741 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2742 }
2743
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2744 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2745 {
2746 struct hnae3_handle *h = hns3_get_handle(netdev);
2747 int ret;
2748
2749 if (hns3_nic_resetting(netdev))
2750 return -EBUSY;
2751
2752 if (!h->ae_algo->ops->set_mtu)
2753 return -EOPNOTSUPP;
2754
2755 netif_dbg(h, drv, netdev,
2756 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2757
2758 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2759 if (ret)
2760 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2761 ret);
2762 else
2763 netdev->mtu = new_mtu;
2764
2765 return ret;
2766 }
2767
hns3_get_timeout_queue(struct net_device * ndev)2768 static int hns3_get_timeout_queue(struct net_device *ndev)
2769 {
2770 int i;
2771
2772 /* Find the stopped queue the same way the stack does */
2773 for (i = 0; i < ndev->num_tx_queues; i++) {
2774 struct netdev_queue *q;
2775 unsigned long trans_start;
2776
2777 q = netdev_get_tx_queue(ndev, i);
2778 trans_start = READ_ONCE(q->trans_start);
2779 if (netif_xmit_stopped(q) &&
2780 time_after(jiffies,
2781 (trans_start + ndev->watchdog_timeo))) {
2782 #ifdef CONFIG_BQL
2783 struct dql *dql = &q->dql;
2784
2785 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2786 dql->last_obj_cnt, dql->num_queued,
2787 dql->adj_limit, dql->num_completed);
2788 #endif
2789 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2790 q->state,
2791 jiffies_to_msecs(jiffies - trans_start));
2792 break;
2793 }
2794 }
2795
2796 return i;
2797 }
2798
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2799 static void hns3_dump_queue_stats(struct net_device *ndev,
2800 struct hns3_enet_ring *tx_ring,
2801 int timeout_queue)
2802 {
2803 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2804 struct hns3_nic_priv *priv = netdev_priv(ndev);
2805
2806 netdev_info(ndev,
2807 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2808 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2809 tx_ring->next_to_clean, napi->state);
2810
2811 netdev_info(ndev,
2812 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2813 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2814 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2815
2816 netdev_info(ndev,
2817 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2818 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2819 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2820
2821 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2822 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2823 }
2824
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2825 static void hns3_dump_queue_reg(struct net_device *ndev,
2826 struct hns3_enet_ring *tx_ring)
2827 {
2828 netdev_info(ndev,
2829 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2830 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2831 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2832 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2833 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2834 readl(tx_ring->tqp_vector->mask_addr));
2835 netdev_info(ndev,
2836 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2837 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2838 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2839 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2840 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2841 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2842 hns3_tqp_read_reg(tx_ring,
2843 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2844 }
2845
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2846 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2847 {
2848 struct hns3_nic_priv *priv = netdev_priv(ndev);
2849 struct hnae3_handle *h = hns3_get_handle(ndev);
2850 struct hns3_enet_ring *tx_ring;
2851 int timeout_queue;
2852
2853 timeout_queue = hns3_get_timeout_queue(ndev);
2854 if (timeout_queue >= ndev->num_tx_queues) {
2855 netdev_info(ndev,
2856 "no netdev TX timeout queue found, timeout count: %llu\n",
2857 priv->tx_timeout_count);
2858 return false;
2859 }
2860
2861 priv->tx_timeout_count++;
2862
2863 tx_ring = &priv->ring[timeout_queue];
2864 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2865
2866 /* When mac received many pause frames continuous, it's unable to send
2867 * packets, which may cause tx timeout
2868 */
2869 if (h->ae_algo->ops->get_mac_stats) {
2870 struct hns3_mac_stats mac_stats;
2871
2872 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2873 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2874 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2875 }
2876
2877 hns3_dump_queue_reg(ndev, tx_ring);
2878
2879 return true;
2880 }
2881
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2882 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2883 {
2884 struct hns3_nic_priv *priv = netdev_priv(ndev);
2885 struct hnae3_handle *h = priv->ae_handle;
2886
2887 if (!hns3_get_tx_timeo_queue_info(ndev))
2888 return;
2889
2890 /* request the reset, and let the hclge to determine
2891 * which reset level should be done
2892 */
2893 if (h->ae_algo->ops->reset_event)
2894 h->ae_algo->ops->reset_event(h->pdev, h);
2895 }
2896
2897 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2898 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2899 u16 rxq_index, u32 flow_id)
2900 {
2901 struct hnae3_handle *h = hns3_get_handle(dev);
2902 struct flow_keys fkeys;
2903
2904 if (!h->ae_algo->ops->add_arfs_entry)
2905 return -EOPNOTSUPP;
2906
2907 if (skb->encapsulation)
2908 return -EPROTONOSUPPORT;
2909
2910 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2911 return -EPROTONOSUPPORT;
2912
2913 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2914 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2915 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2916 fkeys.basic.ip_proto != IPPROTO_UDP))
2917 return -EPROTONOSUPPORT;
2918
2919 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2920 }
2921 #endif
2922
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2923 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2924 struct ifla_vf_info *ivf)
2925 {
2926 struct hnae3_handle *h = hns3_get_handle(ndev);
2927
2928 if (!h->ae_algo->ops->get_vf_config)
2929 return -EOPNOTSUPP;
2930
2931 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2932 }
2933
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2934 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2935 int link_state)
2936 {
2937 struct hnae3_handle *h = hns3_get_handle(ndev);
2938
2939 if (!h->ae_algo->ops->set_vf_link_state)
2940 return -EOPNOTSUPP;
2941
2942 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2943 }
2944
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2945 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2946 int min_tx_rate, int max_tx_rate)
2947 {
2948 struct hnae3_handle *h = hns3_get_handle(ndev);
2949
2950 if (!h->ae_algo->ops->set_vf_rate)
2951 return -EOPNOTSUPP;
2952
2953 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2954 false);
2955 }
2956
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2957 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2958 {
2959 struct hnae3_handle *h = hns3_get_handle(netdev);
2960 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2961
2962 if (!h->ae_algo->ops->set_vf_mac)
2963 return -EOPNOTSUPP;
2964
2965 if (is_multicast_ether_addr(mac)) {
2966 hnae3_format_mac_addr(format_mac_addr, mac);
2967 netdev_err(netdev,
2968 "Invalid MAC:%s specified. Could not set MAC\n",
2969 format_mac_addr);
2970 return -EINVAL;
2971 }
2972
2973 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2974 }
2975
2976 #define HNS3_INVALID_DSCP 0xff
2977 #define HNS3_DSCP_SHIFT 2
2978
hns3_get_skb_dscp(struct sk_buff * skb)2979 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2980 {
2981 __be16 protocol = skb->protocol;
2982 u8 dscp = HNS3_INVALID_DSCP;
2983
2984 if (protocol == htons(ETH_P_8021Q))
2985 protocol = vlan_get_protocol(skb);
2986
2987 if (protocol == htons(ETH_P_IP))
2988 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2989 else if (protocol == htons(ETH_P_IPV6))
2990 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2991
2992 return dscp;
2993 }
2994
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)2995 static u16 hns3_nic_select_queue(struct net_device *netdev,
2996 struct sk_buff *skb,
2997 struct net_device *sb_dev)
2998 {
2999 struct hnae3_handle *h = hns3_get_handle(netdev);
3000 u8 dscp;
3001
3002 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3003 !h->ae_algo->ops->get_dscp_prio)
3004 goto out;
3005
3006 dscp = hns3_get_skb_dscp(skb);
3007 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3008 goto out;
3009
3010 skb->priority = h->kinfo.dscp_prio[dscp];
3011 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3012 skb->priority = 0;
3013
3014 out:
3015 return netdev_pick_tx(netdev, skb, sb_dev);
3016 }
3017
3018 static const struct net_device_ops hns3_nic_netdev_ops = {
3019 .ndo_open = hns3_nic_net_open,
3020 .ndo_stop = hns3_nic_net_stop,
3021 .ndo_start_xmit = hns3_nic_net_xmit,
3022 .ndo_tx_timeout = hns3_nic_net_timeout,
3023 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3024 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3025 .ndo_change_mtu = hns3_nic_change_mtu,
3026 .ndo_set_features = hns3_nic_set_features,
3027 .ndo_features_check = hns3_features_check,
3028 .ndo_get_stats64 = hns3_nic_get_stats64,
3029 .ndo_setup_tc = hns3_nic_setup_tc,
3030 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3031 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3032 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3033 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3034 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3035 .ndo_set_vf_trust = hns3_set_vf_trust,
3036 #ifdef CONFIG_RFS_ACCEL
3037 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3038 #endif
3039 .ndo_get_vf_config = hns3_nic_get_vf_config,
3040 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3041 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3042 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3043 .ndo_select_queue = hns3_nic_select_queue,
3044 };
3045
hns3_is_phys_func(struct pci_dev * pdev)3046 bool hns3_is_phys_func(struct pci_dev *pdev)
3047 {
3048 u32 dev_id = pdev->device;
3049
3050 switch (dev_id) {
3051 case HNAE3_DEV_ID_GE:
3052 case HNAE3_DEV_ID_25GE:
3053 case HNAE3_DEV_ID_25GE_RDMA:
3054 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3055 case HNAE3_DEV_ID_50GE_RDMA:
3056 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3057 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3058 case HNAE3_DEV_ID_200G_RDMA:
3059 return true;
3060 case HNAE3_DEV_ID_VF:
3061 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3062 return false;
3063 default:
3064 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3065 dev_id);
3066 }
3067
3068 return false;
3069 }
3070
hns3_disable_sriov(struct pci_dev * pdev)3071 static void hns3_disable_sriov(struct pci_dev *pdev)
3072 {
3073 /* If our VFs are assigned we cannot shut down SR-IOV
3074 * without causing issues, so just leave the hardware
3075 * available but disabled
3076 */
3077 if (pci_vfs_assigned(pdev)) {
3078 dev_warn(&pdev->dev,
3079 "disabling driver while VFs are assigned\n");
3080 return;
3081 }
3082
3083 pci_disable_sriov(pdev);
3084 }
3085
3086 /* hns3_probe - Device initialization routine
3087 * @pdev: PCI device information struct
3088 * @ent: entry in hns3_pci_tbl
3089 *
3090 * hns3_probe initializes a PF identified by a pci_dev structure.
3091 * The OS initialization, configuring of the PF private structure,
3092 * and a hardware reset occur.
3093 *
3094 * Returns 0 on success, negative on failure
3095 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3096 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3097 {
3098 struct hnae3_ae_dev *ae_dev;
3099 int ret;
3100
3101 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3102 if (!ae_dev)
3103 return -ENOMEM;
3104
3105 ae_dev->pdev = pdev;
3106 ae_dev->flag = ent->driver_data;
3107 pci_set_drvdata(pdev, ae_dev);
3108
3109 ret = hnae3_register_ae_dev(ae_dev);
3110 if (ret)
3111 pci_set_drvdata(pdev, NULL);
3112
3113 return ret;
3114 }
3115
3116 /**
3117 * hns3_clean_vf_config
3118 * @pdev: pointer to a pci_dev structure
3119 * @num_vfs: number of VFs allocated
3120 *
3121 * Clean residual vf config after disable sriov
3122 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3123 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3124 {
3125 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3126
3127 if (ae_dev->ops->clean_vf_config)
3128 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3129 }
3130
3131 /* hns3_remove - Device removal routine
3132 * @pdev: PCI device information struct
3133 */
hns3_remove(struct pci_dev * pdev)3134 static void hns3_remove(struct pci_dev *pdev)
3135 {
3136 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3137
3138 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3139 hns3_disable_sriov(pdev);
3140
3141 hnae3_unregister_ae_dev(ae_dev);
3142 pci_set_drvdata(pdev, NULL);
3143 }
3144
3145 /**
3146 * hns3_pci_sriov_configure
3147 * @pdev: pointer to a pci_dev structure
3148 * @num_vfs: number of VFs to allocate
3149 *
3150 * Enable or change the number of VFs. Called when the user updates the number
3151 * of VFs in sysfs.
3152 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3153 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3154 {
3155 int ret;
3156
3157 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3158 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3159 return -EINVAL;
3160 }
3161
3162 if (num_vfs) {
3163 ret = pci_enable_sriov(pdev, num_vfs);
3164 if (ret)
3165 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3166 else
3167 return num_vfs;
3168 } else if (!pci_vfs_assigned(pdev)) {
3169 int num_vfs_pre = pci_num_vf(pdev);
3170
3171 pci_disable_sriov(pdev);
3172 hns3_clean_vf_config(pdev, num_vfs_pre);
3173 } else {
3174 dev_warn(&pdev->dev,
3175 "Unable to free VFs because some are assigned to VMs.\n");
3176 }
3177
3178 return 0;
3179 }
3180
hns3_shutdown(struct pci_dev * pdev)3181 static void hns3_shutdown(struct pci_dev *pdev)
3182 {
3183 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3184
3185 hnae3_unregister_ae_dev(ae_dev);
3186 pci_set_drvdata(pdev, NULL);
3187
3188 if (system_state == SYSTEM_POWER_OFF)
3189 pci_set_power_state(pdev, PCI_D3hot);
3190 }
3191
hns3_suspend(struct device * dev)3192 static int __maybe_unused hns3_suspend(struct device *dev)
3193 {
3194 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3195
3196 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3197 dev_info(dev, "Begin to suspend.\n");
3198 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3199 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3200 }
3201
3202 return 0;
3203 }
3204
hns3_resume(struct device * dev)3205 static int __maybe_unused hns3_resume(struct device *dev)
3206 {
3207 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3208
3209 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3210 dev_info(dev, "Begin to resume.\n");
3211 if (ae_dev->ops && ae_dev->ops->reset_done)
3212 ae_dev->ops->reset_done(ae_dev);
3213 }
3214
3215 return 0;
3216 }
3217
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3218 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3219 pci_channel_state_t state)
3220 {
3221 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3222 pci_ers_result_t ret;
3223
3224 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3225
3226 if (state == pci_channel_io_perm_failure)
3227 return PCI_ERS_RESULT_DISCONNECT;
3228
3229 if (!ae_dev || !ae_dev->ops) {
3230 dev_err(&pdev->dev,
3231 "Can't recover - error happened before device initialized\n");
3232 return PCI_ERS_RESULT_NONE;
3233 }
3234
3235 if (ae_dev->ops->handle_hw_ras_error)
3236 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3237 else
3238 return PCI_ERS_RESULT_NONE;
3239
3240 return ret;
3241 }
3242
hns3_slot_reset(struct pci_dev * pdev)3243 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3244 {
3245 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3246 const struct hnae3_ae_ops *ops;
3247 enum hnae3_reset_type reset_type;
3248 struct device *dev = &pdev->dev;
3249
3250 if (!ae_dev || !ae_dev->ops)
3251 return PCI_ERS_RESULT_NONE;
3252
3253 ops = ae_dev->ops;
3254 /* request the reset */
3255 if (ops->reset_event && ops->get_reset_level &&
3256 ops->set_default_reset_request) {
3257 if (ae_dev->hw_err_reset_req) {
3258 reset_type = ops->get_reset_level(ae_dev,
3259 &ae_dev->hw_err_reset_req);
3260 ops->set_default_reset_request(ae_dev, reset_type);
3261 dev_info(dev, "requesting reset due to PCI error\n");
3262 ops->reset_event(pdev, NULL);
3263 }
3264
3265 return PCI_ERS_RESULT_RECOVERED;
3266 }
3267
3268 return PCI_ERS_RESULT_DISCONNECT;
3269 }
3270
hns3_reset_prepare(struct pci_dev * pdev)3271 static void hns3_reset_prepare(struct pci_dev *pdev)
3272 {
3273 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3274
3275 dev_info(&pdev->dev, "FLR prepare\n");
3276 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3277 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3278 }
3279
hns3_reset_done(struct pci_dev * pdev)3280 static void hns3_reset_done(struct pci_dev *pdev)
3281 {
3282 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3283
3284 dev_info(&pdev->dev, "FLR done\n");
3285 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3286 ae_dev->ops->reset_done(ae_dev);
3287 }
3288
3289 static const struct pci_error_handlers hns3_err_handler = {
3290 .error_detected = hns3_error_detected,
3291 .slot_reset = hns3_slot_reset,
3292 .reset_prepare = hns3_reset_prepare,
3293 .reset_done = hns3_reset_done,
3294 };
3295
3296 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3297
3298 static struct pci_driver hns3_driver = {
3299 .name = hns3_driver_name,
3300 .id_table = hns3_pci_tbl,
3301 .probe = hns3_probe,
3302 .remove = hns3_remove,
3303 .shutdown = hns3_shutdown,
3304 .driver.pm = &hns3_pm_ops,
3305 .sriov_configure = hns3_pci_sriov_configure,
3306 .err_handler = &hns3_err_handler,
3307 };
3308
3309 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3310 static void hns3_set_default_feature(struct net_device *netdev)
3311 {
3312 struct hnae3_handle *h = hns3_get_handle(netdev);
3313 struct pci_dev *pdev = h->pdev;
3314 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3315
3316 netdev->priv_flags |= IFF_UNICAST_FLT;
3317
3318 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3319 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3320 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3321 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3322 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3323 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3324
3325 if (hnae3_ae_dev_gro_supported(ae_dev))
3326 netdev->features |= NETIF_F_GRO_HW;
3327
3328 if (hnae3_ae_dev_fd_supported(ae_dev))
3329 netdev->features |= NETIF_F_NTUPLE;
3330
3331 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3332 netdev->features |= NETIF_F_GSO_UDP_L4;
3333
3334 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3335 netdev->features |= NETIF_F_HW_CSUM;
3336 else
3337 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3338
3339 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3340 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3341
3342 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3343 netdev->features |= NETIF_F_HW_TC;
3344
3345 netdev->hw_features |= netdev->features;
3346 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3347 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3348
3349 netdev->vlan_features |= netdev->features &
3350 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3351 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3352 NETIF_F_HW_TC);
3353
3354 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3355
3356 /* The device_version V3 hardware can't offload the checksum for IP in
3357 * GRE packets, but can do it for NvGRE. So default to disable the
3358 * checksum and GSO offload for GRE.
3359 */
3360 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3361 netdev->features &= ~NETIF_F_GSO_GRE;
3362 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3363 }
3364 }
3365
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3366 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3367 struct hns3_desc_cb *cb)
3368 {
3369 unsigned int order = hns3_page_order(ring);
3370 struct page *p;
3371
3372 if (ring->page_pool) {
3373 p = page_pool_dev_alloc_frag(ring->page_pool,
3374 &cb->page_offset,
3375 hns3_buf_size(ring));
3376 if (unlikely(!p))
3377 return -ENOMEM;
3378
3379 cb->priv = p;
3380 cb->buf = page_address(p);
3381 cb->dma = page_pool_get_dma_addr(p);
3382 cb->type = DESC_TYPE_PP_FRAG;
3383 cb->reuse_flag = 0;
3384 return 0;
3385 }
3386
3387 p = dev_alloc_pages(order);
3388 if (!p)
3389 return -ENOMEM;
3390
3391 cb->priv = p;
3392 cb->page_offset = 0;
3393 cb->reuse_flag = 0;
3394 cb->buf = page_address(p);
3395 cb->length = hns3_page_size(ring);
3396 cb->type = DESC_TYPE_PAGE;
3397 page_ref_add(p, USHRT_MAX - 1);
3398 cb->pagecnt_bias = USHRT_MAX;
3399
3400 return 0;
3401 }
3402
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3403 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3404 struct hns3_desc_cb *cb, int budget)
3405 {
3406 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3407 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3408 napi_consume_skb(cb->priv, budget);
3409 else if (!HNAE3_IS_TX_RING(ring)) {
3410 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3411 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3412 else if (cb->type & DESC_TYPE_PP_FRAG)
3413 page_pool_put_full_page(ring->page_pool, cb->priv,
3414 false);
3415 }
3416 memset(cb, 0, sizeof(*cb));
3417 }
3418
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3419 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3420 {
3421 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3422 cb->length, ring_to_dma_dir(ring));
3423
3424 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3425 return -EIO;
3426
3427 return 0;
3428 }
3429
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3430 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3431 struct hns3_desc_cb *cb)
3432 {
3433 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3434 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3435 ring_to_dma_dir(ring));
3436 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3437 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3438 ring_to_dma_dir(ring));
3439 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3440 DESC_TYPE_SGL_SKB))
3441 hns3_tx_spare_reclaim_cb(ring, cb);
3442 }
3443
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3444 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3445 {
3446 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3447 ring->desc[i].addr = 0;
3448 ring->desc_cb[i].refill = 0;
3449 }
3450
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3451 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3452 int budget)
3453 {
3454 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3455
3456 if (!ring->desc_cb[i].dma)
3457 return;
3458
3459 hns3_buffer_detach(ring, i);
3460 hns3_free_buffer(ring, cb, budget);
3461 }
3462
hns3_free_buffers(struct hns3_enet_ring * ring)3463 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3464 {
3465 int i;
3466
3467 for (i = 0; i < ring->desc_num; i++)
3468 hns3_free_buffer_detach(ring, i, 0);
3469 }
3470
3471 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3472 static void hns3_free_desc(struct hns3_enet_ring *ring)
3473 {
3474 int size = ring->desc_num * sizeof(ring->desc[0]);
3475
3476 hns3_free_buffers(ring);
3477
3478 if (ring->desc) {
3479 dma_free_coherent(ring_to_dev(ring), size,
3480 ring->desc, ring->desc_dma_addr);
3481 ring->desc = NULL;
3482 }
3483 }
3484
hns3_alloc_desc(struct hns3_enet_ring * ring)3485 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3486 {
3487 int size = ring->desc_num * sizeof(ring->desc[0]);
3488
3489 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3490 &ring->desc_dma_addr, GFP_KERNEL);
3491 if (!ring->desc)
3492 return -ENOMEM;
3493
3494 return 0;
3495 }
3496
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3497 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3498 struct hns3_desc_cb *cb)
3499 {
3500 int ret;
3501
3502 ret = hns3_alloc_buffer(ring, cb);
3503 if (ret || ring->page_pool)
3504 goto out;
3505
3506 ret = hns3_map_buffer(ring, cb);
3507 if (ret)
3508 goto out_with_buf;
3509
3510 return 0;
3511
3512 out_with_buf:
3513 hns3_free_buffer(ring, cb, 0);
3514 out:
3515 return ret;
3516 }
3517
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3518 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3519 {
3520 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3521
3522 if (ret)
3523 return ret;
3524
3525 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3526 ring->desc_cb[i].page_offset);
3527 ring->desc_cb[i].refill = 1;
3528
3529 return 0;
3530 }
3531
3532 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3533 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3534 {
3535 int i, j, ret;
3536
3537 for (i = 0; i < ring->desc_num; i++) {
3538 ret = hns3_alloc_and_attach_buffer(ring, i);
3539 if (ret)
3540 goto out_buffer_fail;
3541 }
3542
3543 return 0;
3544
3545 out_buffer_fail:
3546 for (j = i - 1; j >= 0; j--)
3547 hns3_free_buffer_detach(ring, j, 0);
3548 return ret;
3549 }
3550
3551 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3552 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3553 struct hns3_desc_cb *res_cb)
3554 {
3555 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3556 ring->desc_cb[i] = *res_cb;
3557 ring->desc_cb[i].refill = 1;
3558 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3559 ring->desc_cb[i].page_offset);
3560 ring->desc[i].rx.bd_base_info = 0;
3561 }
3562
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3563 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3564 {
3565 ring->desc_cb[i].reuse_flag = 0;
3566 ring->desc_cb[i].refill = 1;
3567 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3568 ring->desc_cb[i].page_offset);
3569 ring->desc[i].rx.bd_base_info = 0;
3570
3571 dma_sync_single_for_device(ring_to_dev(ring),
3572 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3573 hns3_buf_size(ring),
3574 DMA_FROM_DEVICE);
3575 }
3576
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3577 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3578 int *bytes, int *pkts, int budget)
3579 {
3580 /* This smp_load_acquire() pairs with smp_store_release() in
3581 * hns3_tx_doorbell().
3582 */
3583 int ltu = smp_load_acquire(&ring->last_to_use);
3584 int ntc = ring->next_to_clean;
3585 struct hns3_desc_cb *desc_cb;
3586 bool reclaimed = false;
3587 struct hns3_desc *desc;
3588
3589 while (ltu != ntc) {
3590 desc = &ring->desc[ntc];
3591
3592 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3593 BIT(HNS3_TXD_VLD_B))
3594 break;
3595
3596 desc_cb = &ring->desc_cb[ntc];
3597
3598 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3599 DESC_TYPE_BOUNCE_HEAD |
3600 DESC_TYPE_SGL_SKB)) {
3601 (*pkts)++;
3602 (*bytes) += desc_cb->send_bytes;
3603 }
3604
3605 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3606 hns3_free_buffer_detach(ring, ntc, budget);
3607
3608 if (++ntc == ring->desc_num)
3609 ntc = 0;
3610
3611 /* Issue prefetch for next Tx descriptor */
3612 prefetch(&ring->desc_cb[ntc]);
3613 reclaimed = true;
3614 }
3615
3616 if (unlikely(!reclaimed))
3617 return false;
3618
3619 /* This smp_store_release() pairs with smp_load_acquire() in
3620 * ring_space called by hns3_nic_net_xmit.
3621 */
3622 smp_store_release(&ring->next_to_clean, ntc);
3623
3624 hns3_tx_spare_update(ring);
3625
3626 return true;
3627 }
3628
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3629 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3630 {
3631 struct net_device *netdev = ring_to_netdev(ring);
3632 struct hns3_nic_priv *priv = netdev_priv(netdev);
3633 struct netdev_queue *dev_queue;
3634 int bytes, pkts;
3635
3636 bytes = 0;
3637 pkts = 0;
3638
3639 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3640 return;
3641
3642 ring->tqp_vector->tx_group.total_bytes += bytes;
3643 ring->tqp_vector->tx_group.total_packets += pkts;
3644
3645 u64_stats_update_begin(&ring->syncp);
3646 ring->stats.tx_bytes += bytes;
3647 ring->stats.tx_pkts += pkts;
3648 u64_stats_update_end(&ring->syncp);
3649
3650 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3651 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3652
3653 if (unlikely(netif_carrier_ok(netdev) &&
3654 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3655 /* Make sure that anybody stopping the queue after this
3656 * sees the new next_to_clean.
3657 */
3658 smp_mb();
3659 if (netif_tx_queue_stopped(dev_queue) &&
3660 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3661 netif_tx_wake_queue(dev_queue);
3662 ring->stats.restart_queue++;
3663 }
3664 }
3665 }
3666
hns3_desc_unused(struct hns3_enet_ring * ring)3667 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3668 {
3669 int ntc = ring->next_to_clean;
3670 int ntu = ring->next_to_use;
3671
3672 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3673 return ring->desc_num;
3674
3675 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3676 }
3677
3678 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3679 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3680 int cleand_count)
3681 {
3682 struct hns3_desc_cb *desc_cb;
3683 struct hns3_desc_cb res_cbs;
3684 int i, ret;
3685
3686 for (i = 0; i < cleand_count; i++) {
3687 desc_cb = &ring->desc_cb[ring->next_to_use];
3688 if (desc_cb->reuse_flag) {
3689 hns3_ring_stats_update(ring, reuse_pg_cnt);
3690
3691 hns3_reuse_buffer(ring, ring->next_to_use);
3692 } else {
3693 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3694 if (ret) {
3695 hns3_ring_stats_update(ring, sw_err_cnt);
3696
3697 hns3_rl_err(ring_to_netdev(ring),
3698 "alloc rx buffer failed: %d\n",
3699 ret);
3700
3701 writel(i, ring->tqp->io_base +
3702 HNS3_RING_RX_RING_HEAD_REG);
3703 return true;
3704 }
3705 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3706
3707 hns3_ring_stats_update(ring, non_reuse_pg);
3708 }
3709
3710 ring_ptr_move_fw(ring, next_to_use);
3711 }
3712
3713 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3714 return false;
3715 }
3716
hns3_can_reuse_page(struct hns3_desc_cb * cb)3717 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3718 {
3719 return page_count(cb->priv) == cb->pagecnt_bias;
3720 }
3721
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3722 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3723 struct hns3_enet_ring *ring,
3724 int pull_len,
3725 struct hns3_desc_cb *desc_cb)
3726 {
3727 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3728 u32 frag_offset = desc_cb->page_offset + pull_len;
3729 int size = le16_to_cpu(desc->rx.size);
3730 u32 frag_size = size - pull_len;
3731 void *frag = napi_alloc_frag(frag_size);
3732
3733 if (unlikely(!frag)) {
3734 hns3_ring_stats_update(ring, frag_alloc_err);
3735
3736 hns3_rl_err(ring_to_netdev(ring),
3737 "failed to allocate rx frag\n");
3738 return -ENOMEM;
3739 }
3740
3741 desc_cb->reuse_flag = 1;
3742 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3743 skb_add_rx_frag(skb, i, virt_to_page(frag),
3744 offset_in_page(frag), frag_size, frag_size);
3745
3746 hns3_ring_stats_update(ring, frag_alloc);
3747 return 0;
3748 }
3749
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3750 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3751 struct hns3_enet_ring *ring, int pull_len,
3752 struct hns3_desc_cb *desc_cb)
3753 {
3754 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3755 u32 frag_offset = desc_cb->page_offset + pull_len;
3756 int size = le16_to_cpu(desc->rx.size);
3757 u32 truesize = hns3_buf_size(ring);
3758 u32 frag_size = size - pull_len;
3759 int ret = 0;
3760 bool reused;
3761
3762 if (ring->page_pool) {
3763 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3764 frag_size, truesize);
3765 return;
3766 }
3767
3768 /* Avoid re-using remote or pfmem page */
3769 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3770 goto out;
3771
3772 reused = hns3_can_reuse_page(desc_cb);
3773
3774 /* Rx page can be reused when:
3775 * 1. Rx page is only owned by the driver when page_offset
3776 * is zero, which means 0 @ truesize will be used by
3777 * stack after skb_add_rx_frag() is called, and the rest
3778 * of rx page can be reused by driver.
3779 * Or
3780 * 2. Rx page is only owned by the driver when page_offset
3781 * is non-zero, which means page_offset @ truesize will
3782 * be used by stack after skb_add_rx_frag() is called,
3783 * and 0 @ truesize can be reused by driver.
3784 */
3785 if ((!desc_cb->page_offset && reused) ||
3786 ((desc_cb->page_offset + truesize + truesize) <=
3787 hns3_page_size(ring) && desc_cb->page_offset)) {
3788 desc_cb->page_offset += truesize;
3789 desc_cb->reuse_flag = 1;
3790 } else if (desc_cb->page_offset && reused) {
3791 desc_cb->page_offset = 0;
3792 desc_cb->reuse_flag = 1;
3793 } else if (frag_size <= ring->rx_copybreak) {
3794 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3795 if (!ret)
3796 return;
3797 }
3798
3799 out:
3800 desc_cb->pagecnt_bias--;
3801
3802 if (unlikely(!desc_cb->pagecnt_bias)) {
3803 page_ref_add(desc_cb->priv, USHRT_MAX);
3804 desc_cb->pagecnt_bias = USHRT_MAX;
3805 }
3806
3807 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3808 frag_size, truesize);
3809
3810 if (unlikely(!desc_cb->reuse_flag))
3811 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3812 }
3813
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3814 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3815 {
3816 __be16 type = skb->protocol;
3817 struct tcphdr *th;
3818 int depth = 0;
3819
3820 while (eth_type_vlan(type)) {
3821 struct vlan_hdr *vh;
3822
3823 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3824 return -EFAULT;
3825
3826 vh = (struct vlan_hdr *)(skb->data + depth);
3827 type = vh->h_vlan_encapsulated_proto;
3828 depth += VLAN_HLEN;
3829 }
3830
3831 skb_set_network_header(skb, depth);
3832
3833 if (type == htons(ETH_P_IP)) {
3834 const struct iphdr *iph = ip_hdr(skb);
3835
3836 depth += sizeof(struct iphdr);
3837 skb_set_transport_header(skb, depth);
3838 th = tcp_hdr(skb);
3839 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3840 iph->daddr, 0);
3841 } else if (type == htons(ETH_P_IPV6)) {
3842 const struct ipv6hdr *iph = ipv6_hdr(skb);
3843
3844 depth += sizeof(struct ipv6hdr);
3845 skb_set_transport_header(skb, depth);
3846 th = tcp_hdr(skb);
3847 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3848 &iph->daddr, 0);
3849 } else {
3850 hns3_rl_err(skb->dev,
3851 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3852 be16_to_cpu(type), depth);
3853 return -EFAULT;
3854 }
3855
3856 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3857 if (th->cwr)
3858 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3859
3860 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3861 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3862
3863 skb->csum_start = (unsigned char *)th - skb->head;
3864 skb->csum_offset = offsetof(struct tcphdr, check);
3865 skb->ip_summed = CHECKSUM_PARTIAL;
3866
3867 trace_hns3_gro(skb);
3868
3869 return 0;
3870 }
3871
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3872 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3873 struct sk_buff *skb, u32 ptype, u16 csum)
3874 {
3875 if (ptype == HNS3_INVALID_PTYPE ||
3876 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3877 return;
3878
3879 hns3_ring_stats_update(ring, csum_complete);
3880 skb->ip_summed = CHECKSUM_COMPLETE;
3881 skb->csum = csum_unfold((__force __sum16)csum);
3882 }
3883
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3884 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3885 u32 ol_info, u32 ptype)
3886 {
3887 int l3_type, l4_type;
3888 int ol4_type;
3889
3890 if (ptype != HNS3_INVALID_PTYPE) {
3891 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3892 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3893
3894 return;
3895 }
3896
3897 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3898 HNS3_RXD_OL4ID_S);
3899 switch (ol4_type) {
3900 case HNS3_OL4_TYPE_MAC_IN_UDP:
3901 case HNS3_OL4_TYPE_NVGRE:
3902 skb->csum_level = 1;
3903 fallthrough;
3904 case HNS3_OL4_TYPE_NO_TUN:
3905 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3906 HNS3_RXD_L3ID_S);
3907 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3908 HNS3_RXD_L4ID_S);
3909 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3910 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3911 l3_type == HNS3_L3_TYPE_IPV6) &&
3912 (l4_type == HNS3_L4_TYPE_UDP ||
3913 l4_type == HNS3_L4_TYPE_TCP ||
3914 l4_type == HNS3_L4_TYPE_SCTP))
3915 skb->ip_summed = CHECKSUM_UNNECESSARY;
3916 break;
3917 default:
3918 break;
3919 }
3920 }
3921
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3922 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3923 u32 l234info, u32 bd_base_info, u32 ol_info,
3924 u16 csum)
3925 {
3926 struct net_device *netdev = ring_to_netdev(ring);
3927 struct hns3_nic_priv *priv = netdev_priv(netdev);
3928 u32 ptype = HNS3_INVALID_PTYPE;
3929
3930 skb->ip_summed = CHECKSUM_NONE;
3931
3932 skb_checksum_none_assert(skb);
3933
3934 if (!(netdev->features & NETIF_F_RXCSUM))
3935 return;
3936
3937 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3938 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3939 HNS3_RXD_PTYPE_S);
3940
3941 hns3_checksum_complete(ring, skb, ptype, csum);
3942
3943 /* check if hardware has done checksum */
3944 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3945 return;
3946
3947 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3948 BIT(HNS3_RXD_OL3E_B) |
3949 BIT(HNS3_RXD_OL4E_B)))) {
3950 skb->ip_summed = CHECKSUM_NONE;
3951 hns3_ring_stats_update(ring, l3l4_csum_err);
3952
3953 return;
3954 }
3955
3956 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3957 }
3958
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3959 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3960 {
3961 if (skb_has_frag_list(skb))
3962 napi_gro_flush(&ring->tqp_vector->napi, false);
3963
3964 napi_gro_receive(&ring->tqp_vector->napi, skb);
3965 }
3966
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3967 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3968 struct hns3_desc *desc, u32 l234info,
3969 u16 *vlan_tag)
3970 {
3971 struct hnae3_handle *handle = ring->tqp->handle;
3972 struct pci_dev *pdev = ring->tqp->handle->pdev;
3973 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3974
3975 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3976 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3977 if (!(*vlan_tag & VLAN_VID_MASK))
3978 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3979
3980 return (*vlan_tag != 0);
3981 }
3982
3983 #define HNS3_STRP_OUTER_VLAN 0x1
3984 #define HNS3_STRP_INNER_VLAN 0x2
3985 #define HNS3_STRP_BOTH 0x3
3986
3987 /* Hardware always insert VLAN tag into RX descriptor when
3988 * remove the tag from packet, driver needs to determine
3989 * reporting which tag to stack.
3990 */
3991 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3992 HNS3_RXD_STRP_TAGP_S)) {
3993 case HNS3_STRP_OUTER_VLAN:
3994 if (handle->port_base_vlan_state !=
3995 HNAE3_PORT_BASE_VLAN_DISABLE)
3996 return false;
3997
3998 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3999 return true;
4000 case HNS3_STRP_INNER_VLAN:
4001 if (handle->port_base_vlan_state !=
4002 HNAE3_PORT_BASE_VLAN_DISABLE)
4003 return false;
4004
4005 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4006 return true;
4007 case HNS3_STRP_BOTH:
4008 if (handle->port_base_vlan_state ==
4009 HNAE3_PORT_BASE_VLAN_DISABLE)
4010 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4011 else
4012 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4013
4014 return true;
4015 default:
4016 return false;
4017 }
4018 }
4019
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4020 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4021 {
4022 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4023 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4024 ring->desc_cb[ring->next_to_clean].refill = 0;
4025 ring->next_to_clean += 1;
4026
4027 if (unlikely(ring->next_to_clean == ring->desc_num))
4028 ring->next_to_clean = 0;
4029 }
4030
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4031 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4032 unsigned char *va)
4033 {
4034 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4035 struct net_device *netdev = ring_to_netdev(ring);
4036 struct sk_buff *skb;
4037
4038 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4039 skb = ring->skb;
4040 if (unlikely(!skb)) {
4041 hns3_rl_err(netdev, "alloc rx skb fail\n");
4042 hns3_ring_stats_update(ring, sw_err_cnt);
4043
4044 return -ENOMEM;
4045 }
4046
4047 trace_hns3_rx_desc(ring);
4048 prefetchw(skb->data);
4049
4050 ring->pending_buf = 1;
4051 ring->frag_num = 0;
4052 ring->tail_skb = NULL;
4053 if (length <= HNS3_RX_HEAD_SIZE) {
4054 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4055
4056 /* We can reuse buffer as-is, just make sure it is reusable */
4057 if (dev_page_is_reusable(desc_cb->priv))
4058 desc_cb->reuse_flag = 1;
4059 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4060 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4061 false);
4062 else /* This page cannot be reused so discard it */
4063 __page_frag_cache_drain(desc_cb->priv,
4064 desc_cb->pagecnt_bias);
4065
4066 hns3_rx_ring_move_fw(ring);
4067 return 0;
4068 }
4069
4070 if (ring->page_pool)
4071 skb_mark_for_recycle(skb);
4072
4073 hns3_ring_stats_update(ring, seg_pkt_cnt);
4074
4075 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4076 __skb_put(skb, ring->pull_len);
4077 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4078 desc_cb);
4079 hns3_rx_ring_move_fw(ring);
4080
4081 return 0;
4082 }
4083
hns3_add_frag(struct hns3_enet_ring * ring)4084 static int hns3_add_frag(struct hns3_enet_ring *ring)
4085 {
4086 struct sk_buff *skb = ring->skb;
4087 struct sk_buff *head_skb = skb;
4088 struct sk_buff *new_skb;
4089 struct hns3_desc_cb *desc_cb;
4090 struct hns3_desc *desc;
4091 u32 bd_base_info;
4092
4093 do {
4094 desc = &ring->desc[ring->next_to_clean];
4095 desc_cb = &ring->desc_cb[ring->next_to_clean];
4096 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4097 /* make sure HW write desc complete */
4098 dma_rmb();
4099 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4100 return -ENXIO;
4101
4102 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4103 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4104 if (unlikely(!new_skb)) {
4105 hns3_rl_err(ring_to_netdev(ring),
4106 "alloc rx fraglist skb fail\n");
4107 return -ENXIO;
4108 }
4109
4110 if (ring->page_pool)
4111 skb_mark_for_recycle(new_skb);
4112
4113 ring->frag_num = 0;
4114
4115 if (ring->tail_skb) {
4116 ring->tail_skb->next = new_skb;
4117 ring->tail_skb = new_skb;
4118 } else {
4119 skb_shinfo(skb)->frag_list = new_skb;
4120 ring->tail_skb = new_skb;
4121 }
4122 }
4123
4124 if (ring->tail_skb) {
4125 head_skb->truesize += hns3_buf_size(ring);
4126 head_skb->data_len += le16_to_cpu(desc->rx.size);
4127 head_skb->len += le16_to_cpu(desc->rx.size);
4128 skb = ring->tail_skb;
4129 }
4130
4131 dma_sync_single_for_cpu(ring_to_dev(ring),
4132 desc_cb->dma + desc_cb->page_offset,
4133 hns3_buf_size(ring),
4134 DMA_FROM_DEVICE);
4135
4136 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4137 trace_hns3_rx_desc(ring);
4138 hns3_rx_ring_move_fw(ring);
4139 ring->pending_buf++;
4140 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4141
4142 return 0;
4143 }
4144
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4145 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4146 struct sk_buff *skb, u32 l234info,
4147 u32 bd_base_info, u32 ol_info, u16 csum)
4148 {
4149 struct net_device *netdev = ring_to_netdev(ring);
4150 struct hns3_nic_priv *priv = netdev_priv(netdev);
4151 u32 l3_type;
4152
4153 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4154 HNS3_RXD_GRO_SIZE_M,
4155 HNS3_RXD_GRO_SIZE_S);
4156 /* if there is no HW GRO, do not set gro params */
4157 if (!skb_shinfo(skb)->gso_size) {
4158 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4159 csum);
4160 return 0;
4161 }
4162
4163 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4164 HNS3_RXD_GRO_COUNT_M,
4165 HNS3_RXD_GRO_COUNT_S);
4166
4167 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4168 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4169 HNS3_RXD_PTYPE_S);
4170
4171 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4172 } else {
4173 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4174 HNS3_RXD_L3ID_S);
4175 }
4176
4177 if (l3_type == HNS3_L3_TYPE_IPV4)
4178 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4179 else if (l3_type == HNS3_L3_TYPE_IPV6)
4180 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4181 else
4182 return -EFAULT;
4183
4184 return hns3_gro_complete(skb, l234info);
4185 }
4186
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4187 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4188 struct sk_buff *skb, u32 rss_hash,
4189 u32 l234info, u32 ol_info)
4190 {
4191 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4192 struct net_device *netdev = ring_to_netdev(ring);
4193 struct hns3_nic_priv *priv = netdev_priv(netdev);
4194
4195 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4196 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4197 HNS3_RXD_PTYPE_S);
4198
4199 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4200 } else {
4201 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4202 HNS3_RXD_L3ID_S);
4203 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4204 HNS3_RXD_L4ID_S);
4205
4206 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4207 l3_type == HNS3_L3_TYPE_IPV6) {
4208 if (l4_type == HNS3_L4_TYPE_UDP ||
4209 l4_type == HNS3_L4_TYPE_TCP ||
4210 l4_type == HNS3_L4_TYPE_SCTP)
4211 rss_type = PKT_HASH_TYPE_L4;
4212 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4213 l4_type == HNS3_L4_TYPE_ICMP)
4214 rss_type = PKT_HASH_TYPE_L3;
4215 }
4216 }
4217
4218 skb_set_hash(skb, rss_hash, rss_type);
4219 }
4220
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4221 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4222 struct hns3_desc *desc, struct sk_buff *skb,
4223 u32 bd_base_info)
4224 {
4225 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4226 struct hnae3_handle *h = hns3_get_handle(netdev);
4227 u32 nsec = le32_to_cpu(desc->ts_nsec);
4228 u32 sec = le32_to_cpu(desc->ts_sec);
4229
4230 if (h->ae_algo->ops->get_rx_hwts)
4231 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4232 }
4233 }
4234
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4235 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4236 struct hns3_desc *desc, struct sk_buff *skb,
4237 u32 l234info)
4238 {
4239 struct net_device *netdev = ring_to_netdev(ring);
4240
4241 /* Based on hw strategy, the tag offloaded will be stored at
4242 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4243 * in one layer tag case.
4244 */
4245 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4246 u16 vlan_tag;
4247
4248 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4249 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4250 vlan_tag);
4251 }
4252 }
4253
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4254 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4255 {
4256 struct net_device *netdev = ring_to_netdev(ring);
4257 enum hns3_pkt_l2t_type l2_frame_type;
4258 u32 bd_base_info, l234info, ol_info;
4259 struct hns3_desc *desc;
4260 unsigned int len;
4261 int pre_ntc, ret;
4262 u16 csum;
4263
4264 /* bdinfo handled below is only valid on the last BD of the
4265 * current packet, and ring->next_to_clean indicates the first
4266 * descriptor of next packet, so need - 1 below.
4267 */
4268 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4269 (ring->desc_num - 1);
4270 desc = &ring->desc[pre_ntc];
4271 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4272 l234info = le32_to_cpu(desc->rx.l234_info);
4273 ol_info = le32_to_cpu(desc->rx.ol_info);
4274 csum = le16_to_cpu(desc->csum);
4275
4276 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4277
4278 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4279
4280 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4281 BIT(HNS3_RXD_L2E_B))))) {
4282 u64_stats_update_begin(&ring->syncp);
4283 if (l234info & BIT(HNS3_RXD_L2E_B))
4284 ring->stats.l2_err++;
4285 else
4286 ring->stats.err_pkt_len++;
4287 u64_stats_update_end(&ring->syncp);
4288
4289 return -EFAULT;
4290 }
4291
4292 len = skb->len;
4293
4294 /* Do update ip stack process */
4295 skb->protocol = eth_type_trans(skb, netdev);
4296
4297 /* This is needed in order to enable forwarding support */
4298 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4299 bd_base_info, ol_info, csum);
4300 if (unlikely(ret)) {
4301 hns3_ring_stats_update(ring, rx_err_cnt);
4302 return ret;
4303 }
4304
4305 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4306 HNS3_RXD_DMAC_S);
4307
4308 u64_stats_update_begin(&ring->syncp);
4309 ring->stats.rx_pkts++;
4310 ring->stats.rx_bytes += len;
4311
4312 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4313 ring->stats.rx_multicast++;
4314
4315 u64_stats_update_end(&ring->syncp);
4316
4317 ring->tqp_vector->rx_group.total_bytes += len;
4318
4319 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4320 l234info, ol_info);
4321 return 0;
4322 }
4323
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4324 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4325 {
4326 struct sk_buff *skb = ring->skb;
4327 struct hns3_desc_cb *desc_cb;
4328 struct hns3_desc *desc;
4329 unsigned int length;
4330 u32 bd_base_info;
4331 int ret;
4332
4333 desc = &ring->desc[ring->next_to_clean];
4334 desc_cb = &ring->desc_cb[ring->next_to_clean];
4335
4336 prefetch(desc);
4337
4338 if (!skb) {
4339 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4340 /* Check valid BD */
4341 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4342 return -ENXIO;
4343
4344 dma_rmb();
4345 length = le16_to_cpu(desc->rx.size);
4346
4347 ring->va = desc_cb->buf + desc_cb->page_offset;
4348
4349 dma_sync_single_for_cpu(ring_to_dev(ring),
4350 desc_cb->dma + desc_cb->page_offset,
4351 hns3_buf_size(ring),
4352 DMA_FROM_DEVICE);
4353
4354 /* Prefetch first cache line of first page.
4355 * Idea is to cache few bytes of the header of the packet.
4356 * Our L1 Cache line size is 64B so need to prefetch twice to make
4357 * it 128B. But in actual we can have greater size of caches with
4358 * 128B Level 1 cache lines. In such a case, single fetch would
4359 * suffice to cache in the relevant part of the header.
4360 */
4361 net_prefetch(ring->va);
4362
4363 ret = hns3_alloc_skb(ring, length, ring->va);
4364 skb = ring->skb;
4365
4366 if (ret < 0) /* alloc buffer fail */
4367 return ret;
4368 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4369 ret = hns3_add_frag(ring);
4370 if (ret)
4371 return ret;
4372 }
4373 } else {
4374 ret = hns3_add_frag(ring);
4375 if (ret)
4376 return ret;
4377 }
4378
4379 /* As the head data may be changed when GRO enable, copy
4380 * the head data in after other data rx completed
4381 */
4382 if (skb->len > HNS3_RX_HEAD_SIZE)
4383 memcpy(skb->data, ring->va,
4384 ALIGN(ring->pull_len, sizeof(long)));
4385
4386 ret = hns3_handle_bdinfo(ring, skb);
4387 if (unlikely(ret)) {
4388 dev_kfree_skb_any(skb);
4389 return ret;
4390 }
4391
4392 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4393 return 0;
4394 }
4395
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4396 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4397 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4398 {
4399 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4400 int unused_count = hns3_desc_unused(ring);
4401 bool failure = false;
4402 int recv_pkts = 0;
4403 int err;
4404
4405 unused_count -= ring->pending_buf;
4406
4407 while (recv_pkts < budget) {
4408 /* Reuse or realloc buffers */
4409 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4410 failure = failure ||
4411 hns3_nic_alloc_rx_buffers(ring, unused_count);
4412 unused_count = 0;
4413 }
4414
4415 /* Poll one pkt */
4416 err = hns3_handle_rx_bd(ring);
4417 /* Do not get FE for the packet or failed to alloc skb */
4418 if (unlikely(!ring->skb || err == -ENXIO)) {
4419 goto out;
4420 } else if (likely(!err)) {
4421 rx_fn(ring, ring->skb);
4422 recv_pkts++;
4423 }
4424
4425 unused_count += ring->pending_buf;
4426 ring->skb = NULL;
4427 ring->pending_buf = 0;
4428 }
4429
4430 out:
4431 /* sync head pointer before exiting, since hardware will calculate
4432 * FBD number with head pointer
4433 */
4434 if (unused_count > 0)
4435 failure = failure ||
4436 hns3_nic_alloc_rx_buffers(ring, unused_count);
4437
4438 return failure ? budget : recv_pkts;
4439 }
4440
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4441 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4442 {
4443 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4444 struct dim_sample sample = {};
4445
4446 if (!rx_group->coal.adapt_enable)
4447 return;
4448
4449 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4450 rx_group->total_bytes, &sample);
4451 net_dim(&rx_group->dim, sample);
4452 }
4453
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4454 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4455 {
4456 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4457 struct dim_sample sample = {};
4458
4459 if (!tx_group->coal.adapt_enable)
4460 return;
4461
4462 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4463 tx_group->total_bytes, &sample);
4464 net_dim(&tx_group->dim, sample);
4465 }
4466
hns3_nic_common_poll(struct napi_struct * napi,int budget)4467 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4468 {
4469 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4470 struct hns3_enet_ring *ring;
4471 int rx_pkt_total = 0;
4472
4473 struct hns3_enet_tqp_vector *tqp_vector =
4474 container_of(napi, struct hns3_enet_tqp_vector, napi);
4475 bool clean_complete = true;
4476 int rx_budget = budget;
4477
4478 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4479 napi_complete(napi);
4480 return 0;
4481 }
4482
4483 /* Since the actual Tx work is minimal, we can give the Tx a larger
4484 * budget and be more aggressive about cleaning up the Tx descriptors.
4485 */
4486 hns3_for_each_ring(ring, tqp_vector->tx_group)
4487 hns3_clean_tx_ring(ring, budget);
4488
4489 /* make sure rx ring budget not smaller than 1 */
4490 if (tqp_vector->num_tqps > 1)
4491 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4492
4493 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4494 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4495 hns3_rx_skb);
4496 if (rx_cleaned >= rx_budget)
4497 clean_complete = false;
4498
4499 rx_pkt_total += rx_cleaned;
4500 }
4501
4502 tqp_vector->rx_group.total_packets += rx_pkt_total;
4503
4504 if (!clean_complete)
4505 return budget;
4506
4507 if (napi_complete(napi) &&
4508 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4509 hns3_update_rx_int_coalesce(tqp_vector);
4510 hns3_update_tx_int_coalesce(tqp_vector);
4511
4512 hns3_mask_vector_irq(tqp_vector, 1);
4513 }
4514
4515 return rx_pkt_total;
4516 }
4517
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4518 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4519 struct hnae3_ring_chain_node **head,
4520 bool is_tx)
4521 {
4522 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4523 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4524 struct hnae3_ring_chain_node *cur_chain = *head;
4525 struct pci_dev *pdev = tqp_vector->handle->pdev;
4526 struct hnae3_ring_chain_node *chain;
4527 struct hns3_enet_ring *ring;
4528
4529 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4530
4531 if (cur_chain) {
4532 while (cur_chain->next)
4533 cur_chain = cur_chain->next;
4534 }
4535
4536 while (ring) {
4537 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4538 if (!chain)
4539 return -ENOMEM;
4540 if (cur_chain)
4541 cur_chain->next = chain;
4542 else
4543 *head = chain;
4544 chain->tqp_index = ring->tqp->tqp_index;
4545 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4546 bit_value);
4547 hnae3_set_field(chain->int_gl_idx,
4548 HNAE3_RING_GL_IDX_M,
4549 HNAE3_RING_GL_IDX_S, field_value);
4550
4551 cur_chain = chain;
4552
4553 ring = ring->next;
4554 }
4555
4556 return 0;
4557 }
4558
4559 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4560 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4561 {
4562 struct pci_dev *pdev = tqp_vector->handle->pdev;
4563 struct hnae3_ring_chain_node *cur_chain = NULL;
4564 struct hnae3_ring_chain_node *chain;
4565
4566 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4567 goto err_free_chain;
4568
4569 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4570 goto err_free_chain;
4571
4572 return cur_chain;
4573
4574 err_free_chain:
4575 while (cur_chain) {
4576 chain = cur_chain->next;
4577 devm_kfree(&pdev->dev, cur_chain);
4578 cur_chain = chain;
4579 }
4580
4581 return NULL;
4582 }
4583
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4584 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4585 struct hnae3_ring_chain_node *head)
4586 {
4587 struct pci_dev *pdev = tqp_vector->handle->pdev;
4588 struct hnae3_ring_chain_node *chain_tmp, *chain;
4589
4590 chain = head;
4591
4592 while (chain) {
4593 chain_tmp = chain->next;
4594 devm_kfree(&pdev->dev, chain);
4595 chain = chain_tmp;
4596 }
4597 }
4598
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4599 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4600 struct hns3_enet_ring *ring)
4601 {
4602 ring->next = group->ring;
4603 group->ring = ring;
4604
4605 group->count++;
4606 }
4607
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4608 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4609 {
4610 struct pci_dev *pdev = priv->ae_handle->pdev;
4611 struct hns3_enet_tqp_vector *tqp_vector;
4612 int num_vectors = priv->vector_num;
4613 int numa_node;
4614 int vector_i;
4615
4616 numa_node = dev_to_node(&pdev->dev);
4617
4618 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4619 tqp_vector = &priv->tqp_vector[vector_i];
4620 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4621 &tqp_vector->affinity_mask);
4622 }
4623 }
4624
hns3_rx_dim_work(struct work_struct * work)4625 static void hns3_rx_dim_work(struct work_struct *work)
4626 {
4627 struct dim *dim = container_of(work, struct dim, work);
4628 struct hns3_enet_ring_group *group = container_of(dim,
4629 struct hns3_enet_ring_group, dim);
4630 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4631 struct dim_cq_moder cur_moder =
4632 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4633
4634 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4635 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4636
4637 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4638 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4639 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4640 }
4641
4642 dim->state = DIM_START_MEASURE;
4643 }
4644
hns3_tx_dim_work(struct work_struct * work)4645 static void hns3_tx_dim_work(struct work_struct *work)
4646 {
4647 struct dim *dim = container_of(work, struct dim, work);
4648 struct hns3_enet_ring_group *group = container_of(dim,
4649 struct hns3_enet_ring_group, dim);
4650 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4651 struct dim_cq_moder cur_moder =
4652 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4653
4654 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4655 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4656
4657 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4658 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4659 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4660 }
4661
4662 dim->state = DIM_START_MEASURE;
4663 }
4664
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4665 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4666 {
4667 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4668 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4669 }
4670
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4671 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4672 {
4673 struct hnae3_handle *h = priv->ae_handle;
4674 struct hns3_enet_tqp_vector *tqp_vector;
4675 int ret;
4676 int i;
4677
4678 hns3_nic_set_cpumask(priv);
4679
4680 for (i = 0; i < priv->vector_num; i++) {
4681 tqp_vector = &priv->tqp_vector[i];
4682 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4683 tqp_vector->num_tqps = 0;
4684 hns3_nic_init_dim(tqp_vector);
4685 }
4686
4687 for (i = 0; i < h->kinfo.num_tqps; i++) {
4688 u16 vector_i = i % priv->vector_num;
4689 u16 tqp_num = h->kinfo.num_tqps;
4690
4691 tqp_vector = &priv->tqp_vector[vector_i];
4692
4693 hns3_add_ring_to_group(&tqp_vector->tx_group,
4694 &priv->ring[i]);
4695
4696 hns3_add_ring_to_group(&tqp_vector->rx_group,
4697 &priv->ring[i + tqp_num]);
4698
4699 priv->ring[i].tqp_vector = tqp_vector;
4700 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4701 tqp_vector->num_tqps++;
4702 }
4703
4704 for (i = 0; i < priv->vector_num; i++) {
4705 struct hnae3_ring_chain_node *vector_ring_chain;
4706
4707 tqp_vector = &priv->tqp_vector[i];
4708
4709 tqp_vector->rx_group.total_bytes = 0;
4710 tqp_vector->rx_group.total_packets = 0;
4711 tqp_vector->tx_group.total_bytes = 0;
4712 tqp_vector->tx_group.total_packets = 0;
4713 tqp_vector->handle = h;
4714
4715 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4716 if (!vector_ring_chain) {
4717 ret = -ENOMEM;
4718 goto map_ring_fail;
4719 }
4720
4721 ret = h->ae_algo->ops->map_ring_to_vector(h,
4722 tqp_vector->vector_irq, vector_ring_chain);
4723
4724 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4725
4726 if (ret)
4727 goto map_ring_fail;
4728
4729 netif_napi_add(priv->netdev, &tqp_vector->napi,
4730 hns3_nic_common_poll);
4731 }
4732
4733 return 0;
4734
4735 map_ring_fail:
4736 while (i--)
4737 netif_napi_del(&priv->tqp_vector[i].napi);
4738
4739 return ret;
4740 }
4741
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4742 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4743 {
4744 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4745 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4746 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4747
4748 /* initialize the configuration for interrupt coalescing.
4749 * 1. GL (Interrupt Gap Limiter)
4750 * 2. RL (Interrupt Rate Limiter)
4751 * 3. QL (Interrupt Quantity Limiter)
4752 *
4753 * Default: enable interrupt coalescing self-adaptive and GL
4754 */
4755 tx_coal->adapt_enable = 1;
4756 rx_coal->adapt_enable = 1;
4757
4758 tx_coal->int_gl = HNS3_INT_GL_50K;
4759 rx_coal->int_gl = HNS3_INT_GL_50K;
4760
4761 rx_coal->flow_level = HNS3_FLOW_LOW;
4762 tx_coal->flow_level = HNS3_FLOW_LOW;
4763
4764 if (ae_dev->dev_specs.int_ql_max) {
4765 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4766 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4767 }
4768 }
4769
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4770 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4771 {
4772 struct hnae3_handle *h = priv->ae_handle;
4773 struct hns3_enet_tqp_vector *tqp_vector;
4774 struct hnae3_vector_info *vector;
4775 struct pci_dev *pdev = h->pdev;
4776 u16 tqp_num = h->kinfo.num_tqps;
4777 u16 vector_num;
4778 int ret = 0;
4779 u16 i;
4780
4781 /* RSS size, cpu online and vector_num should be the same */
4782 /* Should consider 2p/4p later */
4783 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4784
4785 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4786 GFP_KERNEL);
4787 if (!vector)
4788 return -ENOMEM;
4789
4790 /* save the actual available vector number */
4791 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4792
4793 priv->vector_num = vector_num;
4794 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4795 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4796 GFP_KERNEL);
4797 if (!priv->tqp_vector) {
4798 ret = -ENOMEM;
4799 goto out;
4800 }
4801
4802 for (i = 0; i < priv->vector_num; i++) {
4803 tqp_vector = &priv->tqp_vector[i];
4804 tqp_vector->idx = i;
4805 tqp_vector->mask_addr = vector[i].io_addr;
4806 tqp_vector->vector_irq = vector[i].vector;
4807 hns3_vector_coalesce_init(tqp_vector, priv);
4808 }
4809
4810 out:
4811 devm_kfree(&pdev->dev, vector);
4812 return ret;
4813 }
4814
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4815 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4816 {
4817 group->ring = NULL;
4818 group->count = 0;
4819 }
4820
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4821 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4822 {
4823 struct hnae3_ring_chain_node *vector_ring_chain;
4824 struct hnae3_handle *h = priv->ae_handle;
4825 struct hns3_enet_tqp_vector *tqp_vector;
4826 int i;
4827
4828 for (i = 0; i < priv->vector_num; i++) {
4829 tqp_vector = &priv->tqp_vector[i];
4830
4831 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4832 continue;
4833
4834 /* Since the mapping can be overwritten, when fail to get the
4835 * chain between vector and ring, we should go on to deal with
4836 * the remaining options.
4837 */
4838 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4839 if (!vector_ring_chain)
4840 dev_warn(priv->dev, "failed to get ring chain\n");
4841
4842 h->ae_algo->ops->unmap_ring_from_vector(h,
4843 tqp_vector->vector_irq, vector_ring_chain);
4844
4845 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4846
4847 hns3_clear_ring_group(&tqp_vector->rx_group);
4848 hns3_clear_ring_group(&tqp_vector->tx_group);
4849 netif_napi_del(&priv->tqp_vector[i].napi);
4850 }
4851 }
4852
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4853 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4854 {
4855 struct hnae3_handle *h = priv->ae_handle;
4856 struct pci_dev *pdev = h->pdev;
4857 int i, ret;
4858
4859 for (i = 0; i < priv->vector_num; i++) {
4860 struct hns3_enet_tqp_vector *tqp_vector;
4861
4862 tqp_vector = &priv->tqp_vector[i];
4863 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4864 if (ret)
4865 return;
4866 }
4867
4868 devm_kfree(&pdev->dev, priv->tqp_vector);
4869 }
4870
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4871 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4872 unsigned int ring_type)
4873 {
4874 int queue_num = priv->ae_handle->kinfo.num_tqps;
4875 struct hns3_enet_ring *ring;
4876 int desc_num;
4877
4878 if (ring_type == HNAE3_RING_TYPE_TX) {
4879 ring = &priv->ring[q->tqp_index];
4880 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4881 ring->queue_index = q->tqp_index;
4882 ring->tx_copybreak = priv->tx_copybreak;
4883 ring->last_to_use = 0;
4884 } else {
4885 ring = &priv->ring[q->tqp_index + queue_num];
4886 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4887 ring->queue_index = q->tqp_index;
4888 ring->rx_copybreak = priv->rx_copybreak;
4889 }
4890
4891 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4892
4893 ring->tqp = q;
4894 ring->desc = NULL;
4895 ring->desc_cb = NULL;
4896 ring->dev = priv->dev;
4897 ring->desc_dma_addr = 0;
4898 ring->buf_size = q->buf_size;
4899 ring->desc_num = desc_num;
4900 ring->next_to_use = 0;
4901 ring->next_to_clean = 0;
4902 }
4903
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4904 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4905 struct hns3_nic_priv *priv)
4906 {
4907 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4908 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4909 }
4910
hns3_get_ring_config(struct hns3_nic_priv * priv)4911 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4912 {
4913 struct hnae3_handle *h = priv->ae_handle;
4914 struct pci_dev *pdev = h->pdev;
4915 int i;
4916
4917 priv->ring = devm_kzalloc(&pdev->dev,
4918 array3_size(h->kinfo.num_tqps,
4919 sizeof(*priv->ring), 2),
4920 GFP_KERNEL);
4921 if (!priv->ring)
4922 return -ENOMEM;
4923
4924 for (i = 0; i < h->kinfo.num_tqps; i++)
4925 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4926
4927 return 0;
4928 }
4929
hns3_put_ring_config(struct hns3_nic_priv * priv)4930 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4931 {
4932 if (!priv->ring)
4933 return;
4934
4935 devm_kfree(priv->dev, priv->ring);
4936 priv->ring = NULL;
4937 }
4938
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4939 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4940 {
4941 struct page_pool_params pp_params = {
4942 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4943 PP_FLAG_DMA_SYNC_DEV,
4944 .order = hns3_page_order(ring),
4945 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4946 (PAGE_SIZE << hns3_page_order(ring)),
4947 .nid = dev_to_node(ring_to_dev(ring)),
4948 .dev = ring_to_dev(ring),
4949 .dma_dir = DMA_FROM_DEVICE,
4950 .offset = 0,
4951 .max_len = PAGE_SIZE << hns3_page_order(ring),
4952 };
4953
4954 ring->page_pool = page_pool_create(&pp_params);
4955 if (IS_ERR(ring->page_pool)) {
4956 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4957 PTR_ERR(ring->page_pool));
4958 ring->page_pool = NULL;
4959 }
4960 }
4961
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)4962 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4963 {
4964 int ret;
4965
4966 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4967 return -EINVAL;
4968
4969 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4970 sizeof(ring->desc_cb[0]), GFP_KERNEL);
4971 if (!ring->desc_cb) {
4972 ret = -ENOMEM;
4973 goto out;
4974 }
4975
4976 ret = hns3_alloc_desc(ring);
4977 if (ret)
4978 goto out_with_desc_cb;
4979
4980 if (!HNAE3_IS_TX_RING(ring)) {
4981 if (page_pool_enabled)
4982 hns3_alloc_page_pool(ring);
4983
4984 ret = hns3_alloc_ring_buffers(ring);
4985 if (ret)
4986 goto out_with_desc;
4987 } else {
4988 hns3_init_tx_spare_buffer(ring);
4989 }
4990
4991 return 0;
4992
4993 out_with_desc:
4994 hns3_free_desc(ring);
4995 out_with_desc_cb:
4996 devm_kfree(ring_to_dev(ring), ring->desc_cb);
4997 ring->desc_cb = NULL;
4998 out:
4999 return ret;
5000 }
5001
hns3_fini_ring(struct hns3_enet_ring * ring)5002 void hns3_fini_ring(struct hns3_enet_ring *ring)
5003 {
5004 hns3_free_desc(ring);
5005 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5006 ring->desc_cb = NULL;
5007 ring->next_to_clean = 0;
5008 ring->next_to_use = 0;
5009 ring->last_to_use = 0;
5010 ring->pending_buf = 0;
5011 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5012 dev_kfree_skb_any(ring->skb);
5013 ring->skb = NULL;
5014 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5015 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5016
5017 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5018 DMA_TO_DEVICE);
5019 free_pages((unsigned long)tx_spare->buf,
5020 get_order(tx_spare->len));
5021 devm_kfree(ring_to_dev(ring), tx_spare);
5022 ring->tx_spare = NULL;
5023 }
5024
5025 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5026 page_pool_destroy(ring->page_pool);
5027 ring->page_pool = NULL;
5028 }
5029 }
5030
hns3_buf_size2type(u32 buf_size)5031 static int hns3_buf_size2type(u32 buf_size)
5032 {
5033 int bd_size_type;
5034
5035 switch (buf_size) {
5036 case 512:
5037 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5038 break;
5039 case 1024:
5040 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5041 break;
5042 case 2048:
5043 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5044 break;
5045 case 4096:
5046 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5047 break;
5048 default:
5049 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5050 }
5051
5052 return bd_size_type;
5053 }
5054
hns3_init_ring_hw(struct hns3_enet_ring * ring)5055 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5056 {
5057 dma_addr_t dma = ring->desc_dma_addr;
5058 struct hnae3_queue *q = ring->tqp;
5059
5060 if (!HNAE3_IS_TX_RING(ring)) {
5061 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5062 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5063 (u32)((dma >> 31) >> 1));
5064
5065 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5066 hns3_buf_size2type(ring->buf_size));
5067 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5068 ring->desc_num / 8 - 1);
5069 } else {
5070 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5071 (u32)dma);
5072 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5073 (u32)((dma >> 31) >> 1));
5074
5075 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5076 ring->desc_num / 8 - 1);
5077 }
5078 }
5079
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5080 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5081 {
5082 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5083 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5084 int i;
5085
5086 for (i = 0; i < tc_info->num_tc; i++) {
5087 int j;
5088
5089 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5090 struct hnae3_queue *q;
5091
5092 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5093 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5094 }
5095 }
5096 }
5097
hns3_init_all_ring(struct hns3_nic_priv * priv)5098 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5099 {
5100 struct hnae3_handle *h = priv->ae_handle;
5101 int ring_num = h->kinfo.num_tqps * 2;
5102 int i, j;
5103 int ret;
5104
5105 for (i = 0; i < ring_num; i++) {
5106 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5107 if (ret) {
5108 dev_err(priv->dev,
5109 "Alloc ring memory fail! ret=%d\n", ret);
5110 goto out_when_alloc_ring_memory;
5111 }
5112
5113 u64_stats_init(&priv->ring[i].syncp);
5114 }
5115
5116 return 0;
5117
5118 out_when_alloc_ring_memory:
5119 for (j = i - 1; j >= 0; j--)
5120 hns3_fini_ring(&priv->ring[j]);
5121
5122 return -ENOMEM;
5123 }
5124
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5125 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5126 {
5127 struct hnae3_handle *h = priv->ae_handle;
5128 int i;
5129
5130 for (i = 0; i < h->kinfo.num_tqps; i++) {
5131 hns3_fini_ring(&priv->ring[i]);
5132 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5133 }
5134 }
5135
5136 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5137 static int hns3_init_mac_addr(struct net_device *netdev)
5138 {
5139 struct hns3_nic_priv *priv = netdev_priv(netdev);
5140 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5141 struct hnae3_handle *h = priv->ae_handle;
5142 u8 mac_addr_temp[ETH_ALEN] = {0};
5143 int ret = 0;
5144
5145 if (h->ae_algo->ops->get_mac_addr)
5146 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5147
5148 /* Check if the MAC address is valid, if not get a random one */
5149 if (!is_valid_ether_addr(mac_addr_temp)) {
5150 eth_hw_addr_random(netdev);
5151 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5152 dev_warn(priv->dev, "using random MAC address %s\n",
5153 format_mac_addr);
5154 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5155 eth_hw_addr_set(netdev, mac_addr_temp);
5156 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5157 } else {
5158 return 0;
5159 }
5160
5161 if (h->ae_algo->ops->set_mac_addr)
5162 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5163
5164 return ret;
5165 }
5166
hns3_init_phy(struct net_device * netdev)5167 static int hns3_init_phy(struct net_device *netdev)
5168 {
5169 struct hnae3_handle *h = hns3_get_handle(netdev);
5170 int ret = 0;
5171
5172 if (h->ae_algo->ops->mac_connect_phy)
5173 ret = h->ae_algo->ops->mac_connect_phy(h);
5174
5175 return ret;
5176 }
5177
hns3_uninit_phy(struct net_device * netdev)5178 static void hns3_uninit_phy(struct net_device *netdev)
5179 {
5180 struct hnae3_handle *h = hns3_get_handle(netdev);
5181
5182 if (h->ae_algo->ops->mac_disconnect_phy)
5183 h->ae_algo->ops->mac_disconnect_phy(h);
5184 }
5185
hns3_client_start(struct hnae3_handle * handle)5186 static int hns3_client_start(struct hnae3_handle *handle)
5187 {
5188 if (!handle->ae_algo->ops->client_start)
5189 return 0;
5190
5191 return handle->ae_algo->ops->client_start(handle);
5192 }
5193
hns3_client_stop(struct hnae3_handle * handle)5194 static void hns3_client_stop(struct hnae3_handle *handle)
5195 {
5196 if (!handle->ae_algo->ops->client_stop)
5197 return;
5198
5199 handle->ae_algo->ops->client_stop(handle);
5200 }
5201
hns3_info_show(struct hns3_nic_priv * priv)5202 static void hns3_info_show(struct hns3_nic_priv *priv)
5203 {
5204 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5205 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5206
5207 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5208 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5209 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5210 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5211 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5212 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5213 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5214 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5215 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5216 kinfo->tc_info.num_tc);
5217 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5218 }
5219
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5220 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5221 enum dim_cq_period_mode mode, bool is_tx)
5222 {
5223 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5224 struct hnae3_handle *handle = priv->ae_handle;
5225 int i;
5226
5227 if (is_tx) {
5228 priv->tx_cqe_mode = mode;
5229
5230 for (i = 0; i < priv->vector_num; i++)
5231 priv->tqp_vector[i].tx_group.dim.mode = mode;
5232 } else {
5233 priv->rx_cqe_mode = mode;
5234
5235 for (i = 0; i < priv->vector_num; i++)
5236 priv->tqp_vector[i].rx_group.dim.mode = mode;
5237 }
5238
5239 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5240 u32 new_mode;
5241 u64 reg;
5242
5243 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5244 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5245 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5246
5247 writel(new_mode, handle->kinfo.io_base + reg);
5248 }
5249 }
5250
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5251 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5252 enum dim_cq_period_mode tx_mode,
5253 enum dim_cq_period_mode rx_mode)
5254 {
5255 hns3_set_cq_period_mode(priv, tx_mode, true);
5256 hns3_set_cq_period_mode(priv, rx_mode, false);
5257 }
5258
hns3_state_init(struct hnae3_handle * handle)5259 static void hns3_state_init(struct hnae3_handle *handle)
5260 {
5261 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5262 struct net_device *netdev = handle->kinfo.netdev;
5263 struct hns3_nic_priv *priv = netdev_priv(netdev);
5264
5265 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5266
5267 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5268 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5269
5270 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5271 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5272
5273 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5274 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5275
5276 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5277 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5278 }
5279
hns3_state_uninit(struct hnae3_handle * handle)5280 static void hns3_state_uninit(struct hnae3_handle *handle)
5281 {
5282 struct hns3_nic_priv *priv = handle->priv;
5283
5284 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5285 }
5286
hns3_client_init(struct hnae3_handle * handle)5287 static int hns3_client_init(struct hnae3_handle *handle)
5288 {
5289 struct pci_dev *pdev = handle->pdev;
5290 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5291 u16 alloc_tqps, max_rss_size;
5292 struct hns3_nic_priv *priv;
5293 struct net_device *netdev;
5294 int ret;
5295
5296 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5297 &max_rss_size);
5298 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5299 if (!netdev)
5300 return -ENOMEM;
5301
5302 priv = netdev_priv(netdev);
5303 priv->dev = &pdev->dev;
5304 priv->netdev = netdev;
5305 priv->ae_handle = handle;
5306 priv->tx_timeout_count = 0;
5307 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5308 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5309
5310 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5311
5312 handle->kinfo.netdev = netdev;
5313 handle->priv = (void *)priv;
5314
5315 hns3_init_mac_addr(netdev);
5316
5317 hns3_set_default_feature(netdev);
5318
5319 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5320 netdev->priv_flags |= IFF_UNICAST_FLT;
5321 netdev->netdev_ops = &hns3_nic_netdev_ops;
5322 SET_NETDEV_DEV(netdev, &pdev->dev);
5323 hns3_ethtool_set_ops(netdev);
5324
5325 /* Carrier off reporting is important to ethtool even BEFORE open */
5326 netif_carrier_off(netdev);
5327
5328 ret = hns3_get_ring_config(priv);
5329 if (ret) {
5330 ret = -ENOMEM;
5331 goto out_get_ring_cfg;
5332 }
5333
5334 hns3_nic_init_coal_cfg(priv);
5335
5336 ret = hns3_nic_alloc_vector_data(priv);
5337 if (ret) {
5338 ret = -ENOMEM;
5339 goto out_alloc_vector_data;
5340 }
5341
5342 ret = hns3_nic_init_vector_data(priv);
5343 if (ret) {
5344 ret = -ENOMEM;
5345 goto out_init_vector_data;
5346 }
5347
5348 ret = hns3_init_all_ring(priv);
5349 if (ret) {
5350 ret = -ENOMEM;
5351 goto out_init_ring;
5352 }
5353
5354 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5355 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5356
5357 ret = hns3_init_phy(netdev);
5358 if (ret)
5359 goto out_init_phy;
5360
5361 /* the device can work without cpu rmap, only aRFS needs it */
5362 ret = hns3_set_rx_cpu_rmap(netdev);
5363 if (ret)
5364 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5365
5366 ret = hns3_nic_init_irq(priv);
5367 if (ret) {
5368 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5369 hns3_free_rx_cpu_rmap(netdev);
5370 goto out_init_irq_fail;
5371 }
5372
5373 ret = hns3_client_start(handle);
5374 if (ret) {
5375 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5376 goto out_client_start;
5377 }
5378
5379 hns3_dcbnl_setup(handle);
5380
5381 ret = hns3_dbg_init(handle);
5382 if (ret) {
5383 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5384 ret);
5385 goto out_client_start;
5386 }
5387
5388 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5389
5390 hns3_state_init(handle);
5391
5392 ret = register_netdev(netdev);
5393 if (ret) {
5394 dev_err(priv->dev, "probe register netdev fail!\n");
5395 goto out_reg_netdev_fail;
5396 }
5397
5398 if (netif_msg_drv(handle))
5399 hns3_info_show(priv);
5400
5401 return ret;
5402
5403 out_reg_netdev_fail:
5404 hns3_state_uninit(handle);
5405 hns3_dbg_uninit(handle);
5406 hns3_client_stop(handle);
5407 out_client_start:
5408 hns3_free_rx_cpu_rmap(netdev);
5409 hns3_nic_uninit_irq(priv);
5410 out_init_irq_fail:
5411 hns3_uninit_phy(netdev);
5412 out_init_phy:
5413 hns3_uninit_all_ring(priv);
5414 out_init_ring:
5415 hns3_nic_uninit_vector_data(priv);
5416 out_init_vector_data:
5417 hns3_nic_dealloc_vector_data(priv);
5418 out_alloc_vector_data:
5419 priv->ring = NULL;
5420 out_get_ring_cfg:
5421 priv->ae_handle = NULL;
5422 free_netdev(netdev);
5423 return ret;
5424 }
5425
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5426 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5427 {
5428 struct net_device *netdev = handle->kinfo.netdev;
5429 struct hns3_nic_priv *priv = netdev_priv(netdev);
5430
5431 if (netdev->reg_state != NETREG_UNINITIALIZED)
5432 unregister_netdev(netdev);
5433
5434 hns3_client_stop(handle);
5435
5436 hns3_uninit_phy(netdev);
5437
5438 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5439 netdev_warn(netdev, "already uninitialized\n");
5440 goto out_netdev_free;
5441 }
5442
5443 hns3_free_rx_cpu_rmap(netdev);
5444
5445 hns3_nic_uninit_irq(priv);
5446
5447 hns3_clear_all_ring(handle, true);
5448
5449 hns3_nic_uninit_vector_data(priv);
5450
5451 hns3_nic_dealloc_vector_data(priv);
5452
5453 hns3_uninit_all_ring(priv);
5454
5455 hns3_put_ring_config(priv);
5456
5457 out_netdev_free:
5458 hns3_dbg_uninit(handle);
5459 free_netdev(netdev);
5460 }
5461
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5462 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5463 {
5464 struct net_device *netdev = handle->kinfo.netdev;
5465
5466 if (!netdev)
5467 return;
5468
5469 if (linkup) {
5470 netif_tx_wake_all_queues(netdev);
5471 netif_carrier_on(netdev);
5472 if (netif_msg_link(handle))
5473 netdev_info(netdev, "link up\n");
5474 } else {
5475 netif_carrier_off(netdev);
5476 netif_tx_stop_all_queues(netdev);
5477 if (netif_msg_link(handle))
5478 netdev_info(netdev, "link down\n");
5479 }
5480 }
5481
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5482 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5483 {
5484 while (ring->next_to_clean != ring->next_to_use) {
5485 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5486 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5487 ring_ptr_move_fw(ring, next_to_clean);
5488 }
5489
5490 ring->pending_buf = 0;
5491 }
5492
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5493 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5494 {
5495 struct hns3_desc_cb res_cbs;
5496 int ret;
5497
5498 while (ring->next_to_use != ring->next_to_clean) {
5499 /* When a buffer is not reused, it's memory has been
5500 * freed in hns3_handle_rx_bd or will be freed by
5501 * stack, so we need to replace the buffer here.
5502 */
5503 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5504 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5505 if (ret) {
5506 hns3_ring_stats_update(ring, sw_err_cnt);
5507 /* if alloc new buffer fail, exit directly
5508 * and reclear in up flow.
5509 */
5510 netdev_warn(ring_to_netdev(ring),
5511 "reserve buffer map failed, ret = %d\n",
5512 ret);
5513 return ret;
5514 }
5515 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5516 }
5517 ring_ptr_move_fw(ring, next_to_use);
5518 }
5519
5520 /* Free the pending skb in rx ring */
5521 if (ring->skb) {
5522 dev_kfree_skb_any(ring->skb);
5523 ring->skb = NULL;
5524 ring->pending_buf = 0;
5525 }
5526
5527 return 0;
5528 }
5529
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5530 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5531 {
5532 while (ring->next_to_use != ring->next_to_clean) {
5533 /* When a buffer is not reused, it's memory has been
5534 * freed in hns3_handle_rx_bd or will be freed by
5535 * stack, so only need to unmap the buffer here.
5536 */
5537 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5538 hns3_unmap_buffer(ring,
5539 &ring->desc_cb[ring->next_to_use]);
5540 ring->desc_cb[ring->next_to_use].dma = 0;
5541 }
5542
5543 ring_ptr_move_fw(ring, next_to_use);
5544 }
5545 }
5546
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5547 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5548 {
5549 struct net_device *ndev = h->kinfo.netdev;
5550 struct hns3_nic_priv *priv = netdev_priv(ndev);
5551 u32 i;
5552
5553 for (i = 0; i < h->kinfo.num_tqps; i++) {
5554 struct hns3_enet_ring *ring;
5555
5556 ring = &priv->ring[i];
5557 hns3_clear_tx_ring(ring);
5558
5559 ring = &priv->ring[i + h->kinfo.num_tqps];
5560 /* Continue to clear other rings even if clearing some
5561 * rings failed.
5562 */
5563 if (force)
5564 hns3_force_clear_rx_ring(ring);
5565 else
5566 hns3_clear_rx_ring(ring);
5567 }
5568 }
5569
hns3_nic_reset_all_ring(struct hnae3_handle * h)5570 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5571 {
5572 struct net_device *ndev = h->kinfo.netdev;
5573 struct hns3_nic_priv *priv = netdev_priv(ndev);
5574 struct hns3_enet_ring *rx_ring;
5575 int i, j;
5576 int ret;
5577
5578 ret = h->ae_algo->ops->reset_queue(h);
5579 if (ret)
5580 return ret;
5581
5582 for (i = 0; i < h->kinfo.num_tqps; i++) {
5583 hns3_init_ring_hw(&priv->ring[i]);
5584
5585 /* We need to clear tx ring here because self test will
5586 * use the ring and will not run down before up
5587 */
5588 hns3_clear_tx_ring(&priv->ring[i]);
5589 priv->ring[i].next_to_clean = 0;
5590 priv->ring[i].next_to_use = 0;
5591 priv->ring[i].last_to_use = 0;
5592
5593 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5594 hns3_init_ring_hw(rx_ring);
5595 ret = hns3_clear_rx_ring(rx_ring);
5596 if (ret)
5597 return ret;
5598
5599 /* We can not know the hardware head and tail when this
5600 * function is called in reset flow, so we reuse all desc.
5601 */
5602 for (j = 0; j < rx_ring->desc_num; j++)
5603 hns3_reuse_buffer(rx_ring, j);
5604
5605 rx_ring->next_to_clean = 0;
5606 rx_ring->next_to_use = 0;
5607 }
5608
5609 hns3_init_tx_ring_tc(priv);
5610
5611 return 0;
5612 }
5613
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5614 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5615 {
5616 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5617 struct net_device *ndev = kinfo->netdev;
5618 struct hns3_nic_priv *priv = netdev_priv(ndev);
5619
5620 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5621 return 0;
5622
5623 if (!netif_running(ndev))
5624 return 0;
5625
5626 return hns3_nic_net_stop(ndev);
5627 }
5628
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5629 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5630 {
5631 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5632 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5633 int ret = 0;
5634
5635 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5636 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5637 return -EFAULT;
5638 }
5639
5640 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5641
5642 if (netif_running(kinfo->netdev)) {
5643 ret = hns3_nic_net_open(kinfo->netdev);
5644 if (ret) {
5645 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5646 netdev_err(kinfo->netdev,
5647 "net up fail, ret=%d!\n", ret);
5648 return ret;
5649 }
5650 }
5651
5652 return ret;
5653 }
5654
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5655 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5656 {
5657 struct net_device *netdev = handle->kinfo.netdev;
5658 struct hns3_nic_priv *priv = netdev_priv(netdev);
5659 int ret;
5660
5661 /* Carrier off reporting is important to ethtool even BEFORE open */
5662 netif_carrier_off(netdev);
5663
5664 ret = hns3_get_ring_config(priv);
5665 if (ret)
5666 return ret;
5667
5668 ret = hns3_nic_alloc_vector_data(priv);
5669 if (ret)
5670 goto err_put_ring;
5671
5672 ret = hns3_nic_init_vector_data(priv);
5673 if (ret)
5674 goto err_dealloc_vector;
5675
5676 ret = hns3_init_all_ring(priv);
5677 if (ret)
5678 goto err_uninit_vector;
5679
5680 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5681
5682 /* the device can work without cpu rmap, only aRFS needs it */
5683 ret = hns3_set_rx_cpu_rmap(netdev);
5684 if (ret)
5685 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5686
5687 ret = hns3_nic_init_irq(priv);
5688 if (ret) {
5689 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5690 hns3_free_rx_cpu_rmap(netdev);
5691 goto err_init_irq_fail;
5692 }
5693
5694 if (!hns3_is_phys_func(handle->pdev))
5695 hns3_init_mac_addr(netdev);
5696
5697 ret = hns3_client_start(handle);
5698 if (ret) {
5699 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5700 goto err_client_start_fail;
5701 }
5702
5703 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5704
5705 return ret;
5706
5707 err_client_start_fail:
5708 hns3_free_rx_cpu_rmap(netdev);
5709 hns3_nic_uninit_irq(priv);
5710 err_init_irq_fail:
5711 hns3_uninit_all_ring(priv);
5712 err_uninit_vector:
5713 hns3_nic_uninit_vector_data(priv);
5714 err_dealloc_vector:
5715 hns3_nic_dealloc_vector_data(priv);
5716 err_put_ring:
5717 hns3_put_ring_config(priv);
5718
5719 return ret;
5720 }
5721
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5722 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5723 {
5724 struct net_device *netdev = handle->kinfo.netdev;
5725 struct hns3_nic_priv *priv = netdev_priv(netdev);
5726
5727 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5728 netdev_warn(netdev, "already uninitialized\n");
5729 return 0;
5730 }
5731
5732 hns3_free_rx_cpu_rmap(netdev);
5733 hns3_nic_uninit_irq(priv);
5734 hns3_clear_all_ring(handle, true);
5735 hns3_reset_tx_queue(priv->ae_handle);
5736
5737 hns3_nic_uninit_vector_data(priv);
5738
5739 hns3_nic_dealloc_vector_data(priv);
5740
5741 hns3_uninit_all_ring(priv);
5742
5743 hns3_put_ring_config(priv);
5744
5745 return 0;
5746 }
5747
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5748 int hns3_reset_notify(struct hnae3_handle *handle,
5749 enum hnae3_reset_notify_type type)
5750 {
5751 int ret = 0;
5752
5753 switch (type) {
5754 case HNAE3_UP_CLIENT:
5755 ret = hns3_reset_notify_up_enet(handle);
5756 break;
5757 case HNAE3_DOWN_CLIENT:
5758 ret = hns3_reset_notify_down_enet(handle);
5759 break;
5760 case HNAE3_INIT_CLIENT:
5761 ret = hns3_reset_notify_init_enet(handle);
5762 break;
5763 case HNAE3_UNINIT_CLIENT:
5764 ret = hns3_reset_notify_uninit_enet(handle);
5765 break;
5766 default:
5767 break;
5768 }
5769
5770 return ret;
5771 }
5772
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5773 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5774 bool rxfh_configured)
5775 {
5776 int ret;
5777
5778 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5779 rxfh_configured);
5780 if (ret) {
5781 dev_err(&handle->pdev->dev,
5782 "Change tqp num(%u) fail.\n", new_tqp_num);
5783 return ret;
5784 }
5785
5786 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5787 if (ret)
5788 return ret;
5789
5790 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5791 if (ret)
5792 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5793
5794 return ret;
5795 }
5796
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5797 int hns3_set_channels(struct net_device *netdev,
5798 struct ethtool_channels *ch)
5799 {
5800 struct hnae3_handle *h = hns3_get_handle(netdev);
5801 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5802 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5803 u32 new_tqp_num = ch->combined_count;
5804 u16 org_tqp_num;
5805 int ret;
5806
5807 if (hns3_nic_resetting(netdev))
5808 return -EBUSY;
5809
5810 if (ch->rx_count || ch->tx_count)
5811 return -EINVAL;
5812
5813 if (kinfo->tc_info.mqprio_active) {
5814 dev_err(&netdev->dev,
5815 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5816 return -EINVAL;
5817 }
5818
5819 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5820 new_tqp_num < 1) {
5821 dev_err(&netdev->dev,
5822 "Change tqps fail, the tqp range is from 1 to %u",
5823 hns3_get_max_available_channels(h));
5824 return -EINVAL;
5825 }
5826
5827 if (kinfo->rss_size == new_tqp_num)
5828 return 0;
5829
5830 netif_dbg(h, drv, netdev,
5831 "set channels: tqp_num=%u, rxfh=%d\n",
5832 new_tqp_num, rxfh_configured);
5833
5834 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5835 if (ret)
5836 return ret;
5837
5838 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5839 if (ret)
5840 return ret;
5841
5842 org_tqp_num = h->kinfo.num_tqps;
5843 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5844 if (ret) {
5845 int ret1;
5846
5847 netdev_warn(netdev,
5848 "Change channels fail, revert to old value\n");
5849 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5850 if (ret1) {
5851 netdev_err(netdev,
5852 "revert to old channel fail\n");
5853 return ret1;
5854 }
5855
5856 return ret;
5857 }
5858
5859 return 0;
5860 }
5861
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5862 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5863 {
5864 struct hns3_nic_priv *priv = netdev_priv(ndev);
5865 struct hnae3_handle *h = priv->ae_handle;
5866 int i;
5867
5868 if (!if_running)
5869 return;
5870
5871 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5872 return;
5873
5874 netif_carrier_off(ndev);
5875 netif_tx_disable(ndev);
5876
5877 for (i = 0; i < priv->vector_num; i++)
5878 hns3_vector_disable(&priv->tqp_vector[i]);
5879
5880 for (i = 0; i < h->kinfo.num_tqps; i++)
5881 hns3_tqp_disable(h->kinfo.tqp[i]);
5882
5883 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5884 * during reset process, because driver may not be able
5885 * to disable the ring through firmware when downing the netdev.
5886 */
5887 if (!hns3_nic_resetting(ndev))
5888 hns3_nic_reset_all_ring(priv->ae_handle);
5889
5890 hns3_reset_tx_queue(priv->ae_handle);
5891 }
5892
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5893 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5894 {
5895 struct hns3_nic_priv *priv = netdev_priv(ndev);
5896 struct hnae3_handle *h = priv->ae_handle;
5897 int i;
5898
5899 if (!if_running)
5900 return;
5901
5902 if (hns3_nic_resetting(ndev))
5903 return;
5904
5905 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5906 return;
5907
5908 if (hns3_nic_reset_all_ring(priv->ae_handle))
5909 return;
5910
5911 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5912
5913 for (i = 0; i < priv->vector_num; i++)
5914 hns3_vector_enable(&priv->tqp_vector[i]);
5915
5916 for (i = 0; i < h->kinfo.num_tqps; i++)
5917 hns3_tqp_enable(h->kinfo.tqp[i]);
5918
5919 netif_tx_wake_all_queues(ndev);
5920
5921 if (h->ae_algo->ops->get_status(h))
5922 netif_carrier_on(ndev);
5923 }
5924
5925 static const struct hns3_hw_error_info hns3_hw_err[] = {
5926 { .type = HNAE3_PPU_POISON_ERROR,
5927 .msg = "PPU poison" },
5928 { .type = HNAE3_CMDQ_ECC_ERROR,
5929 .msg = "IMP CMDQ error" },
5930 { .type = HNAE3_IMP_RD_POISON_ERROR,
5931 .msg = "IMP RD poison" },
5932 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5933 .msg = "ROCEE AXI RESP error" },
5934 };
5935
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5936 static void hns3_process_hw_error(struct hnae3_handle *handle,
5937 enum hnae3_hw_error_type type)
5938 {
5939 int i;
5940
5941 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5942 if (hns3_hw_err[i].type == type) {
5943 dev_err(&handle->pdev->dev, "Detected %s!\n",
5944 hns3_hw_err[i].msg);
5945 break;
5946 }
5947 }
5948 }
5949
5950 static const struct hnae3_client_ops client_ops = {
5951 .init_instance = hns3_client_init,
5952 .uninit_instance = hns3_client_uninit,
5953 .link_status_change = hns3_link_status_change,
5954 .reset_notify = hns3_reset_notify,
5955 .process_hw_error = hns3_process_hw_error,
5956 };
5957
5958 /* hns3_init_module - Driver registration routine
5959 * hns3_init_module is the first routine called when the driver is
5960 * loaded. All it does is register with the PCI subsystem.
5961 */
hns3_init_module(void)5962 static int __init hns3_init_module(void)
5963 {
5964 int ret;
5965
5966 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5967 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5968
5969 client.type = HNAE3_CLIENT_KNIC;
5970 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5971 hns3_driver_name);
5972
5973 client.ops = &client_ops;
5974
5975 INIT_LIST_HEAD(&client.node);
5976
5977 hns3_dbg_register_debugfs(hns3_driver_name);
5978
5979 ret = hnae3_register_client(&client);
5980 if (ret)
5981 goto err_reg_client;
5982
5983 ret = pci_register_driver(&hns3_driver);
5984 if (ret)
5985 goto err_reg_driver;
5986
5987 return ret;
5988
5989 err_reg_driver:
5990 hnae3_unregister_client(&client);
5991 err_reg_client:
5992 hns3_dbg_unregister_debugfs();
5993 return ret;
5994 }
5995 module_init(hns3_init_module);
5996
5997 /* hns3_exit_module - Driver exit cleanup routine
5998 * hns3_exit_module is called just before the driver is removed
5999 * from memory.
6000 */
hns3_exit_module(void)6001 static void __exit hns3_exit_module(void)
6002 {
6003 pci_unregister_driver(&hns3_driver);
6004 hnae3_unregister_client(&client);
6005 hns3_dbg_unregister_debugfs();
6006 }
6007 module_exit(hns3_exit_module);
6008
6009 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6010 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6011 MODULE_LICENSE("GPL");
6012 MODULE_ALIAS("pci:hns-nic");
6013