1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7 #ifndef AMD_IOMMU_H
8 #define AMD_IOMMU_H
9
10 #include <linux/iommu.h>
11
12 #include "amd_iommu_types.h"
13
14 extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
15 extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
16 extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
17 extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
18 extern void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
19 extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
20
21 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
22 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
23 #else
amd_iommu_debugfs_setup(struct amd_iommu * iommu)24 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
25 #endif
26
27 /* Needed for interrupt remapping */
28 extern int amd_iommu_prepare(void);
29 extern int amd_iommu_enable(void);
30 extern void amd_iommu_disable(void);
31 extern int amd_iommu_reenable(int);
32 extern int amd_iommu_enable_faulting(void);
33 extern int amd_iommu_guest_ir;
34 extern enum io_pgtable_fmt amd_iommu_pgtable;
35
36 /* IOMMUv2 specific functions */
37 struct iommu_domain;
38
39 extern bool amd_iommu_v2_supported(void);
40 extern struct amd_iommu *get_amd_iommu(unsigned int idx);
41 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
42 extern bool amd_iommu_pc_supported(void);
43 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
44 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
45 u8 fxn, u64 *value);
46 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
47 u8 fxn, u64 *value);
48
49 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
50 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
51 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
52 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
53 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
54 u64 address);
55 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
56 extern void amd_iommu_domain_update(struct protection_domain *domain);
57 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
58 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
59 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
60 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
61 unsigned long cr3);
62 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
63
64 #ifdef CONFIG_IRQ_REMAP
65 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
66 #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)67 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
68 {
69 return 0;
70 }
71 #endif
72
73 #define PPR_SUCCESS 0x0
74 #define PPR_INVALID 0x1
75 #define PPR_FAILURE 0xf
76
77 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
78 int status, int tag);
79
is_rd890_iommu(struct pci_dev * pdev)80 static inline bool is_rd890_iommu(struct pci_dev *pdev)
81 {
82 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
83 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
84 }
85
iommu_feature(struct amd_iommu * iommu,u64 mask)86 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
87 {
88 return !!(iommu->features & mask);
89 }
90
iommu_virt_to_phys(void * vaddr)91 static inline u64 iommu_virt_to_phys(void *vaddr)
92 {
93 return (u64)__sme_set(virt_to_phys(vaddr));
94 }
95
iommu_phys_to_virt(unsigned long paddr)96 static inline void *iommu_phys_to_virt(unsigned long paddr)
97 {
98 return phys_to_virt(__sme_clr(paddr));
99 }
100
101 static inline
amd_iommu_domain_set_pt_root(struct protection_domain * domain,u64 root)102 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
103 {
104 atomic64_set(&domain->iop.pt_root, root);
105 domain->iop.root = (u64 *)(root & PAGE_MASK);
106 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
107 }
108
109 static inline
amd_iommu_domain_clr_pt_root(struct protection_domain * domain)110 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
111 {
112 amd_iommu_domain_set_pt_root(domain, 0);
113 }
114
get_pci_sbdf_id(struct pci_dev * pdev)115 static inline int get_pci_sbdf_id(struct pci_dev *pdev)
116 {
117 int seg = pci_domain_nr(pdev->bus);
118 u16 devid = pci_dev_id(pdev);
119
120 return PCI_SEG_DEVID_TO_SBDF(seg, devid);
121 }
122
123 extern bool translation_pre_enabled(struct amd_iommu *iommu);
124 extern bool amd_iommu_is_attach_deferred(struct device *dev);
125 extern int __init add_special_device(u8 type, u8 id, u32 *devid,
126 bool cmd_line);
127
128 #ifdef CONFIG_DMI
129 void amd_iommu_apply_ivrs_quirks(void);
130 #else
amd_iommu_apply_ivrs_quirks(void)131 static inline void amd_iommu_apply_ivrs_quirks(void) { }
132 #endif
133
134 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
135 u64 *root, int mode);
136 extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
137
138 extern u64 amd_iommu_efr;
139 extern u64 amd_iommu_efr2;
140
141 extern bool amd_iommu_snp_en;
142 #endif
143