1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #ifndef IRDMA_TYPE_H
4 #define IRDMA_TYPE_H
5 #include "osdep.h"
6 #include "irdma.h"
7 #include "user.h"
8 #include "hmc.h"
9 #include "uda.h"
10 #include "ws.h"
11 #define IRDMA_DEBUG_ERR "ERR"
12 #define IRDMA_DEBUG_INIT "INIT"
13 #define IRDMA_DEBUG_DEV "DEV"
14 #define IRDMA_DEBUG_CM "CM"
15 #define IRDMA_DEBUG_VERBS "VERBS"
16 #define IRDMA_DEBUG_PUDA "PUDA"
17 #define IRDMA_DEBUG_ILQ "ILQ"
18 #define IRDMA_DEBUG_IEQ "IEQ"
19 #define IRDMA_DEBUG_QP "QP"
20 #define IRDMA_DEBUG_CQ "CQ"
21 #define IRDMA_DEBUG_MR "MR"
22 #define IRDMA_DEBUG_PBLE "PBLE"
23 #define IRDMA_DEBUG_WQE "WQE"
24 #define IRDMA_DEBUG_AEQ "AEQ"
25 #define IRDMA_DEBUG_CQP "CQP"
26 #define IRDMA_DEBUG_HMC "HMC"
27 #define IRDMA_DEBUG_USER "USER"
28 #define IRDMA_DEBUG_VIRT "VIRT"
29 #define IRDMA_DEBUG_DCB "DCB"
30 #define IRDMA_DEBUG_CQE "CQE"
31 #define IRDMA_DEBUG_CLNT "CLNT"
32 #define IRDMA_DEBUG_WS "WS"
33 #define IRDMA_DEBUG_STATS "STATS"
34
35 enum irdma_page_size {
36 IRDMA_PAGE_SIZE_4K = 0,
37 IRDMA_PAGE_SIZE_2M,
38 IRDMA_PAGE_SIZE_1G,
39 };
40
41 enum irdma_hdrct_flags {
42 DDP_LEN_FLAG = 0x80,
43 DDP_HDR_FLAG = 0x40,
44 RDMA_HDR_FLAG = 0x20,
45 };
46
47 enum irdma_term_layers {
48 LAYER_RDMA = 0,
49 LAYER_DDP = 1,
50 LAYER_MPA = 2,
51 };
52
53 enum irdma_term_error_types {
54 RDMAP_REMOTE_PROT = 1,
55 RDMAP_REMOTE_OP = 2,
56 DDP_CATASTROPHIC = 0,
57 DDP_TAGGED_BUF = 1,
58 DDP_UNTAGGED_BUF = 2,
59 DDP_LLP = 3,
60 };
61
62 enum irdma_term_rdma_errors {
63 RDMAP_INV_STAG = 0x00,
64 RDMAP_INV_BOUNDS = 0x01,
65 RDMAP_ACCESS = 0x02,
66 RDMAP_UNASSOC_STAG = 0x03,
67 RDMAP_TO_WRAP = 0x04,
68 RDMAP_INV_RDMAP_VER = 0x05,
69 RDMAP_UNEXPECTED_OP = 0x06,
70 RDMAP_CATASTROPHIC_LOCAL = 0x07,
71 RDMAP_CATASTROPHIC_GLOBAL = 0x08,
72 RDMAP_CANT_INV_STAG = 0x09,
73 RDMAP_UNSPECIFIED = 0xff,
74 };
75
76 enum irdma_term_ddp_errors {
77 DDP_CATASTROPHIC_LOCAL = 0x00,
78 DDP_TAGGED_INV_STAG = 0x00,
79 DDP_TAGGED_BOUNDS = 0x01,
80 DDP_TAGGED_UNASSOC_STAG = 0x02,
81 DDP_TAGGED_TO_WRAP = 0x03,
82 DDP_TAGGED_INV_DDP_VER = 0x04,
83 DDP_UNTAGGED_INV_QN = 0x01,
84 DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
85 DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
86 DDP_UNTAGGED_INV_MO = 0x04,
87 DDP_UNTAGGED_INV_TOO_LONG = 0x05,
88 DDP_UNTAGGED_INV_DDP_VER = 0x06,
89 };
90
91 enum irdma_term_mpa_errors {
92 MPA_CLOSED = 0x01,
93 MPA_CRC = 0x02,
94 MPA_MARKER = 0x03,
95 MPA_REQ_RSP = 0x04,
96 };
97
98 enum irdma_qp_event_type {
99 IRDMA_QP_EVENT_CATASTROPHIC,
100 IRDMA_QP_EVENT_ACCESS_ERR,
101 IRDMA_QP_EVENT_REQ_ERR,
102 };
103
104 enum irdma_hw_stats_index_32b {
105 IRDMA_HW_STAT_INDEX_IP4RXDISCARD = 0,
106 IRDMA_HW_STAT_INDEX_IP4RXTRUNC = 1,
107 IRDMA_HW_STAT_INDEX_IP4TXNOROUTE = 2,
108 IRDMA_HW_STAT_INDEX_IP6RXDISCARD = 3,
109 IRDMA_HW_STAT_INDEX_IP6RXTRUNC = 4,
110 IRDMA_HW_STAT_INDEX_IP6TXNOROUTE = 5,
111 IRDMA_HW_STAT_INDEX_TCPRTXSEG = 6,
112 IRDMA_HW_STAT_INDEX_TCPRXOPTERR = 7,
113 IRDMA_HW_STAT_INDEX_TCPRXPROTOERR = 8,
114 IRDMA_HW_STAT_INDEX_MAX_32_GEN_1 = 9, /* Must be same value as next entry */
115 IRDMA_HW_STAT_INDEX_RXVLANERR = 9,
116 IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED = 10,
117 IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED = 11,
118 IRDMA_HW_STAT_INDEX_TXNPCNPSENT = 12,
119 IRDMA_HW_STAT_INDEX_MAX_32, /* Must be last entry */
120 };
121
122 enum irdma_hw_stats_index_64b {
123 IRDMA_HW_STAT_INDEX_IP4RXOCTS = 0,
124 IRDMA_HW_STAT_INDEX_IP4RXPKTS = 1,
125 IRDMA_HW_STAT_INDEX_IP4RXFRAGS = 2,
126 IRDMA_HW_STAT_INDEX_IP4RXMCPKTS = 3,
127 IRDMA_HW_STAT_INDEX_IP4TXOCTS = 4,
128 IRDMA_HW_STAT_INDEX_IP4TXPKTS = 5,
129 IRDMA_HW_STAT_INDEX_IP4TXFRAGS = 6,
130 IRDMA_HW_STAT_INDEX_IP4TXMCPKTS = 7,
131 IRDMA_HW_STAT_INDEX_IP6RXOCTS = 8,
132 IRDMA_HW_STAT_INDEX_IP6RXPKTS = 9,
133 IRDMA_HW_STAT_INDEX_IP6RXFRAGS = 10,
134 IRDMA_HW_STAT_INDEX_IP6RXMCPKTS = 11,
135 IRDMA_HW_STAT_INDEX_IP6TXOCTS = 12,
136 IRDMA_HW_STAT_INDEX_IP6TXPKTS = 13,
137 IRDMA_HW_STAT_INDEX_IP6TXFRAGS = 14,
138 IRDMA_HW_STAT_INDEX_IP6TXMCPKTS = 15,
139 IRDMA_HW_STAT_INDEX_TCPRXSEGS = 16,
140 IRDMA_HW_STAT_INDEX_TCPTXSEG = 17,
141 IRDMA_HW_STAT_INDEX_RDMARXRDS = 18,
142 IRDMA_HW_STAT_INDEX_RDMARXSNDS = 19,
143 IRDMA_HW_STAT_INDEX_RDMARXWRS = 20,
144 IRDMA_HW_STAT_INDEX_RDMATXRDS = 21,
145 IRDMA_HW_STAT_INDEX_RDMATXSNDS = 22,
146 IRDMA_HW_STAT_INDEX_RDMATXWRS = 23,
147 IRDMA_HW_STAT_INDEX_RDMAVBND = 24,
148 IRDMA_HW_STAT_INDEX_RDMAVINV = 25,
149 IRDMA_HW_STAT_INDEX_MAX_64_GEN_1 = 26, /* Must be same value as next entry */
150 IRDMA_HW_STAT_INDEX_IP4RXMCOCTS = 26,
151 IRDMA_HW_STAT_INDEX_IP4TXMCOCTS = 27,
152 IRDMA_HW_STAT_INDEX_IP6RXMCOCTS = 28,
153 IRDMA_HW_STAT_INDEX_IP6TXMCOCTS = 29,
154 IRDMA_HW_STAT_INDEX_UDPRXPKTS = 30,
155 IRDMA_HW_STAT_INDEX_UDPTXPKTS = 31,
156 IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS = 32,
157 IRDMA_HW_STAT_INDEX_MAX_64, /* Must be last entry */
158 };
159
160 enum irdma_feature_type {
161 IRDMA_FEATURE_FW_INFO = 0,
162 IRDMA_HW_VERSION_INFO = 1,
163 IRDMA_QSETS_MAX = 26,
164 IRDMA_MAX_FEATURES, /* Must be last entry */
165 };
166
167 enum irdma_sched_prio_type {
168 IRDMA_PRIO_WEIGHTED_RR = 1,
169 IRDMA_PRIO_STRICT = 2,
170 IRDMA_PRIO_WEIGHTED_STRICT = 3,
171 };
172
173 enum irdma_vm_vf_type {
174 IRDMA_VF_TYPE = 0,
175 IRDMA_VM_TYPE,
176 IRDMA_PF_TYPE,
177 };
178
179 enum irdma_cqp_hmc_profile {
180 IRDMA_HMC_PROFILE_DEFAULT = 1,
181 IRDMA_HMC_PROFILE_FAVOR_VF = 2,
182 IRDMA_HMC_PROFILE_EQUAL = 3,
183 };
184
185 enum irdma_quad_entry_type {
186 IRDMA_QHASH_TYPE_TCP_ESTABLISHED = 1,
187 IRDMA_QHASH_TYPE_TCP_SYN,
188 IRDMA_QHASH_TYPE_UDP_UNICAST,
189 IRDMA_QHASH_TYPE_UDP_MCAST,
190 IRDMA_QHASH_TYPE_ROCE_MCAST,
191 IRDMA_QHASH_TYPE_ROCEV2_HW,
192 };
193
194 enum irdma_quad_hash_manage_type {
195 IRDMA_QHASH_MANAGE_TYPE_DELETE = 0,
196 IRDMA_QHASH_MANAGE_TYPE_ADD,
197 IRDMA_QHASH_MANAGE_TYPE_MODIFY,
198 };
199
200 enum irdma_syn_rst_handling {
201 IRDMA_SYN_RST_HANDLING_HW_TCP_SECURE = 0,
202 IRDMA_SYN_RST_HANDLING_HW_TCP,
203 IRDMA_SYN_RST_HANDLING_FW_TCP_SECURE,
204 IRDMA_SYN_RST_HANDLING_FW_TCP,
205 };
206
207 enum irdma_queue_type {
208 IRDMA_QUEUE_TYPE_SQ_RQ = 0,
209 IRDMA_QUEUE_TYPE_CQP,
210 };
211
212 struct irdma_sc_dev;
213 struct irdma_vsi_pestat;
214
215 struct irdma_dcqcn_cc_params {
216 u8 cc_cfg_valid;
217 u8 min_dec_factor;
218 u8 min_rate;
219 u8 dcqcn_f;
220 u16 rai_factor;
221 u16 hai_factor;
222 u16 dcqcn_t;
223 u32 dcqcn_b;
224 u32 rreduce_mperiod;
225 };
226
227 struct irdma_cqp_init_info {
228 u64 cqp_compl_ctx;
229 u64 host_ctx_pa;
230 u64 sq_pa;
231 struct irdma_sc_dev *dev;
232 struct irdma_cqp_quanta *sq;
233 struct irdma_dcqcn_cc_params dcqcn_params;
234 __le64 *host_ctx;
235 u64 *scratch_array;
236 u32 sq_size;
237 u16 hw_maj_ver;
238 u16 hw_min_ver;
239 u8 struct_ver;
240 u8 hmc_profile;
241 u8 ena_vf_count;
242 u8 ceqs_per_vf;
243 bool en_datacenter_tcp:1;
244 bool disable_packed:1;
245 bool rocev2_rto_policy:1;
246 enum irdma_protocol_used protocol_used;
247 };
248
249 struct irdma_terminate_hdr {
250 u8 layer_etype;
251 u8 error_code;
252 u8 hdrct;
253 u8 rsvd;
254 };
255
256 struct irdma_cqp_sq_wqe {
257 __le64 buf[IRDMA_CQP_WQE_SIZE];
258 };
259
260 struct irdma_sc_aeqe {
261 __le64 buf[IRDMA_AEQE_SIZE];
262 };
263
264 struct irdma_ceqe {
265 __le64 buf[IRDMA_CEQE_SIZE];
266 };
267
268 struct irdma_cqp_ctx {
269 __le64 buf[IRDMA_CQP_CTX_SIZE];
270 };
271
272 struct irdma_cq_shadow_area {
273 __le64 buf[IRDMA_SHADOW_AREA_SIZE];
274 };
275
276 struct irdma_dev_hw_stats_offsets {
277 u32 stats_offset_32[IRDMA_HW_STAT_INDEX_MAX_32];
278 u32 stats_offset_64[IRDMA_HW_STAT_INDEX_MAX_64];
279 };
280
281 struct irdma_dev_hw_stats {
282 u64 stats_val_32[IRDMA_HW_STAT_INDEX_MAX_32];
283 u64 stats_val_64[IRDMA_HW_STAT_INDEX_MAX_64];
284 };
285
286 struct irdma_gather_stats {
287 u32 rsvd1;
288 u32 rxvlanerr;
289 u64 ip4rxocts;
290 u64 ip4rxpkts;
291 u32 ip4rxtrunc;
292 u32 ip4rxdiscard;
293 u64 ip4rxfrags;
294 u64 ip4rxmcocts;
295 u64 ip4rxmcpkts;
296 u64 ip6rxocts;
297 u64 ip6rxpkts;
298 u32 ip6rxtrunc;
299 u32 ip6rxdiscard;
300 u64 ip6rxfrags;
301 u64 ip6rxmcocts;
302 u64 ip6rxmcpkts;
303 u64 ip4txocts;
304 u64 ip4txpkts;
305 u64 ip4txfrag;
306 u64 ip4txmcocts;
307 u64 ip4txmcpkts;
308 u64 ip6txocts;
309 u64 ip6txpkts;
310 u64 ip6txfrags;
311 u64 ip6txmcocts;
312 u64 ip6txmcpkts;
313 u32 ip6txnoroute;
314 u32 ip4txnoroute;
315 u64 tcprxsegs;
316 u32 tcprxprotoerr;
317 u32 tcprxopterr;
318 u64 tcptxsegs;
319 u32 rsvd2;
320 u32 tcprtxseg;
321 u64 udprxpkts;
322 u64 udptxpkts;
323 u64 rdmarxwrs;
324 u64 rdmarxrds;
325 u64 rdmarxsnds;
326 u64 rdmatxwrs;
327 u64 rdmatxrds;
328 u64 rdmatxsnds;
329 u64 rdmavbn;
330 u64 rdmavinv;
331 u64 rxnpecnmrkpkts;
332 u32 rxrpcnphandled;
333 u32 rxrpcnpignored;
334 u32 txnpcnpsent;
335 u32 rsvd3[88];
336 };
337
338 struct irdma_stats_gather_info {
339 bool use_hmc_fcn_index:1;
340 bool use_stats_inst:1;
341 u8 hmc_fcn_index;
342 u8 stats_inst_index;
343 struct irdma_dma_mem stats_buff_mem;
344 void *gather_stats_va;
345 void *last_gather_stats_va;
346 };
347
348 struct irdma_vsi_pestat {
349 struct irdma_hw *hw;
350 struct irdma_dev_hw_stats hw_stats;
351 struct irdma_stats_gather_info gather_info;
352 struct timer_list stats_timer;
353 struct irdma_sc_vsi *vsi;
354 struct irdma_dev_hw_stats last_hw_stats;
355 spinlock_t lock; /* rdma stats lock */
356 };
357
358 struct irdma_hw {
359 u8 __iomem *hw_addr;
360 u8 __iomem *priv_hw_addr;
361 struct device *device;
362 struct irdma_hmc_info hmc;
363 };
364
365 struct irdma_pfpdu {
366 struct list_head rxlist;
367 u32 rcv_nxt;
368 u32 fps;
369 u32 max_fpdu_data;
370 u32 nextseqnum;
371 u32 rcv_start_seq;
372 bool mode:1;
373 bool mpa_crc_err:1;
374 u8 marker_len;
375 u64 total_ieq_bufs;
376 u64 fpdu_processed;
377 u64 bad_seq_num;
378 u64 crc_err;
379 u64 no_tx_bufs;
380 u64 tx_err;
381 u64 out_of_order;
382 u64 pmode_count;
383 struct irdma_sc_ah *ah;
384 struct irdma_puda_buf *ah_buf;
385 spinlock_t lock; /* fpdu processing lock */
386 struct irdma_puda_buf *lastrcv_buf;
387 };
388
389 struct irdma_sc_pd {
390 struct irdma_sc_dev *dev;
391 u32 pd_id;
392 int abi_ver;
393 };
394
395 struct irdma_cqp_quanta {
396 __le64 elem[IRDMA_CQP_WQE_SIZE];
397 };
398
399 struct irdma_sc_cqp {
400 u32 size;
401 u64 sq_pa;
402 u64 host_ctx_pa;
403 void *back_cqp;
404 struct irdma_sc_dev *dev;
405 int (*process_cqp_sds)(struct irdma_sc_dev *dev,
406 struct irdma_update_sds_info *info);
407 struct irdma_dma_mem sdbuf;
408 struct irdma_ring sq_ring;
409 struct irdma_cqp_quanta *sq_base;
410 struct irdma_dcqcn_cc_params dcqcn_params;
411 __le64 *host_ctx;
412 u64 *scratch_array;
413 u64 requested_ops;
414 atomic64_t completed_ops;
415 u32 cqp_id;
416 u32 sq_size;
417 u32 hw_sq_size;
418 u16 hw_maj_ver;
419 u16 hw_min_ver;
420 u8 struct_ver;
421 u8 polarity;
422 u8 hmc_profile;
423 u8 ena_vf_count;
424 u8 timeout_count;
425 u8 ceqs_per_vf;
426 bool en_datacenter_tcp:1;
427 bool disable_packed:1;
428 bool rocev2_rto_policy:1;
429 enum irdma_protocol_used protocol_used;
430 };
431
432 struct irdma_sc_aeq {
433 u32 size;
434 u64 aeq_elem_pa;
435 struct irdma_sc_dev *dev;
436 struct irdma_sc_aeqe *aeqe_base;
437 void *pbl_list;
438 u32 elem_cnt;
439 struct irdma_ring aeq_ring;
440 u8 pbl_chunk_size;
441 u32 first_pm_pbl_idx;
442 u32 msix_idx;
443 u8 polarity;
444 bool virtual_map:1;
445 };
446
447 struct irdma_sc_ceq {
448 u32 size;
449 u64 ceq_elem_pa;
450 struct irdma_sc_dev *dev;
451 struct irdma_ceqe *ceqe_base;
452 void *pbl_list;
453 u32 ceq_id;
454 u32 elem_cnt;
455 struct irdma_ring ceq_ring;
456 u8 pbl_chunk_size;
457 u8 tph_val;
458 u32 first_pm_pbl_idx;
459 u8 polarity;
460 struct irdma_sc_vsi *vsi;
461 struct irdma_sc_cq **reg_cq;
462 u32 reg_cq_size;
463 spinlock_t req_cq_lock; /* protect access to reg_cq array */
464 bool virtual_map:1;
465 bool tph_en:1;
466 bool itr_no_expire:1;
467 };
468
469 struct irdma_sc_cq {
470 struct irdma_cq_uk cq_uk;
471 u64 cq_pa;
472 u64 shadow_area_pa;
473 struct irdma_sc_dev *dev;
474 struct irdma_sc_vsi *vsi;
475 void *pbl_list;
476 void *back_cq;
477 u32 ceq_id;
478 u32 shadow_read_threshold;
479 u8 pbl_chunk_size;
480 u8 cq_type;
481 u8 tph_val;
482 u32 first_pm_pbl_idx;
483 bool ceqe_mask:1;
484 bool virtual_map:1;
485 bool check_overflow:1;
486 bool ceq_id_valid:1;
487 bool tph_en;
488 };
489
490 struct irdma_sc_qp {
491 struct irdma_qp_uk qp_uk;
492 u64 sq_pa;
493 u64 rq_pa;
494 u64 hw_host_ctx_pa;
495 u64 shadow_area_pa;
496 u64 q2_pa;
497 struct irdma_sc_dev *dev;
498 struct irdma_sc_vsi *vsi;
499 struct irdma_sc_pd *pd;
500 __le64 *hw_host_ctx;
501 void *llp_stream_handle;
502 struct irdma_pfpdu pfpdu;
503 u32 ieq_qp;
504 u8 *q2_buf;
505 u64 qp_compl_ctx;
506 u32 push_idx;
507 u16 qs_handle;
508 u16 push_offset;
509 u8 flush_wqes_count;
510 u8 sq_tph_val;
511 u8 rq_tph_val;
512 u8 qp_state;
513 u8 hw_sq_size;
514 u8 hw_rq_size;
515 u8 src_mac_addr_idx;
516 bool on_qoslist:1;
517 bool ieq_pass_thru:1;
518 bool sq_tph_en:1;
519 bool rq_tph_en:1;
520 bool rcv_tph_en:1;
521 bool xmit_tph_en:1;
522 bool virtual_map:1;
523 bool flush_sq:1;
524 bool flush_rq:1;
525 bool sq_flush_code:1;
526 bool rq_flush_code:1;
527 enum irdma_flush_opcode flush_code;
528 enum irdma_qp_event_type event_type;
529 u8 term_flags;
530 u8 user_pri;
531 struct list_head list;
532 };
533
534 struct irdma_stats_inst_info {
535 bool use_hmc_fcn_index;
536 u8 hmc_fn_id;
537 u8 stats_idx;
538 };
539
540 struct irdma_up_info {
541 u8 map[8];
542 u8 cnp_up_override;
543 u8 hmc_fcn_idx;
544 bool use_vlan:1;
545 bool use_cnp_up_override:1;
546 };
547
548 #define IRDMA_MAX_WS_NODES 0x3FF
549 #define IRDMA_WS_NODE_INVALID 0xFFFF
550
551 struct irdma_ws_node_info {
552 u16 id;
553 u16 vsi;
554 u16 parent_id;
555 u16 qs_handle;
556 bool type_leaf:1;
557 bool enable:1;
558 u8 prio_type;
559 u8 tc;
560 u8 weight;
561 };
562
563 struct irdma_hmc_fpm_misc {
564 u32 max_ceqs;
565 u32 max_sds;
566 u32 xf_block_size;
567 u32 q1_block_size;
568 u32 ht_multiplier;
569 u32 timer_bucket;
570 u32 rrf_block_size;
571 u32 ooiscf_block_size;
572 };
573
574 #define IRDMA_LEAF_DEFAULT_REL_BW 64
575 #define IRDMA_PARENT_DEFAULT_REL_BW 1
576
577 struct irdma_qos {
578 struct list_head qplist;
579 struct mutex qos_mutex; /* protect QoS attributes per QoS level */
580 u64 lan_qos_handle;
581 u32 l2_sched_node_id;
582 u16 qs_handle;
583 u8 traffic_class;
584 u8 rel_bw;
585 u8 prio_type;
586 bool valid;
587 };
588
589 #define IRDMA_INVALID_FCN_ID 0xff
590 struct irdma_sc_vsi {
591 u16 vsi_idx;
592 struct irdma_sc_dev *dev;
593 void *back_vsi;
594 u32 ilq_count;
595 struct irdma_virt_mem ilq_mem;
596 struct irdma_puda_rsrc *ilq;
597 u32 ieq_count;
598 struct irdma_virt_mem ieq_mem;
599 struct irdma_puda_rsrc *ieq;
600 u32 exception_lan_q;
601 u16 mtu;
602 u16 vm_id;
603 u8 fcn_id;
604 enum irdma_vm_vf_type vm_vf_type;
605 bool stats_fcn_id_alloc:1;
606 bool tc_change_pending:1;
607 struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY];
608 struct irdma_vsi_pestat *pestat;
609 atomic_t qp_suspend_reqs;
610 int (*register_qset)(struct irdma_sc_vsi *vsi,
611 struct irdma_ws_node *tc_node);
612 void (*unregister_qset)(struct irdma_sc_vsi *vsi,
613 struct irdma_ws_node *tc_node);
614 u8 qos_rel_bw;
615 u8 qos_prio_type;
616 u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
617 bool dscp_mode:1;
618 };
619
620 struct irdma_sc_dev {
621 struct list_head cqp_cmd_head; /* head of the CQP command list */
622 spinlock_t cqp_lock; /* protect CQP list access */
623 bool fcn_id_array[IRDMA_MAX_STATS_COUNT];
624 struct irdma_dma_mem vf_fpm_query_buf[IRDMA_MAX_PE_ENA_VF_COUNT];
625 u64 fpm_query_buf_pa;
626 u64 fpm_commit_buf_pa;
627 __le64 *fpm_query_buf;
628 __le64 *fpm_commit_buf;
629 struct irdma_hw *hw;
630 u8 __iomem *db_addr;
631 u32 __iomem *wqe_alloc_db;
632 u32 __iomem *cq_arm_db;
633 u32 __iomem *aeq_alloc_db;
634 u32 __iomem *cqp_db;
635 u32 __iomem *cq_ack_db;
636 u32 __iomem *ceq_itr_mask_db;
637 u32 __iomem *aeq_itr_mask_db;
638 u32 __iomem *hw_regs[IRDMA_MAX_REGS];
639 u32 ceq_itr; /* Interrupt throttle, usecs between interrupts: 0 disabled. 2 - 8160 */
640 u64 hw_masks[IRDMA_MAX_MASKS];
641 u64 hw_shifts[IRDMA_MAX_SHIFTS];
642 u64 hw_stats_regs_32[IRDMA_HW_STAT_INDEX_MAX_32];
643 u64 hw_stats_regs_64[IRDMA_HW_STAT_INDEX_MAX_64];
644 u64 feature_info[IRDMA_MAX_FEATURES];
645 u64 cqp_cmd_stats[IRDMA_MAX_CQP_OPS];
646 struct irdma_hw_attrs hw_attrs;
647 struct irdma_hmc_info *hmc_info;
648 struct irdma_sc_cqp *cqp;
649 struct irdma_sc_aeq *aeq;
650 struct irdma_sc_ceq *ceq[IRDMA_CEQ_MAX_COUNT];
651 struct irdma_sc_cq *ccq;
652 const struct irdma_irq_ops *irq_ops;
653 struct irdma_hmc_fpm_misc hmc_fpm_misc;
654 struct irdma_ws_node *ws_tree_root;
655 struct mutex ws_mutex; /* ws tree mutex */
656 u16 num_vfs;
657 u8 hmc_fn_id;
658 u8 vf_id;
659 bool vchnl_up:1;
660 bool ceq_valid:1;
661 u8 pci_rev;
662 int (*ws_add)(struct irdma_sc_vsi *vsi, u8 user_pri);
663 void (*ws_remove)(struct irdma_sc_vsi *vsi, u8 user_pri);
664 void (*ws_reset)(struct irdma_sc_vsi *vsi);
665 };
666
667 struct irdma_modify_cq_info {
668 u64 cq_pa;
669 struct irdma_cqe *cq_base;
670 u32 cq_size;
671 u32 shadow_read_threshold;
672 u8 pbl_chunk_size;
673 u32 first_pm_pbl_idx;
674 bool virtual_map:1;
675 bool check_overflow;
676 bool cq_resize:1;
677 };
678
679 struct irdma_create_qp_info {
680 bool ord_valid:1;
681 bool tcp_ctx_valid:1;
682 bool cq_num_valid:1;
683 bool arp_cache_idx_valid:1;
684 bool mac_valid:1;
685 bool force_lpb;
686 u8 next_iwarp_state;
687 };
688
689 struct irdma_modify_qp_info {
690 u64 rx_win0;
691 u64 rx_win1;
692 u16 new_mss;
693 u8 next_iwarp_state;
694 u8 curr_iwarp_state;
695 u8 termlen;
696 bool ord_valid:1;
697 bool tcp_ctx_valid:1;
698 bool udp_ctx_valid:1;
699 bool cq_num_valid:1;
700 bool arp_cache_idx_valid:1;
701 bool reset_tcp_conn:1;
702 bool remove_hash_idx:1;
703 bool dont_send_term:1;
704 bool dont_send_fin:1;
705 bool cached_var_valid:1;
706 bool mss_change:1;
707 bool force_lpb:1;
708 bool mac_valid:1;
709 };
710
711 struct irdma_ccq_cqe_info {
712 struct irdma_sc_cqp *cqp;
713 u64 scratch;
714 u32 op_ret_val;
715 u16 maj_err_code;
716 u16 min_err_code;
717 u8 op_code;
718 bool error;
719 };
720
721 struct irdma_dcb_app_info {
722 u8 priority;
723 u8 selector;
724 u16 prot_id;
725 };
726
727 struct irdma_qos_tc_info {
728 u64 tc_ctx;
729 u8 rel_bw;
730 u8 prio_type;
731 u8 egress_virt_up;
732 u8 ingress_virt_up;
733 };
734
735 struct irdma_l2params {
736 struct irdma_qos_tc_info tc_info[IRDMA_MAX_USER_PRIORITY];
737 struct irdma_dcb_app_info apps[IRDMA_MAX_APPS];
738 u32 num_apps;
739 u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY];
740 u16 mtu;
741 u8 up2tc[IRDMA_MAX_USER_PRIORITY];
742 u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
743 u8 num_tc;
744 u8 vsi_rel_bw;
745 u8 vsi_prio_type;
746 bool mtu_changed:1;
747 bool tc_changed:1;
748 bool dscp_mode:1;
749 };
750
751 struct irdma_vsi_init_info {
752 struct irdma_sc_dev *dev;
753 void *back_vsi;
754 struct irdma_l2params *params;
755 u16 exception_lan_q;
756 u16 pf_data_vsi_num;
757 enum irdma_vm_vf_type vm_vf_type;
758 u16 vm_id;
759 int (*register_qset)(struct irdma_sc_vsi *vsi,
760 struct irdma_ws_node *tc_node);
761 void (*unregister_qset)(struct irdma_sc_vsi *vsi,
762 struct irdma_ws_node *tc_node);
763 };
764
765 struct irdma_vsi_stats_info {
766 struct irdma_vsi_pestat *pestat;
767 u8 fcn_id;
768 bool alloc_fcn_id;
769 };
770
771 struct irdma_device_init_info {
772 u64 fpm_query_buf_pa;
773 u64 fpm_commit_buf_pa;
774 __le64 *fpm_query_buf;
775 __le64 *fpm_commit_buf;
776 struct irdma_hw *hw;
777 void __iomem *bar0;
778 u8 hmc_fn_id;
779 };
780
781 struct irdma_ceq_init_info {
782 u64 ceqe_pa;
783 struct irdma_sc_dev *dev;
784 u64 *ceqe_base;
785 void *pbl_list;
786 u32 elem_cnt;
787 u32 ceq_id;
788 bool virtual_map:1;
789 bool tph_en:1;
790 bool itr_no_expire:1;
791 u8 pbl_chunk_size;
792 u8 tph_val;
793 u32 first_pm_pbl_idx;
794 struct irdma_sc_vsi *vsi;
795 struct irdma_sc_cq **reg_cq;
796 u32 reg_cq_idx;
797 };
798
799 struct irdma_aeq_init_info {
800 u64 aeq_elem_pa;
801 struct irdma_sc_dev *dev;
802 u32 *aeqe_base;
803 void *pbl_list;
804 u32 elem_cnt;
805 bool virtual_map;
806 u8 pbl_chunk_size;
807 u32 first_pm_pbl_idx;
808 u32 msix_idx;
809 };
810
811 struct irdma_ccq_init_info {
812 u64 cq_pa;
813 u64 shadow_area_pa;
814 struct irdma_sc_dev *dev;
815 struct irdma_cqe *cq_base;
816 __le64 *shadow_area;
817 void *pbl_list;
818 u32 num_elem;
819 u32 ceq_id;
820 u32 shadow_read_threshold;
821 bool ceqe_mask:1;
822 bool ceq_id_valid:1;
823 bool avoid_mem_cflct:1;
824 bool virtual_map:1;
825 bool tph_en:1;
826 u8 tph_val;
827 u8 pbl_chunk_size;
828 u32 first_pm_pbl_idx;
829 struct irdma_sc_vsi *vsi;
830 };
831
832 struct irdma_udp_offload_info {
833 bool ipv4:1;
834 bool insert_vlan_tag:1;
835 u8 ttl;
836 u8 tos;
837 u16 src_port;
838 u16 dst_port;
839 u32 dest_ip_addr[4];
840 u32 snd_mss;
841 u16 vlan_tag;
842 u16 arp_idx;
843 u32 flow_label;
844 u8 udp_state;
845 u32 psn_nxt;
846 u32 lsn;
847 u32 epsn;
848 u32 psn_max;
849 u32 psn_una;
850 u32 local_ipaddr[4];
851 u32 cwnd;
852 u8 rexmit_thresh;
853 u8 rnr_nak_thresh;
854 };
855
856 struct irdma_roce_offload_info {
857 u16 p_key;
858 u16 err_rq_idx;
859 u32 qkey;
860 u32 dest_qp;
861 u8 roce_tver;
862 u8 ack_credits;
863 u8 err_rq_idx_valid;
864 u32 pd_id;
865 u16 ord_size;
866 u16 ird_size;
867 bool is_qp1:1;
868 bool udprivcq_en:1;
869 bool dcqcn_en:1;
870 bool rcv_no_icrc:1;
871 bool wr_rdresp_en:1;
872 bool bind_en:1;
873 bool fast_reg_en:1;
874 bool priv_mode_en:1;
875 bool rd_en:1;
876 bool timely_en:1;
877 bool dctcp_en:1;
878 bool fw_cc_enable:1;
879 bool use_stats_inst:1;
880 u16 t_high;
881 u16 t_low;
882 u8 last_byte_sent;
883 u8 mac_addr[ETH_ALEN];
884 u8 rtomin;
885 };
886
887 struct irdma_iwarp_offload_info {
888 u16 rcv_mark_offset;
889 u16 snd_mark_offset;
890 u8 ddp_ver;
891 u8 rdmap_ver;
892 u8 iwarp_mode;
893 u16 err_rq_idx;
894 u32 pd_id;
895 u16 ord_size;
896 u16 ird_size;
897 bool ib_rd_en:1;
898 bool align_hdrs:1;
899 bool rcv_no_mpa_crc:1;
900 bool err_rq_idx_valid:1;
901 bool snd_mark_en:1;
902 bool rcv_mark_en:1;
903 bool wr_rdresp_en:1;
904 bool bind_en:1;
905 bool fast_reg_en:1;
906 bool priv_mode_en:1;
907 bool rd_en:1;
908 bool timely_en:1;
909 bool use_stats_inst:1;
910 bool ecn_en:1;
911 bool dctcp_en:1;
912 u16 t_high;
913 u16 t_low;
914 u8 last_byte_sent;
915 u8 mac_addr[ETH_ALEN];
916 u8 rtomin;
917 };
918
919 struct irdma_tcp_offload_info {
920 bool ipv4:1;
921 bool no_nagle:1;
922 bool insert_vlan_tag:1;
923 bool time_stamp:1;
924 bool drop_ooo_seg:1;
925 bool avoid_stretch_ack:1;
926 bool wscale:1;
927 bool ignore_tcp_opt:1;
928 bool ignore_tcp_uns_opt:1;
929 u8 cwnd_inc_limit;
930 u8 dup_ack_thresh;
931 u8 ttl;
932 u8 src_mac_addr_idx;
933 u8 tos;
934 u16 src_port;
935 u16 dst_port;
936 u32 dest_ip_addr[4];
937 //u32 dest_ip_addr0;
938 //u32 dest_ip_addr1;
939 //u32 dest_ip_addr2;
940 //u32 dest_ip_addr3;
941 u32 snd_mss;
942 u16 syn_rst_handling;
943 u16 vlan_tag;
944 u16 arp_idx;
945 u32 flow_label;
946 u8 tcp_state;
947 u8 snd_wscale;
948 u8 rcv_wscale;
949 u32 time_stamp_recent;
950 u32 time_stamp_age;
951 u32 snd_nxt;
952 u32 snd_wnd;
953 u32 rcv_nxt;
954 u32 rcv_wnd;
955 u32 snd_max;
956 u32 snd_una;
957 u32 srtt;
958 u32 rtt_var;
959 u32 ss_thresh;
960 u32 cwnd;
961 u32 snd_wl1;
962 u32 snd_wl2;
963 u32 max_snd_window;
964 u8 rexmit_thresh;
965 u32 local_ipaddr[4];
966 };
967
968 struct irdma_qp_host_ctx_info {
969 u64 qp_compl_ctx;
970 union {
971 struct irdma_tcp_offload_info *tcp_info;
972 struct irdma_udp_offload_info *udp_info;
973 };
974 union {
975 struct irdma_iwarp_offload_info *iwarp_info;
976 struct irdma_roce_offload_info *roce_info;
977 };
978 u32 send_cq_num;
979 u32 rcv_cq_num;
980 u32 rem_endpoint_idx;
981 u8 stats_idx;
982 bool srq_valid:1;
983 bool tcp_info_valid:1;
984 bool iwarp_info_valid:1;
985 bool stats_idx_valid:1;
986 u8 user_pri;
987 };
988
989 struct irdma_aeqe_info {
990 u64 compl_ctx;
991 u32 qp_cq_id;
992 u16 ae_id;
993 u16 wqe_idx;
994 u8 tcp_state;
995 u8 iwarp_state;
996 bool qp:1;
997 bool cq:1;
998 bool sq:1;
999 bool rq:1;
1000 bool in_rdrsp_wr:1;
1001 bool out_rdrsp:1;
1002 bool aeqe_overflow:1;
1003 u8 q2_data_written;
1004 u8 ae_src;
1005 };
1006
1007 struct irdma_allocate_stag_info {
1008 u64 total_len;
1009 u64 first_pm_pbl_idx;
1010 u32 chunk_size;
1011 u32 stag_idx;
1012 u32 page_size;
1013 u32 pd_id;
1014 u16 access_rights;
1015 bool remote_access:1;
1016 bool use_hmc_fcn_index:1;
1017 bool use_pf_rid:1;
1018 bool all_memory:1;
1019 u8 hmc_fcn_index;
1020 };
1021
1022 struct irdma_mw_alloc_info {
1023 u32 mw_stag_index;
1024 u32 page_size;
1025 u32 pd_id;
1026 bool remote_access:1;
1027 bool mw_wide:1;
1028 bool mw1_bind_dont_vldt_key:1;
1029 };
1030
1031 struct irdma_reg_ns_stag_info {
1032 u64 reg_addr_pa;
1033 u64 va;
1034 u64 total_len;
1035 u32 page_size;
1036 u32 chunk_size;
1037 u32 first_pm_pbl_index;
1038 enum irdma_addressing_type addr_type;
1039 irdma_stag_index stag_idx;
1040 u16 access_rights;
1041 u32 pd_id;
1042 irdma_stag_key stag_key;
1043 bool use_hmc_fcn_index:1;
1044 u8 hmc_fcn_index;
1045 bool use_pf_rid:1;
1046 bool all_memory:1;
1047 };
1048
1049 struct irdma_fast_reg_stag_info {
1050 u64 wr_id;
1051 u64 reg_addr_pa;
1052 u64 fbo;
1053 void *va;
1054 u64 total_len;
1055 u32 page_size;
1056 u32 chunk_size;
1057 u32 first_pm_pbl_index;
1058 enum irdma_addressing_type addr_type;
1059 irdma_stag_index stag_idx;
1060 u16 access_rights;
1061 u32 pd_id;
1062 irdma_stag_key stag_key;
1063 bool local_fence:1;
1064 bool read_fence:1;
1065 bool signaled:1;
1066 bool push_wqe:1;
1067 bool use_hmc_fcn_index:1;
1068 u8 hmc_fcn_index;
1069 bool use_pf_rid:1;
1070 bool defer_flag:1;
1071 };
1072
1073 struct irdma_dealloc_stag_info {
1074 u32 stag_idx;
1075 u32 pd_id;
1076 bool mr:1;
1077 bool dealloc_pbl:1;
1078 };
1079
1080 struct irdma_register_shared_stag {
1081 u64 va;
1082 enum irdma_addressing_type addr_type;
1083 irdma_stag_index new_stag_idx;
1084 irdma_stag_index parent_stag_idx;
1085 u32 access_rights;
1086 u32 pd_id;
1087 u32 page_size;
1088 irdma_stag_key new_stag_key;
1089 };
1090
1091 struct irdma_qp_init_info {
1092 struct irdma_qp_uk_init_info qp_uk_init_info;
1093 struct irdma_sc_pd *pd;
1094 struct irdma_sc_vsi *vsi;
1095 __le64 *host_ctx;
1096 u8 *q2;
1097 u64 sq_pa;
1098 u64 rq_pa;
1099 u64 host_ctx_pa;
1100 u64 q2_pa;
1101 u64 shadow_area_pa;
1102 u8 sq_tph_val;
1103 u8 rq_tph_val;
1104 bool sq_tph_en:1;
1105 bool rq_tph_en:1;
1106 bool rcv_tph_en:1;
1107 bool xmit_tph_en:1;
1108 bool virtual_map:1;
1109 };
1110
1111 struct irdma_cq_init_info {
1112 struct irdma_sc_dev *dev;
1113 u64 cq_base_pa;
1114 u64 shadow_area_pa;
1115 u32 ceq_id;
1116 u32 shadow_read_threshold;
1117 u8 pbl_chunk_size;
1118 u32 first_pm_pbl_idx;
1119 bool virtual_map:1;
1120 bool ceqe_mask:1;
1121 bool ceq_id_valid:1;
1122 bool tph_en:1;
1123 u8 tph_val;
1124 u8 type;
1125 struct irdma_cq_uk_init_info cq_uk_init_info;
1126 struct irdma_sc_vsi *vsi;
1127 };
1128
1129 struct irdma_upload_context_info {
1130 u64 buf_pa;
1131 u32 qp_id;
1132 u8 qp_type;
1133 bool freeze_qp:1;
1134 bool raw_format:1;
1135 };
1136
1137 struct irdma_local_mac_entry_info {
1138 u8 mac_addr[6];
1139 u16 entry_idx;
1140 };
1141
1142 struct irdma_add_arp_cache_entry_info {
1143 u8 mac_addr[ETH_ALEN];
1144 u32 reach_max;
1145 u16 arp_index;
1146 bool permanent;
1147 };
1148
1149 struct irdma_apbvt_info {
1150 u16 port;
1151 bool add;
1152 };
1153
1154 struct irdma_qhash_table_info {
1155 struct irdma_sc_vsi *vsi;
1156 enum irdma_quad_hash_manage_type manage;
1157 enum irdma_quad_entry_type entry_type;
1158 bool vlan_valid:1;
1159 bool ipv4_valid:1;
1160 u8 mac_addr[ETH_ALEN];
1161 u16 vlan_id;
1162 u8 user_pri;
1163 u32 qp_num;
1164 u32 dest_ip[4];
1165 u32 src_ip[4];
1166 u16 dest_port;
1167 u16 src_port;
1168 };
1169
1170 struct irdma_cqp_manage_push_page_info {
1171 u32 push_idx;
1172 u16 qs_handle;
1173 u8 free_page;
1174 u8 push_page_type;
1175 };
1176
1177 struct irdma_qp_flush_info {
1178 u16 sq_minor_code;
1179 u16 sq_major_code;
1180 u16 rq_minor_code;
1181 u16 rq_major_code;
1182 u16 ae_code;
1183 u8 ae_src;
1184 bool sq:1;
1185 bool rq:1;
1186 bool userflushcode:1;
1187 bool generate_ae:1;
1188 };
1189
1190 struct irdma_gen_ae_info {
1191 u16 ae_code;
1192 u8 ae_src;
1193 };
1194
1195 struct irdma_cqp_timeout {
1196 u64 compl_cqp_cmds;
1197 u32 count;
1198 };
1199
1200 struct irdma_irq_ops {
1201 void (*irdma_cfg_aeq)(struct irdma_sc_dev *dev, u32 idx, bool enable);
1202 void (*irdma_cfg_ceq)(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
1203 bool enable);
1204 void (*irdma_dis_irq)(struct irdma_sc_dev *dev, u32 idx);
1205 void (*irdma_en_irq)(struct irdma_sc_dev *dev, u32 idx);
1206 };
1207
1208 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq);
1209 int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
1210 bool check_overflow, bool post_sq);
1211 int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq);
1212 int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
1213 struct irdma_ccq_cqe_info *info);
1214 int irdma_sc_ccq_init(struct irdma_sc_cq *ccq,
1215 struct irdma_ccq_init_info *info);
1216
1217 int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch);
1218 int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq);
1219
1220 int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq);
1221 int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
1222 struct irdma_ceq_init_info *info);
1223 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq);
1224 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq);
1225
1226 int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
1227 struct irdma_aeq_init_info *info);
1228 int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
1229 struct irdma_aeqe_info *info);
1230 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count);
1231
1232 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id,
1233 int abi_ver);
1234 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable);
1235 void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout,
1236 struct irdma_sc_dev *dev);
1237 int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err);
1238 int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp);
1239 int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
1240 struct irdma_cqp_init_info *info);
1241 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);
1242 int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode,
1243 struct irdma_ccq_cqe_info *cmpl_info);
1244 int irdma_sc_fast_register(struct irdma_sc_qp *qp,
1245 struct irdma_fast_reg_stag_info *info, bool post_sq);
1246 int irdma_sc_qp_create(struct irdma_sc_qp *qp,
1247 struct irdma_create_qp_info *info, u64 scratch,
1248 bool post_sq);
1249 int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
1250 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq);
1251 int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
1252 struct irdma_qp_flush_info *info, u64 scratch,
1253 bool post_sq);
1254 int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info);
1255 int irdma_sc_qp_modify(struct irdma_sc_qp *qp,
1256 struct irdma_modify_qp_info *info, u64 scratch,
1257 bool post_sq);
1258 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size,
1259 irdma_stag stag);
1260
1261 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read);
1262 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx,
1263 struct irdma_qp_host_ctx_info *info);
1264 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
1265 struct irdma_qp_host_ctx_info *info);
1266 int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq);
1267 int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info);
1268 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info);
1269 int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
1270 u8 hmc_fn_id, bool post_sq,
1271 bool poll_registers);
1272
1273 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi);
1274 struct cqp_info {
1275 union {
1276 struct {
1277 struct irdma_sc_qp *qp;
1278 struct irdma_create_qp_info info;
1279 u64 scratch;
1280 } qp_create;
1281
1282 struct {
1283 struct irdma_sc_qp *qp;
1284 struct irdma_modify_qp_info info;
1285 u64 scratch;
1286 } qp_modify;
1287
1288 struct {
1289 struct irdma_sc_qp *qp;
1290 u64 scratch;
1291 bool remove_hash_idx;
1292 bool ignore_mw_bnd;
1293 } qp_destroy;
1294
1295 struct {
1296 struct irdma_sc_cq *cq;
1297 u64 scratch;
1298 bool check_overflow;
1299 } cq_create;
1300
1301 struct {
1302 struct irdma_sc_cq *cq;
1303 struct irdma_modify_cq_info info;
1304 u64 scratch;
1305 } cq_modify;
1306
1307 struct {
1308 struct irdma_sc_cq *cq;
1309 u64 scratch;
1310 } cq_destroy;
1311
1312 struct {
1313 struct irdma_sc_dev *dev;
1314 struct irdma_allocate_stag_info info;
1315 u64 scratch;
1316 } alloc_stag;
1317
1318 struct {
1319 struct irdma_sc_dev *dev;
1320 struct irdma_mw_alloc_info info;
1321 u64 scratch;
1322 } mw_alloc;
1323
1324 struct {
1325 struct irdma_sc_dev *dev;
1326 struct irdma_reg_ns_stag_info info;
1327 u64 scratch;
1328 } mr_reg_non_shared;
1329
1330 struct {
1331 struct irdma_sc_dev *dev;
1332 struct irdma_dealloc_stag_info info;
1333 u64 scratch;
1334 } dealloc_stag;
1335
1336 struct {
1337 struct irdma_sc_cqp *cqp;
1338 struct irdma_add_arp_cache_entry_info info;
1339 u64 scratch;
1340 } add_arp_cache_entry;
1341
1342 struct {
1343 struct irdma_sc_cqp *cqp;
1344 u64 scratch;
1345 u16 arp_index;
1346 } del_arp_cache_entry;
1347
1348 struct {
1349 struct irdma_sc_cqp *cqp;
1350 struct irdma_local_mac_entry_info info;
1351 u64 scratch;
1352 } add_local_mac_entry;
1353
1354 struct {
1355 struct irdma_sc_cqp *cqp;
1356 u64 scratch;
1357 u8 entry_idx;
1358 u8 ignore_ref_count;
1359 } del_local_mac_entry;
1360
1361 struct {
1362 struct irdma_sc_cqp *cqp;
1363 u64 scratch;
1364 } alloc_local_mac_entry;
1365
1366 struct {
1367 struct irdma_sc_cqp *cqp;
1368 struct irdma_cqp_manage_push_page_info info;
1369 u64 scratch;
1370 } manage_push_page;
1371
1372 struct {
1373 struct irdma_sc_dev *dev;
1374 struct irdma_upload_context_info info;
1375 u64 scratch;
1376 } qp_upload_context;
1377
1378 struct {
1379 struct irdma_sc_dev *dev;
1380 struct irdma_hmc_fcn_info info;
1381 u64 scratch;
1382 } manage_hmc_pm;
1383
1384 struct {
1385 struct irdma_sc_ceq *ceq;
1386 u64 scratch;
1387 } ceq_create;
1388
1389 struct {
1390 struct irdma_sc_ceq *ceq;
1391 u64 scratch;
1392 } ceq_destroy;
1393
1394 struct {
1395 struct irdma_sc_aeq *aeq;
1396 u64 scratch;
1397 } aeq_create;
1398
1399 struct {
1400 struct irdma_sc_aeq *aeq;
1401 u64 scratch;
1402 } aeq_destroy;
1403
1404 struct {
1405 struct irdma_sc_qp *qp;
1406 struct irdma_qp_flush_info info;
1407 u64 scratch;
1408 } qp_flush_wqes;
1409
1410 struct {
1411 struct irdma_sc_qp *qp;
1412 struct irdma_gen_ae_info info;
1413 u64 scratch;
1414 } gen_ae;
1415
1416 struct {
1417 struct irdma_sc_cqp *cqp;
1418 void *fpm_val_va;
1419 u64 fpm_val_pa;
1420 u8 hmc_fn_id;
1421 u64 scratch;
1422 } query_fpm_val;
1423
1424 struct {
1425 struct irdma_sc_cqp *cqp;
1426 void *fpm_val_va;
1427 u64 fpm_val_pa;
1428 u8 hmc_fn_id;
1429 u64 scratch;
1430 } commit_fpm_val;
1431
1432 struct {
1433 struct irdma_sc_cqp *cqp;
1434 struct irdma_apbvt_info info;
1435 u64 scratch;
1436 } manage_apbvt_entry;
1437
1438 struct {
1439 struct irdma_sc_cqp *cqp;
1440 struct irdma_qhash_table_info info;
1441 u64 scratch;
1442 } manage_qhash_table_entry;
1443
1444 struct {
1445 struct irdma_sc_dev *dev;
1446 struct irdma_update_sds_info info;
1447 u64 scratch;
1448 } update_pe_sds;
1449
1450 struct {
1451 struct irdma_sc_cqp *cqp;
1452 struct irdma_sc_qp *qp;
1453 u64 scratch;
1454 } suspend_resume;
1455
1456 struct {
1457 struct irdma_sc_cqp *cqp;
1458 struct irdma_ah_info info;
1459 u64 scratch;
1460 } ah_create;
1461
1462 struct {
1463 struct irdma_sc_cqp *cqp;
1464 struct irdma_ah_info info;
1465 u64 scratch;
1466 } ah_destroy;
1467
1468 struct {
1469 struct irdma_sc_cqp *cqp;
1470 struct irdma_mcast_grp_info info;
1471 u64 scratch;
1472 } mc_create;
1473
1474 struct {
1475 struct irdma_sc_cqp *cqp;
1476 struct irdma_mcast_grp_info info;
1477 u64 scratch;
1478 } mc_destroy;
1479
1480 struct {
1481 struct irdma_sc_cqp *cqp;
1482 struct irdma_mcast_grp_info info;
1483 u64 scratch;
1484 } mc_modify;
1485
1486 struct {
1487 struct irdma_sc_cqp *cqp;
1488 struct irdma_stats_inst_info info;
1489 u64 scratch;
1490 } stats_manage;
1491
1492 struct {
1493 struct irdma_sc_cqp *cqp;
1494 struct irdma_stats_gather_info info;
1495 u64 scratch;
1496 } stats_gather;
1497
1498 struct {
1499 struct irdma_sc_cqp *cqp;
1500 struct irdma_ws_node_info info;
1501 u64 scratch;
1502 } ws_node;
1503
1504 struct {
1505 struct irdma_sc_cqp *cqp;
1506 struct irdma_up_info info;
1507 u64 scratch;
1508 } up_map;
1509
1510 struct {
1511 struct irdma_sc_cqp *cqp;
1512 struct irdma_dma_mem query_buff_mem;
1513 u64 scratch;
1514 } query_rdma;
1515 } u;
1516 };
1517
1518 struct cqp_cmds_info {
1519 struct list_head cqp_cmd_entry;
1520 u8 cqp_cmd;
1521 u8 post_sq;
1522 struct cqp_info in;
1523 };
1524
1525 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,
1526 u32 *wqe_idx);
1527
1528 /**
1529 * irdma_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
1530 * @cqp: struct for cqp hw
1531 * @scratch: private data for CQP WQE
1532 */
irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp * cqp,u64 scratch)1533 static inline __le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch)
1534 {
1535 u32 wqe_idx;
1536
1537 return irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
1538 }
1539 #endif /* IRDMA_TYPE_H */
1540