1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 41 #define MAX_CLOCK_SOURCES 7 42 #define MAX_SVP_PHANTOM_STREAMS 2 43 #define MAX_SVP_PHANTOM_PLANES 2 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 #include "link_hwss.h" 58 59 /************ link *****************/ 60 struct link_init_data { 61 const struct dc *dc; 62 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 63 uint32_t connector_index; /* this will be mapped to the HPD pins */ 64 uint32_t link_index; /* this is mapped to DAL display_index 65 TODO: remove it when DC is complete. */ 66 bool is_dpia_link; 67 }; 68 69 struct dc_link *link_create(const struct link_init_data *init_params); 70 void link_destroy(struct dc_link **link); 71 72 enum dc_status dc_link_validate_mode_timing( 73 const struct dc_stream_state *stream, 74 struct dc_link *link, 75 const struct dc_crtc_timing *timing); 76 77 void core_link_resume(struct dc_link *link); 78 79 void core_link_enable_stream( 80 struct dc_state *state, 81 struct pipe_ctx *pipe_ctx); 82 83 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 84 85 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 86 /********** DAL Core*********************/ 87 #include "transform.h" 88 #include "dpp.h" 89 90 struct resource_pool; 91 struct dc_state; 92 struct resource_context; 93 struct clk_bw_params; 94 95 struct resource_funcs { 96 void (*destroy)(struct resource_pool **pool); 97 void (*link_init)(struct dc_link *link); 98 struct panel_cntl*(*panel_cntl_create)( 99 const struct panel_cntl_init_data *panel_cntl_init_data); 100 struct link_encoder *(*link_enc_create)( 101 struct dc_context *ctx, 102 const struct encoder_init_data *init); 103 /* Create a minimal link encoder object with no dc_link object 104 * associated with it. */ 105 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 106 107 bool (*validate_bandwidth)( 108 struct dc *dc, 109 struct dc_state *context, 110 bool fast_validate); 111 void (*calculate_wm_and_dlg)( 112 struct dc *dc, struct dc_state *context, 113 display_e2e_pipe_params_st *pipes, 114 int pipe_cnt, 115 int vlevel); 116 void (*update_soc_for_wm_a)( 117 struct dc *dc, struct dc_state *context); 118 119 /** 120 * @populate_dml_pipes - Populate pipe data struct 121 * 122 * Returns: 123 * Total of pipes available in the specific ASIC. 124 */ 125 int (*populate_dml_pipes)( 126 struct dc *dc, 127 struct dc_state *context, 128 display_e2e_pipe_params_st *pipes, 129 bool fast_validate); 130 131 /* 132 * Algorithm for assigning available link encoders to links. 133 * 134 * Update link_enc_assignments table and link_enc_avail list accordingly in 135 * struct resource_context. 136 */ 137 void (*link_encs_assign)( 138 struct dc *dc, 139 struct dc_state *state, 140 struct dc_stream_state *streams[], 141 uint8_t stream_count); 142 /* 143 * Unassign a link encoder from a stream. 144 * 145 * Update link_enc_assignments table and link_enc_avail list accordingly in 146 * struct resource_context. 147 */ 148 void (*link_enc_unassign)( 149 struct dc_state *state, 150 struct dc_stream_state *stream); 151 152 enum dc_status (*validate_global)( 153 struct dc *dc, 154 struct dc_state *context); 155 156 /* 157 * Acquires a free pipe for the head pipe. 158 * The head pipe is first pipe in the current context that matches the stream 159 * and does not have a top pipe or prev_odm_pipe. 160 */ 161 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 162 struct dc_state *context, 163 const struct resource_pool *pool, 164 struct dc_stream_state *stream); 165 166 /* 167 * Acquires a free pipe for the head pipe with some additional checks for odm. 168 * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer 169 * where it is read from the context. So this allows us look for different 170 * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have 171 * a left and right pipe ). 172 * 173 * It also checks the old context to see if: 174 * 175 * 1. a pipe has already been allocated for the head pipe. If so, it will 176 * try to select that pipe as the idle pipe if it is available in the current 177 * context. 178 * 2. if the head_pipe is on the left, it will check if the right pipe has 179 * a pipe already allocated. If so, it will not use that pipe if it is 180 * selected as the idle pipe. 181 */ 182 struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)( 183 struct dc_state *context, 184 const struct resource_pool *pool, 185 struct dc_stream_state *stream, 186 struct pipe_ctx *head_pipe); 187 188 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 189 190 enum dc_status (*add_stream_to_ctx)( 191 struct dc *dc, 192 struct dc_state *new_ctx, 193 struct dc_stream_state *dc_stream); 194 195 enum dc_status (*remove_stream_from_ctx)( 196 struct dc *dc, 197 struct dc_state *new_ctx, 198 struct dc_stream_state *stream); 199 enum dc_status (*patch_unknown_plane_state)( 200 struct dc_plane_state *plane_state); 201 202 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 203 struct resource_context *res_ctx, 204 const struct resource_pool *pool, 205 struct dc_stream_state *stream); 206 void (*populate_dml_writeback_from_context)( 207 struct dc *dc, 208 struct resource_context *res_ctx, 209 display_e2e_pipe_params_st *pipes); 210 211 void (*set_mcif_arb_params)( 212 struct dc *dc, 213 struct dc_state *context, 214 display_e2e_pipe_params_st *pipes, 215 int pipe_cnt); 216 void (*update_bw_bounding_box)( 217 struct dc *dc, 218 struct clk_bw_params *bw_params); 219 bool (*acquire_post_bldn_3dlut)( 220 struct resource_context *res_ctx, 221 const struct resource_pool *pool, 222 int mpcc_id, 223 struct dc_3dlut **lut, 224 struct dc_transfer_func **shaper); 225 226 bool (*release_post_bldn_3dlut)( 227 struct resource_context *res_ctx, 228 const struct resource_pool *pool, 229 struct dc_3dlut **lut, 230 struct dc_transfer_func **shaper); 231 232 enum dc_status (*add_dsc_to_stream_resource)( 233 struct dc *dc, struct dc_state *state, 234 struct dc_stream_state *stream); 235 236 void (*add_phantom_pipes)( 237 struct dc *dc, 238 struct dc_state *context, 239 display_e2e_pipe_params_st *pipes, 240 unsigned int pipe_cnt, 241 unsigned int index); 242 243 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context); 244 void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 245 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 246 }; 247 248 struct audio_support{ 249 bool dp_audio; 250 bool hdmi_audio_on_dongle; 251 bool hdmi_audio_native; 252 }; 253 254 #define NO_UNDERLAY_PIPE -1 255 256 struct resource_pool { 257 struct mem_input *mis[MAX_PIPES]; 258 struct hubp *hubps[MAX_PIPES]; 259 struct input_pixel_processor *ipps[MAX_PIPES]; 260 struct transform *transforms[MAX_PIPES]; 261 struct dpp *dpps[MAX_PIPES]; 262 struct output_pixel_processor *opps[MAX_PIPES]; 263 struct timing_generator *timing_generators[MAX_PIPES]; 264 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 265 struct hubbub *hubbub; 266 struct mpc *mpc; 267 struct pp_smu_funcs *pp_smu; 268 struct dce_aux *engines[MAX_PIPES]; 269 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 270 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 271 bool i2c_hw_buffer_in_use; 272 273 struct dwbc *dwbc[MAX_DWB_PIPES]; 274 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 275 struct { 276 unsigned int gsl_0:1; 277 unsigned int gsl_1:1; 278 unsigned int gsl_2:1; 279 } gsl_groups; 280 281 struct display_stream_compressor *dscs[MAX_PIPES]; 282 283 unsigned int pipe_count; 284 unsigned int underlay_pipe_index; 285 unsigned int stream_enc_count; 286 287 /* An array for accessing the link encoder objects that have been created. 288 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 289 */ 290 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 291 /* Number of DIG link encoder objects created - i.e. number of valid 292 * entries in link_encoders array. 293 */ 294 unsigned int dig_link_enc_count; 295 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 296 unsigned int usb4_dpia_count; 297 298 unsigned int hpo_dp_stream_enc_count; 299 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 300 unsigned int hpo_dp_link_enc_count; 301 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 302 struct dc_3dlut *mpc_lut[MAX_PIPES]; 303 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 304 305 struct { 306 unsigned int xtalin_clock_inKhz; 307 unsigned int dccg_ref_clock_inKhz; 308 unsigned int dchub_ref_clock_inKhz; 309 } ref_clocks; 310 unsigned int timing_generator_count; 311 unsigned int mpcc_count; 312 313 unsigned int writeback_pipe_count; 314 /* 315 * reserved clock source for DP 316 */ 317 struct clock_source *dp_clock_source; 318 319 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 320 unsigned int clk_src_count; 321 322 struct audio *audios[MAX_AUDIOS]; 323 unsigned int audio_count; 324 struct audio_support audio_support; 325 326 struct dccg *dccg; 327 struct irq_service *irqs; 328 329 struct abm *abm; 330 struct dmcu *dmcu; 331 struct dmub_psr *psr; 332 333 struct abm *multiple_abms[MAX_PIPES]; 334 335 const struct resource_funcs *funcs; 336 const struct resource_caps *res_cap; 337 338 struct ddc_service *oem_device; 339 }; 340 341 struct dcn_fe_bandwidth { 342 int dppclk_khz; 343 344 }; 345 346 struct stream_resource { 347 struct output_pixel_processor *opp; 348 struct display_stream_compressor *dsc; 349 struct timing_generator *tg; 350 struct stream_encoder *stream_enc; 351 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 352 struct audio *audio; 353 354 struct pixel_clk_params pix_clk_params; 355 struct encoder_info_frame encoder_info_frame; 356 357 struct abm *abm; 358 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 359 * otherwise it's using group number 'gsl_group-1' 360 */ 361 uint8_t gsl_group; 362 }; 363 364 struct plane_resource { 365 struct scaler_data scl_data; 366 struct hubp *hubp; 367 struct mem_input *mi; 368 struct input_pixel_processor *ipp; 369 struct transform *xfm; 370 struct dpp *dpp; 371 uint8_t mpcc_inst; 372 373 struct dcn_fe_bandwidth bw; 374 }; 375 376 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 377 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 378 379 /* all mappable hardware resources used to enable a link */ 380 struct link_resource { 381 struct hpo_dp_link_encoder *hpo_dp_link_enc; 382 }; 383 384 struct link_config { 385 struct dc_link_settings dp_link_settings; 386 }; 387 union pipe_update_flags { 388 struct { 389 uint32_t enable : 1; 390 uint32_t disable : 1; 391 uint32_t odm : 1; 392 uint32_t global_sync : 1; 393 uint32_t opp_changed : 1; 394 uint32_t tg_changed : 1; 395 uint32_t mpcc : 1; 396 uint32_t dppclk : 1; 397 uint32_t hubp_interdependent : 1; 398 uint32_t hubp_rq_dlg_ttu : 1; 399 uint32_t gamut_remap : 1; 400 uint32_t scaler : 1; 401 uint32_t viewport : 1; 402 uint32_t plane_changed : 1; 403 uint32_t det_size : 1; 404 } bits; 405 uint32_t raw; 406 }; 407 408 struct pipe_ctx { 409 struct dc_plane_state *plane_state; 410 struct dc_stream_state *stream; 411 412 struct plane_resource plane_res; 413 414 /** 415 * @stream_res: Reference to DCN resource components such OPP and DSC. 416 */ 417 struct stream_resource stream_res; 418 struct link_resource link_res; 419 420 struct clock_source *clock_source; 421 422 struct pll_settings pll_settings; 423 424 /* link config records software decision for what link config should be 425 * enabled given current link capability and stream during hw resource 426 * mapping. This is to decouple the dependency on link capability during 427 * dc commit or update. 428 */ 429 struct link_config link_config; 430 431 uint8_t pipe_idx; 432 uint8_t pipe_idx_syncd; 433 434 struct pipe_ctx *top_pipe; 435 struct pipe_ctx *bottom_pipe; 436 struct pipe_ctx *next_odm_pipe; 437 struct pipe_ctx *prev_odm_pipe; 438 439 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 440 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 441 struct _vcs_dpi_display_rq_regs_st rq_regs; 442 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 443 struct _vcs_dpi_display_rq_params_st dml_rq_param; 444 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 445 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 446 int det_buffer_size_kb; 447 bool unbounded_req; 448 449 union pipe_update_flags update_flags; 450 struct dwbc *dwbc; 451 struct mcif_wb *mcif_wb; 452 }; 453 454 /* Data used for dynamic link encoder assignment. 455 * Tracks current and future assignments; available link encoders; 456 * and mode of operation (whether to use current or future assignments). 457 */ 458 struct link_enc_cfg_context { 459 enum link_enc_cfg_mode mode; 460 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 461 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 462 struct link_enc_assignment transient_assignments[MAX_PIPES]; 463 }; 464 465 struct resource_context { 466 struct pipe_ctx pipe_ctx[MAX_PIPES]; 467 bool is_stream_enc_acquired[MAX_PIPES * 2]; 468 bool is_audio_acquired[MAX_PIPES]; 469 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 470 uint8_t dp_clock_source_ref_count; 471 bool is_dsc_acquired[MAX_PIPES]; 472 struct link_enc_cfg_context link_enc_cfg_ctx; 473 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 474 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 475 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 476 bool is_mpc_3dlut_acquired[MAX_PIPES]; 477 }; 478 479 struct dce_bw_output { 480 bool cpuc_state_change_enable; 481 bool cpup_state_change_enable; 482 bool stutter_mode_enable; 483 bool nbp_state_change_enable; 484 bool all_displays_in_sync; 485 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 486 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 487 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 488 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 489 int sclk_khz; 490 int sclk_deep_sleep_khz; 491 int yclk_khz; 492 int dispclk_khz; 493 int blackout_recovery_time_us; 494 }; 495 496 struct dcn_bw_writeback { 497 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 498 }; 499 500 struct dcn_bw_output { 501 struct dc_clocks clk; 502 struct dcn_watermark_set watermarks; 503 struct dcn_bw_writeback bw_writeback; 504 int compbuf_size_kb; 505 unsigned int legacy_svp_drr_stream_index; 506 bool legacy_svp_drr_stream_index_valid; 507 }; 508 509 union bw_output { 510 struct dcn_bw_output dcn; 511 struct dce_bw_output dce; 512 }; 513 514 struct bw_context { 515 union bw_output bw; 516 struct display_mode_lib dml; 517 }; 518 /** 519 * struct dc_state - The full description of a state requested by a user 520 * 521 * @streams: Stream properties 522 * @stream_status: The planes on a given stream 523 * @res_ctx: Persistent state of resources 524 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 525 * @pp_display_cfg: PowerPlay clocks and settings 526 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 527 * 528 */ 529 struct dc_state { 530 struct dc_stream_state *streams[MAX_PIPES]; 531 struct dc_stream_status stream_status[MAX_PIPES]; 532 uint8_t stream_count; 533 uint8_t stream_mask; 534 535 struct resource_context res_ctx; 536 537 struct bw_context bw_ctx; 538 539 /* Note: these are big structures, do *not* put on stack! */ 540 struct dm_pp_display_configuration pp_display_cfg; 541 struct dcn_bw_internal_vars dcn_bw_vars; 542 543 struct clk_mgr *clk_mgr; 544 545 struct kref refcount; 546 547 struct { 548 unsigned int stutter_period_us; 549 } perf_params; 550 }; 551 552 struct dc_bounding_box_max_clk { 553 int max_dcfclk_mhz; 554 int max_dispclk_mhz; 555 int max_dppclk_mhz; 556 int max_phyclk_mhz; 557 }; 558 559 #endif /* _CORE_TYPES_H_ */ 560