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1 // SPDX-License-Identifier: GPL-2.0
2 /* Microchip LAN937X switch driver main logic
3  * Copyright (C) 2019-2022 Microchip Technology Inc.
4  */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/iopoll.h>
8 #include <linux/phy.h>
9 #include <linux/of_net.h>
10 #include <linux/if_bridge.h>
11 #include <linux/if_vlan.h>
12 #include <linux/math.h>
13 #include <net/dsa.h>
14 #include <net/switchdev.h>
15 
16 #include "lan937x_reg.h"
17 #include "ksz_common.h"
18 #include "lan937x.h"
19 
lan937x_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)20 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
21 {
22 	return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
23 }
24 
lan937x_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)25 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
26 			    u8 bits, bool set)
27 {
28 	return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
29 				  bits, set ? bits : 0);
30 }
31 
lan937x_enable_spi_indirect_access(struct ksz_device * dev)32 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
33 {
34 	u16 data16;
35 	int ret;
36 
37 	/* Enable Phy access through SPI */
38 	ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
39 	if (ret < 0)
40 		return ret;
41 
42 	ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
43 	if (ret < 0)
44 		return ret;
45 
46 	/* Allow SPI access */
47 	data16 |= VPHY_SPI_INDIRECT_ENABLE;
48 
49 	return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
50 }
51 
lan937x_vphy_ind_addr_wr(struct ksz_device * dev,int addr,int reg)52 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
53 {
54 	u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
55 	u16 temp;
56 
57 	/* get register address based on the logical port */
58 	temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
59 
60 	return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
61 }
62 
lan937x_internal_phy_write(struct ksz_device * dev,int addr,int reg,u16 val)63 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
64 				      u16 val)
65 {
66 	unsigned int value;
67 	int ret;
68 
69 	/* Check for internal phy port */
70 	if (!dev->info->internal_phy[addr])
71 		return -EOPNOTSUPP;
72 
73 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
74 	if (ret < 0)
75 		return ret;
76 
77 	/* Write the data to be written to the VPHY reg */
78 	ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
79 	if (ret < 0)
80 		return ret;
81 
82 	/* Write the Write En and Busy bit */
83 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
84 			  (VPHY_IND_WRITE | VPHY_IND_BUSY));
85 	if (ret < 0)
86 		return ret;
87 
88 	ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
89 				       value, !(value & VPHY_IND_BUSY), 10,
90 				       1000);
91 	if (ret < 0) {
92 		dev_err(dev->dev, "Failed to write phy register\n");
93 		return ret;
94 	}
95 
96 	return 0;
97 }
98 
lan937x_internal_phy_read(struct ksz_device * dev,int addr,int reg,u16 * val)99 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
100 				     u16 *val)
101 {
102 	unsigned int value;
103 	int ret;
104 
105 	/* Check for internal phy port, return 0xffff for non-existent phy */
106 	if (!dev->info->internal_phy[addr])
107 		return 0xffff;
108 
109 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
110 	if (ret < 0)
111 		return ret;
112 
113 	/* Write Read and Busy bit to start the transaction */
114 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
115 	if (ret < 0)
116 		return ret;
117 
118 	ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
119 				       value, !(value & VPHY_IND_BUSY), 10,
120 				       1000);
121 	if (ret < 0) {
122 		dev_err(dev->dev, "Failed to read phy register\n");
123 		return ret;
124 	}
125 
126 	/* Read the VPHY register which has the PHY data */
127 	return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
128 }
129 
lan937x_r_phy(struct ksz_device * dev,u16 addr,u16 reg,u16 * data)130 int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
131 {
132 	return lan937x_internal_phy_read(dev, addr, reg, data);
133 }
134 
lan937x_w_phy(struct ksz_device * dev,u16 addr,u16 reg,u16 val)135 int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
136 {
137 	return lan937x_internal_phy_write(dev, addr, reg, val);
138 }
139 
lan937x_reset_switch(struct ksz_device * dev)140 int lan937x_reset_switch(struct ksz_device *dev)
141 {
142 	u32 data32;
143 	int ret;
144 
145 	/* reset switch */
146 	ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
147 	if (ret < 0)
148 		return ret;
149 
150 	/* Enable Auto Aging */
151 	ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
152 	if (ret < 0)
153 		return ret;
154 
155 	/* disable interrupts */
156 	ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
157 	if (ret < 0)
158 		return ret;
159 
160 	ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT);
161 	if (ret < 0)
162 		return ret;
163 
164 	ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
165 	if (ret < 0)
166 		return ret;
167 
168 	return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
169 }
170 
lan937x_port_setup(struct ksz_device * dev,int port,bool cpu_port)171 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
172 {
173 	const u32 *masks = dev->info->masks;
174 	const u16 *regs = dev->info->regs;
175 	struct dsa_switch *ds = dev->ds;
176 	u8 member;
177 
178 	/* enable tag tail for host port */
179 	if (cpu_port)
180 		lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
181 				 PORT_TAIL_TAG_ENABLE, true);
182 
183 	/* set back pressure for half duplex */
184 	lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
185 			 true);
186 
187 	/* enable 802.1p priority */
188 	lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
189 
190 	if (!dev->info->internal_phy[port])
191 		lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
192 				 masks[P_MII_TX_FLOW_CTRL] |
193 				 masks[P_MII_RX_FLOW_CTRL],
194 				 true);
195 
196 	if (cpu_port)
197 		member = dsa_user_ports(ds);
198 	else
199 		member = BIT(dsa_upstream_port(ds, port));
200 
201 	dev->dev_ops->cfg_port_member(dev, port, member);
202 }
203 
lan937x_config_cpu_port(struct dsa_switch * ds)204 void lan937x_config_cpu_port(struct dsa_switch *ds)
205 {
206 	struct ksz_device *dev = ds->priv;
207 	struct dsa_port *dp;
208 
209 	dsa_switch_for_each_cpu_port(dp, ds) {
210 		if (dev->info->cpu_ports & (1 << dp->index)) {
211 			dev->cpu_port = dp->index;
212 
213 			/* enable cpu port */
214 			lan937x_port_setup(dev, dp->index, true);
215 		}
216 	}
217 
218 	dsa_switch_for_each_user_port(dp, ds) {
219 		ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
220 	}
221 }
222 
lan937x_change_mtu(struct ksz_device * dev,int port,int new_mtu)223 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
224 {
225 	struct dsa_switch *ds = dev->ds;
226 	int ret;
227 
228 	new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
229 
230 	if (dsa_is_cpu_port(ds, port))
231 		new_mtu += LAN937X_TAG_LEN;
232 
233 	if (new_mtu >= FR_MIN_SIZE)
234 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
235 				       PORT_JUMBO_PACKET, true);
236 	else
237 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
238 				       PORT_JUMBO_PACKET, false);
239 	if (ret < 0) {
240 		dev_err(ds->dev, "failed to enable jumbo\n");
241 		return ret;
242 	}
243 
244 	/* Write the frame size in PORT_MAX_FR_SIZE register */
245 	ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
246 
247 	return 0;
248 }
249 
lan937x_set_ageing_time(struct ksz_device * dev,unsigned int msecs)250 int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs)
251 {
252 	u32 secs = msecs / 1000;
253 	u32 value;
254 	int ret;
255 
256 	value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs);
257 
258 	ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value);
259 	if (ret < 0)
260 		return ret;
261 
262 	value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs);
263 
264 	return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value);
265 }
266 
lan937x_set_tune_adj(struct ksz_device * dev,int port,u16 reg,u8 val)267 static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
268 				 u16 reg, u8 val)
269 {
270 	u16 data16;
271 
272 	ksz_pread16(dev, port, reg, &data16);
273 
274 	/* Update tune Adjust */
275 	data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
276 	ksz_pwrite16(dev, port, reg, data16);
277 
278 	/* write DLL reset to take effect */
279 	data16 |= PORT_DLL_RESET;
280 	ksz_pwrite16(dev, port, reg, data16);
281 }
282 
lan937x_set_rgmii_tx_delay(struct ksz_device * dev,int port)283 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
284 {
285 	u8 val;
286 
287 	/* Apply different codes based on the ports as per characterization
288 	 * results
289 	 */
290 	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
291 		RGMII_2_TX_DELAY_2NS;
292 
293 	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
294 }
295 
lan937x_set_rgmii_rx_delay(struct ksz_device * dev,int port)296 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
297 {
298 	u8 val;
299 
300 	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
301 		RGMII_2_RX_DELAY_2NS;
302 
303 	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
304 }
305 
lan937x_phylink_get_caps(struct ksz_device * dev,int port,struct phylink_config * config)306 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
307 			      struct phylink_config *config)
308 {
309 	config->mac_capabilities = MAC_100FD;
310 
311 	if (dev->info->supports_rgmii[port]) {
312 		/* MII/RMII/RGMII ports */
313 		config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
314 					    MAC_100HD | MAC_10 | MAC_1000FD;
315 	}
316 }
317 
lan937x_setup_rgmii_delay(struct ksz_device * dev,int port)318 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
319 {
320 	struct ksz_port *p = &dev->ports[port];
321 
322 	if (p->rgmii_tx_val) {
323 		lan937x_set_rgmii_tx_delay(dev, port);
324 		dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
325 			 port);
326 	}
327 
328 	if (p->rgmii_rx_val) {
329 		lan937x_set_rgmii_rx_delay(dev, port);
330 		dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
331 			 port);
332 	}
333 }
334 
lan937x_switch_init(struct ksz_device * dev)335 int lan937x_switch_init(struct ksz_device *dev)
336 {
337 	dev->port_mask = (1 << dev->info->port_cnt) - 1;
338 
339 	return 0;
340 }
341 
lan937x_setup(struct dsa_switch * ds)342 int lan937x_setup(struct dsa_switch *ds)
343 {
344 	struct ksz_device *dev = ds->priv;
345 	int ret;
346 
347 	/* enable Indirect Access from SPI to the VPHY registers */
348 	ret = lan937x_enable_spi_indirect_access(dev);
349 	if (ret < 0) {
350 		dev_err(dev->dev, "failed to enable spi indirect access");
351 		return ret;
352 	}
353 
354 	/* The VLAN aware is a global setting. Mixed vlan
355 	 * filterings are not supported.
356 	 */
357 	ds->vlan_filtering_is_global = true;
358 
359 	/* Enable aggressive back off for half duplex & UNH mode */
360 	lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
361 		    (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF),
362 		    true);
363 
364 	/* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
365 	 * packets when 16 or more collisions occur
366 	 */
367 	lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
368 
369 	/* enable global MIB counter freeze function */
370 	lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
371 
372 	/* disable CLK125 & CLK25, 1: disable, 0: enable */
373 	lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
374 		    (SW_CLK125_ENB | SW_CLK25_ENB), true);
375 
376 	return 0;
377 }
378 
lan937x_teardown(struct dsa_switch * ds)379 void lan937x_teardown(struct dsa_switch *ds)
380 {
381 
382 }
383 
lan937x_switch_exit(struct ksz_device * dev)384 void lan937x_switch_exit(struct ksz_device *dev)
385 {
386 	lan937x_reset_switch(dev);
387 }
388 
389 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
390 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
391 MODULE_LICENSE("GPL");
392