1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * cobalt driver internal defines and structures
4 *
5 * Derived from cx18-driver.h
6 *
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
8 * All rights reserved.
9 */
10
11 #ifndef COBALT_DRIVER_H
12 #define COBALT_DRIVER_H
13
14 #include <linux/bitops.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/spinlock.h>
18 #include <linux/i2c.h>
19 #include <linux/list.h>
20 #include <linux/workqueue.h>
21 #include <linux/mutex.h>
22
23 #include <media/v4l2-common.h>
24 #include <media/v4l2-ioctl.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fh.h>
27 #include <media/videobuf2-v4l2.h>
28 #include <media/videobuf2-dma-sg.h>
29
30 #include "m00233_video_measure_memmap_package.h"
31 #include "m00235_fdma_packer_memmap_package.h"
32 #include "m00389_cvi_memmap_package.h"
33 #include "m00460_evcnt_memmap_package.h"
34 #include "m00473_freewheel_memmap_package.h"
35 #include "m00479_clk_loss_detector_memmap_package.h"
36 #include "m00514_syncgen_flow_evcnt_memmap_package.h"
37
38 /* System device ID */
39 #define PCI_DEVICE_ID_COBALT 0x2732
40
41 /* Number of cobalt device nodes. */
42 #define COBALT_NUM_INPUTS 4
43 #define COBALT_NUM_NODES 6
44
45 /* Number of cobalt device streams. */
46 #define COBALT_NUM_STREAMS 12
47
48 #define COBALT_HSMA_IN_NODE 4
49 #define COBALT_HSMA_OUT_NODE 5
50
51 /* Cobalt audio streams */
52 #define COBALT_AUDIO_IN_STREAM 6
53 #define COBALT_AUDIO_OUT_STREAM 11
54
55 /* DMA stuff */
56 #define DMA_CHANNELS_MAX 16
57
58 /* i2c stuff */
59 #define I2C_CLIENTS_MAX 16
60 #define COBALT_NUM_ADAPTERS 5
61
62 #define COBALT_CLK 50000000
63
64 /* System status register */
65 #define COBALT_SYSSTAT_DIP0_MSK BIT(0)
66 #define COBALT_SYSSTAT_DIP1_MSK BIT(1)
67 #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK BIT(2)
68 #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK BIT(3)
69 #define COBALT_SYSSTAT_VI0_5V_MSK BIT(4)
70 #define COBALT_SYSSTAT_VI0_INT1_MSK BIT(5)
71 #define COBALT_SYSSTAT_VI0_INT2_MSK BIT(6)
72 #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK BIT(7)
73 #define COBALT_SYSSTAT_VI1_5V_MSK BIT(8)
74 #define COBALT_SYSSTAT_VI1_INT1_MSK BIT(9)
75 #define COBALT_SYSSTAT_VI1_INT2_MSK BIT(10)
76 #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK BIT(11)
77 #define COBALT_SYSSTAT_VI2_5V_MSK BIT(12)
78 #define COBALT_SYSSTAT_VI2_INT1_MSK BIT(13)
79 #define COBALT_SYSSTAT_VI2_INT2_MSK BIT(14)
80 #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK BIT(15)
81 #define COBALT_SYSSTAT_VI3_5V_MSK BIT(16)
82 #define COBALT_SYSSTAT_VI3_INT1_MSK BIT(17)
83 #define COBALT_SYSSTAT_VI3_INT2_MSK BIT(18)
84 #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK BIT(19)
85 #define COBALT_SYSSTAT_VIHSMA_5V_MSK BIT(20)
86 #define COBALT_SYSSTAT_VIHSMA_INT1_MSK BIT(21)
87 #define COBALT_SYSSTAT_VIHSMA_INT2_MSK BIT(22)
88 #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23)
89 #define COBALT_SYSSTAT_VOHSMA_INT1_MSK BIT(24)
90 #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK BIT(25)
91 #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26)
92 #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK BIT(28)
93 #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29)
94 #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK BIT(30)
95 #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK BIT(31)
96
97 /* Cobalt memory map */
98 #define COBALT_I2C_0_BASE 0x0
99 #define COBALT_I2C_1_BASE 0x080
100 #define COBALT_I2C_2_BASE 0x100
101 #define COBALT_I2C_3_BASE 0x180
102 #define COBALT_I2C_HSMA_BASE 0x200
103
104 #define COBALT_SYS_CTRL_BASE 0x400
105 #define COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT 1
106 #define COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(n) (4 + 4 * (n))
107 #define COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(n) (5 + 4 * (n))
108 #define COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(n) (6 + 4 * (n))
109 #define COBALT_SYS_CTRL_AUDIO_IPP_RESETN_BIT(n) (7 + 4 * (n))
110 #define COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT 24
111 #define COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT 25
112 #define COBALT_SYS_CTRL_AUDIO_OPP_RESETN_BIT 27
113
114 #define COBALT_SYS_STAT_BASE 0x500
115 #define COBALT_SYS_STAT_MASK (COBALT_SYS_STAT_BASE + 0x08)
116 #define COBALT_SYS_STAT_EDGE (COBALT_SYS_STAT_BASE + 0x0c)
117
118 #define COBALT_HDL_INFO_BASE 0x4800
119 #define COBALT_HDL_INFO_SIZE 0x200
120
121 #define COBALT_VID_BASE 0x10000
122 #define COBALT_VID_SIZE 0x1000
123
124 #define COBALT_CVI(cobalt, c) \
125 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
126 #define COBALT_CVI_VMR(cobalt, c) \
127 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
128 #define COBALT_CVI_EVCNT(cobalt, c) \
129 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
130 #define COBALT_CVI_FREEWHEEL(cobalt, c) \
131 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
132 #define COBALT_CVI_CLK_LOSS(cobalt, c) \
133 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
134 #define COBALT_CVI_PACKER(cobalt, c) \
135 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
136
137 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
138
139 #define DMA_INTERRUPT_STATUS_REG 0x08
140
141 #define COBALT_HDL_SEARCH_STR "** HDL version info **"
142
143 /* Cobalt CPU bus interface */
144 #define COBALT_BUS_BAR1_BASE 0x600
145 #define COBALT_BUS_SRAM_BASE 0x0
146 #define COBALT_BUS_CPLD_BASE 0x00600000
147 #define COBALT_BUS_FLASH_BASE 0x08000000
148
149 /* FDMA to PCIe packing */
150 #define COBALT_BYTES_PER_PIXEL_YUYV 2
151 #define COBALT_BYTES_PER_PIXEL_RGB24 3
152 #define COBALT_BYTES_PER_PIXEL_RGB32 4
153
154 /* debugging */
155 extern int cobalt_debug;
156 extern int cobalt_ignore_err;
157
158 #define cobalt_err(fmt, arg...) v4l2_err(&cobalt->v4l2_dev, fmt, ## arg)
159 #define cobalt_warn(fmt, arg...) v4l2_warn(&cobalt->v4l2_dev, fmt, ## arg)
160 #define cobalt_info(fmt, arg...) v4l2_info(&cobalt->v4l2_dev, fmt, ## arg)
161 #define cobalt_dbg(level, fmt, arg...) \
162 v4l2_dbg(level, cobalt_debug, &cobalt->v4l2_dev, fmt, ## arg)
163
164 struct cobalt;
165 struct cobalt_i2c_regs;
166
167 /* Per I2C bus private algo callback data */
168 struct cobalt_i2c_data {
169 struct cobalt *cobalt;
170 struct cobalt_i2c_regs __iomem *regs;
171 };
172
173 struct pci_consistent_buffer {
174 void *virt;
175 dma_addr_t bus;
176 size_t bytes;
177 };
178
179 struct sg_dma_desc_info {
180 void *virt;
181 dma_addr_t bus;
182 unsigned size;
183 void *last_desc_virt;
184 struct device *dev;
185 };
186
187 #define COBALT_MAX_WIDTH 1920
188 #define COBALT_MAX_HEIGHT 1200
189 #define COBALT_MAX_BPP 3
190 #define COBALT_MAX_FRAMESZ \
191 (COBALT_MAX_WIDTH * COBALT_MAX_HEIGHT * COBALT_MAX_BPP)
192
193 #define NR_BUFS VIDEO_MAX_FRAME
194
195 #define COBALT_STREAM_FL_DMA_IRQ 0
196 #define COBALT_STREAM_FL_ADV_IRQ 1
197
198 struct cobalt_buffer {
199 struct vb2_v4l2_buffer vb;
200 struct list_head list;
201 };
202
203 static inline
to_cobalt_buffer(struct vb2_v4l2_buffer * vb2)204 struct cobalt_buffer *to_cobalt_buffer(struct vb2_v4l2_buffer *vb2)
205 {
206 return container_of(vb2, struct cobalt_buffer, vb);
207 }
208
209 struct cobalt_stream {
210 struct video_device vdev;
211 struct vb2_queue q;
212 struct list_head bufs;
213 struct i2c_adapter *i2c_adap;
214 struct v4l2_subdev *sd;
215 struct mutex lock;
216 spinlock_t irqlock;
217 struct v4l2_dv_timings timings;
218 u32 input;
219 u32 pad_source;
220 u32 width, height, bpp;
221 u32 stride;
222 u32 pixfmt;
223 u32 sequence;
224 u32 colorspace;
225 u32 xfer_func;
226 u32 ycbcr_enc;
227 u32 quantization;
228
229 u8 dma_channel;
230 int video_channel;
231 unsigned dma_fifo_mask;
232 unsigned adv_irq_mask;
233 struct sg_dma_desc_info dma_desc_info[NR_BUFS];
234 unsigned long flags;
235 bool unstable_frame;
236 bool enable_cvi;
237 bool enable_freewheel;
238 unsigned skip_first_frames;
239 bool is_output;
240 bool is_audio;
241 bool is_dummy;
242
243 struct cobalt *cobalt;
244 struct snd_cobalt_card *alsa;
245 };
246
247 struct snd_cobalt_card;
248
249 /* Struct to hold info about cobalt cards */
250 struct cobalt {
251 int instance;
252 struct pci_dev *pci_dev;
253 struct v4l2_device v4l2_dev;
254 /* serialize PCI access in cobalt_s_bit_sysctrl() */
255 struct mutex pci_lock;
256
257 void __iomem *bar0, *bar1;
258
259 u8 card_rev;
260 u16 device_id;
261
262 /* device nodes */
263 struct cobalt_stream streams[DMA_CHANNELS_MAX];
264 struct i2c_adapter i2c_adap[COBALT_NUM_ADAPTERS];
265 struct cobalt_i2c_data i2c_data[COBALT_NUM_ADAPTERS];
266 bool have_hsma_rx;
267 bool have_hsma_tx;
268
269 /* irq */
270 struct workqueue_struct *irq_work_queues;
271 struct work_struct irq_work_queue; /* work entry */
272 /* irq counters */
273 u32 irq_adv1;
274 u32 irq_adv2;
275 u32 irq_advout;
276 u32 irq_dma_tot;
277 u32 irq_dma[COBALT_NUM_STREAMS];
278 u32 irq_none;
279 u32 irq_full_fifo;
280
281 /* omnitek dma */
282 int dma_channels;
283 int first_fifo_channel;
284 bool pci_32_bit;
285
286 char hdl_info[COBALT_HDL_INFO_SIZE];
287
288 /* NOR flash */
289 struct mtd_info *mtd;
290 };
291
to_cobalt(struct v4l2_device * v4l2_dev)292 static inline struct cobalt *to_cobalt(struct v4l2_device *v4l2_dev)
293 {
294 return container_of(v4l2_dev, struct cobalt, v4l2_dev);
295 }
296
cobalt_write_bar0(struct cobalt * cobalt,u32 reg,u32 val)297 static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val)
298 {
299 iowrite32(val, cobalt->bar0 + reg);
300 }
301
cobalt_read_bar0(struct cobalt * cobalt,u32 reg)302 static inline u32 cobalt_read_bar0(struct cobalt *cobalt, u32 reg)
303 {
304 return ioread32(cobalt->bar0 + reg);
305 }
306
cobalt_write_bar1(struct cobalt * cobalt,u32 reg,u32 val)307 static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val)
308 {
309 iowrite32(val, cobalt->bar1 + reg);
310 }
311
cobalt_read_bar1(struct cobalt * cobalt,u32 reg)312 static inline u32 cobalt_read_bar1(struct cobalt *cobalt, u32 reg)
313 {
314 return ioread32(cobalt->bar1 + reg);
315 }
316
cobalt_g_sysctrl(struct cobalt * cobalt)317 static inline u32 cobalt_g_sysctrl(struct cobalt *cobalt)
318 {
319 return cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
320 }
321
cobalt_s_bit_sysctrl(struct cobalt * cobalt,int bit,int val)322 static inline void cobalt_s_bit_sysctrl(struct cobalt *cobalt,
323 int bit, int val)
324 {
325 u32 ctrl;
326
327 mutex_lock(&cobalt->pci_lock);
328 ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
329 cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE,
330 (ctrl & ~(1UL << bit)) | (val << bit));
331 mutex_unlock(&cobalt->pci_lock);
332 }
333
cobalt_g_sysstat(struct cobalt * cobalt)334 static inline u32 cobalt_g_sysstat(struct cobalt *cobalt)
335 {
336 return cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE);
337 }
338
339 #define ADRS_REG (bar1 + COBALT_BUS_BAR1_BASE + 0)
340 #define LOWER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 4)
341 #define UPPER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 6)
342
cobalt_bus_read32(void __iomem * bar1,u32 bus_adrs)343 static inline u32 cobalt_bus_read32(void __iomem *bar1, u32 bus_adrs)
344 {
345 iowrite32(bus_adrs, ADRS_REG);
346 return ioread32(LOWER_DATA);
347 }
348
cobalt_bus_write16(void __iomem * bar1,u32 bus_adrs,u16 data)349 static inline void cobalt_bus_write16(void __iomem *bar1,
350 u32 bus_adrs, u16 data)
351 {
352 iowrite32(bus_adrs, ADRS_REG);
353 if (bus_adrs & 2)
354 iowrite16(data, UPPER_DATA);
355 else
356 iowrite16(data, LOWER_DATA);
357 }
358
cobalt_bus_write32(void __iomem * bar1,u32 bus_adrs,u16 data)359 static inline void cobalt_bus_write32(void __iomem *bar1,
360 u32 bus_adrs, u16 data)
361 {
362 iowrite32(bus_adrs, ADRS_REG);
363 if (bus_adrs & 2)
364 iowrite32(data, UPPER_DATA);
365 else
366 iowrite32(data, LOWER_DATA);
367 }
368
369 /*==============Prototypes==================*/
370
371 void cobalt_pcie_status_show(struct cobalt *cobalt);
372
373 #endif
374