1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * serial_tegra.c
4 *
5 * High-speed serial driver for NVIDIA Tegra SoCs
6 *
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pagemap.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_reg.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <linux/termios.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36
37 #define TEGRA_UART_TYPE "TEGRA_UART"
38 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
39 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
40
41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
42 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
43 #define TEGRA_UART_IER_EORD 0x20
44 #define TEGRA_UART_MCR_RTS_EN 0x40
45 #define TEGRA_UART_MCR_CTS_EN 0x20
46 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
47 UART_LSR_PE | UART_LSR_FE)
48 #define TEGRA_UART_IRDA_CSR 0x08
49 #define TEGRA_UART_SIR_ENABLED 0x80
50
51 #define TEGRA_UART_TX_PIO 1
52 #define TEGRA_UART_TX_DMA 2
53 #define TEGRA_UART_MIN_DMA 16
54 #define TEGRA_UART_FIFO_SIZE 32
55
56 /*
57 * Tx fifo trigger level setting in tegra uart is in
58 * reverse way then conventional uart.
59 */
60 #define TEGRA_UART_TX_TRIG_16B 0x00
61 #define TEGRA_UART_TX_TRIG_8B 0x10
62 #define TEGRA_UART_TX_TRIG_4B 0x20
63 #define TEGRA_UART_TX_TRIG_1B 0x30
64
65 #define TEGRA_UART_MAXIMUM 8
66
67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68 #define TEGRA_UART_DEFAULT_BAUD 115200
69 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
70
71 /* Tx transfer mode */
72 #define TEGRA_TX_PIO 1
73 #define TEGRA_TX_DMA 2
74
75 #define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
76
77 /**
78 * struct tegra_uart_chip_data: SOC specific data.
79 *
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
82 * Tegra30 does not allow this.
83 * @support_clk_src_div: Clock source support the clock divider.
84 * @fifo_mode_enable_status: Is FIFO mode enabled?
85 * @uart_max_port: Maximum number of UART ports
86 * @max_dma_burst_bytes: Maximum size of DMA bursts
87 * @error_tolerance_low_range: Lowest number in the error tolerance range
88 * @error_tolerance_high_range: Highest number in the error tolerance range
89 */
90 struct tegra_uart_chip_data {
91 bool tx_fifo_full_status;
92 bool allow_txfifo_reset_fifo_mode;
93 bool support_clk_src_div;
94 bool fifo_mode_enable_status;
95 int uart_max_port;
96 int max_dma_burst_bytes;
97 int error_tolerance_low_range;
98 int error_tolerance_high_range;
99 };
100
101 struct tegra_baud_tolerance {
102 u32 lower_range_baud;
103 u32 upper_range_baud;
104 s32 tolerance;
105 };
106
107 struct tegra_uart_port {
108 struct uart_port uport;
109 const struct tegra_uart_chip_data *cdata;
110
111 struct clk *uart_clk;
112 struct reset_control *rst;
113 unsigned int current_baud;
114
115 /* Register shadow */
116 unsigned long fcr_shadow;
117 unsigned long mcr_shadow;
118 unsigned long lcr_shadow;
119 unsigned long ier_shadow;
120 bool rts_active;
121
122 int tx_in_progress;
123 unsigned int tx_bytes;
124
125 bool enable_modem_interrupt;
126
127 bool rx_timeout;
128 int rx_in_progress;
129 int symb_bit;
130
131 struct dma_chan *rx_dma_chan;
132 struct dma_chan *tx_dma_chan;
133 dma_addr_t rx_dma_buf_phys;
134 dma_addr_t tx_dma_buf_phys;
135 unsigned char *rx_dma_buf_virt;
136 unsigned char *tx_dma_buf_virt;
137 struct dma_async_tx_descriptor *tx_dma_desc;
138 struct dma_async_tx_descriptor *rx_dma_desc;
139 dma_cookie_t tx_cookie;
140 dma_cookie_t rx_cookie;
141 unsigned int tx_bytes_requested;
142 unsigned int rx_bytes_requested;
143 struct tegra_baud_tolerance *baud_tolerance;
144 int n_adjustable_baud_rates;
145 int required_rate;
146 int configured_rate;
147 bool use_rx_pio;
148 bool use_tx_pio;
149 bool rx_dma_active;
150 };
151
152 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
153 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
154 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
155 bool dma_to_memory);
156
tegra_uart_read(struct tegra_uart_port * tup,unsigned long reg)157 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
158 unsigned long reg)
159 {
160 return readl(tup->uport.membase + (reg << tup->uport.regshift));
161 }
162
tegra_uart_write(struct tegra_uart_port * tup,unsigned val,unsigned long reg)163 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
164 unsigned long reg)
165 {
166 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
167 }
168
to_tegra_uport(struct uart_port * u)169 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
170 {
171 return container_of(u, struct tegra_uart_port, uport);
172 }
173
tegra_uart_get_mctrl(struct uart_port * u)174 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
175 {
176 struct tegra_uart_port *tup = to_tegra_uport(u);
177
178 /*
179 * RI - Ring detector is active
180 * CD/DCD/CAR - Carrier detect is always active. For some reason
181 * linux has different names for carrier detect.
182 * DSR - Data Set ready is active as the hardware doesn't support it.
183 * Don't know if the linux support this yet?
184 * CTS - Clear to send. Always set to active, as the hardware handles
185 * CTS automatically.
186 */
187 if (tup->enable_modem_interrupt)
188 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
189 return TIOCM_CTS;
190 }
191
set_rts(struct tegra_uart_port * tup,bool active)192 static void set_rts(struct tegra_uart_port *tup, bool active)
193 {
194 unsigned long mcr;
195
196 mcr = tup->mcr_shadow;
197 if (active)
198 mcr |= TEGRA_UART_MCR_RTS_EN;
199 else
200 mcr &= ~TEGRA_UART_MCR_RTS_EN;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
204 }
205 }
206
set_dtr(struct tegra_uart_port * tup,bool active)207 static void set_dtr(struct tegra_uart_port *tup, bool active)
208 {
209 unsigned long mcr;
210
211 mcr = tup->mcr_shadow;
212 if (active)
213 mcr |= UART_MCR_DTR;
214 else
215 mcr &= ~UART_MCR_DTR;
216 if (mcr != tup->mcr_shadow) {
217 tegra_uart_write(tup, mcr, UART_MCR);
218 tup->mcr_shadow = mcr;
219 }
220 }
221
set_loopbk(struct tegra_uart_port * tup,bool active)222 static void set_loopbk(struct tegra_uart_port *tup, bool active)
223 {
224 unsigned long mcr = tup->mcr_shadow;
225
226 if (active)
227 mcr |= UART_MCR_LOOP;
228 else
229 mcr &= ~UART_MCR_LOOP;
230
231 if (mcr != tup->mcr_shadow) {
232 tegra_uart_write(tup, mcr, UART_MCR);
233 tup->mcr_shadow = mcr;
234 }
235 }
236
tegra_uart_set_mctrl(struct uart_port * u,unsigned int mctrl)237 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
238 {
239 struct tegra_uart_port *tup = to_tegra_uport(u);
240 int enable;
241
242 tup->rts_active = !!(mctrl & TIOCM_RTS);
243 set_rts(tup, tup->rts_active);
244
245 enable = !!(mctrl & TIOCM_DTR);
246 set_dtr(tup, enable);
247
248 enable = !!(mctrl & TIOCM_LOOP);
249 set_loopbk(tup, enable);
250 }
251
tegra_uart_break_ctl(struct uart_port * u,int break_ctl)252 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
253 {
254 struct tegra_uart_port *tup = to_tegra_uport(u);
255 unsigned long lcr;
256
257 lcr = tup->lcr_shadow;
258 if (break_ctl)
259 lcr |= UART_LCR_SBC;
260 else
261 lcr &= ~UART_LCR_SBC;
262 tegra_uart_write(tup, lcr, UART_LCR);
263 tup->lcr_shadow = lcr;
264 }
265
266 /**
267 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
268 *
269 * @tup: Tegra serial port data structure.
270 * @cycles: Number of clock periods to wait.
271 *
272 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
273 * clock speed is 16X the current baud rate.
274 */
tegra_uart_wait_cycle_time(struct tegra_uart_port * tup,unsigned int cycles)275 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
276 unsigned int cycles)
277 {
278 if (tup->current_baud)
279 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
280 }
281
282 /* Wait for a symbol-time. */
tegra_uart_wait_sym_time(struct tegra_uart_port * tup,unsigned int syms)283 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
284 unsigned int syms)
285 {
286 if (tup->current_baud)
287 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
288 tup->current_baud));
289 }
290
tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port * tup)291 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
292 {
293 unsigned long iir;
294 unsigned int tmout = 100;
295
296 do {
297 iir = tegra_uart_read(tup, UART_IIR);
298 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
299 return 0;
300 udelay(1);
301 } while (--tmout);
302
303 return -ETIMEDOUT;
304 }
305
tegra_uart_fifo_reset(struct tegra_uart_port * tup,u8 fcr_bits)306 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
307 {
308 unsigned long fcr = tup->fcr_shadow;
309 unsigned int lsr, tmout = 10000;
310
311 if (tup->rts_active)
312 set_rts(tup, false);
313
314 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
315 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
316 tegra_uart_write(tup, fcr, UART_FCR);
317 } else {
318 fcr &= ~UART_FCR_ENABLE_FIFO;
319 tegra_uart_write(tup, fcr, UART_FCR);
320 udelay(60);
321 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
322 tegra_uart_write(tup, fcr, UART_FCR);
323 fcr |= UART_FCR_ENABLE_FIFO;
324 tegra_uart_write(tup, fcr, UART_FCR);
325 if (tup->cdata->fifo_mode_enable_status)
326 tegra_uart_wait_fifo_mode_enabled(tup);
327 }
328
329 /* Dummy read to ensure the write is posted */
330 tegra_uart_read(tup, UART_SCR);
331
332 /*
333 * For all tegra devices (up to t210), there is a hardware issue that
334 * requires software to wait for 32 UART clock periods for the flush
335 * to propagate, otherwise data could be lost.
336 */
337 tegra_uart_wait_cycle_time(tup, 32);
338
339 do {
340 lsr = tegra_uart_read(tup, UART_LSR);
341 if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
342 break;
343 udelay(1);
344 } while (--tmout);
345
346 if (tup->rts_active)
347 set_rts(tup, true);
348 }
349
tegra_get_tolerance_rate(struct tegra_uart_port * tup,unsigned int baud,long rate)350 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
351 unsigned int baud, long rate)
352 {
353 int i;
354
355 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
356 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
357 baud <= tup->baud_tolerance[i].upper_range_baud)
358 return (rate + (rate *
359 tup->baud_tolerance[i].tolerance) / 10000);
360 }
361
362 return rate;
363 }
364
tegra_check_rate_in_range(struct tegra_uart_port * tup)365 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
366 {
367 long diff;
368
369 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
370 / tup->required_rate;
371 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
372 diff > (tup->cdata->error_tolerance_high_range * 100)) {
373 dev_err(tup->uport.dev,
374 "configured baud rate is out of range by %ld", diff);
375 return -EIO;
376 }
377
378 return 0;
379 }
380
tegra_set_baudrate(struct tegra_uart_port * tup,unsigned int baud)381 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
382 {
383 unsigned long rate;
384 unsigned int divisor;
385 unsigned long lcr;
386 unsigned long flags;
387 int ret;
388
389 if (tup->current_baud == baud)
390 return 0;
391
392 if (tup->cdata->support_clk_src_div) {
393 rate = baud * 16;
394 tup->required_rate = rate;
395
396 if (tup->n_adjustable_baud_rates)
397 rate = tegra_get_tolerance_rate(tup, baud, rate);
398
399 ret = clk_set_rate(tup->uart_clk, rate);
400 if (ret < 0) {
401 dev_err(tup->uport.dev,
402 "clk_set_rate() failed for rate %lu\n", rate);
403 return ret;
404 }
405 tup->configured_rate = clk_get_rate(tup->uart_clk);
406 divisor = 1;
407 ret = tegra_check_rate_in_range(tup);
408 if (ret < 0)
409 return ret;
410 } else {
411 rate = clk_get_rate(tup->uart_clk);
412 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
413 }
414
415 spin_lock_irqsave(&tup->uport.lock, flags);
416 lcr = tup->lcr_shadow;
417 lcr |= UART_LCR_DLAB;
418 tegra_uart_write(tup, lcr, UART_LCR);
419
420 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
421 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
422
423 lcr &= ~UART_LCR_DLAB;
424 tegra_uart_write(tup, lcr, UART_LCR);
425
426 /* Dummy read to ensure the write is posted */
427 tegra_uart_read(tup, UART_SCR);
428 spin_unlock_irqrestore(&tup->uport.lock, flags);
429
430 tup->current_baud = baud;
431
432 /* wait two character intervals at new rate */
433 tegra_uart_wait_sym_time(tup, 2);
434 return 0;
435 }
436
tegra_uart_decode_rx_error(struct tegra_uart_port * tup,unsigned long lsr)437 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
438 unsigned long lsr)
439 {
440 char flag = TTY_NORMAL;
441
442 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
443 if (lsr & UART_LSR_OE) {
444 /* Overrun error */
445 flag = TTY_OVERRUN;
446 tup->uport.icount.overrun++;
447 dev_dbg(tup->uport.dev, "Got overrun errors\n");
448 } else if (lsr & UART_LSR_PE) {
449 /* Parity error */
450 flag = TTY_PARITY;
451 tup->uport.icount.parity++;
452 dev_dbg(tup->uport.dev, "Got Parity errors\n");
453 } else if (lsr & UART_LSR_FE) {
454 flag = TTY_FRAME;
455 tup->uport.icount.frame++;
456 dev_dbg(tup->uport.dev, "Got frame errors\n");
457 } else if (lsr & UART_LSR_BI) {
458 /*
459 * Break error
460 * If FIFO read error without any data, reset Rx FIFO
461 */
462 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
463 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
464 if (tup->uport.ignore_status_mask & UART_LSR_BI)
465 return TTY_BREAK;
466 flag = TTY_BREAK;
467 tup->uport.icount.brk++;
468 dev_dbg(tup->uport.dev, "Got Break\n");
469 }
470 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
471 }
472
473 return flag;
474 }
475
tegra_uart_request_port(struct uart_port * u)476 static int tegra_uart_request_port(struct uart_port *u)
477 {
478 return 0;
479 }
480
tegra_uart_release_port(struct uart_port * u)481 static void tegra_uart_release_port(struct uart_port *u)
482 {
483 /* Nothing to do here */
484 }
485
tegra_uart_fill_tx_fifo(struct tegra_uart_port * tup,int max_bytes)486 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
487 {
488 struct circ_buf *xmit = &tup->uport.state->xmit;
489 int i;
490
491 for (i = 0; i < max_bytes; i++) {
492 BUG_ON(uart_circ_empty(xmit));
493 if (tup->cdata->tx_fifo_full_status) {
494 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
495 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
496 break;
497 }
498 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
499 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
500 tup->uport.icount.tx++;
501 }
502 }
503
tegra_uart_start_pio_tx(struct tegra_uart_port * tup,unsigned int bytes)504 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
505 unsigned int bytes)
506 {
507 if (bytes > TEGRA_UART_MIN_DMA)
508 bytes = TEGRA_UART_MIN_DMA;
509
510 tup->tx_in_progress = TEGRA_UART_TX_PIO;
511 tup->tx_bytes = bytes;
512 tup->ier_shadow |= UART_IER_THRI;
513 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
514 }
515
tegra_uart_tx_dma_complete(void * args)516 static void tegra_uart_tx_dma_complete(void *args)
517 {
518 struct tegra_uart_port *tup = args;
519 struct circ_buf *xmit = &tup->uport.state->xmit;
520 struct dma_tx_state state;
521 unsigned long flags;
522 unsigned int count;
523
524 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
525 count = tup->tx_bytes_requested - state.residue;
526 async_tx_ack(tup->tx_dma_desc);
527 spin_lock_irqsave(&tup->uport.lock, flags);
528 uart_xmit_advance(&tup->uport, count);
529 tup->tx_in_progress = 0;
530 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
531 uart_write_wakeup(&tup->uport);
532 tegra_uart_start_next_tx(tup);
533 spin_unlock_irqrestore(&tup->uport.lock, flags);
534 }
535
tegra_uart_start_tx_dma(struct tegra_uart_port * tup,unsigned long count)536 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
537 unsigned long count)
538 {
539 struct circ_buf *xmit = &tup->uport.state->xmit;
540 dma_addr_t tx_phys_addr;
541
542 tup->tx_bytes = count & ~(0xF);
543 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
544
545 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
546 tup->tx_bytes, DMA_TO_DEVICE);
547
548 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
549 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
550 DMA_PREP_INTERRUPT);
551 if (!tup->tx_dma_desc) {
552 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
553 return -EIO;
554 }
555
556 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
557 tup->tx_dma_desc->callback_param = tup;
558 tup->tx_in_progress = TEGRA_UART_TX_DMA;
559 tup->tx_bytes_requested = tup->tx_bytes;
560 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
561 dma_async_issue_pending(tup->tx_dma_chan);
562 return 0;
563 }
564
tegra_uart_start_next_tx(struct tegra_uart_port * tup)565 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
566 {
567 unsigned long tail;
568 unsigned long count;
569 struct circ_buf *xmit = &tup->uport.state->xmit;
570
571 if (!tup->current_baud)
572 return;
573
574 tail = (unsigned long)&xmit->buf[xmit->tail];
575 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
576 if (!count)
577 return;
578
579 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
580 tegra_uart_start_pio_tx(tup, count);
581 else if (BYTES_TO_ALIGN(tail) > 0)
582 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
583 else
584 tegra_uart_start_tx_dma(tup, count);
585 }
586
587 /* Called by serial core driver with u->lock taken. */
tegra_uart_start_tx(struct uart_port * u)588 static void tegra_uart_start_tx(struct uart_port *u)
589 {
590 struct tegra_uart_port *tup = to_tegra_uport(u);
591 struct circ_buf *xmit = &u->state->xmit;
592
593 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
594 tegra_uart_start_next_tx(tup);
595 }
596
tegra_uart_tx_empty(struct uart_port * u)597 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
598 {
599 struct tegra_uart_port *tup = to_tegra_uport(u);
600 unsigned int ret = 0;
601 unsigned long flags;
602
603 spin_lock_irqsave(&u->lock, flags);
604 if (!tup->tx_in_progress) {
605 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
606 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
607 ret = TIOCSER_TEMT;
608 }
609 spin_unlock_irqrestore(&u->lock, flags);
610 return ret;
611 }
612
tegra_uart_stop_tx(struct uart_port * u)613 static void tegra_uart_stop_tx(struct uart_port *u)
614 {
615 struct tegra_uart_port *tup = to_tegra_uport(u);
616 struct dma_tx_state state;
617 unsigned int count;
618
619 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
620 return;
621
622 dmaengine_pause(tup->tx_dma_chan);
623 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
624 dmaengine_terminate_all(tup->tx_dma_chan);
625 count = tup->tx_bytes_requested - state.residue;
626 async_tx_ack(tup->tx_dma_desc);
627 uart_xmit_advance(&tup->uport, count);
628 tup->tx_in_progress = 0;
629 }
630
tegra_uart_handle_tx_pio(struct tegra_uart_port * tup)631 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
632 {
633 struct circ_buf *xmit = &tup->uport.state->xmit;
634
635 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
636 tup->tx_in_progress = 0;
637 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638 uart_write_wakeup(&tup->uport);
639 tegra_uart_start_next_tx(tup);
640 }
641
tegra_uart_handle_rx_pio(struct tegra_uart_port * tup,struct tty_port * port)642 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
643 struct tty_port *port)
644 {
645 do {
646 char flag = TTY_NORMAL;
647 unsigned long lsr = 0;
648 unsigned char ch;
649
650 lsr = tegra_uart_read(tup, UART_LSR);
651 if (!(lsr & UART_LSR_DR))
652 break;
653
654 flag = tegra_uart_decode_rx_error(tup, lsr);
655 if (flag != TTY_NORMAL)
656 continue;
657
658 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
659 tup->uport.icount.rx++;
660
661 if (uart_handle_sysrq_char(&tup->uport, ch))
662 continue;
663
664 if (tup->uport.ignore_status_mask & UART_LSR_DR)
665 continue;
666
667 tty_insert_flip_char(port, ch, flag);
668 } while (1);
669 }
670
tegra_uart_copy_rx_to_tty(struct tegra_uart_port * tup,struct tty_port * port,unsigned int count)671 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
672 struct tty_port *port,
673 unsigned int count)
674 {
675 int copied;
676
677 /* If count is zero, then there is no data to be copied */
678 if (!count)
679 return;
680
681 tup->uport.icount.rx += count;
682
683 if (tup->uport.ignore_status_mask & UART_LSR_DR)
684 return;
685
686 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
687 count, DMA_FROM_DEVICE);
688 copied = tty_insert_flip_string(port,
689 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
690 if (copied != count) {
691 WARN_ON(1);
692 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
693 }
694 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
695 count, DMA_TO_DEVICE);
696 }
697
do_handle_rx_pio(struct tegra_uart_port * tup)698 static void do_handle_rx_pio(struct tegra_uart_port *tup)
699 {
700 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
701 struct tty_port *port = &tup->uport.state->port;
702
703 tegra_uart_handle_rx_pio(tup, port);
704 if (tty) {
705 tty_flip_buffer_push(port);
706 tty_kref_put(tty);
707 }
708 }
709
tegra_uart_rx_buffer_push(struct tegra_uart_port * tup,unsigned int residue)710 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
711 unsigned int residue)
712 {
713 struct tty_port *port = &tup->uport.state->port;
714 unsigned int count;
715
716 async_tx_ack(tup->rx_dma_desc);
717 count = tup->rx_bytes_requested - residue;
718
719 /* If we are here, DMA is stopped */
720 tegra_uart_copy_rx_to_tty(tup, port, count);
721
722 do_handle_rx_pio(tup);
723 }
724
tegra_uart_rx_dma_complete(void * args)725 static void tegra_uart_rx_dma_complete(void *args)
726 {
727 struct tegra_uart_port *tup = args;
728 struct uart_port *u = &tup->uport;
729 unsigned long flags;
730 struct dma_tx_state state;
731 enum dma_status status;
732
733 spin_lock_irqsave(&u->lock, flags);
734
735 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
736
737 if (status == DMA_IN_PROGRESS) {
738 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
739 goto done;
740 }
741
742 /* Deactivate flow control to stop sender */
743 if (tup->rts_active)
744 set_rts(tup, false);
745
746 tup->rx_dma_active = false;
747 tegra_uart_rx_buffer_push(tup, 0);
748 tegra_uart_start_rx_dma(tup);
749
750 /* Activate flow control to start transfer */
751 if (tup->rts_active)
752 set_rts(tup, true);
753
754 done:
755 spin_unlock_irqrestore(&u->lock, flags);
756 }
757
tegra_uart_terminate_rx_dma(struct tegra_uart_port * tup)758 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
759 {
760 struct dma_tx_state state;
761
762 if (!tup->rx_dma_active) {
763 do_handle_rx_pio(tup);
764 return;
765 }
766
767 dmaengine_pause(tup->rx_dma_chan);
768 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
769 dmaengine_terminate_all(tup->rx_dma_chan);
770
771 tegra_uart_rx_buffer_push(tup, state.residue);
772 tup->rx_dma_active = false;
773 }
774
tegra_uart_handle_rx_dma(struct tegra_uart_port * tup)775 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
776 {
777 /* Deactivate flow control to stop sender */
778 if (tup->rts_active)
779 set_rts(tup, false);
780
781 tegra_uart_terminate_rx_dma(tup);
782
783 if (tup->rts_active)
784 set_rts(tup, true);
785 }
786
tegra_uart_start_rx_dma(struct tegra_uart_port * tup)787 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
788 {
789 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
790
791 if (tup->rx_dma_active)
792 return 0;
793
794 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
795 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
796 DMA_PREP_INTERRUPT);
797 if (!tup->rx_dma_desc) {
798 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
799 return -EIO;
800 }
801
802 tup->rx_dma_active = true;
803 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
804 tup->rx_dma_desc->callback_param = tup;
805 tup->rx_bytes_requested = count;
806 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
807 dma_async_issue_pending(tup->rx_dma_chan);
808 return 0;
809 }
810
tegra_uart_handle_modem_signal_change(struct uart_port * u)811 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
812 {
813 struct tegra_uart_port *tup = to_tegra_uport(u);
814 unsigned long msr;
815
816 msr = tegra_uart_read(tup, UART_MSR);
817 if (!(msr & UART_MSR_ANY_DELTA))
818 return;
819
820 if (msr & UART_MSR_TERI)
821 tup->uport.icount.rng++;
822 if (msr & UART_MSR_DDSR)
823 tup->uport.icount.dsr++;
824 /* We may only get DDCD when HW init and reset */
825 if (msr & UART_MSR_DDCD)
826 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
827 /* Will start/stop_tx accordingly */
828 if (msr & UART_MSR_DCTS)
829 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
830 }
831
tegra_uart_isr(int irq,void * data)832 static irqreturn_t tegra_uart_isr(int irq, void *data)
833 {
834 struct tegra_uart_port *tup = data;
835 struct uart_port *u = &tup->uport;
836 unsigned long iir;
837 unsigned long ier;
838 bool is_rx_start = false;
839 bool is_rx_int = false;
840 unsigned long flags;
841
842 spin_lock_irqsave(&u->lock, flags);
843 while (1) {
844 iir = tegra_uart_read(tup, UART_IIR);
845 if (iir & UART_IIR_NO_INT) {
846 if (!tup->use_rx_pio && is_rx_int) {
847 tegra_uart_handle_rx_dma(tup);
848 if (tup->rx_in_progress) {
849 ier = tup->ier_shadow;
850 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
851 TEGRA_UART_IER_EORD | UART_IER_RDI);
852 tup->ier_shadow = ier;
853 tegra_uart_write(tup, ier, UART_IER);
854 }
855 } else if (is_rx_start) {
856 tegra_uart_start_rx_dma(tup);
857 }
858 spin_unlock_irqrestore(&u->lock, flags);
859 return IRQ_HANDLED;
860 }
861
862 switch ((iir >> 1) & 0x7) {
863 case 0: /* Modem signal change interrupt */
864 tegra_uart_handle_modem_signal_change(u);
865 break;
866
867 case 1: /* Transmit interrupt only triggered when using PIO */
868 tup->ier_shadow &= ~UART_IER_THRI;
869 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
870 tegra_uart_handle_tx_pio(tup);
871 break;
872
873 case 4: /* End of data */
874 case 6: /* Rx timeout */
875 if (!tup->use_rx_pio) {
876 is_rx_int = tup->rx_in_progress;
877 /* Disable Rx interrupts */
878 ier = tup->ier_shadow;
879 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
880 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
881 tup->ier_shadow = ier;
882 tegra_uart_write(tup, ier, UART_IER);
883 break;
884 }
885 fallthrough;
886 case 2: /* Receive */
887 if (!tup->use_rx_pio) {
888 is_rx_start = tup->rx_in_progress;
889 tup->ier_shadow &= ~UART_IER_RDI;
890 tegra_uart_write(tup, tup->ier_shadow,
891 UART_IER);
892 } else {
893 do_handle_rx_pio(tup);
894 }
895 break;
896
897 case 3: /* Receive error */
898 tegra_uart_decode_rx_error(tup,
899 tegra_uart_read(tup, UART_LSR));
900 break;
901
902 case 5: /* break nothing to handle */
903 case 7: /* break nothing to handle */
904 break;
905 }
906 }
907 }
908
tegra_uart_stop_rx(struct uart_port * u)909 static void tegra_uart_stop_rx(struct uart_port *u)
910 {
911 struct tegra_uart_port *tup = to_tegra_uport(u);
912 struct tty_port *port = &tup->uport.state->port;
913 unsigned long ier;
914
915 if (tup->rts_active)
916 set_rts(tup, false);
917
918 if (!tup->rx_in_progress)
919 return;
920
921 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
922
923 ier = tup->ier_shadow;
924 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
925 TEGRA_UART_IER_EORD);
926 tup->ier_shadow = ier;
927 tegra_uart_write(tup, ier, UART_IER);
928 tup->rx_in_progress = 0;
929
930 if (!tup->use_rx_pio)
931 tegra_uart_terminate_rx_dma(tup);
932 else
933 tegra_uart_handle_rx_pio(tup, port);
934 }
935
tegra_uart_hw_deinit(struct tegra_uart_port * tup)936 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
937 {
938 unsigned long flags;
939 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
940 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
941 unsigned long wait_time;
942 unsigned long lsr;
943 unsigned long msr;
944 unsigned long mcr;
945
946 /* Disable interrupts */
947 tegra_uart_write(tup, 0, UART_IER);
948
949 lsr = tegra_uart_read(tup, UART_LSR);
950 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
951 msr = tegra_uart_read(tup, UART_MSR);
952 mcr = tegra_uart_read(tup, UART_MCR);
953 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
954 dev_err(tup->uport.dev,
955 "Tx Fifo not empty, CTS disabled, waiting\n");
956
957 /* Wait for Tx fifo to be empty */
958 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
959 wait_time = min(fifo_empty_time, 100lu);
960 udelay(wait_time);
961 fifo_empty_time -= wait_time;
962 if (!fifo_empty_time) {
963 msr = tegra_uart_read(tup, UART_MSR);
964 mcr = tegra_uart_read(tup, UART_MCR);
965 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
966 (msr & UART_MSR_CTS))
967 dev_err(tup->uport.dev,
968 "Slave not ready\n");
969 break;
970 }
971 lsr = tegra_uart_read(tup, UART_LSR);
972 }
973 }
974
975 spin_lock_irqsave(&tup->uport.lock, flags);
976 /* Reset the Rx and Tx FIFOs */
977 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
978 tup->current_baud = 0;
979 spin_unlock_irqrestore(&tup->uport.lock, flags);
980
981 tup->rx_in_progress = 0;
982 tup->tx_in_progress = 0;
983
984 if (!tup->use_rx_pio)
985 tegra_uart_dma_channel_free(tup, true);
986 if (!tup->use_tx_pio)
987 tegra_uart_dma_channel_free(tup, false);
988
989 clk_disable_unprepare(tup->uart_clk);
990 }
991
tegra_uart_hw_init(struct tegra_uart_port * tup)992 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
993 {
994 int ret;
995
996 tup->fcr_shadow = 0;
997 tup->mcr_shadow = 0;
998 tup->lcr_shadow = 0;
999 tup->ier_shadow = 0;
1000 tup->current_baud = 0;
1001
1002 ret = clk_prepare_enable(tup->uart_clk);
1003 if (ret) {
1004 dev_err(tup->uport.dev, "could not enable clk\n");
1005 return ret;
1006 }
1007
1008 /* Reset the UART controller to clear all previous status.*/
1009 reset_control_assert(tup->rst);
1010 udelay(10);
1011 reset_control_deassert(tup->rst);
1012
1013 tup->rx_in_progress = 0;
1014 tup->tx_in_progress = 0;
1015
1016 /*
1017 * Set the trigger level
1018 *
1019 * For PIO mode:
1020 *
1021 * For receive, this will interrupt the CPU after that many number of
1022 * bytes are received, for the remaining bytes the receive timeout
1023 * interrupt is received. Rx high watermark is set to 4.
1024 *
1025 * For transmit, if the trasnmit interrupt is enabled, this will
1026 * interrupt the CPU when the number of entries in the FIFO reaches the
1027 * low watermark. Tx low watermark is set to 16 bytes.
1028 *
1029 * For DMA mode:
1030 *
1031 * Set the Tx trigger to 16. This should match the DMA burst size that
1032 * programmed in the DMA registers.
1033 */
1034 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1035
1036 if (tup->use_rx_pio) {
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1038 } else {
1039 if (tup->cdata->max_dma_burst_bytes == 8)
1040 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1041 else
1042 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1043 }
1044
1045 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1046 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1047
1048 /* Dummy read to ensure the write is posted */
1049 tegra_uart_read(tup, UART_SCR);
1050
1051 if (tup->cdata->fifo_mode_enable_status) {
1052 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1053 if (ret < 0) {
1054 clk_disable_unprepare(tup->uart_clk);
1055 dev_err(tup->uport.dev,
1056 "Failed to enable FIFO mode: %d\n", ret);
1057 return ret;
1058 }
1059 } else {
1060 /*
1061 * For all tegra devices (up to t210), there is a hardware
1062 * issue that requires software to wait for 3 UART clock
1063 * periods after enabling the TX fifo, otherwise data could
1064 * be lost.
1065 */
1066 tegra_uart_wait_cycle_time(tup, 3);
1067 }
1068
1069 /*
1070 * Initialize the UART with default configuration
1071 * (115200, N, 8, 1) so that the receive DMA buffer may be
1072 * enqueued
1073 */
1074 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1075 if (ret < 0) {
1076 clk_disable_unprepare(tup->uart_clk);
1077 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1078 return ret;
1079 }
1080 if (!tup->use_rx_pio) {
1081 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1082 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1083 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1084 } else {
1085 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1086 }
1087 tup->rx_in_progress = 1;
1088
1089 /*
1090 * Enable IE_RXS for the receive status interrupts like line errors.
1091 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1092 *
1093 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1094 * the DATA is sitting in the FIFO and couldn't be transferred to the
1095 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1096 * triggered when there is a pause of the incomming data stream for 4
1097 * characters long.
1098 *
1099 * For pauses in the data which is not aligned to 4 bytes, we get
1100 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1101 * then the EORD.
1102 */
1103 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1104
1105 /*
1106 * If using DMA mode, enable EORD interrupt to notify about RX
1107 * completion.
1108 */
1109 if (!tup->use_rx_pio)
1110 tup->ier_shadow |= TEGRA_UART_IER_EORD;
1111
1112 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1113 return 0;
1114 }
1115
tegra_uart_dma_channel_free(struct tegra_uart_port * tup,bool dma_to_memory)1116 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1117 bool dma_to_memory)
1118 {
1119 if (dma_to_memory) {
1120 dmaengine_terminate_all(tup->rx_dma_chan);
1121 dma_release_channel(tup->rx_dma_chan);
1122 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1123 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1124 tup->rx_dma_chan = NULL;
1125 tup->rx_dma_buf_phys = 0;
1126 tup->rx_dma_buf_virt = NULL;
1127 } else {
1128 dmaengine_terminate_all(tup->tx_dma_chan);
1129 dma_release_channel(tup->tx_dma_chan);
1130 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1131 UART_XMIT_SIZE, DMA_TO_DEVICE);
1132 tup->tx_dma_chan = NULL;
1133 tup->tx_dma_buf_phys = 0;
1134 tup->tx_dma_buf_virt = NULL;
1135 }
1136 }
1137
tegra_uart_dma_channel_allocate(struct tegra_uart_port * tup,bool dma_to_memory)1138 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1139 bool dma_to_memory)
1140 {
1141 struct dma_chan *dma_chan;
1142 unsigned char *dma_buf;
1143 dma_addr_t dma_phys;
1144 int ret;
1145 struct dma_slave_config dma_sconfig;
1146
1147 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1148 if (IS_ERR(dma_chan)) {
1149 ret = PTR_ERR(dma_chan);
1150 dev_err(tup->uport.dev,
1151 "DMA channel alloc failed: %d\n", ret);
1152 return ret;
1153 }
1154
1155 if (dma_to_memory) {
1156 dma_buf = dma_alloc_coherent(tup->uport.dev,
1157 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1158 &dma_phys, GFP_KERNEL);
1159 if (!dma_buf) {
1160 dev_err(tup->uport.dev,
1161 "Not able to allocate the dma buffer\n");
1162 dma_release_channel(dma_chan);
1163 return -ENOMEM;
1164 }
1165 dma_sync_single_for_device(tup->uport.dev, dma_phys,
1166 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1167 DMA_TO_DEVICE);
1168 dma_sconfig.src_addr = tup->uport.mapbase;
1169 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1170 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1171 tup->rx_dma_chan = dma_chan;
1172 tup->rx_dma_buf_virt = dma_buf;
1173 tup->rx_dma_buf_phys = dma_phys;
1174 } else {
1175 dma_phys = dma_map_single(tup->uport.dev,
1176 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1177 DMA_TO_DEVICE);
1178 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1179 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1180 dma_release_channel(dma_chan);
1181 return -ENOMEM;
1182 }
1183 dma_buf = tup->uport.state->xmit.buf;
1184 dma_sconfig.dst_addr = tup->uport.mapbase;
1185 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1186 dma_sconfig.dst_maxburst = 16;
1187 tup->tx_dma_chan = dma_chan;
1188 tup->tx_dma_buf_virt = dma_buf;
1189 tup->tx_dma_buf_phys = dma_phys;
1190 }
1191
1192 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1193 if (ret < 0) {
1194 dev_err(tup->uport.dev,
1195 "Dma slave config failed, err = %d\n", ret);
1196 tegra_uart_dma_channel_free(tup, dma_to_memory);
1197 return ret;
1198 }
1199
1200 return 0;
1201 }
1202
tegra_uart_startup(struct uart_port * u)1203 static int tegra_uart_startup(struct uart_port *u)
1204 {
1205 struct tegra_uart_port *tup = to_tegra_uport(u);
1206 int ret;
1207
1208 if (!tup->use_tx_pio) {
1209 ret = tegra_uart_dma_channel_allocate(tup, false);
1210 if (ret < 0) {
1211 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1212 ret);
1213 return ret;
1214 }
1215 }
1216
1217 if (!tup->use_rx_pio) {
1218 ret = tegra_uart_dma_channel_allocate(tup, true);
1219 if (ret < 0) {
1220 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1221 ret);
1222 goto fail_rx_dma;
1223 }
1224 }
1225
1226 ret = tegra_uart_hw_init(tup);
1227 if (ret < 0) {
1228 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1229 goto fail_hw_init;
1230 }
1231
1232 ret = request_irq(u->irq, tegra_uart_isr, 0,
1233 dev_name(u->dev), tup);
1234 if (ret < 0) {
1235 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1236 goto fail_request_irq;
1237 }
1238 return 0;
1239
1240 fail_request_irq:
1241 /* tup->uart_clk is already enabled in tegra_uart_hw_init */
1242 clk_disable_unprepare(tup->uart_clk);
1243 fail_hw_init:
1244 if (!tup->use_rx_pio)
1245 tegra_uart_dma_channel_free(tup, true);
1246 fail_rx_dma:
1247 if (!tup->use_tx_pio)
1248 tegra_uart_dma_channel_free(tup, false);
1249 return ret;
1250 }
1251
1252 /*
1253 * Flush any TX data submitted for DMA and PIO. Called when the
1254 * TX circular buffer is reset.
1255 */
tegra_uart_flush_buffer(struct uart_port * u)1256 static void tegra_uart_flush_buffer(struct uart_port *u)
1257 {
1258 struct tegra_uart_port *tup = to_tegra_uport(u);
1259
1260 tup->tx_bytes = 0;
1261 if (tup->tx_dma_chan)
1262 dmaengine_terminate_all(tup->tx_dma_chan);
1263 }
1264
tegra_uart_shutdown(struct uart_port * u)1265 static void tegra_uart_shutdown(struct uart_port *u)
1266 {
1267 struct tegra_uart_port *tup = to_tegra_uport(u);
1268
1269 tegra_uart_hw_deinit(tup);
1270 free_irq(u->irq, tup);
1271 }
1272
tegra_uart_enable_ms(struct uart_port * u)1273 static void tegra_uart_enable_ms(struct uart_port *u)
1274 {
1275 struct tegra_uart_port *tup = to_tegra_uport(u);
1276
1277 if (tup->enable_modem_interrupt) {
1278 tup->ier_shadow |= UART_IER_MSI;
1279 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1280 }
1281 }
1282
tegra_uart_set_termios(struct uart_port * u,struct ktermios * termios,const struct ktermios * oldtermios)1283 static void tegra_uart_set_termios(struct uart_port *u,
1284 struct ktermios *termios,
1285 const struct ktermios *oldtermios)
1286 {
1287 struct tegra_uart_port *tup = to_tegra_uport(u);
1288 unsigned int baud;
1289 unsigned long flags;
1290 unsigned int lcr;
1291 unsigned char char_bits;
1292 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1293 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1294 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1295 int ret;
1296
1297 max_divider *= 16;
1298 spin_lock_irqsave(&u->lock, flags);
1299
1300 /* Changing configuration, it is safe to stop any rx now */
1301 if (tup->rts_active)
1302 set_rts(tup, false);
1303
1304 /* Clear all interrupts as configuration is going to be changed */
1305 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1306 tegra_uart_read(tup, UART_IER);
1307 tegra_uart_write(tup, 0, UART_IER);
1308 tegra_uart_read(tup, UART_IER);
1309
1310 /* Parity */
1311 lcr = tup->lcr_shadow;
1312 lcr &= ~UART_LCR_PARITY;
1313
1314 /* CMSPAR isn't supported by this driver */
1315 termios->c_cflag &= ~CMSPAR;
1316
1317 if ((termios->c_cflag & PARENB) == PARENB) {
1318 if (termios->c_cflag & PARODD) {
1319 lcr |= UART_LCR_PARITY;
1320 lcr &= ~UART_LCR_EPAR;
1321 lcr &= ~UART_LCR_SPAR;
1322 } else {
1323 lcr |= UART_LCR_PARITY;
1324 lcr |= UART_LCR_EPAR;
1325 lcr &= ~UART_LCR_SPAR;
1326 }
1327 }
1328
1329 char_bits = tty_get_char_size(termios->c_cflag);
1330 lcr &= ~UART_LCR_WLEN8;
1331 lcr |= UART_LCR_WLEN(char_bits);
1332
1333 /* Stop bits */
1334 if (termios->c_cflag & CSTOPB)
1335 lcr |= UART_LCR_STOP;
1336 else
1337 lcr &= ~UART_LCR_STOP;
1338
1339 tegra_uart_write(tup, lcr, UART_LCR);
1340 tup->lcr_shadow = lcr;
1341 tup->symb_bit = tty_get_frame_size(termios->c_cflag);
1342
1343 /* Baud rate. */
1344 baud = uart_get_baud_rate(u, termios, oldtermios,
1345 parent_clk_rate/max_divider,
1346 parent_clk_rate/16);
1347 spin_unlock_irqrestore(&u->lock, flags);
1348 ret = tegra_set_baudrate(tup, baud);
1349 if (ret < 0) {
1350 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1351 return;
1352 }
1353 if (tty_termios_baud_rate(termios))
1354 tty_termios_encode_baud_rate(termios, baud, baud);
1355 spin_lock_irqsave(&u->lock, flags);
1356
1357 /* Flow control */
1358 if (termios->c_cflag & CRTSCTS) {
1359 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1360 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1361 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1362 /* if top layer has asked to set rts active then do so here */
1363 if (tup->rts_active)
1364 set_rts(tup, true);
1365 } else {
1366 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1367 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1368 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1369 }
1370
1371 /* update the port timeout based on new settings */
1372 uart_update_timeout(u, termios->c_cflag, baud);
1373
1374 /* Make sure all writes have completed */
1375 tegra_uart_read(tup, UART_IER);
1376
1377 /* Re-enable interrupt */
1378 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1379 tegra_uart_read(tup, UART_IER);
1380
1381 tup->uport.ignore_status_mask = 0;
1382 /* Ignore all characters if CREAD is not set */
1383 if ((termios->c_cflag & CREAD) == 0)
1384 tup->uport.ignore_status_mask |= UART_LSR_DR;
1385 if (termios->c_iflag & IGNBRK)
1386 tup->uport.ignore_status_mask |= UART_LSR_BI;
1387
1388 spin_unlock_irqrestore(&u->lock, flags);
1389 }
1390
tegra_uart_type(struct uart_port * u)1391 static const char *tegra_uart_type(struct uart_port *u)
1392 {
1393 return TEGRA_UART_TYPE;
1394 }
1395
1396 static const struct uart_ops tegra_uart_ops = {
1397 .tx_empty = tegra_uart_tx_empty,
1398 .set_mctrl = tegra_uart_set_mctrl,
1399 .get_mctrl = tegra_uart_get_mctrl,
1400 .stop_tx = tegra_uart_stop_tx,
1401 .start_tx = tegra_uart_start_tx,
1402 .stop_rx = tegra_uart_stop_rx,
1403 .flush_buffer = tegra_uart_flush_buffer,
1404 .enable_ms = tegra_uart_enable_ms,
1405 .break_ctl = tegra_uart_break_ctl,
1406 .startup = tegra_uart_startup,
1407 .shutdown = tegra_uart_shutdown,
1408 .set_termios = tegra_uart_set_termios,
1409 .type = tegra_uart_type,
1410 .request_port = tegra_uart_request_port,
1411 .release_port = tegra_uart_release_port,
1412 };
1413
1414 static struct uart_driver tegra_uart_driver = {
1415 .owner = THIS_MODULE,
1416 .driver_name = "tegra_hsuart",
1417 .dev_name = "ttyTHS",
1418 .cons = NULL,
1419 .nr = TEGRA_UART_MAXIMUM,
1420 };
1421
tegra_uart_parse_dt(struct platform_device * pdev,struct tegra_uart_port * tup)1422 static int tegra_uart_parse_dt(struct platform_device *pdev,
1423 struct tegra_uart_port *tup)
1424 {
1425 struct device_node *np = pdev->dev.of_node;
1426 int port;
1427 int ret;
1428 int index;
1429 u32 pval;
1430 int count;
1431 int n_entries;
1432
1433 port = of_alias_get_id(np, "serial");
1434 if (port < 0) {
1435 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1436 return port;
1437 }
1438 tup->uport.line = port;
1439
1440 tup->enable_modem_interrupt = of_property_read_bool(np,
1441 "nvidia,enable-modem-interrupt");
1442
1443 index = of_property_match_string(np, "dma-names", "rx");
1444 if (index < 0) {
1445 tup->use_rx_pio = true;
1446 dev_info(&pdev->dev, "RX in PIO mode\n");
1447 }
1448 index = of_property_match_string(np, "dma-names", "tx");
1449 if (index < 0) {
1450 tup->use_tx_pio = true;
1451 dev_info(&pdev->dev, "TX in PIO mode\n");
1452 }
1453
1454 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1455 if (n_entries > 0) {
1456 tup->n_adjustable_baud_rates = n_entries / 3;
1457 tup->baud_tolerance =
1458 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1459 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1460 if (!tup->baud_tolerance)
1461 return -ENOMEM;
1462 for (count = 0, index = 0; count < n_entries; count += 3,
1463 index++) {
1464 ret =
1465 of_property_read_u32_index(np,
1466 "nvidia,adjust-baud-rates",
1467 count, &pval);
1468 if (!ret)
1469 tup->baud_tolerance[index].lower_range_baud =
1470 pval;
1471 ret =
1472 of_property_read_u32_index(np,
1473 "nvidia,adjust-baud-rates",
1474 count + 1, &pval);
1475 if (!ret)
1476 tup->baud_tolerance[index].upper_range_baud =
1477 pval;
1478 ret =
1479 of_property_read_u32_index(np,
1480 "nvidia,adjust-baud-rates",
1481 count + 2, &pval);
1482 if (!ret)
1483 tup->baud_tolerance[index].tolerance =
1484 (s32)pval;
1485 }
1486 } else {
1487 tup->n_adjustable_baud_rates = 0;
1488 }
1489
1490 return 0;
1491 }
1492
1493 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1494 .tx_fifo_full_status = false,
1495 .allow_txfifo_reset_fifo_mode = true,
1496 .support_clk_src_div = false,
1497 .fifo_mode_enable_status = false,
1498 .uart_max_port = 5,
1499 .max_dma_burst_bytes = 4,
1500 .error_tolerance_low_range = -4,
1501 .error_tolerance_high_range = 4,
1502 };
1503
1504 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1505 .tx_fifo_full_status = true,
1506 .allow_txfifo_reset_fifo_mode = false,
1507 .support_clk_src_div = true,
1508 .fifo_mode_enable_status = false,
1509 .uart_max_port = 5,
1510 .max_dma_burst_bytes = 4,
1511 .error_tolerance_low_range = -4,
1512 .error_tolerance_high_range = 4,
1513 };
1514
1515 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1516 .tx_fifo_full_status = true,
1517 .allow_txfifo_reset_fifo_mode = false,
1518 .support_clk_src_div = true,
1519 .fifo_mode_enable_status = true,
1520 .uart_max_port = 8,
1521 .max_dma_burst_bytes = 8,
1522 .error_tolerance_low_range = 0,
1523 .error_tolerance_high_range = 4,
1524 };
1525
1526 static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1527 .tx_fifo_full_status = true,
1528 .allow_txfifo_reset_fifo_mode = false,
1529 .support_clk_src_div = true,
1530 .fifo_mode_enable_status = true,
1531 .uart_max_port = 8,
1532 .max_dma_burst_bytes = 8,
1533 .error_tolerance_low_range = -2,
1534 .error_tolerance_high_range = 2,
1535 };
1536
1537 static const struct of_device_id tegra_uart_of_match[] = {
1538 {
1539 .compatible = "nvidia,tegra30-hsuart",
1540 .data = &tegra30_uart_chip_data,
1541 }, {
1542 .compatible = "nvidia,tegra20-hsuart",
1543 .data = &tegra20_uart_chip_data,
1544 }, {
1545 .compatible = "nvidia,tegra186-hsuart",
1546 .data = &tegra186_uart_chip_data,
1547 }, {
1548 .compatible = "nvidia,tegra194-hsuart",
1549 .data = &tegra194_uart_chip_data,
1550 }, {
1551 },
1552 };
1553 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1554
tegra_uart_probe(struct platform_device * pdev)1555 static int tegra_uart_probe(struct platform_device *pdev)
1556 {
1557 struct tegra_uart_port *tup;
1558 struct uart_port *u;
1559 struct resource *resource;
1560 int ret;
1561 const struct tegra_uart_chip_data *cdata;
1562
1563 cdata = of_device_get_match_data(&pdev->dev);
1564 if (!cdata) {
1565 dev_err(&pdev->dev, "Error: No device match found\n");
1566 return -ENODEV;
1567 }
1568
1569 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1570 if (!tup) {
1571 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1572 return -ENOMEM;
1573 }
1574
1575 ret = tegra_uart_parse_dt(pdev, tup);
1576 if (ret < 0)
1577 return ret;
1578
1579 u = &tup->uport;
1580 u->dev = &pdev->dev;
1581 u->ops = &tegra_uart_ops;
1582 u->type = PORT_TEGRA;
1583 u->fifosize = 32;
1584 tup->cdata = cdata;
1585
1586 platform_set_drvdata(pdev, tup);
1587 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1588 if (!resource) {
1589 dev_err(&pdev->dev, "No IO memory resource\n");
1590 return -ENODEV;
1591 }
1592
1593 u->mapbase = resource->start;
1594 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1595 if (IS_ERR(u->membase))
1596 return PTR_ERR(u->membase);
1597
1598 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1599 if (IS_ERR(tup->uart_clk)) {
1600 dev_err(&pdev->dev, "Couldn't get the clock\n");
1601 return PTR_ERR(tup->uart_clk);
1602 }
1603
1604 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1605 if (IS_ERR(tup->rst)) {
1606 dev_err(&pdev->dev, "Couldn't get the reset\n");
1607 return PTR_ERR(tup->rst);
1608 }
1609
1610 u->iotype = UPIO_MEM32;
1611 ret = platform_get_irq(pdev, 0);
1612 if (ret < 0)
1613 return ret;
1614 u->irq = ret;
1615 u->regshift = 2;
1616 ret = uart_add_one_port(&tegra_uart_driver, u);
1617 if (ret < 0) {
1618 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1619 return ret;
1620 }
1621 return ret;
1622 }
1623
tegra_uart_remove(struct platform_device * pdev)1624 static int tegra_uart_remove(struct platform_device *pdev)
1625 {
1626 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1627 struct uart_port *u = &tup->uport;
1628
1629 uart_remove_one_port(&tegra_uart_driver, u);
1630 return 0;
1631 }
1632
1633 #ifdef CONFIG_PM_SLEEP
tegra_uart_suspend(struct device * dev)1634 static int tegra_uart_suspend(struct device *dev)
1635 {
1636 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1637 struct uart_port *u = &tup->uport;
1638
1639 return uart_suspend_port(&tegra_uart_driver, u);
1640 }
1641
tegra_uart_resume(struct device * dev)1642 static int tegra_uart_resume(struct device *dev)
1643 {
1644 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1645 struct uart_port *u = &tup->uport;
1646
1647 return uart_resume_port(&tegra_uart_driver, u);
1648 }
1649 #endif
1650
1651 static const struct dev_pm_ops tegra_uart_pm_ops = {
1652 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1653 };
1654
1655 static struct platform_driver tegra_uart_platform_driver = {
1656 .probe = tegra_uart_probe,
1657 .remove = tegra_uart_remove,
1658 .driver = {
1659 .name = "serial-tegra",
1660 .of_match_table = tegra_uart_of_match,
1661 .pm = &tegra_uart_pm_ops,
1662 },
1663 };
1664
tegra_uart_init(void)1665 static int __init tegra_uart_init(void)
1666 {
1667 int ret;
1668 struct device_node *node;
1669 const struct of_device_id *match = NULL;
1670 const struct tegra_uart_chip_data *cdata = NULL;
1671
1672 node = of_find_matching_node(NULL, tegra_uart_of_match);
1673 if (node)
1674 match = of_match_node(tegra_uart_of_match, node);
1675 of_node_put(node);
1676 if (match)
1677 cdata = match->data;
1678 if (cdata)
1679 tegra_uart_driver.nr = cdata->uart_max_port;
1680
1681 ret = uart_register_driver(&tegra_uart_driver);
1682 if (ret < 0) {
1683 pr_err("Could not register %s driver\n",
1684 tegra_uart_driver.driver_name);
1685 return ret;
1686 }
1687
1688 ret = platform_driver_register(&tegra_uart_platform_driver);
1689 if (ret < 0) {
1690 pr_err("Uart platform driver register failed, e = %d\n", ret);
1691 uart_unregister_driver(&tegra_uart_driver);
1692 return ret;
1693 }
1694 return 0;
1695 }
1696
tegra_uart_exit(void)1697 static void __exit tegra_uart_exit(void)
1698 {
1699 pr_info("Unloading tegra uart driver\n");
1700 platform_driver_unregister(&tegra_uart_platform_driver);
1701 uart_unregister_driver(&tegra_uart_driver);
1702 }
1703
1704 module_init(tegra_uart_init);
1705 module_exit(tegra_uart_exit);
1706
1707 MODULE_ALIAS("platform:serial-tegra");
1708 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1709 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1710 MODULE_LICENSE("GPL v2");
1711