1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/slab.h>
36
37 #include "mlx4.h"
38 #include "fw.h"
39
40 enum {
41 MLX4_RES_QP,
42 MLX4_RES_RDMARC,
43 MLX4_RES_ALTC,
44 MLX4_RES_AUXC,
45 MLX4_RES_SRQ,
46 MLX4_RES_CQ,
47 MLX4_RES_EQ,
48 MLX4_RES_DMPT,
49 MLX4_RES_CMPT,
50 MLX4_RES_MTT,
51 MLX4_RES_MCG,
52 MLX4_RES_NUM
53 };
54
55 static const char *res_name[] = {
56 [MLX4_RES_QP] = "QP",
57 [MLX4_RES_RDMARC] = "RDMARC",
58 [MLX4_RES_ALTC] = "ALTC",
59 [MLX4_RES_AUXC] = "AUXC",
60 [MLX4_RES_SRQ] = "SRQ",
61 [MLX4_RES_CQ] = "CQ",
62 [MLX4_RES_EQ] = "EQ",
63 [MLX4_RES_DMPT] = "DMPT",
64 [MLX4_RES_CMPT] = "CMPT",
65 [MLX4_RES_MTT] = "MTT",
66 [MLX4_RES_MCG] = "MCG",
67 };
68
mlx4_make_profile(struct mlx4_dev * dev,struct mlx4_profile * request,struct mlx4_dev_cap * dev_cap,struct mlx4_init_hca_param * init_hca)69 u64 mlx4_make_profile(struct mlx4_dev *dev,
70 struct mlx4_profile *request,
71 struct mlx4_dev_cap *dev_cap,
72 struct mlx4_init_hca_param *init_hca)
73 {
74 struct mlx4_priv *priv = mlx4_priv(dev);
75 struct mlx4_resource {
76 u64 size;
77 u64 start;
78 int type;
79 u32 num;
80 int log_num;
81 };
82
83 u64 total_size = 0;
84 struct mlx4_resource *profile;
85 struct sysinfo si;
86 int i, j;
87
88 profile = kcalloc(MLX4_RES_NUM, sizeof(*profile), GFP_KERNEL);
89 if (!profile)
90 return -ENOMEM;
91
92 /*
93 * We want to scale the number of MTTs with the size of the
94 * system memory, since it makes sense to register a lot of
95 * memory on a system with a lot of memory. As a heuristic,
96 * make sure we have enough MTTs to cover twice the system
97 * memory (with PAGE_SIZE entries).
98 *
99 * This number has to be a power of two and fit into 32 bits
100 * due to device limitations, so cap this at 2^31 as well.
101 * That limits us to 8TB of memory registration per HCA with
102 * 4KB pages, which is probably OK for the next few months.
103 */
104 si_meminfo(&si);
105 request->num_mtt =
106 roundup_pow_of_two(max_t(unsigned, request->num_mtt,
107 min(1UL << (31 - log_mtts_per_seg),
108 (si.totalram << 1) >> log_mtts_per_seg)));
109
110
111 profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz;
112 profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
113 profile[MLX4_RES_ALTC].size = dev_cap->altc_entry_sz;
114 profile[MLX4_RES_AUXC].size = dev_cap->aux_entry_sz;
115 profile[MLX4_RES_SRQ].size = dev_cap->srq_entry_sz;
116 profile[MLX4_RES_CQ].size = dev_cap->cqc_entry_sz;
117 profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz;
118 profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz;
119 profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz;
120 profile[MLX4_RES_MTT].size = dev_cap->mtt_entry_sz;
121 profile[MLX4_RES_MCG].size = mlx4_get_mgm_entry_size(dev);
122
123 profile[MLX4_RES_QP].num = request->num_qp;
124 profile[MLX4_RES_RDMARC].num = request->num_qp * request->rdmarc_per_qp;
125 profile[MLX4_RES_ALTC].num = request->num_qp;
126 profile[MLX4_RES_AUXC].num = request->num_qp;
127 profile[MLX4_RES_SRQ].num = request->num_srq;
128 profile[MLX4_RES_CQ].num = request->num_cq;
129 profile[MLX4_RES_EQ].num = mlx4_is_mfunc(dev) ? dev->phys_caps.num_phys_eqs :
130 min_t(unsigned, dev_cap->max_eqs, MAX_MSIX);
131 profile[MLX4_RES_DMPT].num = request->num_mpt;
132 profile[MLX4_RES_CMPT].num = MLX4_NUM_CMPTS;
133 profile[MLX4_RES_MTT].num = request->num_mtt * (1 << log_mtts_per_seg);
134 profile[MLX4_RES_MCG].num = request->num_mcg;
135
136 for (i = 0; i < MLX4_RES_NUM; ++i) {
137 profile[i].type = i;
138 profile[i].num = roundup_pow_of_two(profile[i].num);
139 profile[i].log_num = ilog2(profile[i].num);
140 profile[i].size *= profile[i].num;
141 profile[i].size = max(profile[i].size, (u64) PAGE_SIZE);
142 }
143
144 /*
145 * Sort the resources in decreasing order of size. Since they
146 * all have sizes that are powers of 2, we'll be able to keep
147 * resources aligned to their size and pack them without gaps
148 * using the sorted order.
149 */
150 for (i = MLX4_RES_NUM; i > 0; --i)
151 for (j = 1; j < i; ++j) {
152 if (profile[j].size > profile[j - 1].size)
153 swap(profile[j], profile[j - 1]);
154 }
155
156 for (i = 0; i < MLX4_RES_NUM; ++i) {
157 if (profile[i].size) {
158 profile[i].start = total_size;
159 total_size += profile[i].size;
160 }
161
162 if (total_size > dev_cap->max_icm_sz) {
163 mlx4_err(dev, "Profile requires 0x%llx bytes; won't fit in 0x%llx bytes of context memory\n",
164 (unsigned long long) total_size,
165 (unsigned long long) dev_cap->max_icm_sz);
166 kfree(profile);
167 return -ENOMEM;
168 }
169
170 if (profile[i].size)
171 mlx4_dbg(dev, " profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, size 0x%10llx\n",
172 i, res_name[profile[i].type],
173 profile[i].log_num,
174 (unsigned long long) profile[i].start,
175 (unsigned long long) profile[i].size);
176 }
177
178 mlx4_dbg(dev, "HCA context memory: reserving %d KB\n",
179 (int) (total_size >> 10));
180
181 for (i = 0; i < MLX4_RES_NUM; ++i) {
182 switch (profile[i].type) {
183 case MLX4_RES_QP:
184 dev->caps.num_qps = profile[i].num;
185 init_hca->qpc_base = profile[i].start;
186 init_hca->log_num_qps = profile[i].log_num;
187 break;
188 case MLX4_RES_RDMARC:
189 for (priv->qp_table.rdmarc_shift = 0;
190 request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num;
191 ++priv->qp_table.rdmarc_shift)
192 ; /* nothing */
193 dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift;
194 priv->qp_table.rdmarc_base = (u32) profile[i].start;
195 init_hca->rdmarc_base = profile[i].start;
196 init_hca->log_rd_per_qp = priv->qp_table.rdmarc_shift;
197 break;
198 case MLX4_RES_ALTC:
199 init_hca->altc_base = profile[i].start;
200 break;
201 case MLX4_RES_AUXC:
202 init_hca->auxc_base = profile[i].start;
203 break;
204 case MLX4_RES_SRQ:
205 dev->caps.num_srqs = profile[i].num;
206 init_hca->srqc_base = profile[i].start;
207 init_hca->log_num_srqs = profile[i].log_num;
208 break;
209 case MLX4_RES_CQ:
210 dev->caps.num_cqs = profile[i].num;
211 init_hca->cqc_base = profile[i].start;
212 init_hca->log_num_cqs = profile[i].log_num;
213 break;
214 case MLX4_RES_EQ:
215 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
216 init_hca->log_num_eqs = 0x1f;
217 init_hca->eqc_base = profile[i].start;
218 init_hca->num_sys_eqs = dev_cap->num_sys_eqs;
219 } else {
220 dev->caps.num_eqs = roundup_pow_of_two(
221 min_t(unsigned,
222 dev_cap->max_eqs,
223 MAX_MSIX));
224 init_hca->eqc_base = profile[i].start;
225 init_hca->log_num_eqs = ilog2(dev->caps.num_eqs);
226 }
227 break;
228 case MLX4_RES_DMPT:
229 dev->caps.num_mpts = profile[i].num;
230 priv->mr_table.mpt_base = profile[i].start;
231 init_hca->dmpt_base = profile[i].start;
232 init_hca->log_mpt_sz = profile[i].log_num;
233 break;
234 case MLX4_RES_CMPT:
235 init_hca->cmpt_base = profile[i].start;
236 break;
237 case MLX4_RES_MTT:
238 dev->caps.num_mtts = profile[i].num;
239 priv->mr_table.mtt_base = profile[i].start;
240 init_hca->mtt_base = profile[i].start;
241 break;
242 case MLX4_RES_MCG:
243 init_hca->mc_base = profile[i].start;
244 init_hca->log_mc_entry_sz =
245 ilog2(mlx4_get_mgm_entry_size(dev));
246 init_hca->log_mc_table_sz = profile[i].log_num;
247 if (dev->caps.steering_mode ==
248 MLX4_STEERING_MODE_DEVICE_MANAGED) {
249 dev->caps.num_mgms = profile[i].num;
250 } else {
251 init_hca->log_mc_hash_sz =
252 profile[i].log_num - 1;
253 dev->caps.num_mgms = profile[i].num >> 1;
254 dev->caps.num_amgms = profile[i].num >> 1;
255 }
256 break;
257 default:
258 break;
259 }
260 }
261
262 /*
263 * PDs don't take any HCA memory, but we assign them as part
264 * of the HCA profile anyway.
265 */
266 dev->caps.num_pds = MLX4_NUM_PDS;
267
268 kfree(profile);
269 return total_size;
270 }
271