1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/ethtool_netlink.h>
34
35 #include "en.h"
36 #include "en/port.h"
37 #include "en/params.h"
38 #include "en/ptp.h"
39 #include "lib/clock.h"
40 #include "en/fs_ethtool.h"
41
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)42 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
43 struct ethtool_drvinfo *drvinfo)
44 {
45 struct mlx5_core_dev *mdev = priv->mdev;
46 int count;
47
48 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
49 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
50 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),
51 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id);
52 if (count >= sizeof(drvinfo->fw_version))
53 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
54 "%d.%d.%04d", fw_rev_maj(mdev),
55 fw_rev_min(mdev), fw_rev_sub(mdev));
56
57 strscpy(drvinfo->bus_info, dev_name(mdev->device),
58 sizeof(drvinfo->bus_info));
59 }
60
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)61 static void mlx5e_get_drvinfo(struct net_device *dev,
62 struct ethtool_drvinfo *drvinfo)
63 {
64 struct mlx5e_priv *priv = netdev_priv(dev);
65
66 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
67 }
68
69 struct ptys2ethtool_config {
70 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
71 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
72 };
73
74 static
75 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
76 static
77 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
78
79 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
80 ({ \
81 struct ptys2ethtool_config *cfg; \
82 const unsigned int modes[] = { __VA_ARGS__ }; \
83 unsigned int i, bit, idx; \
84 cfg = &ptys2##table##_ethtool_table[reg_]; \
85 bitmap_zero(cfg->supported, \
86 __ETHTOOL_LINK_MODE_MASK_NBITS); \
87 bitmap_zero(cfg->advertised, \
88 __ETHTOOL_LINK_MODE_MASK_NBITS); \
89 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
90 bit = modes[i] % 64; \
91 idx = modes[i] / 64; \
92 __set_bit(bit, &cfg->supported[idx]); \
93 __set_bit(bit, &cfg->advertised[idx]); \
94 } \
95 })
96
mlx5e_build_ptys2ethtool_map(void)97 void mlx5e_build_ptys2ethtool_map(void)
98 {
99 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
100 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
102 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
104 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
106 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
108 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
110 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
112 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
114 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
116 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
118 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
120 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
122 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
124 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
126 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
128 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
130 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
132 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
134 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
136 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
138 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
140 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
142 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
144 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
146 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
148 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
150 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
152 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
154 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
155 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
156 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
158 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
160 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
161 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
162 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
163 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
164 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
165 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
166 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
167 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
168 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
169 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
170 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
171 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
172 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
173 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
174 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
175 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
176 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
177 ext,
178 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
180 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
181 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
182 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
183 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
184 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
185 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
186 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
187 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
188 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
191 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
192 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
193 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
194 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
195 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
196 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
197 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
198 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
199 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
200 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
201 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
202 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
203 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
204 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
205 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
206 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
207 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
208 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
209 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
210 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
211 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
212 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
213 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
214 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
215 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
216 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
217 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
218 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
219 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
220 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
221 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
222 }
223
mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev * mdev,struct ptys2ethtool_config ** arr,u32 * size)224 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
225 struct ptys2ethtool_config **arr,
226 u32 *size)
227 {
228 bool ext = mlx5e_ptys_ext_supported(mdev);
229
230 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
231 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
232 ARRAY_SIZE(ptys2legacy_ethtool_table);
233 }
234
235 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
236
237 struct pflag_desc {
238 char name[ETH_GSTRING_LEN];
239 mlx5e_pflag_handler handler;
240 };
241
242 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
243
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)244 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
245 {
246 switch (sset) {
247 case ETH_SS_STATS:
248 return mlx5e_stats_total_num(priv);
249 case ETH_SS_PRIV_FLAGS:
250 return MLX5E_NUM_PFLAGS;
251 case ETH_SS_TEST:
252 return mlx5e_self_test_num(priv);
253 default:
254 return -EOPNOTSUPP;
255 }
256 }
257
mlx5e_get_sset_count(struct net_device * dev,int sset)258 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
259 {
260 struct mlx5e_priv *priv = netdev_priv(dev);
261
262 return mlx5e_ethtool_get_sset_count(priv, sset);
263 }
264
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)265 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
266 {
267 int i;
268
269 switch (stringset) {
270 case ETH_SS_PRIV_FLAGS:
271 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
272 strcpy(data + i * ETH_GSTRING_LEN,
273 mlx5e_priv_flags[i].name);
274 break;
275
276 case ETH_SS_TEST:
277 mlx5e_self_test_fill_strings(priv, data);
278 break;
279
280 case ETH_SS_STATS:
281 mlx5e_stats_fill_strings(priv, data);
282 break;
283 }
284 }
285
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)286 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
287 {
288 struct mlx5e_priv *priv = netdev_priv(dev);
289
290 mlx5e_ethtool_get_strings(priv, stringset, data);
291 }
292
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)293 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
294 struct ethtool_stats *stats, u64 *data)
295 {
296 int idx = 0;
297
298 mutex_lock(&priv->state_lock);
299 mlx5e_stats_update(priv);
300 mutex_unlock(&priv->state_lock);
301
302 mlx5e_stats_fill(priv, data, idx);
303 }
304
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)305 static void mlx5e_get_ethtool_stats(struct net_device *dev,
306 struct ethtool_stats *stats,
307 u64 *data)
308 {
309 struct mlx5e_priv *priv = netdev_priv(dev);
310
311 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
312 }
313
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param)314 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
315 struct ethtool_ringparam *param,
316 struct kernel_ethtool_ringparam *kernel_param)
317 {
318 /* Limitation for regular RQ. XSK RQ may clamp the queue length in
319 * mlx5e_mpwqe_get_log_rq_size.
320 */
321 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev,
322 PAGE_SHIFT,
323 MLX5E_MPWRQ_UMR_MODE_ALIGNED);
324
325 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE,
326 max_log_mpwrq_pkts);
327 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
328 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
329 param->tx_pending = 1 << priv->channels.params.log_sq_size;
330
331 kernel_param->tcp_data_split =
332 (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) ?
333 ETHTOOL_TCP_DATA_SPLIT_ENABLED :
334 ETHTOOL_TCP_DATA_SPLIT_DISABLED;
335 }
336
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)337 static void mlx5e_get_ringparam(struct net_device *dev,
338 struct ethtool_ringparam *param,
339 struct kernel_ethtool_ringparam *kernel_param,
340 struct netlink_ext_ack *extack)
341 {
342 struct mlx5e_priv *priv = netdev_priv(dev);
343
344 mlx5e_ethtool_get_ringparam(priv, param, kernel_param);
345 }
346
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)347 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
348 struct ethtool_ringparam *param)
349 {
350 struct mlx5e_params new_params;
351 u8 log_rq_size;
352 u8 log_sq_size;
353 int err = 0;
354
355 if (param->rx_jumbo_pending) {
356 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
357 __func__);
358 return -EINVAL;
359 }
360 if (param->rx_mini_pending) {
361 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
362 __func__);
363 return -EINVAL;
364 }
365
366 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
367 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
368 __func__, param->rx_pending,
369 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
370 return -EINVAL;
371 }
372
373 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
374 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
375 __func__, param->tx_pending,
376 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
377 return -EINVAL;
378 }
379
380 log_rq_size = order_base_2(param->rx_pending);
381 log_sq_size = order_base_2(param->tx_pending);
382
383 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
384 log_sq_size == priv->channels.params.log_sq_size)
385 return 0;
386
387 mutex_lock(&priv->state_lock);
388
389 new_params = priv->channels.params;
390 new_params.log_rq_mtu_frames = log_rq_size;
391 new_params.log_sq_size = log_sq_size;
392
393 err = mlx5e_validate_params(priv->mdev, &new_params);
394 if (err)
395 goto unlock;
396
397 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
398
399 unlock:
400 mutex_unlock(&priv->state_lock);
401
402 return err;
403 }
404
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)405 static int mlx5e_set_ringparam(struct net_device *dev,
406 struct ethtool_ringparam *param,
407 struct kernel_ethtool_ringparam *kernel_param,
408 struct netlink_ext_ack *extack)
409 {
410 struct mlx5e_priv *priv = netdev_priv(dev);
411
412 return mlx5e_ethtool_set_ringparam(priv, param);
413 }
414
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)415 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
416 struct ethtool_channels *ch)
417 {
418 mutex_lock(&priv->state_lock);
419 ch->max_combined = priv->max_nch;
420 ch->combined_count = priv->channels.params.num_channels;
421 mutex_unlock(&priv->state_lock);
422 }
423
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)424 static void mlx5e_get_channels(struct net_device *dev,
425 struct ethtool_channels *ch)
426 {
427 struct mlx5e_priv *priv = netdev_priv(dev);
428
429 mlx5e_ethtool_get_channels(priv, ch);
430 }
431
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)432 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
433 struct ethtool_channels *ch)
434 {
435 struct mlx5e_params *cur_params = &priv->channels.params;
436 unsigned int count = ch->combined_count;
437 struct mlx5e_params new_params;
438 bool arfs_enabled;
439 int rss_cnt;
440 bool opened;
441 int err = 0;
442
443 if (!count) {
444 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
445 __func__);
446 return -EINVAL;
447 }
448
449 if (cur_params->num_channels == count)
450 return 0;
451
452 mutex_lock(&priv->state_lock);
453
454 /* Don't allow changing the number of channels if HTB offload is active,
455 * because the numeration of the QoS SQs will change, while per-queue
456 * qdiscs are attached.
457 */
458 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
459 err = -EINVAL;
460 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
461 __func__);
462 goto out;
463 }
464
465 /* Don't allow changing the number of channels if non-default RSS contexts exist,
466 * the kernel doesn't protect against set_channels operations that break them.
467 */
468 rss_cnt = mlx5e_rx_res_rss_cnt(priv->rx_res) - 1;
469 if (rss_cnt) {
470 err = -EINVAL;
471 netdev_err(priv->netdev, "%s: Non-default RSS contexts exist (%d), cannot change the number of channels\n",
472 __func__, rss_cnt);
473 goto out;
474 }
475
476 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active,
477 * because it defines a partition over the channels queues.
478 */
479 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
480 err = -EINVAL;
481 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n",
482 __func__);
483 goto out;
484 }
485
486 new_params = *cur_params;
487 new_params.num_channels = count;
488
489 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
490
491 arfs_enabled = opened && (priv->netdev->features & NETIF_F_NTUPLE);
492 if (arfs_enabled)
493 mlx5e_arfs_disable(priv->fs);
494
495 /* Switch to new channels, set new parameters and close old ones */
496 err = mlx5e_safe_switch_params(priv, &new_params,
497 mlx5e_num_channels_changed_ctx, NULL, true);
498
499 if (arfs_enabled) {
500 int err2 = mlx5e_arfs_enable(priv->fs);
501
502 if (err2)
503 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
504 __func__, err2);
505 }
506
507 out:
508 mutex_unlock(&priv->state_lock);
509
510 return err;
511 }
512
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)513 static int mlx5e_set_channels(struct net_device *dev,
514 struct ethtool_channels *ch)
515 {
516 struct mlx5e_priv *priv = netdev_priv(dev);
517
518 return mlx5e_ethtool_set_channels(priv, ch);
519 }
520
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal)521 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
522 struct ethtool_coalesce *coal,
523 struct kernel_ethtool_coalesce *kernel_coal)
524 {
525 struct dim_cq_moder *rx_moder, *tx_moder;
526
527 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
528 return -EOPNOTSUPP;
529
530 rx_moder = &priv->channels.params.rx_cq_moderation;
531 coal->rx_coalesce_usecs = rx_moder->usec;
532 coal->rx_max_coalesced_frames = rx_moder->pkts;
533 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
534
535 tx_moder = &priv->channels.params.tx_cq_moderation;
536 coal->tx_coalesce_usecs = tx_moder->usec;
537 coal->tx_max_coalesced_frames = tx_moder->pkts;
538 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
539
540 kernel_coal->use_cqe_mode_rx =
541 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_BASED_MODER);
542 kernel_coal->use_cqe_mode_tx =
543 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_CQE_BASED_MODER);
544
545 return 0;
546 }
547
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)548 static int mlx5e_get_coalesce(struct net_device *netdev,
549 struct ethtool_coalesce *coal,
550 struct kernel_ethtool_coalesce *kernel_coal,
551 struct netlink_ext_ack *extack)
552 {
553 struct mlx5e_priv *priv = netdev_priv(netdev);
554
555 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal);
556 }
557
558 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
559 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
560
561 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)562 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
563 {
564 struct mlx5_core_dev *mdev = priv->mdev;
565 int tc;
566 int i;
567
568 for (i = 0; i < priv->channels.num; ++i) {
569 struct mlx5e_channel *c = priv->channels.c[i];
570
571 for (tc = 0; tc < c->num_tc; tc++) {
572 mlx5_core_modify_cq_moderation(mdev,
573 &c->sq[tc].cq.mcq,
574 coal->tx_coalesce_usecs,
575 coal->tx_max_coalesced_frames);
576 }
577 }
578 }
579
580 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)581 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
582 {
583 struct mlx5_core_dev *mdev = priv->mdev;
584 int i;
585
586 for (i = 0; i < priv->channels.num; ++i) {
587 struct mlx5e_channel *c = priv->channels.c[i];
588
589 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
590 coal->rx_coalesce_usecs,
591 coal->rx_max_coalesced_frames);
592 }
593 }
594
595 /* convert a boolean value of cq_mode to mlx5 period mode
596 * true : MLX5_CQ_PERIOD_MODE_START_FROM_CQE
597 * false : MLX5_CQ_PERIOD_MODE_START_FROM_EQE
598 */
cqe_mode_to_period_mode(bool val)599 static int cqe_mode_to_period_mode(bool val)
600 {
601 return val ? MLX5_CQ_PERIOD_MODE_START_FROM_CQE : MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
602 }
603
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)604 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
605 struct ethtool_coalesce *coal,
606 struct kernel_ethtool_coalesce *kernel_coal,
607 struct netlink_ext_ack *extack)
608 {
609 struct dim_cq_moder *rx_moder, *tx_moder;
610 struct mlx5_core_dev *mdev = priv->mdev;
611 struct mlx5e_params new_params;
612 bool reset_rx, reset_tx;
613 bool reset = true;
614 u8 cq_period_mode;
615 int err = 0;
616
617 if (!MLX5_CAP_GEN(mdev, cq_moderation))
618 return -EOPNOTSUPP;
619
620 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
621 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
622 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
623 __func__, MLX5E_MAX_COAL_TIME);
624 return -ERANGE;
625 }
626
627 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
628 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
629 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
630 __func__, MLX5E_MAX_COAL_FRAMES);
631 return -ERANGE;
632 }
633
634 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
635 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) {
636 NL_SET_ERR_MSG_MOD(extack, "cqe_mode_rx/tx is not supported on this device");
637 return -EOPNOTSUPP;
638 }
639
640 mutex_lock(&priv->state_lock);
641 new_params = priv->channels.params;
642
643 rx_moder = &new_params.rx_cq_moderation;
644 rx_moder->usec = coal->rx_coalesce_usecs;
645 rx_moder->pkts = coal->rx_max_coalesced_frames;
646 new_params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
647
648 tx_moder = &new_params.tx_cq_moderation;
649 tx_moder->usec = coal->tx_coalesce_usecs;
650 tx_moder->pkts = coal->tx_max_coalesced_frames;
651 new_params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
652
653 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
654 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
655
656 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_rx);
657 if (cq_period_mode != rx_moder->cq_period_mode) {
658 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode);
659 reset_rx = true;
660 }
661
662 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_tx);
663 if (cq_period_mode != tx_moder->cq_period_mode) {
664 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode);
665 reset_tx = true;
666 }
667
668 if (reset_rx) {
669 u8 mode = MLX5E_GET_PFLAG(&new_params,
670 MLX5E_PFLAG_RX_CQE_BASED_MODER);
671
672 mlx5e_reset_rx_moderation(&new_params, mode);
673 }
674 if (reset_tx) {
675 u8 mode = MLX5E_GET_PFLAG(&new_params,
676 MLX5E_PFLAG_TX_CQE_BASED_MODER);
677
678 mlx5e_reset_tx_moderation(&new_params, mode);
679 }
680
681 /* If DIM state hasn't changed, it's possible to modify interrupt
682 * moderation parameters on the fly, even if the channels are open.
683 */
684 if (!reset_rx && !reset_tx && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
685 if (!coal->use_adaptive_rx_coalesce)
686 mlx5e_set_priv_channels_rx_coalesce(priv, coal);
687 if (!coal->use_adaptive_tx_coalesce)
688 mlx5e_set_priv_channels_tx_coalesce(priv, coal);
689 reset = false;
690 }
691
692 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
693
694 mutex_unlock(&priv->state_lock);
695 return err;
696 }
697
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)698 static int mlx5e_set_coalesce(struct net_device *netdev,
699 struct ethtool_coalesce *coal,
700 struct kernel_ethtool_coalesce *kernel_coal,
701 struct netlink_ext_ack *extack)
702 {
703 struct mlx5e_priv *priv = netdev_priv(netdev);
704
705 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack);
706 }
707
ptys2ethtool_supported_link(struct mlx5_core_dev * mdev,unsigned long * supported_modes,u32 eth_proto_cap)708 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
709 unsigned long *supported_modes,
710 u32 eth_proto_cap)
711 {
712 unsigned long proto_cap = eth_proto_cap;
713 struct ptys2ethtool_config *table;
714 u32 max_size;
715 int proto;
716
717 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
718 for_each_set_bit(proto, &proto_cap, max_size)
719 bitmap_or(supported_modes, supported_modes,
720 table[proto].supported,
721 __ETHTOOL_LINK_MODE_MASK_NBITS);
722 }
723
ptys2ethtool_adver_link(unsigned long * advertising_modes,u32 eth_proto_cap,bool ext)724 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
725 u32 eth_proto_cap, bool ext)
726 {
727 unsigned long proto_cap = eth_proto_cap;
728 struct ptys2ethtool_config *table;
729 u32 max_size;
730 int proto;
731
732 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
733 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
734 ARRAY_SIZE(ptys2legacy_ethtool_table);
735
736 for_each_set_bit(proto, &proto_cap, max_size)
737 bitmap_or(advertising_modes, advertising_modes,
738 table[proto].advertised,
739 __ETHTOOL_LINK_MODE_MASK_NBITS);
740 }
741
742 static const u32 pplm_fec_2_ethtool[] = {
743 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
744 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
745 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
746 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
747 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
748 };
749
pplm2ethtool_fec(u_long fec_mode,unsigned long size)750 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
751 {
752 int mode = 0;
753
754 if (!fec_mode)
755 return ETHTOOL_FEC_AUTO;
756
757 mode = find_first_bit(&fec_mode, size);
758
759 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
760 return pplm_fec_2_ethtool[mode];
761
762 return 0;
763 }
764
765 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
766 do { \
767 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
768 __set_bit(ethtool_fec, \
769 link_ksettings->link_modes.supported);\
770 } while (0)
771
772 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
773 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
774 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
775 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
776 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
777 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
778 };
779
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)780 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
781 struct ethtool_link_ksettings *link_ksettings)
782 {
783 unsigned long active_fec_long;
784 u32 active_fec;
785 u32 bitn;
786 int err;
787
788 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
789 if (err)
790 return (err == -EOPNOTSUPP) ? 0 : err;
791
792 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
793 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
794 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
795 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
796 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
797 ETHTOOL_LINK_MODE_FEC_RS_BIT);
798 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
799 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
800
801 active_fec_long = active_fec;
802 /* active fec is a bit set, find out which bit is set and
803 * advertise the corresponding ethtool bit
804 */
805 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
806 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
807 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
808 link_ksettings->link_modes.advertising);
809
810 return 0;
811 }
812
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)813 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
814 struct ethtool_link_ksettings *link_ksettings,
815 u32 eth_proto_cap, u8 connector_type)
816 {
817 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
818 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
819 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
820 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
821 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
822 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
823 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
824 ethtool_link_ksettings_add_link_mode(link_ksettings,
825 supported,
826 FIBRE);
827 ethtool_link_ksettings_add_link_mode(link_ksettings,
828 advertising,
829 FIBRE);
830 }
831
832 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
833 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
834 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
835 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
836 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
837 ethtool_link_ksettings_add_link_mode(link_ksettings,
838 supported,
839 Backplane);
840 ethtool_link_ksettings_add_link_mode(link_ksettings,
841 advertising,
842 Backplane);
843 }
844 return;
845 }
846
847 switch (connector_type) {
848 case MLX5E_PORT_TP:
849 ethtool_link_ksettings_add_link_mode(link_ksettings,
850 supported, TP);
851 ethtool_link_ksettings_add_link_mode(link_ksettings,
852 advertising, TP);
853 break;
854 case MLX5E_PORT_AUI:
855 ethtool_link_ksettings_add_link_mode(link_ksettings,
856 supported, AUI);
857 ethtool_link_ksettings_add_link_mode(link_ksettings,
858 advertising, AUI);
859 break;
860 case MLX5E_PORT_BNC:
861 ethtool_link_ksettings_add_link_mode(link_ksettings,
862 supported, BNC);
863 ethtool_link_ksettings_add_link_mode(link_ksettings,
864 advertising, BNC);
865 break;
866 case MLX5E_PORT_MII:
867 ethtool_link_ksettings_add_link_mode(link_ksettings,
868 supported, MII);
869 ethtool_link_ksettings_add_link_mode(link_ksettings,
870 advertising, MII);
871 break;
872 case MLX5E_PORT_FIBRE:
873 ethtool_link_ksettings_add_link_mode(link_ksettings,
874 supported, FIBRE);
875 ethtool_link_ksettings_add_link_mode(link_ksettings,
876 advertising, FIBRE);
877 break;
878 case MLX5E_PORT_DA:
879 ethtool_link_ksettings_add_link_mode(link_ksettings,
880 supported, Backplane);
881 ethtool_link_ksettings_add_link_mode(link_ksettings,
882 advertising, Backplane);
883 break;
884 case MLX5E_PORT_NONE:
885 case MLX5E_PORT_OTHER:
886 default:
887 break;
888 }
889 }
890
get_speed_duplex(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)891 static void get_speed_duplex(struct net_device *netdev,
892 u32 eth_proto_oper, bool force_legacy,
893 u16 data_rate_oper,
894 struct ethtool_link_ksettings *link_ksettings)
895 {
896 struct mlx5e_priv *priv = netdev_priv(netdev);
897 u32 speed = SPEED_UNKNOWN;
898 u8 duplex = DUPLEX_UNKNOWN;
899
900 if (!netif_carrier_ok(netdev))
901 goto out;
902
903 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
904 if (!speed) {
905 if (data_rate_oper)
906 speed = 100 * data_rate_oper;
907 else
908 speed = SPEED_UNKNOWN;
909 goto out;
910 }
911
912 duplex = DUPLEX_FULL;
913
914 out:
915 link_ksettings->base.speed = speed;
916 link_ksettings->base.duplex = duplex;
917 }
918
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)919 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
920 struct ethtool_link_ksettings *link_ksettings)
921 {
922 unsigned long *supported = link_ksettings->link_modes.supported;
923 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
924
925 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
926 }
927
get_advertising(u32 eth_proto_cap,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)928 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
929 struct ethtool_link_ksettings *link_ksettings,
930 bool ext)
931 {
932 unsigned long *advertising = link_ksettings->link_modes.advertising;
933 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
934
935 if (rx_pause)
936 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
937 if (tx_pause ^ rx_pause)
938 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
939 }
940
941 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
942 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
943 [MLX5E_PORT_NONE] = PORT_NONE,
944 [MLX5E_PORT_TP] = PORT_TP,
945 [MLX5E_PORT_AUI] = PORT_AUI,
946 [MLX5E_PORT_BNC] = PORT_BNC,
947 [MLX5E_PORT_MII] = PORT_MII,
948 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
949 [MLX5E_PORT_DA] = PORT_DA,
950 [MLX5E_PORT_OTHER] = PORT_OTHER,
951 };
952
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)953 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
954 {
955 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
956 return ptys2connector_type[connector_type];
957
958 if (eth_proto &
959 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
960 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
961 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
962 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
963 return PORT_FIBRE;
964 }
965
966 if (eth_proto &
967 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
968 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
969 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
970 return PORT_DA;
971 }
972
973 if (eth_proto &
974 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
975 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
976 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
977 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
978 return PORT_NONE;
979 }
980
981 return PORT_OTHER;
982 }
983
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)984 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
985 struct ethtool_link_ksettings *link_ksettings)
986 {
987 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
988 bool ext = mlx5e_ptys_ext_supported(mdev);
989
990 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
991 }
992
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)993 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
994 struct ethtool_link_ksettings *link_ksettings)
995 {
996 struct mlx5_core_dev *mdev = priv->mdev;
997 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
998 u32 eth_proto_admin;
999 u8 an_disable_admin;
1000 u16 data_rate_oper;
1001 u32 eth_proto_oper;
1002 u32 eth_proto_cap;
1003 u8 connector_type;
1004 u32 rx_pause = 0;
1005 u32 tx_pause = 0;
1006 u32 eth_proto_lp;
1007 bool admin_ext;
1008 u8 an_status;
1009 bool ext;
1010 int err;
1011
1012 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
1013 if (err) {
1014 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1015 __func__, err);
1016 goto err_query_regs;
1017 }
1018 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
1019 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1020 eth_proto_capability);
1021 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1022 eth_proto_admin);
1023 /* Fields: eth_proto_admin and ext_eth_proto_admin are
1024 * mutually exclusive. Hence try reading legacy advertising
1025 * when extended advertising is zero.
1026 * admin_ext indicates which proto_admin (ext vs. legacy)
1027 * should be read and interpreted
1028 */
1029 admin_ext = ext;
1030 if (ext && !eth_proto_admin) {
1031 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
1032 eth_proto_admin);
1033 admin_ext = false;
1034 }
1035
1036 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
1037 eth_proto_oper);
1038 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1039 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1040 an_status = MLX5_GET(ptys_reg, out, an_status);
1041 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1042 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
1043
1044 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1045
1046 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1047 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1048
1049 get_supported(mdev, eth_proto_cap, link_ksettings);
1050 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
1051 admin_ext);
1052 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
1053 data_rate_oper, link_ksettings);
1054
1055 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1056 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
1057 connector_type : MLX5E_PORT_UNKNOWN;
1058 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
1059 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
1060 connector_type);
1061 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
1062
1063 if (an_status == MLX5_AN_COMPLETE)
1064 ethtool_link_ksettings_add_link_mode(link_ksettings,
1065 lp_advertising, Autoneg);
1066
1067 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1068 AUTONEG_ENABLE;
1069 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1070 Autoneg);
1071
1072 err = get_fec_supported_advertised(mdev, link_ksettings);
1073 if (err) {
1074 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1075 __func__, err);
1076 err = 0; /* don't fail caps query because of FEC error */
1077 }
1078
1079 if (!an_disable_admin)
1080 ethtool_link_ksettings_add_link_mode(link_ksettings,
1081 advertising, Autoneg);
1082
1083 err_query_regs:
1084 return err;
1085 }
1086
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1087 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1088 struct ethtool_link_ksettings *link_ksettings)
1089 {
1090 struct mlx5e_priv *priv = netdev_priv(netdev);
1091
1092 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1093 }
1094
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1095 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1096 const unsigned long link_modes, u8 autoneg)
1097 {
1098 /* Extended link-mode has no speed limitations. */
1099 if (ext)
1100 return 0;
1101
1102 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1103 autoneg != AUTONEG_ENABLE) {
1104 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1105 __func__);
1106 return -EINVAL;
1107 }
1108 return 0;
1109 }
1110
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1111 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1112 {
1113 u32 i, ptys_modes = 0;
1114
1115 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1116 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1117 continue;
1118 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1119 link_modes,
1120 __ETHTOOL_LINK_MODE_MASK_NBITS))
1121 ptys_modes |= MLX5E_PROT_MASK(i);
1122 }
1123
1124 return ptys_modes;
1125 }
1126
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1127 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1128 {
1129 u32 i, ptys_modes = 0;
1130 unsigned long modes[2];
1131
1132 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1133 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1134 ptys2ext_ethtool_table[i].advertised[1] == 0)
1135 continue;
1136 memset(modes, 0, sizeof(modes));
1137 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1138 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1139
1140 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1141 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1142 ptys_modes |= MLX5E_PROT_MASK(i);
1143 }
1144 return ptys_modes;
1145 }
1146
ext_link_mode_requested(const unsigned long * adver)1147 static bool ext_link_mode_requested(const unsigned long *adver)
1148 {
1149 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1150 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1151 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1152
1153 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1154 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1155 }
1156
ext_requested(u8 autoneg,const unsigned long * adver,bool ext_supported)1157 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1158 {
1159 bool ext_link_mode = ext_link_mode_requested(adver);
1160
1161 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1162 }
1163
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1164 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1165 const struct ethtool_link_ksettings *link_ksettings)
1166 {
1167 struct mlx5_core_dev *mdev = priv->mdev;
1168 struct mlx5e_port_eth_proto eproto;
1169 const unsigned long *adver;
1170 bool an_changes = false;
1171 u8 an_disable_admin;
1172 bool ext_supported;
1173 u8 an_disable_cap;
1174 bool an_disable;
1175 u32 link_modes;
1176 u8 an_status;
1177 u8 autoneg;
1178 u32 speed;
1179 bool ext;
1180 int err;
1181
1182 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1183
1184 adver = link_ksettings->link_modes.advertising;
1185 autoneg = link_ksettings->base.autoneg;
1186 speed = link_ksettings->base.speed;
1187
1188 ext_supported = mlx5e_ptys_ext_supported(mdev);
1189 ext = ext_requested(autoneg, adver, ext_supported);
1190 if (!ext_supported && ext)
1191 return -EOPNOTSUPP;
1192
1193 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1194 mlx5e_ethtool2ptys_adver_link;
1195 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1196 if (err) {
1197 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1198 __func__, err);
1199 goto out;
1200 }
1201 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1202 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1203
1204 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1205 if (err)
1206 goto out;
1207
1208 link_modes = link_modes & eproto.cap;
1209 if (!link_modes) {
1210 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1211 __func__);
1212 err = -EINVAL;
1213 goto out;
1214 }
1215
1216 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1217 &an_disable_admin);
1218
1219 an_disable = autoneg == AUTONEG_DISABLE;
1220 an_changes = ((!an_disable && an_disable_admin) ||
1221 (an_disable && !an_disable_admin));
1222
1223 if (!an_changes && link_modes == eproto.admin)
1224 goto out;
1225
1226 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1227 mlx5_toggle_port_link(mdev);
1228
1229 out:
1230 return err;
1231 }
1232
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1233 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1234 const struct ethtool_link_ksettings *link_ksettings)
1235 {
1236 struct mlx5e_priv *priv = netdev_priv(netdev);
1237
1238 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1239 }
1240
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1241 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1242 {
1243 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key);
1244 }
1245
mlx5e_get_rxfh_key_size(struct net_device * netdev)1246 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1247 {
1248 struct mlx5e_priv *priv = netdev_priv(netdev);
1249
1250 return mlx5e_ethtool_get_rxfh_key_size(priv);
1251 }
1252
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1253 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1254 {
1255 return MLX5E_INDIR_RQT_SIZE;
1256 }
1257
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1258 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1259 {
1260 struct mlx5e_priv *priv = netdev_priv(netdev);
1261
1262 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1263 }
1264
mlx5e_get_rxfh_context(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc,u32 rss_context)1265 static int mlx5e_get_rxfh_context(struct net_device *dev, u32 *indir,
1266 u8 *key, u8 *hfunc, u32 rss_context)
1267 {
1268 struct mlx5e_priv *priv = netdev_priv(dev);
1269 int err;
1270
1271 mutex_lock(&priv->state_lock);
1272 err = mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rss_context, indir, key, hfunc);
1273 mutex_unlock(&priv->state_lock);
1274 return err;
1275 }
1276
mlx5e_set_rxfh_context(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc,u32 * rss_context,bool delete)1277 static int mlx5e_set_rxfh_context(struct net_device *dev, const u32 *indir,
1278 const u8 *key, const u8 hfunc,
1279 u32 *rss_context, bool delete)
1280 {
1281 struct mlx5e_priv *priv = netdev_priv(dev);
1282 int err;
1283
1284 mutex_lock(&priv->state_lock);
1285 if (delete) {
1286 err = mlx5e_rx_res_rss_destroy(priv->rx_res, *rss_context);
1287 goto unlock;
1288 }
1289
1290 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
1291 unsigned int count = priv->channels.params.num_channels;
1292
1293 err = mlx5e_rx_res_rss_init(priv->rx_res, rss_context, count);
1294 if (err)
1295 goto unlock;
1296 }
1297
1298 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, *rss_context, indir, key,
1299 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc);
1300
1301 unlock:
1302 mutex_unlock(&priv->state_lock);
1303 return err;
1304 }
1305
mlx5e_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)1306 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1307 u8 *hfunc)
1308 {
1309 return mlx5e_get_rxfh_context(netdev, indir, key, hfunc, 0);
1310 }
1311
mlx5e_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1312 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1313 const u8 *key, const u8 hfunc)
1314 {
1315 struct mlx5e_priv *priv = netdev_priv(dev);
1316 int err;
1317
1318 mutex_lock(&priv->state_lock);
1319 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, 0, indir, key,
1320 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc);
1321 mutex_unlock(&priv->state_lock);
1322 return err;
1323 }
1324
1325 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1326 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1327 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1328 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1329 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1330 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1331 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1332
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1333 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1334 u16 *pfc_prevention_tout)
1335 {
1336 struct mlx5e_priv *priv = netdev_priv(netdev);
1337 struct mlx5_core_dev *mdev = priv->mdev;
1338
1339 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1340 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1341 return -EOPNOTSUPP;
1342
1343 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1344 }
1345
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1346 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1347 u16 pfc_preven)
1348 {
1349 struct mlx5e_priv *priv = netdev_priv(netdev);
1350 struct mlx5_core_dev *mdev = priv->mdev;
1351 u16 critical_tout;
1352 u16 minor;
1353
1354 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1355 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1356 return -EOPNOTSUPP;
1357
1358 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1359 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1360 pfc_preven;
1361
1362 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1363 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1364 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1365 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1366 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1367 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1368 return -EINVAL;
1369 }
1370
1371 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1372 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1373 minor);
1374 }
1375
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1376 static int mlx5e_get_tunable(struct net_device *dev,
1377 const struct ethtool_tunable *tuna,
1378 void *data)
1379 {
1380 int err;
1381
1382 switch (tuna->id) {
1383 case ETHTOOL_PFC_PREVENTION_TOUT:
1384 err = mlx5e_get_pfc_prevention_tout(dev, data);
1385 break;
1386 default:
1387 err = -EINVAL;
1388 break;
1389 }
1390
1391 return err;
1392 }
1393
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1394 static int mlx5e_set_tunable(struct net_device *dev,
1395 const struct ethtool_tunable *tuna,
1396 const void *data)
1397 {
1398 struct mlx5e_priv *priv = netdev_priv(dev);
1399 int err;
1400
1401 mutex_lock(&priv->state_lock);
1402
1403 switch (tuna->id) {
1404 case ETHTOOL_PFC_PREVENTION_TOUT:
1405 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1406 break;
1407 default:
1408 err = -EINVAL;
1409 break;
1410 }
1411
1412 mutex_unlock(&priv->state_lock);
1413 return err;
1414 }
1415
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1416 static void mlx5e_get_pause_stats(struct net_device *netdev,
1417 struct ethtool_pause_stats *pause_stats)
1418 {
1419 struct mlx5e_priv *priv = netdev_priv(netdev);
1420
1421 mlx5e_stats_pause_get(priv, pause_stats);
1422 }
1423
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1424 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1425 struct ethtool_pauseparam *pauseparam)
1426 {
1427 struct mlx5_core_dev *mdev = priv->mdev;
1428 int err;
1429
1430 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1431 &pauseparam->tx_pause);
1432 if (err) {
1433 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1434 __func__, err);
1435 }
1436 }
1437
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1438 static void mlx5e_get_pauseparam(struct net_device *netdev,
1439 struct ethtool_pauseparam *pauseparam)
1440 {
1441 struct mlx5e_priv *priv = netdev_priv(netdev);
1442
1443 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1444 }
1445
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1446 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1447 struct ethtool_pauseparam *pauseparam)
1448 {
1449 struct mlx5_core_dev *mdev = priv->mdev;
1450 int err;
1451
1452 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1453 return -EOPNOTSUPP;
1454
1455 if (pauseparam->autoneg)
1456 return -EINVAL;
1457
1458 err = mlx5_set_port_pause(mdev,
1459 pauseparam->rx_pause ? 1 : 0,
1460 pauseparam->tx_pause ? 1 : 0);
1461 if (err) {
1462 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1463 __func__, err);
1464 }
1465
1466 return err;
1467 }
1468
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1469 static int mlx5e_set_pauseparam(struct net_device *netdev,
1470 struct ethtool_pauseparam *pauseparam)
1471 {
1472 struct mlx5e_priv *priv = netdev_priv(netdev);
1473
1474 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1475 }
1476
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct ethtool_ts_info * info)1477 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1478 struct ethtool_ts_info *info)
1479 {
1480 struct mlx5_core_dev *mdev = priv->mdev;
1481
1482 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1483
1484 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1485 info->phc_index == -1)
1486 return 0;
1487
1488 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1489 SOF_TIMESTAMPING_RX_HARDWARE |
1490 SOF_TIMESTAMPING_RAW_HARDWARE;
1491
1492 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1493 BIT(HWTSTAMP_TX_ON);
1494
1495 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1496 BIT(HWTSTAMP_FILTER_ALL);
1497
1498 return 0;
1499 }
1500
mlx5e_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1501 static int mlx5e_get_ts_info(struct net_device *dev,
1502 struct ethtool_ts_info *info)
1503 {
1504 struct mlx5e_priv *priv = netdev_priv(dev);
1505
1506 return mlx5e_ethtool_get_ts_info(priv, info);
1507 }
1508
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1509 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1510 {
1511 __u32 ret = 0;
1512
1513 if (MLX5_CAP_GEN(mdev, wol_g))
1514 ret |= WAKE_MAGIC;
1515
1516 if (MLX5_CAP_GEN(mdev, wol_s))
1517 ret |= WAKE_MAGICSECURE;
1518
1519 if (MLX5_CAP_GEN(mdev, wol_a))
1520 ret |= WAKE_ARP;
1521
1522 if (MLX5_CAP_GEN(mdev, wol_b))
1523 ret |= WAKE_BCAST;
1524
1525 if (MLX5_CAP_GEN(mdev, wol_m))
1526 ret |= WAKE_MCAST;
1527
1528 if (MLX5_CAP_GEN(mdev, wol_u))
1529 ret |= WAKE_UCAST;
1530
1531 if (MLX5_CAP_GEN(mdev, wol_p))
1532 ret |= WAKE_PHY;
1533
1534 return ret;
1535 }
1536
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1537 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1538 {
1539 __u32 ret = 0;
1540
1541 if (mode & MLX5_WOL_MAGIC)
1542 ret |= WAKE_MAGIC;
1543
1544 if (mode & MLX5_WOL_SECURED_MAGIC)
1545 ret |= WAKE_MAGICSECURE;
1546
1547 if (mode & MLX5_WOL_ARP)
1548 ret |= WAKE_ARP;
1549
1550 if (mode & MLX5_WOL_BROADCAST)
1551 ret |= WAKE_BCAST;
1552
1553 if (mode & MLX5_WOL_MULTICAST)
1554 ret |= WAKE_MCAST;
1555
1556 if (mode & MLX5_WOL_UNICAST)
1557 ret |= WAKE_UCAST;
1558
1559 if (mode & MLX5_WOL_PHY_ACTIVITY)
1560 ret |= WAKE_PHY;
1561
1562 return ret;
1563 }
1564
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1565 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1566 {
1567 u8 ret = 0;
1568
1569 if (mode & WAKE_MAGIC)
1570 ret |= MLX5_WOL_MAGIC;
1571
1572 if (mode & WAKE_MAGICSECURE)
1573 ret |= MLX5_WOL_SECURED_MAGIC;
1574
1575 if (mode & WAKE_ARP)
1576 ret |= MLX5_WOL_ARP;
1577
1578 if (mode & WAKE_BCAST)
1579 ret |= MLX5_WOL_BROADCAST;
1580
1581 if (mode & WAKE_MCAST)
1582 ret |= MLX5_WOL_MULTICAST;
1583
1584 if (mode & WAKE_UCAST)
1585 ret |= MLX5_WOL_UNICAST;
1586
1587 if (mode & WAKE_PHY)
1588 ret |= MLX5_WOL_PHY_ACTIVITY;
1589
1590 return ret;
1591 }
1592
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1593 static void mlx5e_get_wol(struct net_device *netdev,
1594 struct ethtool_wolinfo *wol)
1595 {
1596 struct mlx5e_priv *priv = netdev_priv(netdev);
1597 struct mlx5_core_dev *mdev = priv->mdev;
1598 u8 mlx5_wol_mode;
1599 int err;
1600
1601 memset(wol, 0, sizeof(*wol));
1602
1603 wol->supported = mlx5e_get_wol_supported(mdev);
1604 if (!wol->supported)
1605 return;
1606
1607 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1608 if (err)
1609 return;
1610
1611 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1612 }
1613
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1614 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1615 {
1616 struct mlx5e_priv *priv = netdev_priv(netdev);
1617 struct mlx5_core_dev *mdev = priv->mdev;
1618 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1619 u32 mlx5_wol_mode;
1620
1621 if (!wol_supported)
1622 return -EOPNOTSUPP;
1623
1624 if (wol->wolopts & ~wol_supported)
1625 return -EINVAL;
1626
1627 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1628
1629 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1630 }
1631
mlx5e_get_fec_stats(struct net_device * netdev,struct ethtool_fec_stats * fec_stats)1632 static void mlx5e_get_fec_stats(struct net_device *netdev,
1633 struct ethtool_fec_stats *fec_stats)
1634 {
1635 struct mlx5e_priv *priv = netdev_priv(netdev);
1636
1637 mlx5e_stats_fec_get(priv, fec_stats);
1638 }
1639
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1640 static int mlx5e_get_fecparam(struct net_device *netdev,
1641 struct ethtool_fecparam *fecparam)
1642 {
1643 struct mlx5e_priv *priv = netdev_priv(netdev);
1644 struct mlx5_core_dev *mdev = priv->mdev;
1645 u16 fec_configured;
1646 u32 fec_active;
1647 int err;
1648
1649 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1650
1651 if (err)
1652 return err;
1653
1654 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1655 sizeof(unsigned long) * BITS_PER_BYTE);
1656
1657 if (!fecparam->active_fec)
1658 return -EOPNOTSUPP;
1659
1660 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1661 sizeof(unsigned long) * BITS_PER_BYTE);
1662
1663 return 0;
1664 }
1665
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1666 static int mlx5e_set_fecparam(struct net_device *netdev,
1667 struct ethtool_fecparam *fecparam)
1668 {
1669 struct mlx5e_priv *priv = netdev_priv(netdev);
1670 struct mlx5_core_dev *mdev = priv->mdev;
1671 unsigned long fec_bitmap;
1672 u16 fec_policy = 0;
1673 int mode;
1674 int err;
1675
1676 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1677 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1678 return -EOPNOTSUPP;
1679
1680 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1681 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1682 continue;
1683 fec_policy |= (1 << mode);
1684 break;
1685 }
1686
1687 err = mlx5e_set_fec_mode(mdev, fec_policy);
1688
1689 if (err)
1690 return err;
1691
1692 mlx5_toggle_port_link(mdev);
1693
1694 return 0;
1695 }
1696
mlx5e_get_msglevel(struct net_device * dev)1697 static u32 mlx5e_get_msglevel(struct net_device *dev)
1698 {
1699 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1700 }
1701
mlx5e_set_msglevel(struct net_device * dev,u32 val)1702 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1703 {
1704 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1705 }
1706
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1707 static int mlx5e_set_phys_id(struct net_device *dev,
1708 enum ethtool_phys_id_state state)
1709 {
1710 struct mlx5e_priv *priv = netdev_priv(dev);
1711 struct mlx5_core_dev *mdev = priv->mdev;
1712 u16 beacon_duration;
1713
1714 if (!MLX5_CAP_GEN(mdev, beacon_led))
1715 return -EOPNOTSUPP;
1716
1717 switch (state) {
1718 case ETHTOOL_ID_ACTIVE:
1719 beacon_duration = MLX5_BEACON_DURATION_INF;
1720 break;
1721 case ETHTOOL_ID_INACTIVE:
1722 beacon_duration = MLX5_BEACON_DURATION_OFF;
1723 break;
1724 default:
1725 return -EOPNOTSUPP;
1726 }
1727
1728 return mlx5_set_port_beacon(mdev, beacon_duration);
1729 }
1730
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1731 static int mlx5e_get_module_info(struct net_device *netdev,
1732 struct ethtool_modinfo *modinfo)
1733 {
1734 struct mlx5e_priv *priv = netdev_priv(netdev);
1735 struct mlx5_core_dev *dev = priv->mdev;
1736 int size_read = 0;
1737 u8 data[4] = {0};
1738
1739 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1740 if (size_read < 2)
1741 return -EIO;
1742
1743 /* data[0] = identifier byte */
1744 switch (data[0]) {
1745 case MLX5_MODULE_ID_QSFP:
1746 modinfo->type = ETH_MODULE_SFF_8436;
1747 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1748 break;
1749 case MLX5_MODULE_ID_QSFP_PLUS:
1750 case MLX5_MODULE_ID_QSFP28:
1751 /* data[1] = revision id */
1752 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1753 modinfo->type = ETH_MODULE_SFF_8636;
1754 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1755 } else {
1756 modinfo->type = ETH_MODULE_SFF_8436;
1757 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1758 }
1759 break;
1760 case MLX5_MODULE_ID_SFP:
1761 modinfo->type = ETH_MODULE_SFF_8472;
1762 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1763 break;
1764 default:
1765 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1766 __func__, data[0]);
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771 }
1772
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1773 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1774 struct ethtool_eeprom *ee,
1775 u8 *data)
1776 {
1777 struct mlx5e_priv *priv = netdev_priv(netdev);
1778 struct mlx5_core_dev *mdev = priv->mdev;
1779 int offset = ee->offset;
1780 int size_read;
1781 int i = 0;
1782
1783 if (!ee->len)
1784 return -EINVAL;
1785
1786 memset(data, 0, ee->len);
1787
1788 while (i < ee->len) {
1789 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1790 data + i);
1791
1792 if (!size_read)
1793 /* Done reading */
1794 return 0;
1795
1796 if (size_read < 0) {
1797 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1798 __func__, size_read);
1799 return size_read;
1800 }
1801
1802 i += size_read;
1803 offset += size_read;
1804 }
1805
1806 return 0;
1807 }
1808
mlx5e_get_module_eeprom_by_page(struct net_device * netdev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)1809 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev,
1810 const struct ethtool_module_eeprom *page_data,
1811 struct netlink_ext_ack *extack)
1812 {
1813 struct mlx5e_priv *priv = netdev_priv(netdev);
1814 struct mlx5_module_eeprom_query_params query;
1815 struct mlx5_core_dev *mdev = priv->mdev;
1816 u8 *data = page_data->data;
1817 int size_read;
1818 int i = 0;
1819
1820 if (!page_data->length)
1821 return -EINVAL;
1822
1823 memset(data, 0, page_data->length);
1824
1825 query.offset = page_data->offset;
1826 query.i2c_address = page_data->i2c_address;
1827 query.bank = page_data->bank;
1828 query.page = page_data->page;
1829 while (i < page_data->length) {
1830 query.size = page_data->length - i;
1831 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i);
1832
1833 /* Done reading, return how many bytes was read */
1834 if (!size_read)
1835 return i;
1836
1837 if (size_read == -EINVAL)
1838 return -EINVAL;
1839 if (size_read < 0) {
1840 netdev_err(priv->netdev, "%s: mlx5_query_module_eeprom_by_page failed:0x%x\n",
1841 __func__, size_read);
1842 return i;
1843 }
1844
1845 i += size_read;
1846 query.offset += size_read;
1847 }
1848
1849 return i;
1850 }
1851
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)1852 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1853 struct ethtool_flash *flash)
1854 {
1855 struct mlx5_core_dev *mdev = priv->mdev;
1856 struct net_device *dev = priv->netdev;
1857 const struct firmware *fw;
1858 int err;
1859
1860 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1861 return -EOPNOTSUPP;
1862
1863 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1864 if (err)
1865 return err;
1866
1867 dev_hold(dev);
1868 rtnl_unlock();
1869
1870 err = mlx5_firmware_flash(mdev, fw, NULL);
1871 release_firmware(fw);
1872
1873 rtnl_lock();
1874 dev_put(dev);
1875 return err;
1876 }
1877
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)1878 static int mlx5e_flash_device(struct net_device *dev,
1879 struct ethtool_flash *flash)
1880 {
1881 struct mlx5e_priv *priv = netdev_priv(dev);
1882
1883 return mlx5e_ethtool_flash_device(priv, flash);
1884 }
1885
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)1886 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1887 bool is_rx_cq)
1888 {
1889 struct mlx5e_priv *priv = netdev_priv(netdev);
1890 u8 cq_period_mode, current_cq_period_mode;
1891 struct mlx5e_params new_params;
1892
1893 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1894 return -EOPNOTSUPP;
1895
1896 cq_period_mode = cqe_mode_to_period_mode(enable);
1897
1898 current_cq_period_mode = is_rx_cq ?
1899 priv->channels.params.rx_cq_moderation.cq_period_mode :
1900 priv->channels.params.tx_cq_moderation.cq_period_mode;
1901
1902 if (cq_period_mode == current_cq_period_mode)
1903 return 0;
1904
1905 new_params = priv->channels.params;
1906 if (is_rx_cq)
1907 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode);
1908 else
1909 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode);
1910
1911 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
1912 }
1913
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)1914 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1915 {
1916 return set_pflag_cqe_based_moder(netdev, enable, false);
1917 }
1918
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)1919 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1920 {
1921 return set_pflag_cqe_based_moder(netdev, enable, true);
1922 }
1923
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val,bool rx_filter)1924 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
1925 {
1926 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1927 struct mlx5e_params new_params;
1928 int err = 0;
1929
1930 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1931 return new_val ? -EOPNOTSUPP : 0;
1932
1933 if (curr_val == new_val)
1934 return 0;
1935
1936 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) {
1937 netdev_err(priv->netdev,
1938 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
1939 return -EINVAL;
1940 }
1941
1942 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
1943 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n");
1944 return -EINVAL;
1945 }
1946
1947 new_params = priv->channels.params;
1948 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1949 if (rx_filter)
1950 new_params.ptp_rx = new_val;
1951
1952 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
1953 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
1954 else
1955 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
1956 &new_params.ptp_rx, true);
1957 if (err)
1958 return err;
1959
1960 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1961 MLX5E_GET_PFLAG(&priv->channels.params,
1962 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1963
1964 return 0;
1965 }
1966
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)1967 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1968 bool enable)
1969 {
1970 struct mlx5e_priv *priv = netdev_priv(netdev);
1971 struct mlx5_core_dev *mdev = priv->mdev;
1972 bool rx_filter;
1973 int err;
1974
1975 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1976 return -EOPNOTSUPP;
1977
1978 rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE;
1979 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
1980 if (err)
1981 return err;
1982
1983 priv->channels.params.rx_cqe_compress_def = enable;
1984
1985 return 0;
1986 }
1987
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)1988 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1989 {
1990 struct mlx5e_priv *priv = netdev_priv(netdev);
1991 struct mlx5_core_dev *mdev = priv->mdev;
1992 struct mlx5e_params new_params;
1993
1994 if (enable) {
1995 /* Checking the regular RQ here; mlx5e_validate_xsk_param called
1996 * from mlx5e_open_xsk will check for each XSK queue, and
1997 * mlx5e_safe_switch_params will be reverted if any check fails.
1998 */
1999 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params);
2000
2001 if (err)
2002 return err;
2003 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
2004 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n");
2005 return -EINVAL;
2006 }
2007
2008 new_params = priv->channels.params;
2009
2010 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
2011 mlx5e_set_rq_type(mdev, &new_params);
2012
2013 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2014 }
2015
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)2016 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
2017 {
2018 struct mlx5e_priv *priv = netdev_priv(netdev);
2019 struct mlx5e_channels *channels = &priv->channels;
2020 struct mlx5e_channel *c;
2021 int i;
2022
2023 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
2024 priv->channels.params.xdp_prog)
2025 return 0;
2026
2027 for (i = 0; i < channels->num; i++) {
2028 c = channels->c[i];
2029 if (enable)
2030 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2031 else
2032 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2033 }
2034
2035 return 0;
2036 }
2037
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)2038 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
2039 {
2040 struct mlx5e_priv *priv = netdev_priv(netdev);
2041 struct mlx5_core_dev *mdev = priv->mdev;
2042 struct mlx5e_params new_params;
2043
2044 if (enable && !mlx5e_tx_mpwqe_supported(mdev))
2045 return -EOPNOTSUPP;
2046
2047 new_params = priv->channels.params;
2048
2049 MLX5E_SET_PFLAG(&new_params, flag, enable);
2050
2051 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2052 }
2053
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)2054 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
2055 {
2056 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
2057 }
2058
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)2059 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
2060 {
2061 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
2062 }
2063
set_pflag_tx_port_ts(struct net_device * netdev,bool enable)2064 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
2065 {
2066 struct mlx5e_priv *priv = netdev_priv(netdev);
2067 struct mlx5_core_dev *mdev = priv->mdev;
2068 struct mlx5e_params new_params;
2069 int err;
2070
2071 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
2072 return -EOPNOTSUPP;
2073
2074 /* Don't allow changing the PTP state if HTB offload is active, because
2075 * the numeration of the QoS SQs will change, while per-queue qdiscs are
2076 * attached.
2077 */
2078 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
2079 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
2080 __func__);
2081 return -EINVAL;
2082 }
2083
2084 new_params = priv->channels.params;
2085 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is
2086 * active, since it defines explicitly which TC accepts the packet.
2087 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific
2088 * HW TX-queue.
2089 */
2090 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
2091 netdev_err(priv->netdev,
2092 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n",
2093 __func__);
2094 return -EINVAL;
2095 }
2096 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable);
2097 /* No need to verify SQ stop room as
2098 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2099 * has the same log_sq_size.
2100 */
2101
2102 err = mlx5e_safe_switch_params(priv, &new_params,
2103 mlx5e_num_channels_changed_ctx, NULL, true);
2104 if (!err)
2105 priv->tx_ptp_opened = true;
2106
2107 return err;
2108 }
2109
2110 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2111 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
2112 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
2113 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
2114 { "rx_striding_rq", set_pflag_rx_striding_rq },
2115 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2116 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
2117 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
2118 { "tx_port_ts", set_pflag_tx_port_ts },
2119 };
2120
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)2121 static int mlx5e_handle_pflag(struct net_device *netdev,
2122 u32 wanted_flags,
2123 enum mlx5e_priv_flag flag)
2124 {
2125 struct mlx5e_priv *priv = netdev_priv(netdev);
2126 bool enable = !!(wanted_flags & BIT(flag));
2127 u32 changes = wanted_flags ^ priv->channels.params.pflags;
2128 int err;
2129
2130 if (!(changes & BIT(flag)))
2131 return 0;
2132
2133 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2134 if (err) {
2135 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2136 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2137 return err;
2138 }
2139
2140 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2141 return 0;
2142 }
2143
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2144 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2145 {
2146 struct mlx5e_priv *priv = netdev_priv(netdev);
2147 enum mlx5e_priv_flag pflag;
2148 int err;
2149
2150 mutex_lock(&priv->state_lock);
2151
2152 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2153 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2154 if (err)
2155 break;
2156 }
2157
2158 mutex_unlock(&priv->state_lock);
2159
2160 /* Need to fix some features.. */
2161 netdev_update_features(netdev);
2162
2163 return err;
2164 }
2165
mlx5e_get_priv_flags(struct net_device * netdev)2166 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2167 {
2168 struct mlx5e_priv *priv = netdev_priv(netdev);
2169
2170 return priv->channels.params.pflags;
2171 }
2172
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2173 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2174 u32 *rule_locs)
2175 {
2176 struct mlx5e_priv *priv = netdev_priv(dev);
2177
2178 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2179 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2180 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2181 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2182 */
2183 if (info->cmd == ETHTOOL_GRXRINGS) {
2184 info->data = priv->channels.params.num_channels;
2185 return 0;
2186 }
2187
2188 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs);
2189 }
2190
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2191 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2192 {
2193 struct mlx5e_priv *priv = netdev_priv(dev);
2194
2195 return mlx5e_ethtool_set_rxnfc(priv, cmd);
2196 }
2197
query_port_status_opcode(struct mlx5_core_dev * mdev,u32 * status_opcode)2198 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode)
2199 {
2200 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page;
2201 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {};
2202 u32 out[MLX5_ST_SZ_DW(pddr_reg)];
2203 int err;
2204
2205 MLX5_SET(pddr_reg, in, local_port, 1);
2206 MLX5_SET(pddr_reg, in, page_select,
2207 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE);
2208
2209 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data);
2210 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2211 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR);
2212 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
2213 sizeof(out), MLX5_REG_PDDR, 0, 0);
2214 if (err)
2215 return err;
2216
2217 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data);
2218 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2219 status_opcode);
2220 return 0;
2221 }
2222
2223 struct mlx5e_ethtool_link_ext_state_opcode_mapping {
2224 u32 status_opcode;
2225 enum ethtool_link_ext_state link_ext_state;
2226 u8 link_ext_substate;
2227 };
2228
2229 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping
2230 mlx5e_link_ext_state_opcode_map[] = {
2231 /* States relating to the autonegotiation or issues therein */
2232 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2233 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
2234 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2235 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
2236 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2237 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
2238 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2239 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
2240 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2241 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
2242 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2243 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
2244
2245 /* Failure during link training */
2246 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2247 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
2248 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2249 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
2250 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2251 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
2252 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
2253 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2254 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
2255
2256 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */
2257 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2258 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
2259 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2260 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
2261 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2262 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
2263 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2264 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
2265 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2266 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
2267
2268 /* Signal integrity issues */
2269 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
2270 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2271 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
2272 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2273 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
2274
2275 /* No cable connected */
2276 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
2277
2278 /* Failure is related to cable, e.g., unsupported cable */
2279 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2280 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2281 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2282 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2283 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2284 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2285 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2286 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2287 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2288 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2289 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
2290
2291 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */
2292 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
2293
2294 /* Failure during calibration algorithm */
2295 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
2296
2297 /* The hardware is not able to provide the power required from cable or module */
2298 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
2299
2300 /* The module is overheated */
2301 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
2302 };
2303
2304 static void
mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)2305 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping
2306 link_ext_state_mapping,
2307 struct ethtool_link_ext_state_info *link_ext_state_info)
2308 {
2309 switch (link_ext_state_mapping.link_ext_state) {
2310 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
2311 link_ext_state_info->autoneg =
2312 link_ext_state_mapping.link_ext_substate;
2313 break;
2314 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
2315 link_ext_state_info->link_training =
2316 link_ext_state_mapping.link_ext_substate;
2317 break;
2318 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
2319 link_ext_state_info->link_logical_mismatch =
2320 link_ext_state_mapping.link_ext_substate;
2321 break;
2322 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
2323 link_ext_state_info->bad_signal_integrity =
2324 link_ext_state_mapping.link_ext_substate;
2325 break;
2326 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
2327 link_ext_state_info->cable_issue =
2328 link_ext_state_mapping.link_ext_substate;
2329 break;
2330 default:
2331 break;
2332 }
2333
2334 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
2335 }
2336
2337 static int
mlx5e_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)2338 mlx5e_get_link_ext_state(struct net_device *dev,
2339 struct ethtool_link_ext_state_info *link_ext_state_info)
2340 {
2341 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
2342 struct mlx5e_priv *priv = netdev_priv(dev);
2343 u32 status_opcode = 0;
2344 int i;
2345
2346 /* Exit without data if the interface state is OK, since no extended data is
2347 * available in such case
2348 */
2349 if (netif_carrier_ok(dev))
2350 return -ENODATA;
2351
2352 if (query_port_status_opcode(priv->mdev, &status_opcode) ||
2353 !status_opcode)
2354 return -ENODATA;
2355
2356 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) {
2357 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i];
2358 if (link_ext_state_mapping.status_opcode == status_opcode) {
2359 mlx5e_set_link_ext_state(link_ext_state_mapping,
2360 link_ext_state_info);
2361 return 0;
2362 }
2363 }
2364
2365 return -ENODATA;
2366 }
2367
mlx5e_get_eth_phy_stats(struct net_device * netdev,struct ethtool_eth_phy_stats * phy_stats)2368 static void mlx5e_get_eth_phy_stats(struct net_device *netdev,
2369 struct ethtool_eth_phy_stats *phy_stats)
2370 {
2371 struct mlx5e_priv *priv = netdev_priv(netdev);
2372
2373 mlx5e_stats_eth_phy_get(priv, phy_stats);
2374 }
2375
mlx5e_get_eth_mac_stats(struct net_device * netdev,struct ethtool_eth_mac_stats * mac_stats)2376 static void mlx5e_get_eth_mac_stats(struct net_device *netdev,
2377 struct ethtool_eth_mac_stats *mac_stats)
2378 {
2379 struct mlx5e_priv *priv = netdev_priv(netdev);
2380
2381 mlx5e_stats_eth_mac_get(priv, mac_stats);
2382 }
2383
mlx5e_get_eth_ctrl_stats(struct net_device * netdev,struct ethtool_eth_ctrl_stats * ctrl_stats)2384 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev,
2385 struct ethtool_eth_ctrl_stats *ctrl_stats)
2386 {
2387 struct mlx5e_priv *priv = netdev_priv(netdev);
2388
2389 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats);
2390 }
2391
mlx5e_get_rmon_stats(struct net_device * netdev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)2392 static void mlx5e_get_rmon_stats(struct net_device *netdev,
2393 struct ethtool_rmon_stats *rmon_stats,
2394 const struct ethtool_rmon_hist_range **ranges)
2395 {
2396 struct mlx5e_priv *priv = netdev_priv(netdev);
2397
2398 mlx5e_stats_rmon_get(priv, rmon_stats, ranges);
2399 }
2400
2401 const struct ethtool_ops mlx5e_ethtool_ops = {
2402 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2403 ETHTOOL_COALESCE_MAX_FRAMES |
2404 ETHTOOL_COALESCE_USE_ADAPTIVE |
2405 ETHTOOL_COALESCE_USE_CQE,
2406 .get_drvinfo = mlx5e_get_drvinfo,
2407 .get_link = ethtool_op_get_link,
2408 .get_link_ext_state = mlx5e_get_link_ext_state,
2409 .get_strings = mlx5e_get_strings,
2410 .get_sset_count = mlx5e_get_sset_count,
2411 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2412 .get_ringparam = mlx5e_get_ringparam,
2413 .set_ringparam = mlx5e_set_ringparam,
2414 .get_channels = mlx5e_get_channels,
2415 .set_channels = mlx5e_set_channels,
2416 .get_coalesce = mlx5e_get_coalesce,
2417 .set_coalesce = mlx5e_set_coalesce,
2418 .get_link_ksettings = mlx5e_get_link_ksettings,
2419 .set_link_ksettings = mlx5e_set_link_ksettings,
2420 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2421 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2422 .get_rxfh = mlx5e_get_rxfh,
2423 .set_rxfh = mlx5e_set_rxfh,
2424 .get_rxfh_context = mlx5e_get_rxfh_context,
2425 .set_rxfh_context = mlx5e_set_rxfh_context,
2426 .get_rxnfc = mlx5e_get_rxnfc,
2427 .set_rxnfc = mlx5e_set_rxnfc,
2428 .get_tunable = mlx5e_get_tunable,
2429 .set_tunable = mlx5e_set_tunable,
2430 .get_pause_stats = mlx5e_get_pause_stats,
2431 .get_pauseparam = mlx5e_get_pauseparam,
2432 .set_pauseparam = mlx5e_set_pauseparam,
2433 .get_ts_info = mlx5e_get_ts_info,
2434 .set_phys_id = mlx5e_set_phys_id,
2435 .get_wol = mlx5e_get_wol,
2436 .set_wol = mlx5e_set_wol,
2437 .get_module_info = mlx5e_get_module_info,
2438 .get_module_eeprom = mlx5e_get_module_eeprom,
2439 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page,
2440 .flash_device = mlx5e_flash_device,
2441 .get_priv_flags = mlx5e_get_priv_flags,
2442 .set_priv_flags = mlx5e_set_priv_flags,
2443 .self_test = mlx5e_self_test,
2444 .get_msglevel = mlx5e_get_msglevel,
2445 .set_msglevel = mlx5e_set_msglevel,
2446 .get_fec_stats = mlx5e_get_fec_stats,
2447 .get_fecparam = mlx5e_get_fecparam,
2448 .set_fecparam = mlx5e_set_fecparam,
2449 .get_eth_phy_stats = mlx5e_get_eth_phy_stats,
2450 .get_eth_mac_stats = mlx5e_get_eth_mac_stats,
2451 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats,
2452 .get_rmon_stats = mlx5e_get_rmon_stats,
2453 };
2454