1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2022 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12
13 static int
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27 {
28 writeq(b, addr);
29 }
30 #else
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32 {
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37 }
38 #endif
39
40 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42 {
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54 }
55
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57 {
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64 }
65
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67 {
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70 }
71
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73 {
74 mrioc->intr_enabled = 1;
75 }
76
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78 {
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95 }
96
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99 {
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105 }
106
mpi3mr_build_zero_len_sge(void * paddr)107 void mpi3mr_build_zero_len_sge(void *paddr)
108 {
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112 }
113
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116 {
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125 }
126
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129 {
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134 }
135
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138 {
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152 }
153
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156 {
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169 }
170
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173 {
174 char *desc = NULL;
175 u16 event;
176
177 event = event_reply->event;
178
179 switch (event) {
180 case MPI3_EVENT_LOG_DATA:
181 desc = "Log Data";
182 break;
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
185 break;
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
188 break;
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
191 break;
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
194 break;
195 case MPI3_EVENT_DEVICE_ADDED:
196 {
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
201 return;
202 }
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
204 {
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
209 return;
210 }
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
212 {
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
217 return;
218 }
219 case MPI3_EVENT_SAS_DISCOVERY:
220 {
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
225 "start" : "stop",
226 le32_to_cpu(event_data->discovery_status));
227 return;
228 }
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
231 break;
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
234 break;
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
237 break;
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
240 break;
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
243 break;
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
249 break;
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
252 break;
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
255 break;
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
258 break;
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
261 break;
262 case MPI3_EVENT_PCIE_ENUMERATION:
263 {
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
272 return;
273 }
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
276 break;
277 }
278
279 if (!desc)
280 return;
281
282 ioc_info(mrioc, "%s\n", desc);
283 }
284
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
286 struct mpi3_default_reply *def_reply)
287 {
288 struct mpi3_event_notification_reply *event_reply =
289 (struct mpi3_event_notification_reply *)def_reply;
290
291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
292 mpi3mr_print_event_data(mrioc, event_reply);
293 mpi3mr_os_handle_events(mrioc, event_reply);
294 }
295
296 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
298 struct mpi3_default_reply *def_reply)
299 {
300 u16 idx;
301
302 switch (host_tag) {
303 case MPI3MR_HOSTTAG_INITCMDS:
304 return &mrioc->init_cmds;
305 case MPI3MR_HOSTTAG_CFG_CMDS:
306 return &mrioc->cfg_cmds;
307 case MPI3MR_HOSTTAG_BSG_CMDS:
308 return &mrioc->bsg_cmds;
309 case MPI3MR_HOSTTAG_BLK_TMS:
310 return &mrioc->host_tm_cmds;
311 case MPI3MR_HOSTTAG_PEL_ABORT:
312 return &mrioc->pel_abort_cmd;
313 case MPI3MR_HOSTTAG_PEL_WAIT:
314 return &mrioc->pel_cmds;
315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
316 return &mrioc->transport_cmds;
317 case MPI3MR_HOSTTAG_INVALID:
318 if (def_reply && def_reply->function ==
319 MPI3_FUNCTION_EVENT_NOTIFICATION)
320 mpi3mr_handle_events(mrioc, def_reply);
321 return NULL;
322 default:
323 break;
324 }
325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
328 return &mrioc->dev_rmhs_cmds[idx];
329 }
330
331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
334 return &mrioc->evtack_cmds[idx];
335 }
336
337 return NULL;
338 }
339
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
342 {
343 u16 reply_desc_type, host_tag = 0;
344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
345 u32 ioc_loginfo = 0;
346 struct mpi3_status_reply_descriptor *status_desc;
347 struct mpi3_address_reply_descriptor *addr_desc;
348 struct mpi3_success_reply_descriptor *success_desc;
349 struct mpi3_default_reply *def_reply = NULL;
350 struct mpi3mr_drv_cmd *cmdptr = NULL;
351 struct mpi3_scsi_io_reply *scsi_reply;
352 u8 *sense_buf = NULL;
353
354 *reply_dma = 0;
355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
357 switch (reply_desc_type) {
358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
360 host_tag = le16_to_cpu(status_desc->host_tag);
361 ioc_status = le16_to_cpu(status_desc->ioc_status);
362 if (ioc_status &
363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
366 break;
367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
371 if (!def_reply)
372 goto out;
373 host_tag = le16_to_cpu(def_reply->host_tag);
374 ioc_status = le16_to_cpu(def_reply->ioc_status);
375 if (ioc_status &
376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
382 le64_to_cpu(scsi_reply->sense_data_buffer_address));
383 }
384 break;
385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
387 host_tag = le16_to_cpu(success_desc->host_tag);
388 break;
389 default:
390 break;
391 }
392
393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
394 if (cmdptr) {
395 if (cmdptr->state & MPI3MR_CMD_PENDING) {
396 cmdptr->state |= MPI3MR_CMD_COMPLETE;
397 cmdptr->ioc_loginfo = ioc_loginfo;
398 cmdptr->ioc_status = ioc_status;
399 cmdptr->state &= ~MPI3MR_CMD_PENDING;
400 if (def_reply) {
401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
403 mrioc->reply_sz);
404 }
405 if (sense_buf && cmdptr->sensebuf) {
406 cmdptr->is_sense = 1;
407 memcpy(cmdptr->sensebuf, sense_buf,
408 MPI3MR_SENSE_BUF_SZ);
409 }
410 if (cmdptr->is_waiting) {
411 complete(&cmdptr->done);
412 cmdptr->is_waiting = 0;
413 } else if (cmdptr->callback)
414 cmdptr->callback(mrioc, cmdptr);
415 }
416 }
417 out:
418 if (sense_buf)
419 mpi3mr_repost_sense_buf(mrioc,
420 le64_to_cpu(scsi_reply->sense_data_buffer_address));
421 }
422
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)423 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
424 {
425 u32 exp_phase = mrioc->admin_reply_ephase;
426 u32 admin_reply_ci = mrioc->admin_reply_ci;
427 u32 num_admin_replies = 0;
428 u64 reply_dma = 0;
429 struct mpi3_default_reply_descriptor *reply_desc;
430
431 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
432 return 0;
433
434 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
435 admin_reply_ci;
436
437 if ((le16_to_cpu(reply_desc->reply_flags) &
438 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
439 atomic_dec(&mrioc->admin_reply_q_in_use);
440 return 0;
441 }
442
443 do {
444 if (mrioc->unrecoverable)
445 break;
446
447 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
448 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
449 if (reply_dma)
450 mpi3mr_repost_reply_buf(mrioc, reply_dma);
451 num_admin_replies++;
452 if (++admin_reply_ci == mrioc->num_admin_replies) {
453 admin_reply_ci = 0;
454 exp_phase ^= 1;
455 }
456 reply_desc =
457 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
458 admin_reply_ci;
459 if ((le16_to_cpu(reply_desc->reply_flags) &
460 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
461 break;
462 } while (1);
463
464 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
465 mrioc->admin_reply_ci = admin_reply_ci;
466 mrioc->admin_reply_ephase = exp_phase;
467 atomic_dec(&mrioc->admin_reply_q_in_use);
468
469 return num_admin_replies;
470 }
471
472 /**
473 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
474 * queue's consumer index from operational reply descriptor queue.
475 * @op_reply_q: op_reply_qinfo object
476 * @reply_ci: operational reply descriptor's queue consumer index
477 *
478 * Returns reply descriptor frame address
479 */
480 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)481 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
482 {
483 void *segment_base_addr;
484 struct segments *segments = op_reply_q->q_segments;
485 struct mpi3_default_reply_descriptor *reply_desc = NULL;
486
487 segment_base_addr =
488 segments[reply_ci / op_reply_q->segment_qd].segment;
489 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
490 (reply_ci % op_reply_q->segment_qd);
491 return reply_desc;
492 }
493
494 /**
495 * mpi3mr_process_op_reply_q - Operational reply queue handler
496 * @mrioc: Adapter instance reference
497 * @op_reply_q: Operational reply queue info
498 *
499 * Checks the specific operational reply queue and drains the
500 * reply queue entries until the queue is empty and process the
501 * individual reply descriptors.
502 *
503 * Return: 0 if queue is already processed,or number of reply
504 * descriptors processed.
505 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)506 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
507 struct op_reply_qinfo *op_reply_q)
508 {
509 struct op_req_qinfo *op_req_q;
510 u32 exp_phase;
511 u32 reply_ci;
512 u32 num_op_reply = 0;
513 u64 reply_dma = 0;
514 struct mpi3_default_reply_descriptor *reply_desc;
515 u16 req_q_idx = 0, reply_qidx;
516
517 reply_qidx = op_reply_q->qid - 1;
518
519 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
520 return 0;
521
522 exp_phase = op_reply_q->ephase;
523 reply_ci = op_reply_q->ci;
524
525 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
526 if ((le16_to_cpu(reply_desc->reply_flags) &
527 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
528 atomic_dec(&op_reply_q->in_use);
529 return 0;
530 }
531
532 do {
533 if (mrioc->unrecoverable)
534 break;
535
536 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
537 op_req_q = &mrioc->req_qinfo[req_q_idx];
538
539 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
540 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
541 reply_qidx);
542 atomic_dec(&op_reply_q->pend_ios);
543 if (reply_dma)
544 mpi3mr_repost_reply_buf(mrioc, reply_dma);
545 num_op_reply++;
546
547 if (++reply_ci == op_reply_q->num_replies) {
548 reply_ci = 0;
549 exp_phase ^= 1;
550 }
551
552 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
553
554 if ((le16_to_cpu(reply_desc->reply_flags) &
555 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
556 break;
557 #ifndef CONFIG_PREEMPT_RT
558 /*
559 * Exit completion loop to avoid CPU lockup
560 * Ensure remaining completion happens from threaded ISR.
561 */
562 if (num_op_reply > mrioc->max_host_ios) {
563 op_reply_q->enable_irq_poll = true;
564 break;
565 }
566 #endif
567 } while (1);
568
569 writel(reply_ci,
570 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
571 op_reply_q->ci = reply_ci;
572 op_reply_q->ephase = exp_phase;
573
574 atomic_dec(&op_reply_q->in_use);
575 return num_op_reply;
576 }
577
578 /**
579 * mpi3mr_blk_mq_poll - Operational reply queue handler
580 * @shost: SCSI Host reference
581 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
582 *
583 * Checks the specific operational reply queue and drains the
584 * reply queue entries until the queue is empty and process the
585 * individual reply descriptors.
586 *
587 * Return: 0 if queue is already processed,or number of reply
588 * descriptors processed.
589 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)590 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
591 {
592 int num_entries = 0;
593 struct mpi3mr_ioc *mrioc;
594
595 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
596
597 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
598 mrioc->unrecoverable))
599 return 0;
600
601 num_entries = mpi3mr_process_op_reply_q(mrioc,
602 &mrioc->op_reply_qinfo[queue_num]);
603
604 return num_entries;
605 }
606
mpi3mr_isr_primary(int irq,void * privdata)607 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
608 {
609 struct mpi3mr_intr_info *intr_info = privdata;
610 struct mpi3mr_ioc *mrioc;
611 u16 midx;
612 u32 num_admin_replies = 0, num_op_reply = 0;
613
614 if (!intr_info)
615 return IRQ_NONE;
616
617 mrioc = intr_info->mrioc;
618
619 if (!mrioc->intr_enabled)
620 return IRQ_NONE;
621
622 midx = intr_info->msix_index;
623
624 if (!midx)
625 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
626 if (intr_info->op_reply_q)
627 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
628 intr_info->op_reply_q);
629
630 if (num_admin_replies || num_op_reply)
631 return IRQ_HANDLED;
632 else
633 return IRQ_NONE;
634 }
635
636 #ifndef CONFIG_PREEMPT_RT
637
mpi3mr_isr(int irq,void * privdata)638 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
639 {
640 struct mpi3mr_intr_info *intr_info = privdata;
641 int ret;
642
643 if (!intr_info)
644 return IRQ_NONE;
645
646 /* Call primary ISR routine */
647 ret = mpi3mr_isr_primary(irq, privdata);
648
649 /*
650 * If more IOs are expected, schedule IRQ polling thread.
651 * Otherwise exit from ISR.
652 */
653 if (!intr_info->op_reply_q)
654 return ret;
655
656 if (!intr_info->op_reply_q->enable_irq_poll ||
657 !atomic_read(&intr_info->op_reply_q->pend_ios))
658 return ret;
659
660 disable_irq_nosync(intr_info->os_irq);
661
662 return IRQ_WAKE_THREAD;
663 }
664
665 /**
666 * mpi3mr_isr_poll - Reply queue polling routine
667 * @irq: IRQ
668 * @privdata: Interrupt info
669 *
670 * poll for pending I/O completions in a loop until pending I/Os
671 * present or controller queue depth I/Os are processed.
672 *
673 * Return: IRQ_NONE or IRQ_HANDLED
674 */
mpi3mr_isr_poll(int irq,void * privdata)675 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
676 {
677 struct mpi3mr_intr_info *intr_info = privdata;
678 struct mpi3mr_ioc *mrioc;
679 u16 midx;
680 u32 num_op_reply = 0;
681
682 if (!intr_info || !intr_info->op_reply_q)
683 return IRQ_NONE;
684
685 mrioc = intr_info->mrioc;
686 midx = intr_info->msix_index;
687
688 /* Poll for pending IOs completions */
689 do {
690 if (!mrioc->intr_enabled || mrioc->unrecoverable)
691 break;
692
693 if (!midx)
694 mpi3mr_process_admin_reply_q(mrioc);
695 if (intr_info->op_reply_q)
696 num_op_reply +=
697 mpi3mr_process_op_reply_q(mrioc,
698 intr_info->op_reply_q);
699
700 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
701
702 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
703 (num_op_reply < mrioc->max_host_ios));
704
705 intr_info->op_reply_q->enable_irq_poll = false;
706 enable_irq(intr_info->os_irq);
707
708 return IRQ_HANDLED;
709 }
710
711 #endif
712
713 /**
714 * mpi3mr_request_irq - Request IRQ and register ISR
715 * @mrioc: Adapter instance reference
716 * @index: IRQ vector index
717 *
718 * Request threaded ISR with primary ISR and secondary
719 *
720 * Return: 0 on success and non zero on failures.
721 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)722 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
723 {
724 struct pci_dev *pdev = mrioc->pdev;
725 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
726 int retval = 0;
727
728 intr_info->mrioc = mrioc;
729 intr_info->msix_index = index;
730 intr_info->op_reply_q = NULL;
731
732 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
733 mrioc->driver_name, mrioc->id, index);
734
735 #ifndef CONFIG_PREEMPT_RT
736 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
737 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
738 #else
739 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
740 NULL, IRQF_SHARED, intr_info->name, intr_info);
741 #endif
742 if (retval) {
743 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
744 intr_info->name, pci_irq_vector(pdev, index));
745 return retval;
746 }
747
748 intr_info->os_irq = pci_irq_vector(pdev, index);
749 return retval;
750 }
751
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)752 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
753 {
754 if (!mrioc->requested_poll_qcount)
755 return;
756
757 /* Reserved for Admin and Default Queue */
758 if (max_vectors > 2 &&
759 (mrioc->requested_poll_qcount < max_vectors - 2)) {
760 ioc_info(mrioc,
761 "enabled polled queues (%d) msix (%d)\n",
762 mrioc->requested_poll_qcount, max_vectors);
763 } else {
764 ioc_info(mrioc,
765 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
766 mrioc->requested_poll_qcount, max_vectors);
767 mrioc->requested_poll_qcount = 0;
768 }
769 }
770
771 /**
772 * mpi3mr_setup_isr - Setup ISR for the controller
773 * @mrioc: Adapter instance reference
774 * @setup_one: Request one IRQ or more
775 *
776 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
777 *
778 * Return: 0 on success and non zero on failures.
779 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)780 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
781 {
782 unsigned int irq_flags = PCI_IRQ_MSIX;
783 int max_vectors, min_vec;
784 int retval;
785 int i;
786 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
787
788 if (mrioc->is_intr_info_set)
789 return 0;
790
791 mpi3mr_cleanup_isr(mrioc);
792
793 if (setup_one || reset_devices) {
794 max_vectors = 1;
795 retval = pci_alloc_irq_vectors(mrioc->pdev,
796 1, max_vectors, irq_flags);
797 if (retval < 0) {
798 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
799 retval);
800 goto out_failed;
801 }
802 } else {
803 max_vectors =
804 min_t(int, mrioc->cpu_count + 1 +
805 mrioc->requested_poll_qcount, mrioc->msix_count);
806
807 mpi3mr_calc_poll_queues(mrioc, max_vectors);
808
809 ioc_info(mrioc,
810 "MSI-X vectors supported: %d, no of cores: %d,",
811 mrioc->msix_count, mrioc->cpu_count);
812 ioc_info(mrioc,
813 "MSI-x vectors requested: %d poll_queues %d\n",
814 max_vectors, mrioc->requested_poll_qcount);
815
816 desc.post_vectors = mrioc->requested_poll_qcount;
817 min_vec = desc.pre_vectors + desc.post_vectors;
818 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
819
820 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
821 min_vec, max_vectors, irq_flags, &desc);
822
823 if (retval < 0) {
824 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
825 retval);
826 goto out_failed;
827 }
828
829
830 /*
831 * If only one MSI-x is allocated, then MSI-x 0 will be shared
832 * between Admin queue and operational queue
833 */
834 if (retval == min_vec)
835 mrioc->op_reply_q_offset = 0;
836 else if (retval != (max_vectors)) {
837 ioc_info(mrioc,
838 "allocated vectors (%d) are less than configured (%d)\n",
839 retval, max_vectors);
840 }
841
842 max_vectors = retval;
843 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
844
845 mpi3mr_calc_poll_queues(mrioc, max_vectors);
846
847 }
848
849 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
850 GFP_KERNEL);
851 if (!mrioc->intr_info) {
852 retval = -ENOMEM;
853 pci_free_irq_vectors(mrioc->pdev);
854 goto out_failed;
855 }
856 for (i = 0; i < max_vectors; i++) {
857 retval = mpi3mr_request_irq(mrioc, i);
858 if (retval) {
859 mrioc->intr_info_count = i;
860 goto out_failed;
861 }
862 }
863 if (reset_devices || !setup_one)
864 mrioc->is_intr_info_set = true;
865 mrioc->intr_info_count = max_vectors;
866 mpi3mr_ioc_enable_intr(mrioc);
867 return 0;
868
869 out_failed:
870 mpi3mr_cleanup_isr(mrioc);
871
872 return retval;
873 }
874
875 static const struct {
876 enum mpi3mr_iocstate value;
877 char *name;
878 } mrioc_states[] = {
879 { MRIOC_STATE_READY, "ready" },
880 { MRIOC_STATE_FAULT, "fault" },
881 { MRIOC_STATE_RESET, "reset" },
882 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
883 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
884 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
885 };
886
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)887 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
888 {
889 int i;
890 char *name = NULL;
891
892 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
893 if (mrioc_states[i].value == mrioc_state) {
894 name = mrioc_states[i].name;
895 break;
896 }
897 }
898 return name;
899 }
900
901 /* Reset reason to name mapper structure*/
902 static const struct {
903 enum mpi3mr_reset_reason value;
904 char *name;
905 } mpi3mr_reset_reason_codes[] = {
906 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
907 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
908 { MPI3MR_RESET_FROM_APP, "application invocation" },
909 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
910 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
911 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
912 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
913 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
914 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
915 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
916 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
917 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
918 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
919 {
920 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
921 "create request queue timeout"
922 },
923 {
924 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
925 "create reply queue timeout"
926 },
927 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
928 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
929 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
930 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
931 {
932 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
933 "component image activation timeout"
934 },
935 {
936 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
937 "get package version timeout"
938 },
939 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
940 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
941 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
942 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
943 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
944 };
945
946 /**
947 * mpi3mr_reset_rc_name - get reset reason code name
948 * @reason_code: reset reason code value
949 *
950 * Map reset reason to an NULL terminated ASCII string
951 *
952 * Return: name corresponding to reset reason value or NULL.
953 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)954 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
955 {
956 int i;
957 char *name = NULL;
958
959 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
960 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
961 name = mpi3mr_reset_reason_codes[i].name;
962 break;
963 }
964 }
965 return name;
966 }
967
968 /* Reset type to name mapper structure*/
969 static const struct {
970 u16 reset_type;
971 char *name;
972 } mpi3mr_reset_types[] = {
973 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
974 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
975 };
976
977 /**
978 * mpi3mr_reset_type_name - get reset type name
979 * @reset_type: reset type value
980 *
981 * Map reset type to an NULL terminated ASCII string
982 *
983 * Return: name corresponding to reset type value or NULL.
984 */
mpi3mr_reset_type_name(u16 reset_type)985 static const char *mpi3mr_reset_type_name(u16 reset_type)
986 {
987 int i;
988 char *name = NULL;
989
990 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
991 if (mpi3mr_reset_types[i].reset_type == reset_type) {
992 name = mpi3mr_reset_types[i].name;
993 break;
994 }
995 }
996 return name;
997 }
998
999 /**
1000 * mpi3mr_print_fault_info - Display fault information
1001 * @mrioc: Adapter instance reference
1002 *
1003 * Display the controller fault information if there is a
1004 * controller fault.
1005 *
1006 * Return: Nothing.
1007 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1008 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1009 {
1010 u32 ioc_status, code, code1, code2, code3;
1011
1012 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1013
1014 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1015 code = readl(&mrioc->sysif_regs->fault);
1016 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1017 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1018 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1019
1020 ioc_info(mrioc,
1021 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1022 code, code1, code2, code3);
1023 }
1024 }
1025
1026 /**
1027 * mpi3mr_get_iocstate - Get IOC State
1028 * @mrioc: Adapter instance reference
1029 *
1030 * Return a proper IOC state enum based on the IOC status and
1031 * IOC configuration and unrcoverable state of the controller.
1032 *
1033 * Return: Current IOC state.
1034 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1035 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1036 {
1037 u32 ioc_status, ioc_config;
1038 u8 ready, enabled;
1039
1040 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1041 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1042
1043 if (mrioc->unrecoverable)
1044 return MRIOC_STATE_UNRECOVERABLE;
1045 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1046 return MRIOC_STATE_FAULT;
1047
1048 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1049 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1050
1051 if (ready && enabled)
1052 return MRIOC_STATE_READY;
1053 if ((!ready) && (!enabled))
1054 return MRIOC_STATE_RESET;
1055 if ((!ready) && (enabled))
1056 return MRIOC_STATE_BECOMING_READY;
1057
1058 return MRIOC_STATE_RESET_REQUESTED;
1059 }
1060
1061 /**
1062 * mpi3mr_clear_reset_history - clear reset history
1063 * @mrioc: Adapter instance reference
1064 *
1065 * Write the reset history bit in IOC status to clear the bit,
1066 * if it is already set.
1067 *
1068 * Return: Nothing.
1069 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1070 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1071 {
1072 u32 ioc_status;
1073
1074 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1075 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1076 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1077 }
1078
1079 /**
1080 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1081 * @mrioc: Adapter instance reference
1082 * @reset_reason: Reset reason code
1083 *
1084 * Issue Message unit Reset to the controller and wait for it to
1085 * be complete.
1086 *
1087 * Return: 0 on success, -1 on failure.
1088 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1089 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1090 u32 reset_reason)
1091 {
1092 u32 ioc_config, timeout, ioc_status;
1093 int retval = -1;
1094
1095 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1096 if (mrioc->unrecoverable) {
1097 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1098 return retval;
1099 }
1100 mpi3mr_clear_reset_history(mrioc);
1101 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1102 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1103 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1104 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1105
1106 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1107 do {
1108 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1109 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1110 mpi3mr_clear_reset_history(mrioc);
1111 break;
1112 }
1113 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1114 mpi3mr_print_fault_info(mrioc);
1115 break;
1116 }
1117 msleep(100);
1118 } while (--timeout);
1119
1120 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1121 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1122 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1123 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1124 retval = 0;
1125
1126 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1127 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1128 return retval;
1129 }
1130
1131 /**
1132 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1133 * during reset/resume
1134 * @mrioc: Adapter instance reference
1135 *
1136 * Return zero if the new IOCFacts parameters value is compatible with
1137 * older values else return -EPERM
1138 */
1139 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1140 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1141 {
1142 void *removepend_bitmap;
1143
1144 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1145 ioc_err(mrioc,
1146 "cannot increase reply size from %d to %d\n",
1147 mrioc->reply_sz, mrioc->facts.reply_sz);
1148 return -EPERM;
1149 }
1150
1151 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1152 ioc_err(mrioc,
1153 "cannot reduce number of operational reply queues from %d to %d\n",
1154 mrioc->num_op_reply_q,
1155 mrioc->facts.max_op_reply_q);
1156 return -EPERM;
1157 }
1158
1159 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1160 ioc_err(mrioc,
1161 "cannot reduce number of operational request queues from %d to %d\n",
1162 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1163 return -EPERM;
1164 }
1165
1166 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1167 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1168 ioc_err(mrioc,
1169 "critical error: multipath capability is enabled at the\n"
1170 "\tcontroller while sas transport support is enabled at the\n"
1171 "\tdriver, please reboot the system or reload the driver\n");
1172
1173 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1174 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1175 GFP_KERNEL);
1176 if (!removepend_bitmap) {
1177 ioc_err(mrioc,
1178 "failed to increase removepend_bitmap bits from %d to %d\n",
1179 mrioc->dev_handle_bitmap_bits,
1180 mrioc->facts.max_devhandle);
1181 return -EPERM;
1182 }
1183 bitmap_free(mrioc->removepend_bitmap);
1184 mrioc->removepend_bitmap = removepend_bitmap;
1185 ioc_info(mrioc,
1186 "increased bits of dev_handle_bitmap from %d to %d\n",
1187 mrioc->dev_handle_bitmap_bits,
1188 mrioc->facts.max_devhandle);
1189 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1190 }
1191
1192 return 0;
1193 }
1194
1195 /**
1196 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1197 * @mrioc: Adapter instance reference
1198 *
1199 * Set Enable IOC bit in IOC configuration register and wait for
1200 * the controller to become ready.
1201 *
1202 * Return: 0 on success, appropriate error on failure.
1203 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1204 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1205 {
1206 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1207 int retval = 0;
1208 enum mpi3mr_iocstate ioc_state;
1209 u64 base_info;
1210
1211 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1212 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1213 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1214 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1215 ioc_status, ioc_config, base_info);
1216
1217 /*The timeout value is in 2sec unit, changing it to seconds*/
1218 mrioc->ready_timeout =
1219 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1220 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1221
1222 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1223
1224 ioc_state = mpi3mr_get_iocstate(mrioc);
1225 ioc_info(mrioc, "controller is in %s state during detection\n",
1226 mpi3mr_iocstate_name(ioc_state));
1227
1228 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1229 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1230 timeout = mrioc->ready_timeout * 10;
1231 do {
1232 msleep(100);
1233 } while (--timeout);
1234
1235 if (!pci_device_is_present(mrioc->pdev)) {
1236 mrioc->unrecoverable = 1;
1237 ioc_err(mrioc,
1238 "controller is not present while waiting to reset\n");
1239 retval = -1;
1240 goto out_device_not_present;
1241 }
1242
1243 ioc_state = mpi3mr_get_iocstate(mrioc);
1244 ioc_info(mrioc,
1245 "controller is in %s state after waiting to reset\n",
1246 mpi3mr_iocstate_name(ioc_state));
1247 }
1248
1249 if (ioc_state == MRIOC_STATE_READY) {
1250 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1251 retval = mpi3mr_issue_and_process_mur(mrioc,
1252 MPI3MR_RESET_FROM_BRINGUP);
1253 ioc_state = mpi3mr_get_iocstate(mrioc);
1254 if (retval)
1255 ioc_err(mrioc,
1256 "message unit reset failed with error %d current state %s\n",
1257 retval, mpi3mr_iocstate_name(ioc_state));
1258 }
1259 if (ioc_state != MRIOC_STATE_RESET) {
1260 if (ioc_state == MRIOC_STATE_FAULT) {
1261 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1262 mpi3mr_print_fault_info(mrioc);
1263 do {
1264 host_diagnostic =
1265 readl(&mrioc->sysif_regs->host_diagnostic);
1266 if (!(host_diagnostic &
1267 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1268 break;
1269 if (!pci_device_is_present(mrioc->pdev)) {
1270 mrioc->unrecoverable = 1;
1271 ioc_err(mrioc, "controller is not present at the bringup\n");
1272 goto out_device_not_present;
1273 }
1274 msleep(100);
1275 } while (--timeout);
1276 }
1277 mpi3mr_print_fault_info(mrioc);
1278 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1279 retval = mpi3mr_issue_reset(mrioc,
1280 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1281 MPI3MR_RESET_FROM_BRINGUP);
1282 if (retval) {
1283 ioc_err(mrioc,
1284 "soft reset failed with error %d\n", retval);
1285 goto out_failed;
1286 }
1287 }
1288 ioc_state = mpi3mr_get_iocstate(mrioc);
1289 if (ioc_state != MRIOC_STATE_RESET) {
1290 ioc_err(mrioc,
1291 "cannot bring controller to reset state, current state: %s\n",
1292 mpi3mr_iocstate_name(ioc_state));
1293 goto out_failed;
1294 }
1295 mpi3mr_clear_reset_history(mrioc);
1296 retval = mpi3mr_setup_admin_qpair(mrioc);
1297 if (retval) {
1298 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1299 retval);
1300 goto out_failed;
1301 }
1302
1303 ioc_info(mrioc, "bringing controller to ready state\n");
1304 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1305 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1306 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1307
1308 timeout = mrioc->ready_timeout * 10;
1309 do {
1310 ioc_state = mpi3mr_get_iocstate(mrioc);
1311 if (ioc_state == MRIOC_STATE_READY) {
1312 ioc_info(mrioc,
1313 "successfully transitioned to %s state\n",
1314 mpi3mr_iocstate_name(ioc_state));
1315 return 0;
1316 }
1317 if (!pci_device_is_present(mrioc->pdev)) {
1318 mrioc->unrecoverable = 1;
1319 ioc_err(mrioc,
1320 "controller is not present at the bringup\n");
1321 retval = -1;
1322 goto out_device_not_present;
1323 }
1324 msleep(100);
1325 } while (--timeout);
1326
1327 out_failed:
1328 ioc_state = mpi3mr_get_iocstate(mrioc);
1329 ioc_err(mrioc,
1330 "failed to bring to ready state, current state: %s\n",
1331 mpi3mr_iocstate_name(ioc_state));
1332 out_device_not_present:
1333 return retval;
1334 }
1335
1336 /**
1337 * mpi3mr_soft_reset_success - Check softreset is success or not
1338 * @ioc_status: IOC status register value
1339 * @ioc_config: IOC config register value
1340 *
1341 * Check whether the soft reset is successful or not based on
1342 * IOC status and IOC config register values.
1343 *
1344 * Return: True when the soft reset is success, false otherwise.
1345 */
1346 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1347 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1348 {
1349 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1350 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1351 return true;
1352 return false;
1353 }
1354
1355 /**
1356 * mpi3mr_diagfault_success - Check diag fault is success or not
1357 * @mrioc: Adapter reference
1358 * @ioc_status: IOC status register value
1359 *
1360 * Check whether the controller hit diag reset fault code.
1361 *
1362 * Return: True when there is diag fault, false otherwise.
1363 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1364 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1365 u32 ioc_status)
1366 {
1367 u32 fault;
1368
1369 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1370 return false;
1371 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1372 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1373 mpi3mr_print_fault_info(mrioc);
1374 return true;
1375 }
1376 return false;
1377 }
1378
1379 /**
1380 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1381 * @mrioc: Adapter reference
1382 *
1383 * Set diag save bit in IOC configuration register to enable
1384 * snapdump.
1385 *
1386 * Return: Nothing.
1387 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1388 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1389 {
1390 u32 ioc_config;
1391
1392 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1393 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1394 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1395 }
1396
1397 /**
1398 * mpi3mr_issue_reset - Issue reset to the controller
1399 * @mrioc: Adapter reference
1400 * @reset_type: Reset type
1401 * @reset_reason: Reset reason code
1402 *
1403 * Unlock the host diagnostic registers and write the specific
1404 * reset type to that, wait for reset acknowledgment from the
1405 * controller, if the reset is not successful retry for the
1406 * predefined number of times.
1407 *
1408 * Return: 0 on success, non-zero on failure.
1409 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u32 reset_reason)1410 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1411 u32 reset_reason)
1412 {
1413 int retval = -1;
1414 u8 unlock_retry_count = 0;
1415 u32 host_diagnostic, ioc_status, ioc_config;
1416 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1417
1418 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1419 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1420 return retval;
1421 if (mrioc->unrecoverable)
1422 return retval;
1423 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1424 retval = 0;
1425 return retval;
1426 }
1427
1428 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1429 mpi3mr_reset_type_name(reset_type),
1430 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1431
1432 mpi3mr_clear_reset_history(mrioc);
1433 do {
1434 ioc_info(mrioc,
1435 "Write magic sequence to unlock host diag register (retry=%d)\n",
1436 ++unlock_retry_count);
1437 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1438 ioc_err(mrioc,
1439 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1440 mpi3mr_reset_type_name(reset_type),
1441 host_diagnostic);
1442 mrioc->unrecoverable = 1;
1443 return retval;
1444 }
1445
1446 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1447 &mrioc->sysif_regs->write_sequence);
1448 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1449 &mrioc->sysif_regs->write_sequence);
1450 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1451 &mrioc->sysif_regs->write_sequence);
1452 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1453 &mrioc->sysif_regs->write_sequence);
1454 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1455 &mrioc->sysif_regs->write_sequence);
1456 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1457 &mrioc->sysif_regs->write_sequence);
1458 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1459 &mrioc->sysif_regs->write_sequence);
1460 usleep_range(1000, 1100);
1461 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1462 ioc_info(mrioc,
1463 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1464 unlock_retry_count, host_diagnostic);
1465 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1466
1467 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1468 writel(host_diagnostic | reset_type,
1469 &mrioc->sysif_regs->host_diagnostic);
1470 switch (reset_type) {
1471 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1472 do {
1473 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1474 ioc_config =
1475 readl(&mrioc->sysif_regs->ioc_configuration);
1476 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1477 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1478 ) {
1479 mpi3mr_clear_reset_history(mrioc);
1480 retval = 0;
1481 break;
1482 }
1483 msleep(100);
1484 } while (--timeout);
1485 mpi3mr_print_fault_info(mrioc);
1486 break;
1487 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1488 do {
1489 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1490 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1491 retval = 0;
1492 break;
1493 }
1494 msleep(100);
1495 } while (--timeout);
1496 break;
1497 default:
1498 break;
1499 }
1500
1501 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1502 &mrioc->sysif_regs->write_sequence);
1503
1504 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1505 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1506 ioc_info(mrioc,
1507 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1508 (!retval)?"successful":"failed", ioc_status,
1509 ioc_config);
1510 if (retval)
1511 mrioc->unrecoverable = 1;
1512 return retval;
1513 }
1514
1515 /**
1516 * mpi3mr_admin_request_post - Post request to admin queue
1517 * @mrioc: Adapter reference
1518 * @admin_req: MPI3 request
1519 * @admin_req_sz: Request size
1520 * @ignore_reset: Ignore reset in process
1521 *
1522 * Post the MPI3 request into admin request queue and
1523 * inform the controller, if the queue is full return
1524 * appropriate error.
1525 *
1526 * Return: 0 on success, non-zero on failure.
1527 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1528 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1529 u16 admin_req_sz, u8 ignore_reset)
1530 {
1531 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1532 int retval = 0;
1533 unsigned long flags;
1534 u8 *areq_entry;
1535
1536 if (mrioc->unrecoverable) {
1537 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1538 return -EFAULT;
1539 }
1540
1541 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1542 areq_pi = mrioc->admin_req_pi;
1543 areq_ci = mrioc->admin_req_ci;
1544 max_entries = mrioc->num_admin_req;
1545 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1546 (areq_pi == (max_entries - 1)))) {
1547 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1548 retval = -EAGAIN;
1549 goto out;
1550 }
1551 if (!ignore_reset && mrioc->reset_in_progress) {
1552 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1553 retval = -EAGAIN;
1554 goto out;
1555 }
1556 areq_entry = (u8 *)mrioc->admin_req_base +
1557 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1558 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1559 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1560
1561 if (++areq_pi == max_entries)
1562 areq_pi = 0;
1563 mrioc->admin_req_pi = areq_pi;
1564
1565 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1566
1567 out:
1568 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1569
1570 return retval;
1571 }
1572
1573 /**
1574 * mpi3mr_free_op_req_q_segments - free request memory segments
1575 * @mrioc: Adapter instance reference
1576 * @q_idx: operational request queue index
1577 *
1578 * Free memory segments allocated for operational request queue
1579 *
1580 * Return: Nothing.
1581 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1582 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1583 {
1584 u16 j;
1585 int size;
1586 struct segments *segments;
1587
1588 segments = mrioc->req_qinfo[q_idx].q_segments;
1589 if (!segments)
1590 return;
1591
1592 if (mrioc->enable_segqueue) {
1593 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1594 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1595 dma_free_coherent(&mrioc->pdev->dev,
1596 MPI3MR_MAX_SEG_LIST_SIZE,
1597 mrioc->req_qinfo[q_idx].q_segment_list,
1598 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1599 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1600 }
1601 } else
1602 size = mrioc->req_qinfo[q_idx].segment_qd *
1603 mrioc->facts.op_req_sz;
1604
1605 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1606 if (!segments[j].segment)
1607 continue;
1608 dma_free_coherent(&mrioc->pdev->dev,
1609 size, segments[j].segment, segments[j].segment_dma);
1610 segments[j].segment = NULL;
1611 }
1612 kfree(mrioc->req_qinfo[q_idx].q_segments);
1613 mrioc->req_qinfo[q_idx].q_segments = NULL;
1614 mrioc->req_qinfo[q_idx].qid = 0;
1615 }
1616
1617 /**
1618 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1619 * @mrioc: Adapter instance reference
1620 * @q_idx: operational reply queue index
1621 *
1622 * Free memory segments allocated for operational reply queue
1623 *
1624 * Return: Nothing.
1625 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1626 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1627 {
1628 u16 j;
1629 int size;
1630 struct segments *segments;
1631
1632 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1633 if (!segments)
1634 return;
1635
1636 if (mrioc->enable_segqueue) {
1637 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1638 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1639 dma_free_coherent(&mrioc->pdev->dev,
1640 MPI3MR_MAX_SEG_LIST_SIZE,
1641 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1642 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1643 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1644 }
1645 } else
1646 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1647 mrioc->op_reply_desc_sz;
1648
1649 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1650 if (!segments[j].segment)
1651 continue;
1652 dma_free_coherent(&mrioc->pdev->dev,
1653 size, segments[j].segment, segments[j].segment_dma);
1654 segments[j].segment = NULL;
1655 }
1656
1657 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1658 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1659 mrioc->op_reply_qinfo[q_idx].qid = 0;
1660 }
1661
1662 /**
1663 * mpi3mr_delete_op_reply_q - delete operational reply queue
1664 * @mrioc: Adapter instance reference
1665 * @qidx: operational reply queue index
1666 *
1667 * Delete operatinal reply queue by issuing MPI request
1668 * through admin queue.
1669 *
1670 * Return: 0 on success, non-zero on failure.
1671 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1672 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1673 {
1674 struct mpi3_delete_reply_queue_request delq_req;
1675 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1676 int retval = 0;
1677 u16 reply_qid = 0, midx;
1678
1679 reply_qid = op_reply_q->qid;
1680
1681 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1682
1683 if (!reply_qid) {
1684 retval = -1;
1685 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1686 goto out;
1687 }
1688
1689 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1690 mrioc->active_poll_qcount--;
1691
1692 memset(&delq_req, 0, sizeof(delq_req));
1693 mutex_lock(&mrioc->init_cmds.mutex);
1694 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1695 retval = -1;
1696 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1697 mutex_unlock(&mrioc->init_cmds.mutex);
1698 goto out;
1699 }
1700 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1701 mrioc->init_cmds.is_waiting = 1;
1702 mrioc->init_cmds.callback = NULL;
1703 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1704 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1705 delq_req.queue_id = cpu_to_le16(reply_qid);
1706
1707 init_completion(&mrioc->init_cmds.done);
1708 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1709 1);
1710 if (retval) {
1711 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1712 goto out_unlock;
1713 }
1714 wait_for_completion_timeout(&mrioc->init_cmds.done,
1715 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1716 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1717 ioc_err(mrioc, "delete reply queue timed out\n");
1718 mpi3mr_check_rh_fault_ioc(mrioc,
1719 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1720 retval = -1;
1721 goto out_unlock;
1722 }
1723 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1724 != MPI3_IOCSTATUS_SUCCESS) {
1725 ioc_err(mrioc,
1726 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1727 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1728 mrioc->init_cmds.ioc_loginfo);
1729 retval = -1;
1730 goto out_unlock;
1731 }
1732 mrioc->intr_info[midx].op_reply_q = NULL;
1733
1734 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1735 out_unlock:
1736 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1737 mutex_unlock(&mrioc->init_cmds.mutex);
1738 out:
1739
1740 return retval;
1741 }
1742
1743 /**
1744 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1745 * @mrioc: Adapter instance reference
1746 * @qidx: request queue index
1747 *
1748 * Allocate segmented memory pools for operational reply
1749 * queue.
1750 *
1751 * Return: 0 on success, non-zero on failure.
1752 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1753 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1754 {
1755 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1756 int i, size;
1757 u64 *q_segment_list_entry = NULL;
1758 struct segments *segments;
1759
1760 if (mrioc->enable_segqueue) {
1761 op_reply_q->segment_qd =
1762 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1763
1764 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1765
1766 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1767 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1768 GFP_KERNEL);
1769 if (!op_reply_q->q_segment_list)
1770 return -ENOMEM;
1771 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1772 } else {
1773 op_reply_q->segment_qd = op_reply_q->num_replies;
1774 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1775 }
1776
1777 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1778 op_reply_q->segment_qd);
1779
1780 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1781 sizeof(struct segments), GFP_KERNEL);
1782 if (!op_reply_q->q_segments)
1783 return -ENOMEM;
1784
1785 segments = op_reply_q->q_segments;
1786 for (i = 0; i < op_reply_q->num_segments; i++) {
1787 segments[i].segment =
1788 dma_alloc_coherent(&mrioc->pdev->dev,
1789 size, &segments[i].segment_dma, GFP_KERNEL);
1790 if (!segments[i].segment)
1791 return -ENOMEM;
1792 if (mrioc->enable_segqueue)
1793 q_segment_list_entry[i] =
1794 (unsigned long)segments[i].segment_dma;
1795 }
1796
1797 return 0;
1798 }
1799
1800 /**
1801 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1802 * @mrioc: Adapter instance reference
1803 * @qidx: request queue index
1804 *
1805 * Allocate segmented memory pools for operational request
1806 * queue.
1807 *
1808 * Return: 0 on success, non-zero on failure.
1809 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1810 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1811 {
1812 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1813 int i, size;
1814 u64 *q_segment_list_entry = NULL;
1815 struct segments *segments;
1816
1817 if (mrioc->enable_segqueue) {
1818 op_req_q->segment_qd =
1819 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1820
1821 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1822
1823 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1824 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1825 GFP_KERNEL);
1826 if (!op_req_q->q_segment_list)
1827 return -ENOMEM;
1828 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1829
1830 } else {
1831 op_req_q->segment_qd = op_req_q->num_requests;
1832 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1833 }
1834
1835 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1836 op_req_q->segment_qd);
1837
1838 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1839 sizeof(struct segments), GFP_KERNEL);
1840 if (!op_req_q->q_segments)
1841 return -ENOMEM;
1842
1843 segments = op_req_q->q_segments;
1844 for (i = 0; i < op_req_q->num_segments; i++) {
1845 segments[i].segment =
1846 dma_alloc_coherent(&mrioc->pdev->dev,
1847 size, &segments[i].segment_dma, GFP_KERNEL);
1848 if (!segments[i].segment)
1849 return -ENOMEM;
1850 if (mrioc->enable_segqueue)
1851 q_segment_list_entry[i] =
1852 (unsigned long)segments[i].segment_dma;
1853 }
1854
1855 return 0;
1856 }
1857
1858 /**
1859 * mpi3mr_create_op_reply_q - create operational reply queue
1860 * @mrioc: Adapter instance reference
1861 * @qidx: operational reply queue index
1862 *
1863 * Create operatinal reply queue by issuing MPI request
1864 * through admin queue.
1865 *
1866 * Return: 0 on success, non-zero on failure.
1867 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1868 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1869 {
1870 struct mpi3_create_reply_queue_request create_req;
1871 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1872 int retval = 0;
1873 u16 reply_qid = 0, midx;
1874
1875 reply_qid = op_reply_q->qid;
1876
1877 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1878
1879 if (reply_qid) {
1880 retval = -1;
1881 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1882 reply_qid);
1883
1884 return retval;
1885 }
1886
1887 reply_qid = qidx + 1;
1888 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1889 if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
1890 !mrioc->pdev->revision)
1891 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1892 op_reply_q->ci = 0;
1893 op_reply_q->ephase = 1;
1894 atomic_set(&op_reply_q->pend_ios, 0);
1895 atomic_set(&op_reply_q->in_use, 0);
1896 op_reply_q->enable_irq_poll = false;
1897
1898 if (!op_reply_q->q_segments) {
1899 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1900 if (retval) {
1901 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1902 goto out;
1903 }
1904 }
1905
1906 memset(&create_req, 0, sizeof(create_req));
1907 mutex_lock(&mrioc->init_cmds.mutex);
1908 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1909 retval = -1;
1910 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1911 goto out_unlock;
1912 }
1913 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1914 mrioc->init_cmds.is_waiting = 1;
1915 mrioc->init_cmds.callback = NULL;
1916 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1917 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1918 create_req.queue_id = cpu_to_le16(reply_qid);
1919
1920 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1921 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1922 else
1923 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1924
1925 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1926 create_req.flags =
1927 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1928 create_req.msix_index =
1929 cpu_to_le16(mrioc->intr_info[midx].msix_index);
1930 } else {
1931 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1932 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1933 reply_qid, midx);
1934 if (!mrioc->active_poll_qcount)
1935 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1936 mrioc->intr_info_count - 1));
1937 }
1938
1939 if (mrioc->enable_segqueue) {
1940 create_req.flags |=
1941 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1942 create_req.base_address = cpu_to_le64(
1943 op_reply_q->q_segment_list_dma);
1944 } else
1945 create_req.base_address = cpu_to_le64(
1946 op_reply_q->q_segments[0].segment_dma);
1947
1948 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1949
1950 init_completion(&mrioc->init_cmds.done);
1951 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1952 sizeof(create_req), 1);
1953 if (retval) {
1954 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1955 goto out_unlock;
1956 }
1957 wait_for_completion_timeout(&mrioc->init_cmds.done,
1958 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1959 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1960 ioc_err(mrioc, "create reply queue timed out\n");
1961 mpi3mr_check_rh_fault_ioc(mrioc,
1962 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1963 retval = -1;
1964 goto out_unlock;
1965 }
1966 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1967 != MPI3_IOCSTATUS_SUCCESS) {
1968 ioc_err(mrioc,
1969 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1970 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1971 mrioc->init_cmds.ioc_loginfo);
1972 retval = -1;
1973 goto out_unlock;
1974 }
1975 op_reply_q->qid = reply_qid;
1976 if (midx < mrioc->intr_info_count)
1977 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1978
1979 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1980 mrioc->active_poll_qcount++;
1981
1982 out_unlock:
1983 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1984 mutex_unlock(&mrioc->init_cmds.mutex);
1985 out:
1986
1987 return retval;
1988 }
1989
1990 /**
1991 * mpi3mr_create_op_req_q - create operational request queue
1992 * @mrioc: Adapter instance reference
1993 * @idx: operational request queue index
1994 * @reply_qid: Reply queue ID
1995 *
1996 * Create operatinal request queue by issuing MPI request
1997 * through admin queue.
1998 *
1999 * Return: 0 on success, non-zero on failure.
2000 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2001 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2002 u16 reply_qid)
2003 {
2004 struct mpi3_create_request_queue_request create_req;
2005 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2006 int retval = 0;
2007 u16 req_qid = 0;
2008
2009 req_qid = op_req_q->qid;
2010
2011 if (req_qid) {
2012 retval = -1;
2013 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2014 req_qid);
2015
2016 return retval;
2017 }
2018 req_qid = idx + 1;
2019
2020 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2021 op_req_q->ci = 0;
2022 op_req_q->pi = 0;
2023 op_req_q->reply_qid = reply_qid;
2024 spin_lock_init(&op_req_q->q_lock);
2025
2026 if (!op_req_q->q_segments) {
2027 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2028 if (retval) {
2029 mpi3mr_free_op_req_q_segments(mrioc, idx);
2030 goto out;
2031 }
2032 }
2033
2034 memset(&create_req, 0, sizeof(create_req));
2035 mutex_lock(&mrioc->init_cmds.mutex);
2036 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2037 retval = -1;
2038 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2039 goto out_unlock;
2040 }
2041 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2042 mrioc->init_cmds.is_waiting = 1;
2043 mrioc->init_cmds.callback = NULL;
2044 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2045 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2046 create_req.queue_id = cpu_to_le16(req_qid);
2047 if (mrioc->enable_segqueue) {
2048 create_req.flags =
2049 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2050 create_req.base_address = cpu_to_le64(
2051 op_req_q->q_segment_list_dma);
2052 } else
2053 create_req.base_address = cpu_to_le64(
2054 op_req_q->q_segments[0].segment_dma);
2055 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2056 create_req.size = cpu_to_le16(op_req_q->num_requests);
2057
2058 init_completion(&mrioc->init_cmds.done);
2059 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2060 sizeof(create_req), 1);
2061 if (retval) {
2062 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2063 goto out_unlock;
2064 }
2065 wait_for_completion_timeout(&mrioc->init_cmds.done,
2066 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2067 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2068 ioc_err(mrioc, "create request queue timed out\n");
2069 mpi3mr_check_rh_fault_ioc(mrioc,
2070 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2071 retval = -1;
2072 goto out_unlock;
2073 }
2074 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2075 != MPI3_IOCSTATUS_SUCCESS) {
2076 ioc_err(mrioc,
2077 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2078 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2079 mrioc->init_cmds.ioc_loginfo);
2080 retval = -1;
2081 goto out_unlock;
2082 }
2083 op_req_q->qid = req_qid;
2084
2085 out_unlock:
2086 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2087 mutex_unlock(&mrioc->init_cmds.mutex);
2088 out:
2089
2090 return retval;
2091 }
2092
2093 /**
2094 * mpi3mr_create_op_queues - create operational queue pairs
2095 * @mrioc: Adapter instance reference
2096 *
2097 * Allocate memory for operational queue meta data and call
2098 * create request and reply queue functions.
2099 *
2100 * Return: 0 on success, non-zero on failures.
2101 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2102 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2103 {
2104 int retval = 0;
2105 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2106
2107 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2108 mrioc->facts.max_op_req_q);
2109
2110 msix_count_op_q =
2111 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2112 if (!mrioc->num_queues)
2113 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2114 /*
2115 * During reset set the num_queues to the number of queues
2116 * that was set before the reset.
2117 */
2118 num_queues = mrioc->num_op_reply_q ?
2119 mrioc->num_op_reply_q : mrioc->num_queues;
2120 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2121 num_queues);
2122
2123 if (!mrioc->req_qinfo) {
2124 mrioc->req_qinfo = kcalloc(num_queues,
2125 sizeof(struct op_req_qinfo), GFP_KERNEL);
2126 if (!mrioc->req_qinfo) {
2127 retval = -1;
2128 goto out_failed;
2129 }
2130
2131 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2132 num_queues, GFP_KERNEL);
2133 if (!mrioc->op_reply_qinfo) {
2134 retval = -1;
2135 goto out_failed;
2136 }
2137 }
2138
2139 if (mrioc->enable_segqueue)
2140 ioc_info(mrioc,
2141 "allocating operational queues through segmented queues\n");
2142
2143 for (i = 0; i < num_queues; i++) {
2144 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2145 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2146 break;
2147 }
2148 if (mpi3mr_create_op_req_q(mrioc, i,
2149 mrioc->op_reply_qinfo[i].qid)) {
2150 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2151 mpi3mr_delete_op_reply_q(mrioc, i);
2152 break;
2153 }
2154 }
2155
2156 if (i == 0) {
2157 /* Not even one queue is created successfully*/
2158 retval = -1;
2159 goto out_failed;
2160 }
2161 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2162 ioc_info(mrioc,
2163 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2164 mrioc->num_op_reply_q, mrioc->default_qcount,
2165 mrioc->active_poll_qcount);
2166
2167 return retval;
2168 out_failed:
2169 kfree(mrioc->req_qinfo);
2170 mrioc->req_qinfo = NULL;
2171
2172 kfree(mrioc->op_reply_qinfo);
2173 mrioc->op_reply_qinfo = NULL;
2174
2175 return retval;
2176 }
2177
2178 /**
2179 * mpi3mr_op_request_post - Post request to operational queue
2180 * @mrioc: Adapter reference
2181 * @op_req_q: Operational request queue info
2182 * @req: MPI3 request
2183 *
2184 * Post the MPI3 request into operational request queue and
2185 * inform the controller, if the queue is full return
2186 * appropriate error.
2187 *
2188 * Return: 0 on success, non-zero on failure.
2189 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2190 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2191 struct op_req_qinfo *op_req_q, u8 *req)
2192 {
2193 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2194 int retval = 0;
2195 unsigned long flags;
2196 u8 *req_entry;
2197 void *segment_base_addr;
2198 u16 req_sz = mrioc->facts.op_req_sz;
2199 struct segments *segments = op_req_q->q_segments;
2200
2201 reply_qidx = op_req_q->reply_qid - 1;
2202
2203 if (mrioc->unrecoverable)
2204 return -EFAULT;
2205
2206 spin_lock_irqsave(&op_req_q->q_lock, flags);
2207 pi = op_req_q->pi;
2208 max_entries = op_req_q->num_requests;
2209
2210 if (mpi3mr_check_req_qfull(op_req_q)) {
2211 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2212 reply_qidx, mrioc->op_reply_q_offset);
2213 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2214
2215 if (mpi3mr_check_req_qfull(op_req_q)) {
2216 retval = -EAGAIN;
2217 goto out;
2218 }
2219 }
2220
2221 if (mrioc->reset_in_progress) {
2222 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2223 retval = -EAGAIN;
2224 goto out;
2225 }
2226
2227 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2228 req_entry = (u8 *)segment_base_addr +
2229 ((pi % op_req_q->segment_qd) * req_sz);
2230
2231 memset(req_entry, 0, req_sz);
2232 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2233
2234 if (++pi == max_entries)
2235 pi = 0;
2236 op_req_q->pi = pi;
2237
2238 #ifndef CONFIG_PREEMPT_RT
2239 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2240 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2241 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2242 #else
2243 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2244 #endif
2245
2246 writel(op_req_q->pi,
2247 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2248
2249 out:
2250 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2251 return retval;
2252 }
2253
2254 /**
2255 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2256 * controller
2257 * @mrioc: Adapter instance reference
2258 * @reason_code: reason code for the fault.
2259 *
2260 * This routine will save snapdump and fault the controller with
2261 * the given reason code if it is not already in the fault or
2262 * not asynchronosuly reset. This will be used to handle
2263 * initilaization time faults/resets/timeout as in those cases
2264 * immediate soft reset invocation is not required.
2265 *
2266 * Return: None.
2267 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2268 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2269 {
2270 u32 ioc_status, host_diagnostic, timeout;
2271
2272 if (mrioc->unrecoverable) {
2273 ioc_err(mrioc, "controller is unrecoverable\n");
2274 return;
2275 }
2276
2277 if (!pci_device_is_present(mrioc->pdev)) {
2278 mrioc->unrecoverable = 1;
2279 ioc_err(mrioc, "controller is not present\n");
2280 return;
2281 }
2282
2283 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2284 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2285 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2286 mpi3mr_print_fault_info(mrioc);
2287 return;
2288 }
2289 mpi3mr_set_diagsave(mrioc);
2290 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2291 reason_code);
2292 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2293 do {
2294 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2295 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2296 break;
2297 msleep(100);
2298 } while (--timeout);
2299 }
2300
2301 /**
2302 * mpi3mr_sync_timestamp - Issue time stamp sync request
2303 * @mrioc: Adapter reference
2304 *
2305 * Issue IO unit control MPI request to synchornize firmware
2306 * timestamp with host time.
2307 *
2308 * Return: 0 on success, non-zero on failure.
2309 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2310 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2311 {
2312 ktime_t current_time;
2313 struct mpi3_iounit_control_request iou_ctrl;
2314 int retval = 0;
2315
2316 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2317 mutex_lock(&mrioc->init_cmds.mutex);
2318 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2319 retval = -1;
2320 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2321 mutex_unlock(&mrioc->init_cmds.mutex);
2322 goto out;
2323 }
2324 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2325 mrioc->init_cmds.is_waiting = 1;
2326 mrioc->init_cmds.callback = NULL;
2327 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2328 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2329 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2330 current_time = ktime_get_real();
2331 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2332
2333 init_completion(&mrioc->init_cmds.done);
2334 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2335 sizeof(iou_ctrl), 0);
2336 if (retval) {
2337 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2338 goto out_unlock;
2339 }
2340
2341 wait_for_completion_timeout(&mrioc->init_cmds.done,
2342 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2343 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2344 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2345 mrioc->init_cmds.is_waiting = 0;
2346 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2347 mpi3mr_soft_reset_handler(mrioc,
2348 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2349 retval = -1;
2350 goto out_unlock;
2351 }
2352 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2353 != MPI3_IOCSTATUS_SUCCESS) {
2354 ioc_err(mrioc,
2355 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2356 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2357 mrioc->init_cmds.ioc_loginfo);
2358 retval = -1;
2359 goto out_unlock;
2360 }
2361
2362 out_unlock:
2363 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2364 mutex_unlock(&mrioc->init_cmds.mutex);
2365
2366 out:
2367 return retval;
2368 }
2369
2370 /**
2371 * mpi3mr_print_pkg_ver - display controller fw package version
2372 * @mrioc: Adapter reference
2373 *
2374 * Retrieve firmware package version from the component image
2375 * header of the controller flash and display it.
2376 *
2377 * Return: 0 on success and non-zero on failure.
2378 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2379 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2380 {
2381 struct mpi3_ci_upload_request ci_upload;
2382 int retval = -1;
2383 void *data = NULL;
2384 dma_addr_t data_dma;
2385 struct mpi3_ci_manifest_mpi *manifest;
2386 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2387 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2388
2389 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2390 GFP_KERNEL);
2391 if (!data)
2392 return -ENOMEM;
2393
2394 memset(&ci_upload, 0, sizeof(ci_upload));
2395 mutex_lock(&mrioc->init_cmds.mutex);
2396 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2397 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2398 mutex_unlock(&mrioc->init_cmds.mutex);
2399 goto out;
2400 }
2401 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2402 mrioc->init_cmds.is_waiting = 1;
2403 mrioc->init_cmds.callback = NULL;
2404 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2405 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2406 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2407 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2408 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2409 ci_upload.segment_size = cpu_to_le32(data_len);
2410
2411 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2412 data_dma);
2413 init_completion(&mrioc->init_cmds.done);
2414 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2415 sizeof(ci_upload), 1);
2416 if (retval) {
2417 ioc_err(mrioc, "posting get package version failed\n");
2418 goto out_unlock;
2419 }
2420 wait_for_completion_timeout(&mrioc->init_cmds.done,
2421 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2422 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2423 ioc_err(mrioc, "get package version timed out\n");
2424 mpi3mr_check_rh_fault_ioc(mrioc,
2425 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2426 retval = -1;
2427 goto out_unlock;
2428 }
2429 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2430 == MPI3_IOCSTATUS_SUCCESS) {
2431 manifest = (struct mpi3_ci_manifest_mpi *) data;
2432 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2433 ioc_info(mrioc,
2434 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2435 manifest->package_version.gen_major,
2436 manifest->package_version.gen_minor,
2437 manifest->package_version.phase_major,
2438 manifest->package_version.phase_minor,
2439 manifest->package_version.customer_id,
2440 manifest->package_version.build_num);
2441 }
2442 }
2443 retval = 0;
2444 out_unlock:
2445 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2446 mutex_unlock(&mrioc->init_cmds.mutex);
2447
2448 out:
2449 if (data)
2450 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2451 data_dma);
2452 return retval;
2453 }
2454
2455 /**
2456 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2457 * @work: work struct
2458 *
2459 * Watch dog work periodically executed (1 second interval) to
2460 * monitor firmware fault and to issue periodic timer sync to
2461 * the firmware.
2462 *
2463 * Return: Nothing.
2464 */
mpi3mr_watchdog_work(struct work_struct * work)2465 static void mpi3mr_watchdog_work(struct work_struct *work)
2466 {
2467 struct mpi3mr_ioc *mrioc =
2468 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2469 unsigned long flags;
2470 enum mpi3mr_iocstate ioc_state;
2471 u32 fault, host_diagnostic, ioc_status;
2472 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2473
2474 if (mrioc->reset_in_progress)
2475 return;
2476
2477 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2478 ioc_err(mrioc, "watchdog could not detect the controller\n");
2479 mrioc->unrecoverable = 1;
2480 }
2481
2482 if (mrioc->unrecoverable) {
2483 ioc_err(mrioc,
2484 "flush pending commands for unrecoverable controller\n");
2485 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2486 return;
2487 }
2488
2489 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2490 mrioc->ts_update_counter = 0;
2491 mpi3mr_sync_timestamp(mrioc);
2492 }
2493
2494 if ((mrioc->prepare_for_reset) &&
2495 ((mrioc->prepare_for_reset_timeout_counter++) >=
2496 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2497 mpi3mr_soft_reset_handler(mrioc,
2498 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2499 return;
2500 }
2501
2502 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2503 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2504 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2505 return;
2506 }
2507
2508 /*Check for fault state every one second and issue Soft reset*/
2509 ioc_state = mpi3mr_get_iocstate(mrioc);
2510 if (ioc_state != MRIOC_STATE_FAULT)
2511 goto schedule_work;
2512
2513 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2514 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2515 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2516 if (!mrioc->diagsave_timeout) {
2517 mpi3mr_print_fault_info(mrioc);
2518 ioc_warn(mrioc, "diag save in progress\n");
2519 }
2520 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2521 goto schedule_work;
2522 }
2523
2524 mpi3mr_print_fault_info(mrioc);
2525 mrioc->diagsave_timeout = 0;
2526
2527 switch (fault) {
2528 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2529 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2530 ioc_warn(mrioc,
2531 "controller requires system power cycle, marking controller as unrecoverable\n");
2532 mrioc->unrecoverable = 1;
2533 goto schedule_work;
2534 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2535 goto schedule_work;
2536 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2537 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2538 break;
2539 default:
2540 break;
2541 }
2542 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2543 return;
2544
2545 schedule_work:
2546 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2547 if (mrioc->watchdog_work_q)
2548 queue_delayed_work(mrioc->watchdog_work_q,
2549 &mrioc->watchdog_work,
2550 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2551 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2552 return;
2553 }
2554
2555 /**
2556 * mpi3mr_start_watchdog - Start watchdog
2557 * @mrioc: Adapter instance reference
2558 *
2559 * Create and start the watchdog thread to monitor controller
2560 * faults.
2561 *
2562 * Return: Nothing.
2563 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)2564 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2565 {
2566 if (mrioc->watchdog_work_q)
2567 return;
2568
2569 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2570 snprintf(mrioc->watchdog_work_q_name,
2571 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2572 mrioc->id);
2573 mrioc->watchdog_work_q =
2574 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2575 if (!mrioc->watchdog_work_q) {
2576 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2577 return;
2578 }
2579
2580 if (mrioc->watchdog_work_q)
2581 queue_delayed_work(mrioc->watchdog_work_q,
2582 &mrioc->watchdog_work,
2583 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2584 }
2585
2586 /**
2587 * mpi3mr_stop_watchdog - Stop watchdog
2588 * @mrioc: Adapter instance reference
2589 *
2590 * Stop the watchdog thread created to monitor controller
2591 * faults.
2592 *
2593 * Return: Nothing.
2594 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)2595 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2596 {
2597 unsigned long flags;
2598 struct workqueue_struct *wq;
2599
2600 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2601 wq = mrioc->watchdog_work_q;
2602 mrioc->watchdog_work_q = NULL;
2603 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2604 if (wq) {
2605 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2606 flush_workqueue(wq);
2607 destroy_workqueue(wq);
2608 }
2609 }
2610
2611 /**
2612 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2613 * @mrioc: Adapter instance reference
2614 *
2615 * Allocate memory for admin queue pair if required and register
2616 * the admin queue with the controller.
2617 *
2618 * Return: 0 on success, non-zero on failures.
2619 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)2620 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2621 {
2622 int retval = 0;
2623 u32 num_admin_entries = 0;
2624
2625 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2626 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2627 MPI3MR_ADMIN_REQ_FRAME_SZ;
2628 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2629 mrioc->admin_req_base = NULL;
2630
2631 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2632 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2633 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2634 mrioc->admin_reply_ci = 0;
2635 mrioc->admin_reply_ephase = 1;
2636 mrioc->admin_reply_base = NULL;
2637 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2638
2639 if (!mrioc->admin_req_base) {
2640 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2641 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2642
2643 if (!mrioc->admin_req_base) {
2644 retval = -1;
2645 goto out_failed;
2646 }
2647
2648 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2649 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2650 GFP_KERNEL);
2651
2652 if (!mrioc->admin_reply_base) {
2653 retval = -1;
2654 goto out_failed;
2655 }
2656 }
2657
2658 num_admin_entries = (mrioc->num_admin_replies << 16) |
2659 (mrioc->num_admin_req);
2660 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2661 mpi3mr_writeq(mrioc->admin_req_dma,
2662 &mrioc->sysif_regs->admin_request_queue_address);
2663 mpi3mr_writeq(mrioc->admin_reply_dma,
2664 &mrioc->sysif_regs->admin_reply_queue_address);
2665 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2666 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2667 return retval;
2668
2669 out_failed:
2670
2671 if (mrioc->admin_reply_base) {
2672 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2673 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2674 mrioc->admin_reply_base = NULL;
2675 }
2676 if (mrioc->admin_req_base) {
2677 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2678 mrioc->admin_req_base, mrioc->admin_req_dma);
2679 mrioc->admin_req_base = NULL;
2680 }
2681 return retval;
2682 }
2683
2684 /**
2685 * mpi3mr_issue_iocfacts - Send IOC Facts
2686 * @mrioc: Adapter instance reference
2687 * @facts_data: Cached IOC facts data
2688 *
2689 * Issue IOC Facts MPI request through admin queue and wait for
2690 * the completion of it or time out.
2691 *
2692 * Return: 0 on success, non-zero on failures.
2693 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2694 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2695 struct mpi3_ioc_facts_data *facts_data)
2696 {
2697 struct mpi3_ioc_facts_request iocfacts_req;
2698 void *data = NULL;
2699 dma_addr_t data_dma;
2700 u32 data_len = sizeof(*facts_data);
2701 int retval = 0;
2702 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2703
2704 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2705 GFP_KERNEL);
2706
2707 if (!data) {
2708 retval = -1;
2709 goto out;
2710 }
2711
2712 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2713 mutex_lock(&mrioc->init_cmds.mutex);
2714 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2715 retval = -1;
2716 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2717 mutex_unlock(&mrioc->init_cmds.mutex);
2718 goto out;
2719 }
2720 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2721 mrioc->init_cmds.is_waiting = 1;
2722 mrioc->init_cmds.callback = NULL;
2723 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2724 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2725
2726 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2727 data_dma);
2728
2729 init_completion(&mrioc->init_cmds.done);
2730 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2731 sizeof(iocfacts_req), 1);
2732 if (retval) {
2733 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2734 goto out_unlock;
2735 }
2736 wait_for_completion_timeout(&mrioc->init_cmds.done,
2737 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2738 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2739 ioc_err(mrioc, "ioc_facts timed out\n");
2740 mpi3mr_check_rh_fault_ioc(mrioc,
2741 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2742 retval = -1;
2743 goto out_unlock;
2744 }
2745 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2746 != MPI3_IOCSTATUS_SUCCESS) {
2747 ioc_err(mrioc,
2748 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2749 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2750 mrioc->init_cmds.ioc_loginfo);
2751 retval = -1;
2752 goto out_unlock;
2753 }
2754 memcpy(facts_data, (u8 *)data, data_len);
2755 mpi3mr_process_factsdata(mrioc, facts_data);
2756 out_unlock:
2757 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2758 mutex_unlock(&mrioc->init_cmds.mutex);
2759
2760 out:
2761 if (data)
2762 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2763
2764 return retval;
2765 }
2766
2767 /**
2768 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2769 * @mrioc: Adapter instance reference
2770 *
2771 * Check whether the new DMA mask requested through IOCFacts by
2772 * firmware needs to be set, if so set it .
2773 *
2774 * Return: 0 on success, non-zero on failure.
2775 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)2776 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2777 {
2778 struct pci_dev *pdev = mrioc->pdev;
2779 int r;
2780 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2781
2782 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2783 return 0;
2784
2785 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2786 mrioc->dma_mask, facts_dma_mask);
2787
2788 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2789 if (r) {
2790 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2791 facts_dma_mask, r);
2792 return r;
2793 }
2794 mrioc->dma_mask = facts_dma_mask;
2795 return r;
2796 }
2797
2798 /**
2799 * mpi3mr_process_factsdata - Process IOC facts data
2800 * @mrioc: Adapter instance reference
2801 * @facts_data: Cached IOC facts data
2802 *
2803 * Convert IOC facts data into cpu endianness and cache it in
2804 * the driver .
2805 *
2806 * Return: Nothing.
2807 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2808 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2809 struct mpi3_ioc_facts_data *facts_data)
2810 {
2811 u32 ioc_config, req_sz, facts_flags;
2812
2813 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2814 (sizeof(*facts_data) / 4)) {
2815 ioc_warn(mrioc,
2816 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2817 sizeof(*facts_data),
2818 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2819 }
2820
2821 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2822 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2823 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2824 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2825 ioc_err(mrioc,
2826 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2827 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2828 }
2829
2830 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2831
2832 facts_flags = le32_to_cpu(facts_data->flags);
2833 mrioc->facts.op_req_sz = req_sz;
2834 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2835 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2836 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2837
2838 mrioc->facts.ioc_num = facts_data->ioc_number;
2839 mrioc->facts.who_init = facts_data->who_init;
2840 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2841 mrioc->facts.personality = (facts_flags &
2842 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2843 mrioc->facts.dma_mask = (facts_flags &
2844 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2845 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2846 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2847 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2848 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2849 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2850 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2851 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2852 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2853 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2854 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2855 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2856 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2857 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2858 mrioc->facts.max_pcie_switches =
2859 le16_to_cpu(facts_data->max_pcie_switches);
2860 mrioc->facts.max_sasexpanders =
2861 le16_to_cpu(facts_data->max_sas_expanders);
2862 mrioc->facts.max_sasinitiators =
2863 le16_to_cpu(facts_data->max_sas_initiators);
2864 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2865 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2866 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2867 mrioc->facts.max_op_req_q =
2868 le16_to_cpu(facts_data->max_operational_request_queues);
2869 mrioc->facts.max_op_reply_q =
2870 le16_to_cpu(facts_data->max_operational_reply_queues);
2871 mrioc->facts.ioc_capabilities =
2872 le32_to_cpu(facts_data->ioc_capabilities);
2873 mrioc->facts.fw_ver.build_num =
2874 le16_to_cpu(facts_data->fw_version.build_num);
2875 mrioc->facts.fw_ver.cust_id =
2876 le16_to_cpu(facts_data->fw_version.customer_id);
2877 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2878 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2879 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2880 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2881 mrioc->msix_count = min_t(int, mrioc->msix_count,
2882 mrioc->facts.max_msix_vectors);
2883 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2884 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2885 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2886 mrioc->facts.shutdown_timeout =
2887 le16_to_cpu(facts_data->shutdown_timeout);
2888
2889 mrioc->facts.max_dev_per_tg =
2890 facts_data->max_devices_per_throttle_group;
2891 mrioc->facts.io_throttle_data_length =
2892 le16_to_cpu(facts_data->io_throttle_data_length);
2893 mrioc->facts.max_io_throttle_group =
2894 le16_to_cpu(facts_data->max_io_throttle_group);
2895 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2896 mrioc->facts.io_throttle_high =
2897 le16_to_cpu(facts_data->io_throttle_high);
2898
2899 /* Store in 512b block count */
2900 if (mrioc->facts.io_throttle_data_length)
2901 mrioc->io_throttle_data_length =
2902 (mrioc->facts.io_throttle_data_length * 2 * 4);
2903 else
2904 /* set the length to 1MB + 1K to disable throttle */
2905 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2906
2907 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2908 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2909
2910 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2911 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2912 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2913 ioc_info(mrioc,
2914 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2915 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2916 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2917 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2918 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2919 mrioc->facts.sge_mod_shift);
2920 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2921 mrioc->facts.dma_mask, (facts_flags &
2922 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2923 ioc_info(mrioc,
2924 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2925 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2926 ioc_info(mrioc,
2927 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2928 mrioc->facts.io_throttle_data_length * 4,
2929 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2930 }
2931
2932 /**
2933 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2934 * @mrioc: Adapter instance reference
2935 *
2936 * Allocate and initialize the reply free buffers, sense
2937 * buffers, reply free queue and sense buffer queue.
2938 *
2939 * Return: 0 on success, non-zero on failures.
2940 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)2941 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2942 {
2943 int retval = 0;
2944 u32 sz, i;
2945
2946 if (mrioc->init_cmds.reply)
2947 return retval;
2948
2949 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2950 if (!mrioc->init_cmds.reply)
2951 goto out_failed;
2952
2953 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2954 if (!mrioc->bsg_cmds.reply)
2955 goto out_failed;
2956
2957 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2958 if (!mrioc->transport_cmds.reply)
2959 goto out_failed;
2960
2961 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2962 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2963 GFP_KERNEL);
2964 if (!mrioc->dev_rmhs_cmds[i].reply)
2965 goto out_failed;
2966 }
2967
2968 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2969 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2970 GFP_KERNEL);
2971 if (!mrioc->evtack_cmds[i].reply)
2972 goto out_failed;
2973 }
2974
2975 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2976 if (!mrioc->host_tm_cmds.reply)
2977 goto out_failed;
2978
2979 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2980 if (!mrioc->pel_cmds.reply)
2981 goto out_failed;
2982
2983 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2984 if (!mrioc->pel_abort_cmd.reply)
2985 goto out_failed;
2986
2987 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
2988 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
2989 GFP_KERNEL);
2990 if (!mrioc->removepend_bitmap)
2991 goto out_failed;
2992
2993 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
2994 if (!mrioc->devrem_bitmap)
2995 goto out_failed;
2996
2997 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
2998 GFP_KERNEL);
2999 if (!mrioc->evtack_cmds_bitmap)
3000 goto out_failed;
3001
3002 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3003 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3004 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3005 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3006
3007 /* reply buffer pool, 16 byte align */
3008 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3009 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3010 &mrioc->pdev->dev, sz, 16, 0);
3011 if (!mrioc->reply_buf_pool) {
3012 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3013 goto out_failed;
3014 }
3015
3016 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3017 &mrioc->reply_buf_dma);
3018 if (!mrioc->reply_buf)
3019 goto out_failed;
3020
3021 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3022
3023 /* reply free queue, 8 byte align */
3024 sz = mrioc->reply_free_qsz * 8;
3025 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3026 &mrioc->pdev->dev, sz, 8, 0);
3027 if (!mrioc->reply_free_q_pool) {
3028 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3029 goto out_failed;
3030 }
3031 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3032 GFP_KERNEL, &mrioc->reply_free_q_dma);
3033 if (!mrioc->reply_free_q)
3034 goto out_failed;
3035
3036 /* sense buffer pool, 4 byte align */
3037 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3038 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3039 &mrioc->pdev->dev, sz, 4, 0);
3040 if (!mrioc->sense_buf_pool) {
3041 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3042 goto out_failed;
3043 }
3044 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3045 &mrioc->sense_buf_dma);
3046 if (!mrioc->sense_buf)
3047 goto out_failed;
3048
3049 /* sense buffer queue, 8 byte align */
3050 sz = mrioc->sense_buf_q_sz * 8;
3051 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3052 &mrioc->pdev->dev, sz, 8, 0);
3053 if (!mrioc->sense_buf_q_pool) {
3054 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3055 goto out_failed;
3056 }
3057 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3058 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3059 if (!mrioc->sense_buf_q)
3060 goto out_failed;
3061
3062 return retval;
3063
3064 out_failed:
3065 retval = -1;
3066 return retval;
3067 }
3068
3069 /**
3070 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3071 * buffers
3072 * @mrioc: Adapter instance reference
3073 *
3074 * Helper function to initialize reply and sense buffers along
3075 * with some debug prints.
3076 *
3077 * Return: None.
3078 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3079 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3080 {
3081 u32 sz, i;
3082 dma_addr_t phy_addr;
3083
3084 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3085 ioc_info(mrioc,
3086 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3087 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3088 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3089 sz = mrioc->reply_free_qsz * 8;
3090 ioc_info(mrioc,
3091 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3092 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3093 (unsigned long long)mrioc->reply_free_q_dma);
3094 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3095 ioc_info(mrioc,
3096 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3097 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3098 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3099 sz = mrioc->sense_buf_q_sz * 8;
3100 ioc_info(mrioc,
3101 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3102 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3103 (unsigned long long)mrioc->sense_buf_q_dma);
3104
3105 /* initialize Reply buffer Queue */
3106 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3107 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3108 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3109 mrioc->reply_free_q[i] = cpu_to_le64(0);
3110
3111 /* initialize Sense Buffer Queue */
3112 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3113 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3114 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3115 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3116 }
3117
3118 /**
3119 * mpi3mr_issue_iocinit - Send IOC Init
3120 * @mrioc: Adapter instance reference
3121 *
3122 * Issue IOC Init MPI request through admin queue and wait for
3123 * the completion of it or time out.
3124 *
3125 * Return: 0 on success, non-zero on failures.
3126 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3127 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3128 {
3129 struct mpi3_ioc_init_request iocinit_req;
3130 struct mpi3_driver_info_layout *drv_info;
3131 dma_addr_t data_dma;
3132 u32 data_len = sizeof(*drv_info);
3133 int retval = 0;
3134 ktime_t current_time;
3135
3136 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3137 GFP_KERNEL);
3138 if (!drv_info) {
3139 retval = -1;
3140 goto out;
3141 }
3142 mpimr_initialize_reply_sbuf_queues(mrioc);
3143
3144 drv_info->information_length = cpu_to_le32(data_len);
3145 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3146 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3147 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3148 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3149 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3150 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3151 sizeof(drv_info->driver_release_date));
3152 drv_info->driver_capabilities = 0;
3153 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3154 sizeof(mrioc->driver_info));
3155
3156 memset(&iocinit_req, 0, sizeof(iocinit_req));
3157 mutex_lock(&mrioc->init_cmds.mutex);
3158 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3159 retval = -1;
3160 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3161 mutex_unlock(&mrioc->init_cmds.mutex);
3162 goto out;
3163 }
3164 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3165 mrioc->init_cmds.is_waiting = 1;
3166 mrioc->init_cmds.callback = NULL;
3167 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3168 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3169 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3170 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3171 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3172 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3173 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3174 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3175 iocinit_req.reply_free_queue_address =
3176 cpu_to_le64(mrioc->reply_free_q_dma);
3177 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3178 iocinit_req.sense_buffer_free_queue_depth =
3179 cpu_to_le16(mrioc->sense_buf_q_sz);
3180 iocinit_req.sense_buffer_free_queue_address =
3181 cpu_to_le64(mrioc->sense_buf_q_dma);
3182 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3183
3184 current_time = ktime_get_real();
3185 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3186
3187 init_completion(&mrioc->init_cmds.done);
3188 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3189 sizeof(iocinit_req), 1);
3190 if (retval) {
3191 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3192 goto out_unlock;
3193 }
3194 wait_for_completion_timeout(&mrioc->init_cmds.done,
3195 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3196 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3197 mpi3mr_check_rh_fault_ioc(mrioc,
3198 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3199 ioc_err(mrioc, "ioc_init timed out\n");
3200 retval = -1;
3201 goto out_unlock;
3202 }
3203 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3204 != MPI3_IOCSTATUS_SUCCESS) {
3205 ioc_err(mrioc,
3206 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3207 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3208 mrioc->init_cmds.ioc_loginfo);
3209 retval = -1;
3210 goto out_unlock;
3211 }
3212
3213 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3214 writel(mrioc->reply_free_queue_host_index,
3215 &mrioc->sysif_regs->reply_free_host_index);
3216
3217 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3218 writel(mrioc->sbq_host_index,
3219 &mrioc->sysif_regs->sense_buffer_free_host_index);
3220 out_unlock:
3221 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3222 mutex_unlock(&mrioc->init_cmds.mutex);
3223
3224 out:
3225 if (drv_info)
3226 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3227 data_dma);
3228
3229 return retval;
3230 }
3231
3232 /**
3233 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3234 * @mrioc: Adapter instance reference
3235 * @event: MPI event ID
3236 *
3237 * Un mask the specific event by resetting the event_mask
3238 * bitmap.
3239 *
3240 * Return: 0 on success, non-zero on failures.
3241 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3242 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3243 {
3244 u32 desired_event;
3245 u8 word;
3246
3247 if (event >= 128)
3248 return;
3249
3250 desired_event = (1 << (event % 32));
3251 word = event / 32;
3252
3253 mrioc->event_masks[word] &= ~desired_event;
3254 }
3255
3256 /**
3257 * mpi3mr_issue_event_notification - Send event notification
3258 * @mrioc: Adapter instance reference
3259 *
3260 * Issue event notification MPI request through admin queue and
3261 * wait for the completion of it or time out.
3262 *
3263 * Return: 0 on success, non-zero on failures.
3264 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3265 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3266 {
3267 struct mpi3_event_notification_request evtnotify_req;
3268 int retval = 0;
3269 u8 i;
3270
3271 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3272 mutex_lock(&mrioc->init_cmds.mutex);
3273 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3274 retval = -1;
3275 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3276 mutex_unlock(&mrioc->init_cmds.mutex);
3277 goto out;
3278 }
3279 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3280 mrioc->init_cmds.is_waiting = 1;
3281 mrioc->init_cmds.callback = NULL;
3282 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3283 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3284 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3285 evtnotify_req.event_masks[i] =
3286 cpu_to_le32(mrioc->event_masks[i]);
3287 init_completion(&mrioc->init_cmds.done);
3288 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3289 sizeof(evtnotify_req), 1);
3290 if (retval) {
3291 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3292 goto out_unlock;
3293 }
3294 wait_for_completion_timeout(&mrioc->init_cmds.done,
3295 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3296 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3297 ioc_err(mrioc, "event notification timed out\n");
3298 mpi3mr_check_rh_fault_ioc(mrioc,
3299 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3300 retval = -1;
3301 goto out_unlock;
3302 }
3303 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3304 != MPI3_IOCSTATUS_SUCCESS) {
3305 ioc_err(mrioc,
3306 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3307 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3308 mrioc->init_cmds.ioc_loginfo);
3309 retval = -1;
3310 goto out_unlock;
3311 }
3312
3313 out_unlock:
3314 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3315 mutex_unlock(&mrioc->init_cmds.mutex);
3316 out:
3317 return retval;
3318 }
3319
3320 /**
3321 * mpi3mr_process_event_ack - Process event acknowledgment
3322 * @mrioc: Adapter instance reference
3323 * @event: MPI3 event ID
3324 * @event_ctx: event context
3325 *
3326 * Send event acknowledgment through admin queue and wait for
3327 * it to complete.
3328 *
3329 * Return: 0 on success, non-zero on failures.
3330 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3331 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3332 u32 event_ctx)
3333 {
3334 struct mpi3_event_ack_request evtack_req;
3335 int retval = 0;
3336
3337 memset(&evtack_req, 0, sizeof(evtack_req));
3338 mutex_lock(&mrioc->init_cmds.mutex);
3339 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3340 retval = -1;
3341 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3342 mutex_unlock(&mrioc->init_cmds.mutex);
3343 goto out;
3344 }
3345 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3346 mrioc->init_cmds.is_waiting = 1;
3347 mrioc->init_cmds.callback = NULL;
3348 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3349 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3350 evtack_req.event = event;
3351 evtack_req.event_context = cpu_to_le32(event_ctx);
3352
3353 init_completion(&mrioc->init_cmds.done);
3354 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3355 sizeof(evtack_req), 1);
3356 if (retval) {
3357 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3358 goto out_unlock;
3359 }
3360 wait_for_completion_timeout(&mrioc->init_cmds.done,
3361 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3362 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3363 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3364 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3365 mpi3mr_soft_reset_handler(mrioc,
3366 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3367 retval = -1;
3368 goto out_unlock;
3369 }
3370 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3371 != MPI3_IOCSTATUS_SUCCESS) {
3372 ioc_err(mrioc,
3373 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3374 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3375 mrioc->init_cmds.ioc_loginfo);
3376 retval = -1;
3377 goto out_unlock;
3378 }
3379
3380 out_unlock:
3381 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3382 mutex_unlock(&mrioc->init_cmds.mutex);
3383 out:
3384 return retval;
3385 }
3386
3387 /**
3388 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3389 * @mrioc: Adapter instance reference
3390 *
3391 * Allocate chain buffers and set a bitmap to indicate free
3392 * chain buffers. Chain buffers are used to pass the SGE
3393 * information along with MPI3 SCSI IO requests for host I/O.
3394 *
3395 * Return: 0 on success, non-zero on failure
3396 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3397 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3398 {
3399 int retval = 0;
3400 u32 sz, i;
3401 u16 num_chains;
3402
3403 if (mrioc->chain_sgl_list)
3404 return retval;
3405
3406 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3407
3408 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3409 | SHOST_DIX_TYPE1_PROTECTION
3410 | SHOST_DIX_TYPE2_PROTECTION
3411 | SHOST_DIX_TYPE3_PROTECTION))
3412 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3413
3414 mrioc->chain_buf_count = num_chains;
3415 sz = sizeof(struct chain_element) * num_chains;
3416 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3417 if (!mrioc->chain_sgl_list)
3418 goto out_failed;
3419
3420 sz = MPI3MR_PAGE_SIZE_4K;
3421 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3422 &mrioc->pdev->dev, sz, 16, 0);
3423 if (!mrioc->chain_buf_pool) {
3424 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3425 goto out_failed;
3426 }
3427
3428 for (i = 0; i < num_chains; i++) {
3429 mrioc->chain_sgl_list[i].addr =
3430 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3431 &mrioc->chain_sgl_list[i].dma_addr);
3432
3433 if (!mrioc->chain_sgl_list[i].addr)
3434 goto out_failed;
3435 }
3436 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3437 if (!mrioc->chain_bitmap)
3438 goto out_failed;
3439 return retval;
3440 out_failed:
3441 retval = -1;
3442 return retval;
3443 }
3444
3445 /**
3446 * mpi3mr_port_enable_complete - Mark port enable complete
3447 * @mrioc: Adapter instance reference
3448 * @drv_cmd: Internal command tracker
3449 *
3450 * Call back for asynchronous port enable request sets the
3451 * driver command to indicate port enable request is complete.
3452 *
3453 * Return: Nothing
3454 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3455 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3456 struct mpi3mr_drv_cmd *drv_cmd)
3457 {
3458 drv_cmd->callback = NULL;
3459 mrioc->scan_started = 0;
3460 if (drv_cmd->state & MPI3MR_CMD_RESET)
3461 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3462 else
3463 mrioc->scan_failed = drv_cmd->ioc_status;
3464 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3465 }
3466
3467 /**
3468 * mpi3mr_issue_port_enable - Issue Port Enable
3469 * @mrioc: Adapter instance reference
3470 * @async: Flag to wait for completion or not
3471 *
3472 * Issue Port Enable MPI request through admin queue and if the
3473 * async flag is not set wait for the completion of the port
3474 * enable or time out.
3475 *
3476 * Return: 0 on success, non-zero on failures.
3477 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3478 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3479 {
3480 struct mpi3_port_enable_request pe_req;
3481 int retval = 0;
3482 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3483
3484 memset(&pe_req, 0, sizeof(pe_req));
3485 mutex_lock(&mrioc->init_cmds.mutex);
3486 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3487 retval = -1;
3488 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3489 mutex_unlock(&mrioc->init_cmds.mutex);
3490 goto out;
3491 }
3492 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3493 if (async) {
3494 mrioc->init_cmds.is_waiting = 0;
3495 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3496 } else {
3497 mrioc->init_cmds.is_waiting = 1;
3498 mrioc->init_cmds.callback = NULL;
3499 init_completion(&mrioc->init_cmds.done);
3500 }
3501 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3502 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3503
3504 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3505 if (retval) {
3506 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3507 goto out_unlock;
3508 }
3509 if (async) {
3510 mutex_unlock(&mrioc->init_cmds.mutex);
3511 goto out;
3512 }
3513
3514 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3515 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3516 ioc_err(mrioc, "port enable timed out\n");
3517 retval = -1;
3518 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3519 goto out_unlock;
3520 }
3521 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3522
3523 out_unlock:
3524 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3525 mutex_unlock(&mrioc->init_cmds.mutex);
3526 out:
3527 return retval;
3528 }
3529
3530 /* Protocol type to name mapper structure */
3531 static const struct {
3532 u8 protocol;
3533 char *name;
3534 } mpi3mr_protocols[] = {
3535 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3536 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3537 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3538 };
3539
3540 /* Capability to name mapper structure*/
3541 static const struct {
3542 u32 capability;
3543 char *name;
3544 } mpi3mr_capabilities[] = {
3545 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3546 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3547 };
3548
3549 /**
3550 * mpi3mr_print_ioc_info - Display controller information
3551 * @mrioc: Adapter instance reference
3552 *
3553 * Display controller personalit, capability, supported
3554 * protocols etc.
3555 *
3556 * Return: Nothing
3557 */
3558 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)3559 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3560 {
3561 int i = 0, bytes_written = 0;
3562 char personality[16];
3563 char protocol[50] = {0};
3564 char capabilities[100] = {0};
3565 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3566
3567 switch (mrioc->facts.personality) {
3568 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3569 strncpy(personality, "Enhanced HBA", sizeof(personality));
3570 break;
3571 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3572 strncpy(personality, "RAID", sizeof(personality));
3573 break;
3574 default:
3575 strncpy(personality, "Unknown", sizeof(personality));
3576 break;
3577 }
3578
3579 ioc_info(mrioc, "Running in %s Personality", personality);
3580
3581 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3582 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3583 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3584
3585 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3586 if (mrioc->facts.protocol_flags &
3587 mpi3mr_protocols[i].protocol) {
3588 bytes_written += scnprintf(protocol + bytes_written,
3589 sizeof(protocol) - bytes_written, "%s%s",
3590 bytes_written ? "," : "",
3591 mpi3mr_protocols[i].name);
3592 }
3593 }
3594
3595 bytes_written = 0;
3596 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3597 if (mrioc->facts.protocol_flags &
3598 mpi3mr_capabilities[i].capability) {
3599 bytes_written += scnprintf(capabilities + bytes_written,
3600 sizeof(capabilities) - bytes_written, "%s%s",
3601 bytes_written ? "," : "",
3602 mpi3mr_capabilities[i].name);
3603 }
3604 }
3605
3606 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3607 protocol, capabilities);
3608 }
3609
3610 /**
3611 * mpi3mr_cleanup_resources - Free PCI resources
3612 * @mrioc: Adapter instance reference
3613 *
3614 * Unmap PCI device memory and disable PCI device.
3615 *
3616 * Return: 0 on success and non-zero on failure.
3617 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)3618 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3619 {
3620 struct pci_dev *pdev = mrioc->pdev;
3621
3622 mpi3mr_cleanup_isr(mrioc);
3623
3624 if (mrioc->sysif_regs) {
3625 iounmap((void __iomem *)mrioc->sysif_regs);
3626 mrioc->sysif_regs = NULL;
3627 }
3628
3629 if (pci_is_enabled(pdev)) {
3630 if (mrioc->bars)
3631 pci_release_selected_regions(pdev, mrioc->bars);
3632 pci_disable_device(pdev);
3633 }
3634 }
3635
3636 /**
3637 * mpi3mr_setup_resources - Enable PCI resources
3638 * @mrioc: Adapter instance reference
3639 *
3640 * Enable PCI device memory, MSI-x registers and set DMA mask.
3641 *
3642 * Return: 0 on success and non-zero on failure.
3643 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)3644 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3645 {
3646 struct pci_dev *pdev = mrioc->pdev;
3647 u32 memap_sz = 0;
3648 int i, retval = 0, capb = 0;
3649 u16 message_control;
3650 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3651 (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) &&
3652 (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3653
3654 if (pci_enable_device_mem(pdev)) {
3655 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3656 retval = -ENODEV;
3657 goto out_failed;
3658 }
3659
3660 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3661 if (!capb) {
3662 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3663 retval = -ENODEV;
3664 goto out_failed;
3665 }
3666 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3667
3668 if (pci_request_selected_regions(pdev, mrioc->bars,
3669 mrioc->driver_name)) {
3670 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3671 retval = -ENODEV;
3672 goto out_failed;
3673 }
3674
3675 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3676 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3677 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3678 memap_sz = pci_resource_len(pdev, i);
3679 mrioc->sysif_regs =
3680 ioremap(mrioc->sysif_regs_phys, memap_sz);
3681 break;
3682 }
3683 }
3684
3685 pci_set_master(pdev);
3686
3687 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3688 if (retval) {
3689 if (dma_mask != DMA_BIT_MASK(32)) {
3690 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3691 dma_mask = DMA_BIT_MASK(32);
3692 retval = dma_set_mask_and_coherent(&pdev->dev,
3693 dma_mask);
3694 }
3695 if (retval) {
3696 mrioc->dma_mask = 0;
3697 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3698 goto out_failed;
3699 }
3700 }
3701 mrioc->dma_mask = dma_mask;
3702
3703 if (!mrioc->sysif_regs) {
3704 ioc_err(mrioc,
3705 "Unable to map adapter memory or resource not found\n");
3706 retval = -EINVAL;
3707 goto out_failed;
3708 }
3709
3710 pci_read_config_word(pdev, capb + 2, &message_control);
3711 mrioc->msix_count = (message_control & 0x3FF) + 1;
3712
3713 pci_save_state(pdev);
3714
3715 pci_set_drvdata(pdev, mrioc->shost);
3716
3717 mpi3mr_ioc_disable_intr(mrioc);
3718
3719 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3720 (unsigned long long)mrioc->sysif_regs_phys,
3721 mrioc->sysif_regs, memap_sz);
3722 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3723 mrioc->msix_count);
3724
3725 if (!reset_devices && poll_queues > 0)
3726 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3727 mrioc->msix_count - 2);
3728 return retval;
3729
3730 out_failed:
3731 mpi3mr_cleanup_resources(mrioc);
3732 return retval;
3733 }
3734
3735 /**
3736 * mpi3mr_enable_events - Enable required events
3737 * @mrioc: Adapter instance reference
3738 *
3739 * This routine unmasks the events required by the driver by
3740 * sennding appropriate event mask bitmapt through an event
3741 * notification request.
3742 *
3743 * Return: 0 on success and non-zero on failure.
3744 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)3745 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3746 {
3747 int retval = 0;
3748 u32 i;
3749
3750 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3751 mrioc->event_masks[i] = -1;
3752
3753 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3754 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3755 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3756 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3757 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3758 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3759 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3760 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3761 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3762 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3763 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3764 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3765 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3766 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3767
3768 retval = mpi3mr_issue_event_notification(mrioc);
3769 if (retval)
3770 ioc_err(mrioc, "failed to issue event notification %d\n",
3771 retval);
3772 return retval;
3773 }
3774
3775 /**
3776 * mpi3mr_init_ioc - Initialize the controller
3777 * @mrioc: Adapter instance reference
3778 *
3779 * This the controller initialization routine, executed either
3780 * after soft reset or from pci probe callback.
3781 * Setup the required resources, memory map the controller
3782 * registers, create admin and operational reply queue pairs,
3783 * allocate required memory for reply pool, sense buffer pool,
3784 * issue IOC init request to the firmware, unmask the events and
3785 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3786 * volumes.
3787 *
3788 * Return: 0 on success and non-zero on failure.
3789 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)3790 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3791 {
3792 int retval = 0;
3793 u8 retry = 0;
3794 struct mpi3_ioc_facts_data facts_data;
3795 u32 sz;
3796
3797 retry_init:
3798 retval = mpi3mr_bring_ioc_ready(mrioc);
3799 if (retval) {
3800 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3801 retval);
3802 goto out_failed_noretry;
3803 }
3804
3805 retval = mpi3mr_setup_isr(mrioc, 1);
3806 if (retval) {
3807 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3808 retval);
3809 goto out_failed_noretry;
3810 }
3811
3812 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3813 if (retval) {
3814 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3815 retval);
3816 goto out_failed;
3817 }
3818
3819 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3820
3821 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3822 atomic_set(&mrioc->pend_large_data_sz, 0);
3823
3824 if (reset_devices)
3825 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3826 MPI3MR_HOST_IOS_KDUMP);
3827
3828 if (!(mrioc->facts.ioc_capabilities &
3829 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3830 mrioc->sas_transport_enabled = 1;
3831 mrioc->scsi_device_channel = 1;
3832 mrioc->shost->max_channel = 1;
3833 mrioc->shost->transportt = mpi3mr_transport_template;
3834 }
3835
3836 mrioc->reply_sz = mrioc->facts.reply_sz;
3837
3838 retval = mpi3mr_check_reset_dma_mask(mrioc);
3839 if (retval) {
3840 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3841 retval);
3842 goto out_failed_noretry;
3843 }
3844
3845 mpi3mr_print_ioc_info(mrioc);
3846
3847 if (!mrioc->cfg_page) {
3848 dprint_init(mrioc, "allocating config page buffers\n");
3849 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3850 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3851 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
3852 if (!mrioc->cfg_page) {
3853 retval = -1;
3854 goto out_failed_noretry;
3855 }
3856 }
3857
3858 if (!mrioc->init_cmds.reply) {
3859 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3860 if (retval) {
3861 ioc_err(mrioc,
3862 "%s :Failed to allocated reply sense buffers %d\n",
3863 __func__, retval);
3864 goto out_failed_noretry;
3865 }
3866 }
3867
3868 if (!mrioc->chain_sgl_list) {
3869 retval = mpi3mr_alloc_chain_bufs(mrioc);
3870 if (retval) {
3871 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3872 retval);
3873 goto out_failed_noretry;
3874 }
3875 }
3876
3877 retval = mpi3mr_issue_iocinit(mrioc);
3878 if (retval) {
3879 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3880 retval);
3881 goto out_failed;
3882 }
3883
3884 retval = mpi3mr_print_pkg_ver(mrioc);
3885 if (retval) {
3886 ioc_err(mrioc, "failed to get package version\n");
3887 goto out_failed;
3888 }
3889
3890 retval = mpi3mr_setup_isr(mrioc, 0);
3891 if (retval) {
3892 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3893 retval);
3894 goto out_failed_noretry;
3895 }
3896
3897 retval = mpi3mr_create_op_queues(mrioc);
3898 if (retval) {
3899 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3900 retval);
3901 goto out_failed;
3902 }
3903
3904 if (!mrioc->pel_seqnum_virt) {
3905 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3906 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3907 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3908 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3909 GFP_KERNEL);
3910 if (!mrioc->pel_seqnum_virt) {
3911 retval = -ENOMEM;
3912 goto out_failed_noretry;
3913 }
3914 }
3915
3916 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3917 dprint_init(mrioc, "allocating memory for throttle groups\n");
3918 sz = sizeof(struct mpi3mr_throttle_group_info);
3919 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3920 if (!mrioc->throttle_groups) {
3921 retval = -1;
3922 goto out_failed_noretry;
3923 }
3924 }
3925
3926 retval = mpi3mr_enable_events(mrioc);
3927 if (retval) {
3928 ioc_err(mrioc, "failed to enable events %d\n",
3929 retval);
3930 goto out_failed;
3931 }
3932
3933 ioc_info(mrioc, "controller initialization completed successfully\n");
3934 return retval;
3935 out_failed:
3936 if (retry < 2) {
3937 retry++;
3938 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3939 retry);
3940 mpi3mr_memset_buffers(mrioc);
3941 goto retry_init;
3942 }
3943 retval = -1;
3944 out_failed_noretry:
3945 ioc_err(mrioc, "controller initialization failed\n");
3946 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3947 MPI3MR_RESET_FROM_CTLR_CLEANUP);
3948 mrioc->unrecoverable = 1;
3949 return retval;
3950 }
3951
3952 /**
3953 * mpi3mr_reinit_ioc - Re-Initialize the controller
3954 * @mrioc: Adapter instance reference
3955 * @is_resume: Called from resume or reset path
3956 *
3957 * This the controller re-initialization routine, executed from
3958 * the soft reset handler or resume callback. Creates
3959 * operational reply queue pairs, allocate required memory for
3960 * reply pool, sense buffer pool, issue IOC init request to the
3961 * firmware, unmask the events and issue port enable to discover
3962 * SAS/SATA/NVMe devices and RAID volumes.
3963 *
3964 * Return: 0 on success and non-zero on failure.
3965 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)3966 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3967 {
3968 int retval = 0;
3969 u8 retry = 0;
3970 struct mpi3_ioc_facts_data facts_data;
3971 u32 pe_timeout, ioc_status;
3972
3973 retry_init:
3974 pe_timeout =
3975 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3976
3977 dprint_reset(mrioc, "bringing up the controller to ready state\n");
3978 retval = mpi3mr_bring_ioc_ready(mrioc);
3979 if (retval) {
3980 ioc_err(mrioc, "failed to bring to ready state\n");
3981 goto out_failed_noretry;
3982 }
3983
3984 if (is_resume) {
3985 dprint_reset(mrioc, "setting up single ISR\n");
3986 retval = mpi3mr_setup_isr(mrioc, 1);
3987 if (retval) {
3988 ioc_err(mrioc, "failed to setup ISR\n");
3989 goto out_failed_noretry;
3990 }
3991 } else
3992 mpi3mr_ioc_enable_intr(mrioc);
3993
3994 dprint_reset(mrioc, "getting ioc_facts\n");
3995 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3996 if (retval) {
3997 ioc_err(mrioc, "failed to get ioc_facts\n");
3998 goto out_failed;
3999 }
4000
4001 dprint_reset(mrioc, "validating ioc_facts\n");
4002 retval = mpi3mr_revalidate_factsdata(mrioc);
4003 if (retval) {
4004 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4005 goto out_failed_noretry;
4006 }
4007
4008 mpi3mr_print_ioc_info(mrioc);
4009
4010 dprint_reset(mrioc, "sending ioc_init\n");
4011 retval = mpi3mr_issue_iocinit(mrioc);
4012 if (retval) {
4013 ioc_err(mrioc, "failed to send ioc_init\n");
4014 goto out_failed;
4015 }
4016
4017 dprint_reset(mrioc, "getting package version\n");
4018 retval = mpi3mr_print_pkg_ver(mrioc);
4019 if (retval) {
4020 ioc_err(mrioc, "failed to get package version\n");
4021 goto out_failed;
4022 }
4023
4024 if (is_resume) {
4025 dprint_reset(mrioc, "setting up multiple ISR\n");
4026 retval = mpi3mr_setup_isr(mrioc, 0);
4027 if (retval) {
4028 ioc_err(mrioc, "failed to re-setup ISR\n");
4029 goto out_failed_noretry;
4030 }
4031 }
4032
4033 dprint_reset(mrioc, "creating operational queue pairs\n");
4034 retval = mpi3mr_create_op_queues(mrioc);
4035 if (retval) {
4036 ioc_err(mrioc, "failed to create operational queue pairs\n");
4037 goto out_failed;
4038 }
4039
4040 if (!mrioc->pel_seqnum_virt) {
4041 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4042 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4043 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4044 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4045 GFP_KERNEL);
4046 if (!mrioc->pel_seqnum_virt) {
4047 retval = -ENOMEM;
4048 goto out_failed_noretry;
4049 }
4050 }
4051
4052 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4053 ioc_err(mrioc,
4054 "cannot create minimum number of operational queues expected:%d created:%d\n",
4055 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4056 retval = -1;
4057 goto out_failed_noretry;
4058 }
4059
4060 dprint_reset(mrioc, "enabling events\n");
4061 retval = mpi3mr_enable_events(mrioc);
4062 if (retval) {
4063 ioc_err(mrioc, "failed to enable events\n");
4064 goto out_failed;
4065 }
4066
4067 mrioc->device_refresh_on = 1;
4068 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4069
4070 ioc_info(mrioc, "sending port enable\n");
4071 retval = mpi3mr_issue_port_enable(mrioc, 1);
4072 if (retval) {
4073 ioc_err(mrioc, "failed to issue port enable\n");
4074 goto out_failed;
4075 }
4076 do {
4077 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4078 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4079 break;
4080 if (!pci_device_is_present(mrioc->pdev))
4081 mrioc->unrecoverable = 1;
4082 if (mrioc->unrecoverable) {
4083 retval = -1;
4084 goto out_failed_noretry;
4085 }
4086 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4087 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4088 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4089 mpi3mr_print_fault_info(mrioc);
4090 mrioc->init_cmds.is_waiting = 0;
4091 mrioc->init_cmds.callback = NULL;
4092 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4093 goto out_failed;
4094 }
4095 } while (--pe_timeout);
4096
4097 if (!pe_timeout) {
4098 ioc_err(mrioc, "port enable timed out\n");
4099 mpi3mr_check_rh_fault_ioc(mrioc,
4100 MPI3MR_RESET_FROM_PE_TIMEOUT);
4101 mrioc->init_cmds.is_waiting = 0;
4102 mrioc->init_cmds.callback = NULL;
4103 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4104 goto out_failed;
4105 } else if (mrioc->scan_failed) {
4106 ioc_err(mrioc,
4107 "port enable failed with status=0x%04x\n",
4108 mrioc->scan_failed);
4109 } else
4110 ioc_info(mrioc, "port enable completed successfully\n");
4111
4112 ioc_info(mrioc, "controller %s completed successfully\n",
4113 (is_resume)?"resume":"re-initialization");
4114 return retval;
4115 out_failed:
4116 if (retry < 2) {
4117 retry++;
4118 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4119 (is_resume)?"resume":"re-initialization", retry);
4120 mpi3mr_memset_buffers(mrioc);
4121 goto retry_init;
4122 }
4123 retval = -1;
4124 out_failed_noretry:
4125 ioc_err(mrioc, "controller %s is failed\n",
4126 (is_resume)?"resume":"re-initialization");
4127 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4128 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4129 mrioc->unrecoverable = 1;
4130 return retval;
4131 }
4132
4133 /**
4134 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4135 * segments
4136 * @mrioc: Adapter instance reference
4137 * @qidx: Operational reply queue index
4138 *
4139 * Return: Nothing.
4140 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4141 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4142 {
4143 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4144 struct segments *segments;
4145 int i, size;
4146
4147 if (!op_reply_q->q_segments)
4148 return;
4149
4150 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4151 segments = op_reply_q->q_segments;
4152 for (i = 0; i < op_reply_q->num_segments; i++)
4153 memset(segments[i].segment, 0, size);
4154 }
4155
4156 /**
4157 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4158 * segments
4159 * @mrioc: Adapter instance reference
4160 * @qidx: Operational request queue index
4161 *
4162 * Return: Nothing.
4163 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4164 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4165 {
4166 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4167 struct segments *segments;
4168 int i, size;
4169
4170 if (!op_req_q->q_segments)
4171 return;
4172
4173 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4174 segments = op_req_q->q_segments;
4175 for (i = 0; i < op_req_q->num_segments; i++)
4176 memset(segments[i].segment, 0, size);
4177 }
4178
4179 /**
4180 * mpi3mr_memset_buffers - memset memory for a controller
4181 * @mrioc: Adapter instance reference
4182 *
4183 * clear all the memory allocated for a controller, typically
4184 * called post reset to reuse the memory allocated during the
4185 * controller init.
4186 *
4187 * Return: Nothing.
4188 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4189 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4190 {
4191 u16 i;
4192 struct mpi3mr_throttle_group_info *tg;
4193
4194 mrioc->change_count = 0;
4195 mrioc->active_poll_qcount = 0;
4196 mrioc->default_qcount = 0;
4197 if (mrioc->admin_req_base)
4198 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4199 if (mrioc->admin_reply_base)
4200 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4201 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4202
4203 if (mrioc->init_cmds.reply) {
4204 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4205 memset(mrioc->bsg_cmds.reply, 0,
4206 sizeof(*mrioc->bsg_cmds.reply));
4207 memset(mrioc->host_tm_cmds.reply, 0,
4208 sizeof(*mrioc->host_tm_cmds.reply));
4209 memset(mrioc->pel_cmds.reply, 0,
4210 sizeof(*mrioc->pel_cmds.reply));
4211 memset(mrioc->pel_abort_cmd.reply, 0,
4212 sizeof(*mrioc->pel_abort_cmd.reply));
4213 memset(mrioc->transport_cmds.reply, 0,
4214 sizeof(*mrioc->transport_cmds.reply));
4215 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4216 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4217 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4218 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4219 memset(mrioc->evtack_cmds[i].reply, 0,
4220 sizeof(*mrioc->evtack_cmds[i].reply));
4221 bitmap_clear(mrioc->removepend_bitmap, 0,
4222 mrioc->dev_handle_bitmap_bits);
4223 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4224 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4225 MPI3MR_NUM_EVTACKCMD);
4226 }
4227
4228 for (i = 0; i < mrioc->num_queues; i++) {
4229 mrioc->op_reply_qinfo[i].qid = 0;
4230 mrioc->op_reply_qinfo[i].ci = 0;
4231 mrioc->op_reply_qinfo[i].num_replies = 0;
4232 mrioc->op_reply_qinfo[i].ephase = 0;
4233 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4234 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4235 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4236
4237 mrioc->req_qinfo[i].ci = 0;
4238 mrioc->req_qinfo[i].pi = 0;
4239 mrioc->req_qinfo[i].num_requests = 0;
4240 mrioc->req_qinfo[i].qid = 0;
4241 mrioc->req_qinfo[i].reply_qid = 0;
4242 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4243 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4244 }
4245
4246 atomic_set(&mrioc->pend_large_data_sz, 0);
4247 if (mrioc->throttle_groups) {
4248 tg = mrioc->throttle_groups;
4249 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4250 tg->id = 0;
4251 tg->fw_qd = 0;
4252 tg->modified_qd = 0;
4253 tg->io_divert = 0;
4254 tg->need_qd_reduction = 0;
4255 tg->high = 0;
4256 tg->low = 0;
4257 tg->qd_reduction = 0;
4258 atomic_set(&tg->pend_large_data_sz, 0);
4259 }
4260 }
4261 }
4262
4263 /**
4264 * mpi3mr_free_mem - Free memory allocated for a controller
4265 * @mrioc: Adapter instance reference
4266 *
4267 * Free all the memory allocated for a controller.
4268 *
4269 * Return: Nothing.
4270 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4271 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4272 {
4273 u16 i;
4274 struct mpi3mr_intr_info *intr_info;
4275
4276 mpi3mr_free_enclosure_list(mrioc);
4277
4278 if (mrioc->sense_buf_pool) {
4279 if (mrioc->sense_buf)
4280 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4281 mrioc->sense_buf_dma);
4282 dma_pool_destroy(mrioc->sense_buf_pool);
4283 mrioc->sense_buf = NULL;
4284 mrioc->sense_buf_pool = NULL;
4285 }
4286 if (mrioc->sense_buf_q_pool) {
4287 if (mrioc->sense_buf_q)
4288 dma_pool_free(mrioc->sense_buf_q_pool,
4289 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4290 dma_pool_destroy(mrioc->sense_buf_q_pool);
4291 mrioc->sense_buf_q = NULL;
4292 mrioc->sense_buf_q_pool = NULL;
4293 }
4294
4295 if (mrioc->reply_buf_pool) {
4296 if (mrioc->reply_buf)
4297 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4298 mrioc->reply_buf_dma);
4299 dma_pool_destroy(mrioc->reply_buf_pool);
4300 mrioc->reply_buf = NULL;
4301 mrioc->reply_buf_pool = NULL;
4302 }
4303 if (mrioc->reply_free_q_pool) {
4304 if (mrioc->reply_free_q)
4305 dma_pool_free(mrioc->reply_free_q_pool,
4306 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4307 dma_pool_destroy(mrioc->reply_free_q_pool);
4308 mrioc->reply_free_q = NULL;
4309 mrioc->reply_free_q_pool = NULL;
4310 }
4311
4312 for (i = 0; i < mrioc->num_op_req_q; i++)
4313 mpi3mr_free_op_req_q_segments(mrioc, i);
4314
4315 for (i = 0; i < mrioc->num_op_reply_q; i++)
4316 mpi3mr_free_op_reply_q_segments(mrioc, i);
4317
4318 for (i = 0; i < mrioc->intr_info_count; i++) {
4319 intr_info = mrioc->intr_info + i;
4320 intr_info->op_reply_q = NULL;
4321 }
4322
4323 kfree(mrioc->req_qinfo);
4324 mrioc->req_qinfo = NULL;
4325 mrioc->num_op_req_q = 0;
4326
4327 kfree(mrioc->op_reply_qinfo);
4328 mrioc->op_reply_qinfo = NULL;
4329 mrioc->num_op_reply_q = 0;
4330
4331 kfree(mrioc->init_cmds.reply);
4332 mrioc->init_cmds.reply = NULL;
4333
4334 kfree(mrioc->bsg_cmds.reply);
4335 mrioc->bsg_cmds.reply = NULL;
4336
4337 kfree(mrioc->host_tm_cmds.reply);
4338 mrioc->host_tm_cmds.reply = NULL;
4339
4340 kfree(mrioc->pel_cmds.reply);
4341 mrioc->pel_cmds.reply = NULL;
4342
4343 kfree(mrioc->pel_abort_cmd.reply);
4344 mrioc->pel_abort_cmd.reply = NULL;
4345
4346 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4347 kfree(mrioc->evtack_cmds[i].reply);
4348 mrioc->evtack_cmds[i].reply = NULL;
4349 }
4350
4351 bitmap_free(mrioc->removepend_bitmap);
4352 mrioc->removepend_bitmap = NULL;
4353
4354 bitmap_free(mrioc->devrem_bitmap);
4355 mrioc->devrem_bitmap = NULL;
4356
4357 bitmap_free(mrioc->evtack_cmds_bitmap);
4358 mrioc->evtack_cmds_bitmap = NULL;
4359
4360 bitmap_free(mrioc->chain_bitmap);
4361 mrioc->chain_bitmap = NULL;
4362
4363 kfree(mrioc->transport_cmds.reply);
4364 mrioc->transport_cmds.reply = NULL;
4365
4366 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4367 kfree(mrioc->dev_rmhs_cmds[i].reply);
4368 mrioc->dev_rmhs_cmds[i].reply = NULL;
4369 }
4370
4371 if (mrioc->chain_buf_pool) {
4372 for (i = 0; i < mrioc->chain_buf_count; i++) {
4373 if (mrioc->chain_sgl_list[i].addr) {
4374 dma_pool_free(mrioc->chain_buf_pool,
4375 mrioc->chain_sgl_list[i].addr,
4376 mrioc->chain_sgl_list[i].dma_addr);
4377 mrioc->chain_sgl_list[i].addr = NULL;
4378 }
4379 }
4380 dma_pool_destroy(mrioc->chain_buf_pool);
4381 mrioc->chain_buf_pool = NULL;
4382 }
4383
4384 kfree(mrioc->chain_sgl_list);
4385 mrioc->chain_sgl_list = NULL;
4386
4387 if (mrioc->admin_reply_base) {
4388 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4389 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4390 mrioc->admin_reply_base = NULL;
4391 }
4392 if (mrioc->admin_req_base) {
4393 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4394 mrioc->admin_req_base, mrioc->admin_req_dma);
4395 mrioc->admin_req_base = NULL;
4396 }
4397 if (mrioc->cfg_page) {
4398 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4399 mrioc->cfg_page, mrioc->cfg_page_dma);
4400 mrioc->cfg_page = NULL;
4401 }
4402 if (mrioc->pel_seqnum_virt) {
4403 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4404 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4405 mrioc->pel_seqnum_virt = NULL;
4406 }
4407
4408 kfree(mrioc->throttle_groups);
4409 mrioc->throttle_groups = NULL;
4410
4411 kfree(mrioc->logdata_buf);
4412 mrioc->logdata_buf = NULL;
4413
4414 }
4415
4416 /**
4417 * mpi3mr_issue_ioc_shutdown - shutdown controller
4418 * @mrioc: Adapter instance reference
4419 *
4420 * Send shutodwn notification to the controller and wait for the
4421 * shutdown_timeout for it to be completed.
4422 *
4423 * Return: Nothing.
4424 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)4425 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4426 {
4427 u32 ioc_config, ioc_status;
4428 u8 retval = 1;
4429 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4430
4431 ioc_info(mrioc, "Issuing shutdown Notification\n");
4432 if (mrioc->unrecoverable) {
4433 ioc_warn(mrioc,
4434 "IOC is unrecoverable shutdown is not issued\n");
4435 return;
4436 }
4437 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4438 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4439 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4440 ioc_info(mrioc, "shutdown already in progress\n");
4441 return;
4442 }
4443
4444 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4445 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4446 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4447
4448 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4449
4450 if (mrioc->facts.shutdown_timeout)
4451 timeout = mrioc->facts.shutdown_timeout * 10;
4452
4453 do {
4454 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4455 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4456 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4457 retval = 0;
4458 break;
4459 }
4460 msleep(100);
4461 } while (--timeout);
4462
4463 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4464 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4465
4466 if (retval) {
4467 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4468 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4469 ioc_warn(mrioc,
4470 "shutdown still in progress after timeout\n");
4471 }
4472
4473 ioc_info(mrioc,
4474 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4475 (!retval) ? "successful" : "failed", ioc_status,
4476 ioc_config);
4477 }
4478
4479 /**
4480 * mpi3mr_cleanup_ioc - Cleanup controller
4481 * @mrioc: Adapter instance reference
4482 *
4483 * controller cleanup handler, Message unit reset or soft reset
4484 * and shutdown notification is issued to the controller.
4485 *
4486 * Return: Nothing.
4487 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)4488 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4489 {
4490 enum mpi3mr_iocstate ioc_state;
4491
4492 dprint_exit(mrioc, "cleaning up the controller\n");
4493 mpi3mr_ioc_disable_intr(mrioc);
4494
4495 ioc_state = mpi3mr_get_iocstate(mrioc);
4496
4497 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4498 (ioc_state == MRIOC_STATE_READY)) {
4499 if (mpi3mr_issue_and_process_mur(mrioc,
4500 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4501 mpi3mr_issue_reset(mrioc,
4502 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4503 MPI3MR_RESET_FROM_MUR_FAILURE);
4504 mpi3mr_issue_ioc_shutdown(mrioc);
4505 }
4506 dprint_exit(mrioc, "controller cleanup completed\n");
4507 }
4508
4509 /**
4510 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4511 * @mrioc: Adapter instance reference
4512 * @cmdptr: Internal command tracker
4513 *
4514 * Complete an internal driver commands with state indicating it
4515 * is completed due to reset.
4516 *
4517 * Return: Nothing.
4518 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)4519 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4520 struct mpi3mr_drv_cmd *cmdptr)
4521 {
4522 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4523 cmdptr->state |= MPI3MR_CMD_RESET;
4524 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4525 if (cmdptr->is_waiting) {
4526 complete(&cmdptr->done);
4527 cmdptr->is_waiting = 0;
4528 } else if (cmdptr->callback)
4529 cmdptr->callback(mrioc, cmdptr);
4530 }
4531 }
4532
4533 /**
4534 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4535 * @mrioc: Adapter instance reference
4536 *
4537 * Flush all internal driver commands post reset
4538 *
4539 * Return: Nothing.
4540 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)4541 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4542 {
4543 struct mpi3mr_drv_cmd *cmdptr;
4544 u8 i;
4545
4546 cmdptr = &mrioc->init_cmds;
4547 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4548
4549 cmdptr = &mrioc->cfg_cmds;
4550 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4551
4552 cmdptr = &mrioc->bsg_cmds;
4553 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4554 cmdptr = &mrioc->host_tm_cmds;
4555 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4556
4557 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4558 cmdptr = &mrioc->dev_rmhs_cmds[i];
4559 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4560 }
4561
4562 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4563 cmdptr = &mrioc->evtack_cmds[i];
4564 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4565 }
4566
4567 cmdptr = &mrioc->pel_cmds;
4568 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4569
4570 cmdptr = &mrioc->pel_abort_cmd;
4571 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4572
4573 cmdptr = &mrioc->transport_cmds;
4574 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4575 }
4576
4577 /**
4578 * mpi3mr_pel_wait_post - Issue PEL Wait
4579 * @mrioc: Adapter instance reference
4580 * @drv_cmd: Internal command tracker
4581 *
4582 * Issue PEL Wait MPI request through admin queue and return.
4583 *
4584 * Return: Nothing.
4585 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4586 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4587 struct mpi3mr_drv_cmd *drv_cmd)
4588 {
4589 struct mpi3_pel_req_action_wait pel_wait;
4590
4591 mrioc->pel_abort_requested = false;
4592
4593 memset(&pel_wait, 0, sizeof(pel_wait));
4594 drv_cmd->state = MPI3MR_CMD_PENDING;
4595 drv_cmd->is_waiting = 0;
4596 drv_cmd->callback = mpi3mr_pel_wait_complete;
4597 drv_cmd->ioc_status = 0;
4598 drv_cmd->ioc_loginfo = 0;
4599 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4600 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4601 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4602 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4603 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4604 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4605 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4606 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4607 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4608
4609 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4610 dprint_bsg_err(mrioc,
4611 "Issuing PELWait: Admin post failed\n");
4612 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4613 drv_cmd->callback = NULL;
4614 drv_cmd->retry_count = 0;
4615 mrioc->pel_enabled = false;
4616 }
4617 }
4618
4619 /**
4620 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4621 * @mrioc: Adapter instance reference
4622 * @drv_cmd: Internal command tracker
4623 *
4624 * Issue PEL get sequence number MPI request through admin queue
4625 * and return.
4626 *
4627 * Return: 0 on success, non-zero on failure.
4628 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4629 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4630 struct mpi3mr_drv_cmd *drv_cmd)
4631 {
4632 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4633 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4634 int retval = 0;
4635
4636 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4637 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4638 mrioc->pel_cmds.is_waiting = 0;
4639 mrioc->pel_cmds.ioc_status = 0;
4640 mrioc->pel_cmds.ioc_loginfo = 0;
4641 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4642 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4643 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4644 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4645 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4646 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4647
4648 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4649 sizeof(pel_getseq_req), 0);
4650 if (retval) {
4651 if (drv_cmd) {
4652 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4653 drv_cmd->callback = NULL;
4654 drv_cmd->retry_count = 0;
4655 }
4656 mrioc->pel_enabled = false;
4657 }
4658
4659 return retval;
4660 }
4661
4662 /**
4663 * mpi3mr_pel_wait_complete - PELWait Completion callback
4664 * @mrioc: Adapter instance reference
4665 * @drv_cmd: Internal command tracker
4666 *
4667 * This is a callback handler for the PELWait request and
4668 * firmware completes a PELWait request when it is aborted or a
4669 * new PEL entry is available. This sends AEN to the application
4670 * and if the PELwait completion is not due to PELAbort then
4671 * this will send a request for new PEL Sequence number
4672 *
4673 * Return: Nothing.
4674 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4675 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4676 struct mpi3mr_drv_cmd *drv_cmd)
4677 {
4678 struct mpi3_pel_reply *pel_reply = NULL;
4679 u16 ioc_status, pe_log_status;
4680 bool do_retry = false;
4681
4682 if (drv_cmd->state & MPI3MR_CMD_RESET)
4683 goto cleanup_drv_cmd;
4684
4685 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4686 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4687 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4688 __func__, ioc_status, drv_cmd->ioc_loginfo);
4689 dprint_bsg_err(mrioc,
4690 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4691 ioc_status, drv_cmd->ioc_loginfo);
4692 do_retry = true;
4693 }
4694
4695 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4696 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4697
4698 if (!pel_reply) {
4699 dprint_bsg_err(mrioc,
4700 "pel_wait: failed due to no reply\n");
4701 goto out_failed;
4702 }
4703
4704 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4705 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4706 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4707 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4708 __func__, pe_log_status);
4709 dprint_bsg_err(mrioc,
4710 "pel_wait: failed due to pel_log_status(0x%04x)\n",
4711 pe_log_status);
4712 do_retry = true;
4713 }
4714
4715 if (do_retry) {
4716 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4717 drv_cmd->retry_count++;
4718 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4719 drv_cmd->retry_count);
4720 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4721 return;
4722 }
4723 dprint_bsg_err(mrioc,
4724 "pel_wait: failed after all retries(%d)\n",
4725 drv_cmd->retry_count);
4726 goto out_failed;
4727 }
4728 atomic64_inc(&event_counter);
4729 if (!mrioc->pel_abort_requested) {
4730 mrioc->pel_cmds.retry_count = 0;
4731 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4732 }
4733
4734 return;
4735 out_failed:
4736 mrioc->pel_enabled = false;
4737 cleanup_drv_cmd:
4738 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4739 drv_cmd->callback = NULL;
4740 drv_cmd->retry_count = 0;
4741 }
4742
4743 /**
4744 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4745 * @mrioc: Adapter instance reference
4746 * @drv_cmd: Internal command tracker
4747 *
4748 * This is a callback handler for the PEL get sequence number
4749 * request and a new PEL wait request will be issued to the
4750 * firmware from this
4751 *
4752 * Return: Nothing.
4753 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4754 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4755 struct mpi3mr_drv_cmd *drv_cmd)
4756 {
4757 struct mpi3_pel_reply *pel_reply = NULL;
4758 struct mpi3_pel_seq *pel_seqnum_virt;
4759 u16 ioc_status;
4760 bool do_retry = false;
4761
4762 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4763
4764 if (drv_cmd->state & MPI3MR_CMD_RESET)
4765 goto cleanup_drv_cmd;
4766
4767 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4768 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4769 dprint_bsg_err(mrioc,
4770 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4771 ioc_status, drv_cmd->ioc_loginfo);
4772 do_retry = true;
4773 }
4774
4775 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4776 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4777 if (!pel_reply) {
4778 dprint_bsg_err(mrioc,
4779 "pel_get_seqnum: failed due to no reply\n");
4780 goto out_failed;
4781 }
4782
4783 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4784 dprint_bsg_err(mrioc,
4785 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4786 le16_to_cpu(pel_reply->pe_log_status));
4787 do_retry = true;
4788 }
4789
4790 if (do_retry) {
4791 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4792 drv_cmd->retry_count++;
4793 dprint_bsg_err(mrioc,
4794 "pel_get_seqnum: retrying(%d)\n",
4795 drv_cmd->retry_count);
4796 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4797 return;
4798 }
4799
4800 dprint_bsg_err(mrioc,
4801 "pel_get_seqnum: failed after all retries(%d)\n",
4802 drv_cmd->retry_count);
4803 goto out_failed;
4804 }
4805 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4806 drv_cmd->retry_count = 0;
4807 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4808
4809 return;
4810 out_failed:
4811 mrioc->pel_enabled = false;
4812 cleanup_drv_cmd:
4813 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4814 drv_cmd->callback = NULL;
4815 drv_cmd->retry_count = 0;
4816 }
4817
4818 /**
4819 * mpi3mr_soft_reset_handler - Reset the controller
4820 * @mrioc: Adapter instance reference
4821 * @reset_reason: Reset reason code
4822 * @snapdump: Flag to generate snapdump in firmware or not
4823 *
4824 * This is an handler for recovering controller by issuing soft
4825 * reset are diag fault reset. This is a blocking function and
4826 * when one reset is executed if any other resets they will be
4827 * blocked. All BSG requests will be blocked during the reset. If
4828 * controller reset is successful then the controller will be
4829 * reinitalized, otherwise the controller will be marked as not
4830 * recoverable
4831 *
4832 * In snapdump bit is set, the controller is issued with diag
4833 * fault reset so that the firmware can create a snap dump and
4834 * post that the firmware will result in F000 fault and the
4835 * driver will issue soft reset to recover from that.
4836 *
4837 * Return: 0 on success, non-zero on failure.
4838 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u32 reset_reason,u8 snapdump)4839 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4840 u32 reset_reason, u8 snapdump)
4841 {
4842 int retval = 0, i;
4843 unsigned long flags;
4844 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4845
4846 /* Block the reset handler until diag save in progress*/
4847 dprint_reset(mrioc,
4848 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4849 mrioc->diagsave_timeout);
4850 while (mrioc->diagsave_timeout)
4851 ssleep(1);
4852 /*
4853 * Block new resets until the currently executing one is finished and
4854 * return the status of the existing reset for all blocked resets
4855 */
4856 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4857 if (!mutex_trylock(&mrioc->reset_mutex)) {
4858 ioc_info(mrioc,
4859 "controller reset triggered by %s is blocked due to another reset in progress\n",
4860 mpi3mr_reset_rc_name(reset_reason));
4861 do {
4862 ssleep(1);
4863 } while (mrioc->reset_in_progress == 1);
4864 ioc_info(mrioc,
4865 "returning previous reset result(%d) for the reset triggered by %s\n",
4866 mrioc->prev_reset_result,
4867 mpi3mr_reset_rc_name(reset_reason));
4868 return mrioc->prev_reset_result;
4869 }
4870 ioc_info(mrioc, "controller reset is triggered by %s\n",
4871 mpi3mr_reset_rc_name(reset_reason));
4872
4873 mrioc->device_refresh_on = 0;
4874 mrioc->reset_in_progress = 1;
4875 mrioc->stop_bsgs = 1;
4876 mrioc->prev_reset_result = -1;
4877
4878 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4879 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4880 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4881 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4882 mrioc->event_masks[i] = -1;
4883
4884 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4885 mpi3mr_issue_event_notification(mrioc);
4886 }
4887
4888 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4889
4890 mpi3mr_ioc_disable_intr(mrioc);
4891
4892 if (snapdump) {
4893 mpi3mr_set_diagsave(mrioc);
4894 retval = mpi3mr_issue_reset(mrioc,
4895 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4896 if (!retval) {
4897 do {
4898 host_diagnostic =
4899 readl(&mrioc->sysif_regs->host_diagnostic);
4900 if (!(host_diagnostic &
4901 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4902 break;
4903 msleep(100);
4904 } while (--timeout);
4905 }
4906 }
4907
4908 retval = mpi3mr_issue_reset(mrioc,
4909 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4910 if (retval) {
4911 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4912 goto out;
4913 }
4914 if (mrioc->num_io_throttle_group !=
4915 mrioc->facts.max_io_throttle_group) {
4916 ioc_err(mrioc,
4917 "max io throttle group doesn't match old(%d), new(%d)\n",
4918 mrioc->num_io_throttle_group,
4919 mrioc->facts.max_io_throttle_group);
4920 retval = -EPERM;
4921 goto out;
4922 }
4923
4924 mpi3mr_flush_delayed_cmd_lists(mrioc);
4925 mpi3mr_flush_drv_cmds(mrioc);
4926 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4927 bitmap_clear(mrioc->removepend_bitmap, 0,
4928 mrioc->dev_handle_bitmap_bits);
4929 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4930 mpi3mr_flush_host_io(mrioc);
4931 mpi3mr_cleanup_fwevt_list(mrioc);
4932 mpi3mr_invalidate_devhandles(mrioc);
4933 mpi3mr_free_enclosure_list(mrioc);
4934
4935 if (mrioc->prepare_for_reset) {
4936 mrioc->prepare_for_reset = 0;
4937 mrioc->prepare_for_reset_timeout_counter = 0;
4938 }
4939 mpi3mr_memset_buffers(mrioc);
4940 retval = mpi3mr_reinit_ioc(mrioc, 0);
4941 if (retval) {
4942 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4943 mrioc->name, reset_reason);
4944 goto out;
4945 }
4946 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4947
4948 out:
4949 if (!retval) {
4950 mrioc->diagsave_timeout = 0;
4951 mrioc->reset_in_progress = 0;
4952 mrioc->pel_abort_requested = 0;
4953 if (mrioc->pel_enabled) {
4954 mrioc->pel_cmds.retry_count = 0;
4955 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4956 }
4957
4958 mrioc->device_refresh_on = 0;
4959
4960 mrioc->ts_update_counter = 0;
4961 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4962 if (mrioc->watchdog_work_q)
4963 queue_delayed_work(mrioc->watchdog_work_q,
4964 &mrioc->watchdog_work,
4965 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4966 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4967 mrioc->stop_bsgs = 0;
4968 if (mrioc->pel_enabled)
4969 atomic64_inc(&event_counter);
4970 } else {
4971 mpi3mr_issue_reset(mrioc,
4972 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4973 mrioc->device_refresh_on = 0;
4974 mrioc->unrecoverable = 1;
4975 mrioc->reset_in_progress = 0;
4976 retval = -1;
4977 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4978 }
4979 mrioc->prev_reset_result = retval;
4980 mutex_unlock(&mrioc->reset_mutex);
4981 ioc_info(mrioc, "controller reset is %s\n",
4982 ((retval == 0) ? "successful" : "failed"));
4983 return retval;
4984 }
4985
4986
4987 /**
4988 * mpi3mr_free_config_dma_memory - free memory for config page
4989 * @mrioc: Adapter instance reference
4990 * @mem_desc: memory descriptor structure
4991 *
4992 * Check whether the size of the buffer specified by the memory
4993 * descriptor is greater than the default page size if so then
4994 * free the memory pointed by the descriptor.
4995 *
4996 * Return: Nothing.
4997 */
mpi3mr_free_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)4998 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4999 struct dma_memory_desc *mem_desc)
5000 {
5001 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
5002 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
5003 mem_desc->addr, mem_desc->dma_addr);
5004 mem_desc->addr = NULL;
5005 }
5006 }
5007
5008 /**
5009 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5010 * @mrioc: Adapter instance reference
5011 * @mem_desc: Memory descriptor to hold dma memory info
5012 *
5013 * This function allocates new dmaable memory or provides the
5014 * default config page dmaable memory based on the memory size
5015 * described by the descriptor.
5016 *
5017 * Return: 0 on success, non-zero on failure.
5018 */
mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5019 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5020 struct dma_memory_desc *mem_desc)
5021 {
5022 if (mem_desc->size > mrioc->cfg_page_sz) {
5023 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5024 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5025 if (!mem_desc->addr)
5026 return -ENOMEM;
5027 } else {
5028 mem_desc->addr = mrioc->cfg_page;
5029 mem_desc->dma_addr = mrioc->cfg_page_dma;
5030 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5031 }
5032 return 0;
5033 }
5034
5035 /**
5036 * mpi3mr_post_cfg_req - Issue config requests and wait
5037 * @mrioc: Adapter instance reference
5038 * @cfg_req: Configuration request
5039 * @timeout: Timeout in seconds
5040 * @ioc_status: Pointer to return ioc status
5041 *
5042 * A generic function for posting MPI3 configuration request to
5043 * the firmware. This blocks for the completion of request for
5044 * timeout seconds and if the request times out this function
5045 * faults the controller with proper reason code.
5046 *
5047 * On successful completion of the request this function returns
5048 * appropriate ioc status from the firmware back to the caller.
5049 *
5050 * Return: 0 on success, non-zero on failure.
5051 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5052 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5053 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5054 {
5055 int retval = 0;
5056
5057 mutex_lock(&mrioc->cfg_cmds.mutex);
5058 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5059 retval = -1;
5060 ioc_err(mrioc, "sending config request failed due to command in use\n");
5061 mutex_unlock(&mrioc->cfg_cmds.mutex);
5062 goto out;
5063 }
5064 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5065 mrioc->cfg_cmds.is_waiting = 1;
5066 mrioc->cfg_cmds.callback = NULL;
5067 mrioc->cfg_cmds.ioc_status = 0;
5068 mrioc->cfg_cmds.ioc_loginfo = 0;
5069
5070 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5071 cfg_req->function = MPI3_FUNCTION_CONFIG;
5072
5073 init_completion(&mrioc->cfg_cmds.done);
5074 dprint_cfg_info(mrioc, "posting config request\n");
5075 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5076 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5077 "mpi3_cfg_req");
5078 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5079 if (retval) {
5080 ioc_err(mrioc, "posting config request failed\n");
5081 goto out_unlock;
5082 }
5083 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5084 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5085 mpi3mr_check_rh_fault_ioc(mrioc,
5086 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5087 ioc_err(mrioc, "config request timed out\n");
5088 retval = -1;
5089 goto out_unlock;
5090 }
5091 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5092 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5093 dprint_cfg_err(mrioc,
5094 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5095 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5096
5097 out_unlock:
5098 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5099 mutex_unlock(&mrioc->cfg_cmds.mutex);
5100
5101 out:
5102 return retval;
5103 }
5104
5105 /**
5106 * mpi3mr_process_cfg_req - config page request processor
5107 * @mrioc: Adapter instance reference
5108 * @cfg_req: Configuration request
5109 * @cfg_hdr: Configuration page header
5110 * @timeout: Timeout in seconds
5111 * @ioc_status: Pointer to return ioc status
5112 * @cfg_buf: Memory pointer to copy config page or header
5113 * @cfg_buf_sz: Size of the memory to get config page or header
5114 *
5115 * This is handler for config page read, write and config page
5116 * header read operations.
5117 *
5118 * This function expects the cfg_req to be populated with page
5119 * type, page number, action for the header read and with page
5120 * address for all other operations.
5121 *
5122 * The cfg_hdr can be passed as null for reading required header
5123 * details for read/write pages the cfg_hdr should point valid
5124 * configuration page header.
5125 *
5126 * This allocates dmaable memory based on the size of the config
5127 * buffer and set the SGE of the cfg_req.
5128 *
5129 * For write actions, the config page data has to be passed in
5130 * the cfg_buf and size of the data has to be mentioned in the
5131 * cfg_buf_sz.
5132 *
5133 * For read/header actions, on successful completion of the
5134 * request with successful ioc_status the data will be copied
5135 * into the cfg_buf limited to a minimum of actual page size and
5136 * cfg_buf_sz
5137 *
5138 *
5139 * Return: 0 on success, non-zero on failure.
5140 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5141 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5142 struct mpi3_config_request *cfg_req,
5143 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5144 void *cfg_buf, u32 cfg_buf_sz)
5145 {
5146 struct dma_memory_desc mem_desc;
5147 int retval = -1;
5148 u8 invalid_action = 0;
5149 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5150
5151 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5152
5153 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5154 mem_desc.size = sizeof(struct mpi3_config_page_header);
5155 else {
5156 if (!cfg_hdr) {
5157 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5158 cfg_req->action, cfg_req->page_type,
5159 cfg_req->page_number);
5160 goto out;
5161 }
5162 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5163 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5164 if (cfg_req->action
5165 != MPI3_CONFIG_ACTION_READ_CURRENT)
5166 invalid_action = 1;
5167 break;
5168 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5169 if ((cfg_req->action ==
5170 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5171 (cfg_req->action ==
5172 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5173 invalid_action = 1;
5174 break;
5175 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5176 default:
5177 break;
5178 }
5179 if (invalid_action) {
5180 ioc_err(mrioc,
5181 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5182 cfg_req->action, cfg_req->page_type,
5183 cfg_req->page_number, cfg_hdr->page_attribute);
5184 goto out;
5185 }
5186 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5187 cfg_req->page_length = cfg_hdr->page_length;
5188 cfg_req->page_version = cfg_hdr->page_version;
5189 }
5190 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5191 goto out;
5192
5193 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5194 mem_desc.dma_addr);
5195
5196 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5197 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5198 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5199 cfg_buf_sz));
5200 dprint_cfg_info(mrioc, "config buffer to be written\n");
5201 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5202 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5203 }
5204
5205 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5206 goto out;
5207
5208 retval = 0;
5209 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5210 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5211 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5212 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5213 cfg_buf_sz));
5214 dprint_cfg_info(mrioc, "config buffer read\n");
5215 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5216 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5217 }
5218
5219 out:
5220 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5221 return retval;
5222 }
5223
5224 /**
5225 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5226 * @mrioc: Adapter instance reference
5227 * @ioc_status: Pointer to return ioc status
5228 * @dev_pg0: Pointer to return device page 0
5229 * @pg_sz: Size of the memory allocated to the page pointer
5230 * @form: The form to be used for addressing the page
5231 * @form_spec: Form specific information like device handle
5232 *
5233 * This is handler for config page read for a specific device
5234 * page0. The ioc_status has the controller returned ioc_status.
5235 * This routine doesn't check ioc_status to decide whether the
5236 * page read is success or not and it is the callers
5237 * responsibility.
5238 *
5239 * Return: 0 on success, non-zero on failure.
5240 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5241 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5242 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5243 {
5244 struct mpi3_config_page_header cfg_hdr;
5245 struct mpi3_config_request cfg_req;
5246 u32 page_address;
5247
5248 memset(dev_pg0, 0, pg_sz);
5249 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5250 memset(&cfg_req, 0, sizeof(cfg_req));
5251
5252 cfg_req.function = MPI3_FUNCTION_CONFIG;
5253 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5254 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5255 cfg_req.page_number = 0;
5256 cfg_req.page_address = 0;
5257
5258 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5259 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5260 ioc_err(mrioc, "device page0 header read failed\n");
5261 goto out_failed;
5262 }
5263 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5264 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5265 *ioc_status);
5266 goto out_failed;
5267 }
5268 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5269 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5270 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5271 cfg_req.page_address = cpu_to_le32(page_address);
5272 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5273 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5274 ioc_err(mrioc, "device page0 read failed\n");
5275 goto out_failed;
5276 }
5277 return 0;
5278 out_failed:
5279 return -1;
5280 }
5281
5282
5283 /**
5284 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5285 * @mrioc: Adapter instance reference
5286 * @ioc_status: Pointer to return ioc status
5287 * @phy_pg0: Pointer to return SAS Phy page 0
5288 * @pg_sz: Size of the memory allocated to the page pointer
5289 * @form: The form to be used for addressing the page
5290 * @form_spec: Form specific information like phy number
5291 *
5292 * This is handler for config page read for a specific SAS Phy
5293 * page0. The ioc_status has the controller returned ioc_status.
5294 * This routine doesn't check ioc_status to decide whether the
5295 * page read is success or not and it is the callers
5296 * responsibility.
5297 *
5298 * Return: 0 on success, non-zero on failure.
5299 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)5300 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5301 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5302 u32 form_spec)
5303 {
5304 struct mpi3_config_page_header cfg_hdr;
5305 struct mpi3_config_request cfg_req;
5306 u32 page_address;
5307
5308 memset(phy_pg0, 0, pg_sz);
5309 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5310 memset(&cfg_req, 0, sizeof(cfg_req));
5311
5312 cfg_req.function = MPI3_FUNCTION_CONFIG;
5313 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5314 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5315 cfg_req.page_number = 0;
5316 cfg_req.page_address = 0;
5317
5318 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5319 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5320 ioc_err(mrioc, "sas phy page0 header read failed\n");
5321 goto out_failed;
5322 }
5323 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5324 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5325 *ioc_status);
5326 goto out_failed;
5327 }
5328 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5329 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5330 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5331 cfg_req.page_address = cpu_to_le32(page_address);
5332 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5333 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5334 ioc_err(mrioc, "sas phy page0 read failed\n");
5335 goto out_failed;
5336 }
5337 return 0;
5338 out_failed:
5339 return -1;
5340 }
5341
5342 /**
5343 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5344 * @mrioc: Adapter instance reference
5345 * @ioc_status: Pointer to return ioc status
5346 * @phy_pg1: Pointer to return SAS Phy page 1
5347 * @pg_sz: Size of the memory allocated to the page pointer
5348 * @form: The form to be used for addressing the page
5349 * @form_spec: Form specific information like phy number
5350 *
5351 * This is handler for config page read for a specific SAS Phy
5352 * page1. The ioc_status has the controller returned ioc_status.
5353 * This routine doesn't check ioc_status to decide whether the
5354 * page read is success or not and it is the callers
5355 * responsibility.
5356 *
5357 * Return: 0 on success, non-zero on failure.
5358 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)5359 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5360 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5361 u32 form_spec)
5362 {
5363 struct mpi3_config_page_header cfg_hdr;
5364 struct mpi3_config_request cfg_req;
5365 u32 page_address;
5366
5367 memset(phy_pg1, 0, pg_sz);
5368 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5369 memset(&cfg_req, 0, sizeof(cfg_req));
5370
5371 cfg_req.function = MPI3_FUNCTION_CONFIG;
5372 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5373 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5374 cfg_req.page_number = 1;
5375 cfg_req.page_address = 0;
5376
5377 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5378 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5379 ioc_err(mrioc, "sas phy page1 header read failed\n");
5380 goto out_failed;
5381 }
5382 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5383 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5384 *ioc_status);
5385 goto out_failed;
5386 }
5387 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5388 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5389 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5390 cfg_req.page_address = cpu_to_le32(page_address);
5391 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5392 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5393 ioc_err(mrioc, "sas phy page1 read failed\n");
5394 goto out_failed;
5395 }
5396 return 0;
5397 out_failed:
5398 return -1;
5399 }
5400
5401
5402 /**
5403 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5404 * @mrioc: Adapter instance reference
5405 * @ioc_status: Pointer to return ioc status
5406 * @exp_pg0: Pointer to return SAS Expander page 0
5407 * @pg_sz: Size of the memory allocated to the page pointer
5408 * @form: The form to be used for addressing the page
5409 * @form_spec: Form specific information like device handle
5410 *
5411 * This is handler for config page read for a specific SAS
5412 * Expander page0. The ioc_status has the controller returned
5413 * ioc_status. This routine doesn't check ioc_status to decide
5414 * whether the page read is success or not and it is the callers
5415 * responsibility.
5416 *
5417 * Return: 0 on success, non-zero on failure.
5418 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)5419 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5420 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5421 u32 form_spec)
5422 {
5423 struct mpi3_config_page_header cfg_hdr;
5424 struct mpi3_config_request cfg_req;
5425 u32 page_address;
5426
5427 memset(exp_pg0, 0, pg_sz);
5428 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5429 memset(&cfg_req, 0, sizeof(cfg_req));
5430
5431 cfg_req.function = MPI3_FUNCTION_CONFIG;
5432 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5433 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5434 cfg_req.page_number = 0;
5435 cfg_req.page_address = 0;
5436
5437 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5438 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5439 ioc_err(mrioc, "expander page0 header read failed\n");
5440 goto out_failed;
5441 }
5442 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5443 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5444 *ioc_status);
5445 goto out_failed;
5446 }
5447 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5448 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5449 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5450 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5451 cfg_req.page_address = cpu_to_le32(page_address);
5452 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5453 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5454 ioc_err(mrioc, "expander page0 read failed\n");
5455 goto out_failed;
5456 }
5457 return 0;
5458 out_failed:
5459 return -1;
5460 }
5461
5462 /**
5463 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5464 * @mrioc: Adapter instance reference
5465 * @ioc_status: Pointer to return ioc status
5466 * @exp_pg1: Pointer to return SAS Expander page 1
5467 * @pg_sz: Size of the memory allocated to the page pointer
5468 * @form: The form to be used for addressing the page
5469 * @form_spec: Form specific information like phy number
5470 *
5471 * This is handler for config page read for a specific SAS
5472 * Expander page1. The ioc_status has the controller returned
5473 * ioc_status. This routine doesn't check ioc_status to decide
5474 * whether the page read is success or not and it is the callers
5475 * responsibility.
5476 *
5477 * Return: 0 on success, non-zero on failure.
5478 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)5479 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5480 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5481 u32 form_spec)
5482 {
5483 struct mpi3_config_page_header cfg_hdr;
5484 struct mpi3_config_request cfg_req;
5485 u32 page_address;
5486
5487 memset(exp_pg1, 0, pg_sz);
5488 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5489 memset(&cfg_req, 0, sizeof(cfg_req));
5490
5491 cfg_req.function = MPI3_FUNCTION_CONFIG;
5492 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5493 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5494 cfg_req.page_number = 1;
5495 cfg_req.page_address = 0;
5496
5497 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5498 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5499 ioc_err(mrioc, "expander page1 header read failed\n");
5500 goto out_failed;
5501 }
5502 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5503 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5504 *ioc_status);
5505 goto out_failed;
5506 }
5507 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5508 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5509 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5510 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5511 cfg_req.page_address = cpu_to_le32(page_address);
5512 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5513 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5514 ioc_err(mrioc, "expander page1 read failed\n");
5515 goto out_failed;
5516 }
5517 return 0;
5518 out_failed:
5519 return -1;
5520 }
5521
5522 /**
5523 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5524 * @mrioc: Adapter instance reference
5525 * @ioc_status: Pointer to return ioc status
5526 * @encl_pg0: Pointer to return Enclosure page 0
5527 * @pg_sz: Size of the memory allocated to the page pointer
5528 * @form: The form to be used for addressing the page
5529 * @form_spec: Form specific information like device handle
5530 *
5531 * This is handler for config page read for a specific Enclosure
5532 * page0. The ioc_status has the controller returned ioc_status.
5533 * This routine doesn't check ioc_status to decide whether the
5534 * page read is success or not and it is the callers
5535 * responsibility.
5536 *
5537 * Return: 0 on success, non-zero on failure.
5538 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)5539 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5540 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5541 u32 form_spec)
5542 {
5543 struct mpi3_config_page_header cfg_hdr;
5544 struct mpi3_config_request cfg_req;
5545 u32 page_address;
5546
5547 memset(encl_pg0, 0, pg_sz);
5548 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5549 memset(&cfg_req, 0, sizeof(cfg_req));
5550
5551 cfg_req.function = MPI3_FUNCTION_CONFIG;
5552 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5553 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5554 cfg_req.page_number = 0;
5555 cfg_req.page_address = 0;
5556
5557 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5558 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5559 ioc_err(mrioc, "enclosure page0 header read failed\n");
5560 goto out_failed;
5561 }
5562 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5563 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5564 *ioc_status);
5565 goto out_failed;
5566 }
5567 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5568 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5569 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5570 cfg_req.page_address = cpu_to_le32(page_address);
5571 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5572 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5573 ioc_err(mrioc, "enclosure page0 read failed\n");
5574 goto out_failed;
5575 }
5576 return 0;
5577 out_failed:
5578 return -1;
5579 }
5580
5581
5582 /**
5583 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5584 * @mrioc: Adapter instance reference
5585 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5586 * @pg_sz: Size of the memory allocated to the page pointer
5587 *
5588 * This is handler for config page read for the SAS IO Unit
5589 * page0. This routine checks ioc_status to decide whether the
5590 * page read is success or not.
5591 *
5592 * Return: 0 on success, non-zero on failure.
5593 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)5594 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5595 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5596 {
5597 struct mpi3_config_page_header cfg_hdr;
5598 struct mpi3_config_request cfg_req;
5599 u16 ioc_status = 0;
5600
5601 memset(sas_io_unit_pg0, 0, pg_sz);
5602 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5603 memset(&cfg_req, 0, sizeof(cfg_req));
5604
5605 cfg_req.function = MPI3_FUNCTION_CONFIG;
5606 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5607 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5608 cfg_req.page_number = 0;
5609 cfg_req.page_address = 0;
5610
5611 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5612 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5613 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5614 goto out_failed;
5615 }
5616 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5617 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5618 ioc_status);
5619 goto out_failed;
5620 }
5621 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5622
5623 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5624 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5625 ioc_err(mrioc, "sas io unit page0 read failed\n");
5626 goto out_failed;
5627 }
5628 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5629 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5630 ioc_status);
5631 goto out_failed;
5632 }
5633 return 0;
5634 out_failed:
5635 return -1;
5636 }
5637
5638 /**
5639 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5640 * @mrioc: Adapter instance reference
5641 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5642 * @pg_sz: Size of the memory allocated to the page pointer
5643 *
5644 * This is handler for config page read for the SAS IO Unit
5645 * page1. This routine checks ioc_status to decide whether the
5646 * page read is success or not.
5647 *
5648 * Return: 0 on success, non-zero on failure.
5649 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5650 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5651 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5652 {
5653 struct mpi3_config_page_header cfg_hdr;
5654 struct mpi3_config_request cfg_req;
5655 u16 ioc_status = 0;
5656
5657 memset(sas_io_unit_pg1, 0, pg_sz);
5658 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5659 memset(&cfg_req, 0, sizeof(cfg_req));
5660
5661 cfg_req.function = MPI3_FUNCTION_CONFIG;
5662 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5663 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5664 cfg_req.page_number = 1;
5665 cfg_req.page_address = 0;
5666
5667 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5668 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5669 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5670 goto out_failed;
5671 }
5672 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5673 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5674 ioc_status);
5675 goto out_failed;
5676 }
5677 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5678
5679 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5680 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5681 ioc_err(mrioc, "sas io unit page1 read failed\n");
5682 goto out_failed;
5683 }
5684 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5685 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5686 ioc_status);
5687 goto out_failed;
5688 }
5689 return 0;
5690 out_failed:
5691 return -1;
5692 }
5693
5694 /**
5695 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5696 * @mrioc: Adapter instance reference
5697 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5698 * @pg_sz: Size of the memory allocated to the page pointer
5699 *
5700 * This is handler for config page write for the SAS IO Unit
5701 * page1. This routine checks ioc_status to decide whether the
5702 * page read is success or not. This will modify both current
5703 * and persistent page.
5704 *
5705 * Return: 0 on success, non-zero on failure.
5706 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5707 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5708 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5709 {
5710 struct mpi3_config_page_header cfg_hdr;
5711 struct mpi3_config_request cfg_req;
5712 u16 ioc_status = 0;
5713
5714 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5715 memset(&cfg_req, 0, sizeof(cfg_req));
5716
5717 cfg_req.function = MPI3_FUNCTION_CONFIG;
5718 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5719 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5720 cfg_req.page_number = 1;
5721 cfg_req.page_address = 0;
5722
5723 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5724 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5725 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5726 goto out_failed;
5727 }
5728 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5729 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5730 ioc_status);
5731 goto out_failed;
5732 }
5733 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5734
5735 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5736 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5737 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5738 goto out_failed;
5739 }
5740 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5741 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5742 ioc_status);
5743 goto out_failed;
5744 }
5745
5746 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5747
5748 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5749 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5750 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5751 goto out_failed;
5752 }
5753 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5754 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5755 ioc_status);
5756 goto out_failed;
5757 }
5758 return 0;
5759 out_failed:
5760 return -1;
5761 }
5762
5763 /**
5764 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5765 * @mrioc: Adapter instance reference
5766 * @driver_pg1: Pointer to return Driver page 1
5767 * @pg_sz: Size of the memory allocated to the page pointer
5768 *
5769 * This is handler for config page read for the Driver page1.
5770 * This routine checks ioc_status to decide whether the page
5771 * read is success or not.
5772 *
5773 * Return: 0 on success, non-zero on failure.
5774 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)5775 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5776 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5777 {
5778 struct mpi3_config_page_header cfg_hdr;
5779 struct mpi3_config_request cfg_req;
5780 u16 ioc_status = 0;
5781
5782 memset(driver_pg1, 0, pg_sz);
5783 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5784 memset(&cfg_req, 0, sizeof(cfg_req));
5785
5786 cfg_req.function = MPI3_FUNCTION_CONFIG;
5787 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5788 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5789 cfg_req.page_number = 1;
5790 cfg_req.page_address = 0;
5791
5792 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5793 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5794 ioc_err(mrioc, "driver page1 header read failed\n");
5795 goto out_failed;
5796 }
5797 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5798 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5799 ioc_status);
5800 goto out_failed;
5801 }
5802 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5803
5804 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5805 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5806 ioc_err(mrioc, "driver page1 read failed\n");
5807 goto out_failed;
5808 }
5809 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5810 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5811 ioc_status);
5812 goto out_failed;
5813 }
5814 return 0;
5815 out_failed:
5816 return -1;
5817 }
5818