1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/timekeeping.h>
6 #include "mt7915.h"
7 #include "../dma.h"
8 #include "mac.h"
9 #include "mcu.h"
10
11 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
12
13 static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
14 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
15 .radar_pattern = {
16 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
17 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
18 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
19 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
20 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
21 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
22 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
23 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
24 },
25 };
26
27 static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
28 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
29 .radar_pattern = {
30 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
31 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
32 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
33 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
34 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
35 },
36 };
37
38 static const struct mt7915_dfs_radar_spec jp_radar_specs = {
39 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
40 .radar_pattern = {
41 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
42 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
43 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
44 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
45 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
46 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
47 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
48 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
49 },
50 };
51
mt7915_rx_get_wcid(struct mt7915_dev * dev,u16 idx,bool unicast)52 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
53 u16 idx, bool unicast)
54 {
55 struct mt7915_sta *sta;
56 struct mt76_wcid *wcid;
57
58 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
59 return NULL;
60
61 wcid = rcu_dereference(dev->mt76.wcid[idx]);
62 if (unicast || !wcid)
63 return wcid;
64
65 if (!wcid->sta)
66 return NULL;
67
68 sta = container_of(wcid, struct mt7915_sta, wcid);
69 if (!sta->vif)
70 return NULL;
71
72 return &sta->vif->sta.wcid;
73 }
74
mt7915_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)75 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
76 {
77 }
78
mt7915_mac_wtbl_update(struct mt7915_dev * dev,int idx,u32 mask)79 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
80 {
81 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
82 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
83
84 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
85 0, 5000);
86 }
87
mt7915_mac_wtbl_lmac_addr(struct mt7915_dev * dev,u16 wcid,u8 dw)88 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw)
89 {
90 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
91 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
92
93 return MT_WTBL_LMAC_OFFS(wcid, dw);
94 }
95
mt7915_mac_sta_poll(struct mt7915_dev * dev)96 static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
97 {
98 static const u8 ac_to_tid[] = {
99 [IEEE80211_AC_BE] = 0,
100 [IEEE80211_AC_BK] = 1,
101 [IEEE80211_AC_VI] = 4,
102 [IEEE80211_AC_VO] = 6
103 };
104 struct ieee80211_sta *sta;
105 struct mt7915_sta *msta;
106 struct rate_info *rate;
107 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
108 LIST_HEAD(sta_poll_list);
109 int i;
110
111 spin_lock_bh(&dev->sta_poll_lock);
112 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
113 spin_unlock_bh(&dev->sta_poll_lock);
114
115 rcu_read_lock();
116
117 while (true) {
118 bool clear = false;
119 u32 addr, val;
120 u16 idx;
121 u8 bw;
122
123 spin_lock_bh(&dev->sta_poll_lock);
124 if (list_empty(&sta_poll_list)) {
125 spin_unlock_bh(&dev->sta_poll_lock);
126 break;
127 }
128 msta = list_first_entry(&sta_poll_list,
129 struct mt7915_sta, poll_list);
130 list_del_init(&msta->poll_list);
131 spin_unlock_bh(&dev->sta_poll_lock);
132
133 idx = msta->wcid.idx;
134 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20);
135
136 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
137 u32 tx_last = msta->airtime_ac[i];
138 u32 rx_last = msta->airtime_ac[i + 4];
139
140 msta->airtime_ac[i] = mt76_rr(dev, addr);
141 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
142
143 tx_time[i] = msta->airtime_ac[i] - tx_last;
144 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
145
146 if ((tx_last | rx_last) & BIT(30))
147 clear = true;
148
149 addr += 8;
150 }
151
152 if (clear) {
153 mt7915_mac_wtbl_update(dev, idx,
154 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
155 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
156 }
157
158 if (!msta->wcid.sta)
159 continue;
160
161 sta = container_of((void *)msta, struct ieee80211_sta,
162 drv_priv);
163 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
164 u8 q = mt76_connac_lmac_mapping(i);
165 u32 tx_cur = tx_time[q];
166 u32 rx_cur = rx_time[q];
167 u8 tid = ac_to_tid[i];
168
169 if (!tx_cur && !rx_cur)
170 continue;
171
172 ieee80211_sta_register_airtime(sta, tid, tx_cur,
173 rx_cur);
174 }
175
176 /*
177 * We don't support reading GI info from txs packets.
178 * For accurate tx status reporting and AQL improvement,
179 * we need to make sure that flags match so polling GI
180 * from per-sta counters directly.
181 */
182 rate = &msta->wcid.rate;
183 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7);
184 val = mt76_rr(dev, addr);
185
186 switch (rate->bw) {
187 case RATE_INFO_BW_160:
188 bw = IEEE80211_STA_RX_BW_160;
189 break;
190 case RATE_INFO_BW_80:
191 bw = IEEE80211_STA_RX_BW_80;
192 break;
193 case RATE_INFO_BW_40:
194 bw = IEEE80211_STA_RX_BW_40;
195 break;
196 default:
197 bw = IEEE80211_STA_RX_BW_20;
198 break;
199 }
200
201 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) {
202 u8 offs = 24 + 2 * bw;
203
204 rate->he_gi = (val & (0x3 << offs)) >> offs;
205 } else if (rate->flags &
206 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) {
207 if (val & BIT(12 + bw))
208 rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
209 else
210 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI;
211 }
212 }
213
214 rcu_read_unlock();
215 }
216
217 static int
mt7915_mac_fill_rx(struct mt7915_dev * dev,struct sk_buff * skb)218 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
219 {
220 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
221 struct mt76_phy *mphy = &dev->mt76.phy;
222 struct mt7915_phy *phy = &dev->phy;
223 struct ieee80211_supported_band *sband;
224 __le32 *rxd = (__le32 *)skb->data;
225 __le32 *rxv = NULL;
226 u32 rxd0 = le32_to_cpu(rxd[0]);
227 u32 rxd1 = le32_to_cpu(rxd[1]);
228 u32 rxd2 = le32_to_cpu(rxd[2]);
229 u32 rxd3 = le32_to_cpu(rxd[3]);
230 u32 rxd4 = le32_to_cpu(rxd[4]);
231 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
232 bool unicast, insert_ccmp_hdr = false;
233 u8 remove_pad, amsdu_info;
234 u8 mode = 0, qos_ctl = 0;
235 struct mt7915_sta *msta = NULL;
236 u32 csum_status = *(u32 *)skb->cb;
237 bool hdr_trans;
238 u16 hdr_gap;
239 u16 seq_ctrl = 0;
240 __le16 fc = 0;
241 int idx;
242
243 memset(status, 0, sizeof(*status));
244
245 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) {
246 mphy = dev->mt76.phys[MT_BAND1];
247 if (!mphy)
248 return -EINVAL;
249
250 phy = mphy->priv;
251 status->phy_idx = 1;
252 }
253
254 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
255 return -EINVAL;
256
257 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
258 return -EINVAL;
259
260 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS;
261 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM))
262 return -EINVAL;
263
264 /* ICV error or CCMP/BIP/WPI MIC error */
265 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR)
266 status->flag |= RX_FLAG_ONLY_MONITOR;
267
268 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
269 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
270 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
271
272 if (status->wcid) {
273 msta = container_of(status->wcid, struct mt7915_sta, wcid);
274 spin_lock_bh(&dev->sta_poll_lock);
275 if (list_empty(&msta->poll_list))
276 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
277 spin_unlock_bh(&dev->sta_poll_lock);
278 }
279
280 status->freq = mphy->chandef.chan->center_freq;
281 status->band = mphy->chandef.chan->band;
282 if (status->band == NL80211_BAND_5GHZ)
283 sband = &mphy->sband_5g.sband;
284 else if (status->band == NL80211_BAND_6GHZ)
285 sband = &mphy->sband_6g.sband;
286 else
287 sband = &mphy->sband_2g.sband;
288
289 if (!sband->channels)
290 return -EINVAL;
291
292 if ((rxd0 & csum_mask) == csum_mask &&
293 !(csum_status & (BIT(0) | BIT(2) | BIT(3))))
294 skb->ip_summed = CHECKSUM_UNNECESSARY;
295
296 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
297 status->flag |= RX_FLAG_FAILED_FCS_CRC;
298
299 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
300 status->flag |= RX_FLAG_MMIC_ERROR;
301
302 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
303 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
304 status->flag |= RX_FLAG_DECRYPTED;
305 status->flag |= RX_FLAG_IV_STRIPPED;
306 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
307 }
308
309 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
310
311 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
312 return -EINVAL;
313
314 rxd += 6;
315 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
316 u32 v0 = le32_to_cpu(rxd[0]);
317 u32 v2 = le32_to_cpu(rxd[2]);
318
319 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
320 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2);
321 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
322
323 rxd += 4;
324 if ((u8 *)rxd - skb->data >= skb->len)
325 return -EINVAL;
326 }
327
328 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
329 u8 *data = (u8 *)rxd;
330
331 if (status->flag & RX_FLAG_DECRYPTED) {
332 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) {
333 case MT_CIPHER_AES_CCMP:
334 case MT_CIPHER_CCMP_CCX:
335 case MT_CIPHER_CCMP_256:
336 insert_ccmp_hdr =
337 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
338 fallthrough;
339 case MT_CIPHER_TKIP:
340 case MT_CIPHER_TKIP_NO_MIC:
341 case MT_CIPHER_GCMP:
342 case MT_CIPHER_GCMP_256:
343 status->iv[0] = data[5];
344 status->iv[1] = data[4];
345 status->iv[2] = data[3];
346 status->iv[3] = data[2];
347 status->iv[4] = data[1];
348 status->iv[5] = data[0];
349 break;
350 default:
351 break;
352 }
353 }
354 rxd += 4;
355 if ((u8 *)rxd - skb->data >= skb->len)
356 return -EINVAL;
357 }
358
359 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
360 status->timestamp = le32_to_cpu(rxd[0]);
361 status->flag |= RX_FLAG_MACTIME_START;
362
363 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
364 status->flag |= RX_FLAG_AMPDU_DETAILS;
365
366 /* all subframes of an A-MPDU have the same timestamp */
367 if (phy->rx_ampdu_ts != status->timestamp) {
368 if (!++phy->ampdu_ref)
369 phy->ampdu_ref++;
370 }
371 phy->rx_ampdu_ts = status->timestamp;
372
373 status->ampdu_ref = phy->ampdu_ref;
374 }
375
376 rxd += 2;
377 if ((u8 *)rxd - skb->data >= skb->len)
378 return -EINVAL;
379 }
380
381 /* RXD Group 3 - P-RXV */
382 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
383 u32 v0, v1;
384 int ret;
385
386 rxv = rxd;
387 rxd += 2;
388 if ((u8 *)rxd - skb->data >= skb->len)
389 return -EINVAL;
390
391 v0 = le32_to_cpu(rxv[0]);
392 v1 = le32_to_cpu(rxv[1]);
393
394 if (v0 & MT_PRXV_HT_AD_CODE)
395 status->enc_flags |= RX_ENC_FLAG_LDPC;
396
397 status->chains = mphy->antenna_mask;
398 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
399 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
400 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
401 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
402
403 /* RXD Group 5 - C-RXV */
404 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
405 rxd += 18;
406 if ((u8 *)rxd - skb->data >= skb->len)
407 return -EINVAL;
408 }
409
410 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) {
411 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status,
412 sband, rxv, &mode);
413 if (ret < 0)
414 return ret;
415 }
416 }
417
418 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4);
419 status->amsdu = !!amsdu_info;
420 if (status->amsdu) {
421 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
422 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
423 }
424
425 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
426 if (hdr_trans && ieee80211_has_morefrags(fc)) {
427 struct ieee80211_vif *vif;
428 int err;
429
430 if (!msta || !msta->vif)
431 return -EINVAL;
432
433 vif = container_of((void *)msta->vif, struct ieee80211_vif,
434 drv_priv);
435 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap);
436 if (err)
437 return err;
438
439 hdr_trans = false;
440 } else {
441 int pad_start = 0;
442
443 skb_pull(skb, hdr_gap);
444 if (!hdr_trans && status->amsdu) {
445 pad_start = ieee80211_get_hdrlen_from_skb(skb);
446 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
447 /*
448 * When header translation failure is indicated,
449 * the hardware will insert an extra 2-byte field
450 * containing the data length after the protocol
451 * type field. This happens either when the LLC-SNAP
452 * pattern did not match, or if a VLAN header was
453 * detected.
454 */
455 pad_start = 12;
456 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
457 pad_start += 4;
458 else
459 pad_start = 0;
460 }
461
462 if (pad_start) {
463 memmove(skb->data + 2, skb->data, pad_start);
464 skb_pull(skb, 2);
465 }
466 }
467
468 if (!hdr_trans) {
469 struct ieee80211_hdr *hdr;
470
471 if (insert_ccmp_hdr) {
472 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
473
474 mt76_insert_ccmp_hdr(skb, key_id);
475 }
476
477 hdr = mt76_skb_get_hdr(skb);
478 fc = hdr->frame_control;
479 if (ieee80211_is_data_qos(fc)) {
480 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
481 qos_ctl = *ieee80211_get_qos_ctl(hdr);
482 }
483 } else {
484 status->flag |= RX_FLAG_8023;
485 }
486
487 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
488 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode);
489
490 if (!status->wcid || !ieee80211_is_data_qos(fc))
491 return 0;
492
493 status->aggr = unicast &&
494 !ieee80211_is_qos_nullfunc(fc);
495 status->qos_ctl = qos_ctl;
496 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
497
498 return 0;
499 }
500
501 static void
mt7915_mac_fill_rx_vector(struct mt7915_dev * dev,struct sk_buff * skb)502 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb)
503 {
504 #ifdef CONFIG_NL80211_TESTMODE
505 struct mt7915_phy *phy = &dev->phy;
506 __le32 *rxd = (__le32 *)skb->data;
507 __le32 *rxv_hdr = rxd + 2;
508 __le32 *rxv = rxd + 4;
509 u32 rcpi, ib_rssi, wb_rssi, v20, v21;
510 u8 band_idx;
511 s32 foe;
512 u8 snr;
513 int i;
514
515 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX);
516 if (band_idx && !phy->band_idx) {
517 phy = mt7915_ext_phy(dev);
518 if (!phy)
519 goto out;
520 }
521
522 rcpi = le32_to_cpu(rxv[6]);
523 ib_rssi = le32_to_cpu(rxv[7]);
524 wb_rssi = le32_to_cpu(rxv[8]) >> 5;
525
526 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) {
527 if (i == 3)
528 wb_rssi = le32_to_cpu(rxv[9]);
529
530 phy->test.last_rcpi[i] = rcpi & 0xff;
531 phy->test.last_ib_rssi[i] = ib_rssi & 0xff;
532 phy->test.last_wb_rssi[i] = wb_rssi & 0xff;
533 }
534
535 v20 = le32_to_cpu(rxv[20]);
536 v21 = le32_to_cpu(rxv[21]);
537
538 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |
539 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT);
540
541 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;
542
543 phy->test.last_freq_offset = foe;
544 phy->test.last_snr = snr;
545 out:
546 #endif
547 dev_kfree_skb(skb);
548 }
549
550 static void
mt7915_mac_write_txwi_tm(struct mt7915_phy * phy,__le32 * txwi,struct sk_buff * skb)551 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
552 struct sk_buff *skb)
553 {
554 #ifdef CONFIG_NL80211_TESTMODE
555 struct mt76_testmode_data *td = &phy->mt76->test;
556 const struct ieee80211_rate *r;
557 u8 bw, mode, nss = td->tx_rate_nss;
558 u8 rate_idx = td->tx_rate_idx;
559 u16 rateval = 0;
560 u32 val;
561 bool cck = false;
562 int band;
563
564 if (skb != phy->mt76->test.tx_skb)
565 return;
566
567 switch (td->tx_rate_mode) {
568 case MT76_TM_TX_MODE_HT:
569 nss = 1 + (rate_idx >> 3);
570 mode = MT_PHY_TYPE_HT;
571 break;
572 case MT76_TM_TX_MODE_VHT:
573 mode = MT_PHY_TYPE_VHT;
574 break;
575 case MT76_TM_TX_MODE_HE_SU:
576 mode = MT_PHY_TYPE_HE_SU;
577 break;
578 case MT76_TM_TX_MODE_HE_EXT_SU:
579 mode = MT_PHY_TYPE_HE_EXT_SU;
580 break;
581 case MT76_TM_TX_MODE_HE_TB:
582 mode = MT_PHY_TYPE_HE_TB;
583 break;
584 case MT76_TM_TX_MODE_HE_MU:
585 mode = MT_PHY_TYPE_HE_MU;
586 break;
587 case MT76_TM_TX_MODE_CCK:
588 cck = true;
589 fallthrough;
590 case MT76_TM_TX_MODE_OFDM:
591 band = phy->mt76->chandef.chan->band;
592 if (band == NL80211_BAND_2GHZ && !cck)
593 rate_idx += 4;
594
595 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx];
596 val = cck ? r->hw_value_short : r->hw_value;
597
598 mode = val >> 8;
599 rate_idx = val & 0xff;
600 break;
601 default:
602 mode = MT_PHY_TYPE_OFDM;
603 break;
604 }
605
606 switch (phy->mt76->chandef.width) {
607 case NL80211_CHAN_WIDTH_40:
608 bw = 1;
609 break;
610 case NL80211_CHAN_WIDTH_80:
611 bw = 2;
612 break;
613 case NL80211_CHAN_WIDTH_80P80:
614 case NL80211_CHAN_WIDTH_160:
615 bw = 3;
616 break;
617 default:
618 bw = 0;
619 break;
620 }
621
622 if (td->tx_rate_stbc && nss == 1) {
623 nss++;
624 rateval |= MT_TX_RATE_STBC;
625 }
626
627 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
628 FIELD_PREP(MT_TX_RATE_MODE, mode) |
629 FIELD_PREP(MT_TX_RATE_NSS, nss - 1);
630
631 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
632
633 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT);
634 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT)
635 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
636
637 val = MT_TXD6_FIXED_BW |
638 FIELD_PREP(MT_TXD6_BW, bw) |
639 FIELD_PREP(MT_TXD6_TX_RATE, rateval) |
640 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi);
641
642 /* for HE_SU/HE_EXT_SU PPDU
643 * - 1x, 2x, 4x LTF + 0.8us GI
644 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
645 * for HE_MU PPDU
646 * - 2x, 4x LTF + 0.8us GI
647 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
648 * for HE_TB PPDU
649 * - 1x, 2x LTF + 1.6us GI
650 * - 4x LTF + 3.2us GI
651 */
652 if (mode >= MT_PHY_TYPE_HE_SU)
653 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
654
655 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
656 val |= MT_TXD6_LDPC;
657
658 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
659 txwi[6] |= cpu_to_le32(val);
660 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
661 phy->test.spe_idx));
662 #endif
663 }
664
mt7915_mac_write_txwi(struct mt76_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,int pid,struct ieee80211_key_conf * key,enum mt76_txq_id qid,u32 changed)665 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
666 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
667 struct ieee80211_key_conf *key,
668 enum mt76_txq_id qid, u32 changed)
669 {
670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
671 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
672 struct mt76_phy *mphy = &dev->phy;
673
674 if (phy_idx && dev->phys[MT_BAND1])
675 mphy = dev->phys[MT_BAND1];
676
677 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed);
678
679 if (mt76_testmode_enabled(mphy))
680 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb);
681 }
682
mt7915_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)683 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
684 enum mt76_txq_id qid, struct mt76_wcid *wcid,
685 struct ieee80211_sta *sta,
686 struct mt76_tx_info *tx_info)
687 {
688 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
689 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
691 struct ieee80211_key_conf *key = info->control.hw_key;
692 struct ieee80211_vif *vif = info->control.vif;
693 struct mt76_connac_fw_txp *txp;
694 struct mt76_txwi_cache *t;
695 int id, i, nbuf = tx_info->nbuf - 1;
696 u8 *txwi = (u8 *)txwi_ptr;
697 int pid;
698
699 if (unlikely(tx_info->skb->len <= ETH_HLEN))
700 return -EINVAL;
701
702 if (!wcid)
703 wcid = &dev->mt76.global_wcid;
704
705 if (sta) {
706 struct mt7915_sta *msta;
707
708 msta = (struct mt7915_sta *)sta->drv_priv;
709
710 if (time_after(jiffies, msta->jiffies + HZ / 4)) {
711 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS;
712 msta->jiffies = jiffies;
713 }
714 }
715
716 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
717 t->skb = tx_info->skb;
718
719 id = mt76_token_consume(mdev, &t);
720 if (id < 0)
721 return id;
722
723 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
724 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key,
725 qid, 0);
726
727 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE);
728 for (i = 0; i < nbuf; i++) {
729 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
730 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
731 }
732 txp->nbuf = nbuf;
733
734 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST);
735
736 if (!key)
737 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
738
739 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
740 ieee80211_is_mgmt(hdr->frame_control))
741 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
742
743 if (vif) {
744 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
745
746 txp->bss_idx = mvif->mt76.idx;
747 }
748
749 txp->token = cpu_to_le16(id);
750 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags))
751 txp->rept_wds_wcid = cpu_to_le16(wcid->idx);
752 else
753 txp->rept_wds_wcid = cpu_to_le16(0x3ff);
754 tx_info->skb = DMA_DUMMY_DATA;
755
756 /* pass partial skb header to fw */
757 tx_info->buf[1].len = MT_CT_PARSE_LEN;
758 tx_info->buf[1].skip_unmap = true;
759 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
760
761 return 0;
762 }
763
mt7915_wed_init_buf(void * ptr,dma_addr_t phys,int token_id)764 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
765 {
766 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE;
767 __le32 *txwi = ptr;
768 u32 val;
769
770 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp));
771
772 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) |
773 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT);
774 txwi[0] = cpu_to_le32(val);
775
776 val = MT_TXD1_LONG_FORMAT |
777 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3);
778 txwi[1] = cpu_to_le32(val);
779
780 txp->token = cpu_to_le16(token_id);
781 txp->nbuf = 1;
782 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
783
784 return MT_TXD_SIZE + sizeof(*txp);
785 }
786
787 static void
mt7915_tx_check_aggr(struct ieee80211_sta * sta,__le32 * txwi)788 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
789 {
790 struct mt7915_sta *msta;
791 u16 fc, tid;
792 u32 val;
793
794 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he))
795 return;
796
797 tid = le32_get_bits(txwi[1], MT_TXD1_TID);
798 if (tid >= 6) /* skip VO queue */
799 return;
800
801 val = le32_to_cpu(txwi[2]);
802 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
803 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
804 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
805 return;
806
807 msta = (struct mt7915_sta *)sta->drv_priv;
808 if (!test_and_set_bit(tid, &msta->ampdu_state))
809 ieee80211_start_tx_ba_session(sta, tid, 0);
810 }
811
812 static void
mt7915_txwi_free(struct mt7915_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_sta * sta,struct list_head * free_list)813 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
814 struct ieee80211_sta *sta, struct list_head *free_list)
815 {
816 struct mt76_dev *mdev = &dev->mt76;
817 struct mt7915_sta *msta;
818 struct mt76_wcid *wcid;
819 __le32 *txwi;
820 u16 wcid_idx;
821
822 mt76_connac_txp_skb_unmap(mdev, t);
823 if (!t->skb)
824 goto out;
825
826 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t);
827 if (sta) {
828 wcid = (struct mt76_wcid *)sta->drv_priv;
829 wcid_idx = wcid->idx;
830 } else {
831 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX);
832 wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]);
833
834 if (wcid && wcid->sta) {
835 msta = container_of(wcid, struct mt7915_sta, wcid);
836 sta = container_of((void *)msta, struct ieee80211_sta,
837 drv_priv);
838 spin_lock_bh(&dev->sta_poll_lock);
839 if (list_empty(&msta->poll_list))
840 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
841 spin_unlock_bh(&dev->sta_poll_lock);
842 }
843 }
844
845 if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
846 mt7915_tx_check_aggr(sta, txwi);
847
848 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list);
849
850 out:
851 t->skb = NULL;
852 mt76_put_txwi(mdev, t);
853 }
854
855 static void
mt7915_mac_tx_free_prepare(struct mt7915_dev * dev)856 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev)
857 {
858 struct mt76_dev *mdev = &dev->mt76;
859 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1];
860
861 /* clean DMA queues and unmap buffers first */
862 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
863 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
864 if (mphy_ext) {
865 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
866 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
867 }
868 }
869
870 static void
mt7915_mac_tx_free_done(struct mt7915_dev * dev,struct list_head * free_list,bool wake)871 mt7915_mac_tx_free_done(struct mt7915_dev *dev,
872 struct list_head *free_list, bool wake)
873 {
874 struct sk_buff *skb, *tmp;
875
876 mt7915_mac_sta_poll(dev);
877
878 if (wake)
879 mt76_set_tx_blocked(&dev->mt76, false);
880
881 mt76_worker_schedule(&dev->mt76.tx_worker);
882
883 list_for_each_entry_safe(skb, tmp, free_list, list) {
884 skb_list_del_init(skb);
885 napi_consume_skb(skb, 1);
886 }
887 }
888
889 static void
mt7915_mac_tx_free(struct mt7915_dev * dev,void * data,int len)890 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
891 {
892 struct mt76_connac_tx_free *free = data;
893 __le32 *tx_info = (__le32 *)(data + sizeof(*free));
894 struct mt76_dev *mdev = &dev->mt76;
895 struct mt76_txwi_cache *txwi;
896 struct ieee80211_sta *sta = NULL;
897 LIST_HEAD(free_list);
898 void *end = data + len;
899 bool v3, wake = false;
900 u16 total, count = 0;
901 u32 txd = le32_to_cpu(free->txd);
902 __le32 *cur_info;
903
904 mt7915_mac_tx_free_prepare(dev);
905
906 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT);
907 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4);
908 if (WARN_ON_ONCE((void *)&tx_info[total >> v3] > end))
909 return;
910
911 for (cur_info = tx_info; count < total; cur_info++) {
912 u32 msdu, info = le32_to_cpu(*cur_info);
913 u8 i;
914
915 /*
916 * 1'b1: new wcid pair.
917 * 1'b0: msdu_id with the same 'wcid pair' as above.
918 */
919 if (info & MT_TX_FREE_PAIR) {
920 struct mt7915_sta *msta;
921 struct mt76_wcid *wcid;
922 u16 idx;
923
924 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
925 wcid = rcu_dereference(dev->mt76.wcid[idx]);
926 sta = wcid_to_sta(wcid);
927 if (!sta)
928 continue;
929
930 msta = container_of(wcid, struct mt7915_sta, wcid);
931 spin_lock_bh(&dev->sta_poll_lock);
932 if (list_empty(&msta->poll_list))
933 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
934 spin_unlock_bh(&dev->sta_poll_lock);
935 continue;
936 }
937
938 if (v3 && (info & MT_TX_FREE_MPDU_HEADER))
939 continue;
940
941 for (i = 0; i < 1 + v3; i++) {
942 if (v3) {
943 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3;
944 if (msdu == MT_TX_FREE_MSDU_ID_V3)
945 continue;
946 } else {
947 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
948 }
949 count++;
950 txwi = mt76_token_release(mdev, msdu, &wake);
951 if (!txwi)
952 continue;
953
954 mt7915_txwi_free(dev, txwi, sta, &free_list);
955 }
956 }
957
958 mt7915_mac_tx_free_done(dev, &free_list, wake);
959 }
960
961 static void
mt7915_mac_tx_free_v0(struct mt7915_dev * dev,void * data,int len)962 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len)
963 {
964 struct mt76_connac_tx_free *free = data;
965 __le16 *info = (__le16 *)(data + sizeof(*free));
966 struct mt76_dev *mdev = &dev->mt76;
967 void *end = data + len;
968 LIST_HEAD(free_list);
969 bool wake = false;
970 u8 i, count;
971
972 mt7915_mac_tx_free_prepare(dev);
973
974 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl));
975 if (WARN_ON_ONCE((void *)&info[count] > end))
976 return;
977
978 for (i = 0; i < count; i++) {
979 struct mt76_txwi_cache *txwi;
980 u16 msdu = le16_to_cpu(info[i]);
981
982 txwi = mt76_token_release(mdev, msdu, &wake);
983 if (!txwi)
984 continue;
985
986 mt7915_txwi_free(dev, txwi, NULL, &free_list);
987 }
988
989 mt7915_mac_tx_free_done(dev, &free_list, wake);
990 }
991
mt7915_mac_add_txs(struct mt7915_dev * dev,void * data)992 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
993 {
994 struct mt7915_sta *msta = NULL;
995 struct mt76_wcid *wcid;
996 __le32 *txs_data = data;
997 u16 wcidx;
998 u8 pid;
999
1000 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
1001 pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
1002
1003 if (pid < MT_PACKET_ID_WED)
1004 return;
1005
1006 if (wcidx >= mt7915_wtbl_size(dev))
1007 return;
1008
1009 rcu_read_lock();
1010
1011 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1012 if (!wcid)
1013 goto out;
1014
1015 msta = container_of(wcid, struct mt7915_sta, wcid);
1016
1017 if (pid == MT_PACKET_ID_WED)
1018 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data);
1019 else
1020 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data);
1021
1022 if (!wcid->sta)
1023 goto out;
1024
1025 spin_lock_bh(&dev->sta_poll_lock);
1026 if (list_empty(&msta->poll_list))
1027 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1028 spin_unlock_bh(&dev->sta_poll_lock);
1029
1030 out:
1031 rcu_read_unlock();
1032 }
1033
mt7915_rx_check(struct mt76_dev * mdev,void * data,int len)1034 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
1035 {
1036 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1037 __le32 *rxd = (__le32 *)data;
1038 __le32 *end = (__le32 *)&rxd[len / 4];
1039 enum rx_pkt_type type;
1040
1041 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1042
1043 switch (type) {
1044 case PKT_TYPE_TXRX_NOTIFY:
1045 mt7915_mac_tx_free(dev, data, len);
1046 return false;
1047 case PKT_TYPE_TXRX_NOTIFY_V0:
1048 mt7915_mac_tx_free_v0(dev, data, len);
1049 return false;
1050 case PKT_TYPE_TXS:
1051 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1052 mt7915_mac_add_txs(dev, rxd);
1053 return false;
1054 case PKT_TYPE_RX_FW_MONITOR:
1055 mt7915_debugfs_rx_fw_monitor(dev, data, len);
1056 return false;
1057 default:
1058 return true;
1059 }
1060 }
1061
mt7915_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)1062 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1063 struct sk_buff *skb)
1064 {
1065 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1066 __le32 *rxd = (__le32 *)skb->data;
1067 __le32 *end = (__le32 *)&skb->data[skb->len];
1068 enum rx_pkt_type type;
1069
1070 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1071
1072 switch (type) {
1073 case PKT_TYPE_TXRX_NOTIFY:
1074 mt7915_mac_tx_free(dev, skb->data, skb->len);
1075 napi_consume_skb(skb, 1);
1076 break;
1077 case PKT_TYPE_TXRX_NOTIFY_V0:
1078 mt7915_mac_tx_free_v0(dev, skb->data, skb->len);
1079 napi_consume_skb(skb, 1);
1080 break;
1081 case PKT_TYPE_RX_EVENT:
1082 mt7915_mcu_rx_event(dev, skb);
1083 break;
1084 case PKT_TYPE_TXRXV:
1085 mt7915_mac_fill_rx_vector(dev, skb);
1086 break;
1087 case PKT_TYPE_TXS:
1088 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1089 mt7915_mac_add_txs(dev, rxd);
1090 dev_kfree_skb(skb);
1091 break;
1092 case PKT_TYPE_RX_FW_MONITOR:
1093 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len);
1094 dev_kfree_skb(skb);
1095 break;
1096 case PKT_TYPE_NORMAL:
1097 if (!mt7915_mac_fill_rx(dev, skb)) {
1098 mt76_rx(&dev->mt76, q, skb);
1099 return;
1100 }
1101 fallthrough;
1102 default:
1103 dev_kfree_skb(skb);
1104 break;
1105 }
1106 }
1107
mt7915_mac_cca_stats_reset(struct mt7915_phy * phy)1108 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
1109 {
1110 struct mt7915_dev *dev = phy->dev;
1111 u32 reg = MT_WF_PHY_RX_CTRL1(phy->band_idx);
1112
1113 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
1114 mt76_set(dev, reg, BIT(11) | BIT(9));
1115 }
1116
mt7915_mac_reset_counters(struct mt7915_phy * phy)1117 void mt7915_mac_reset_counters(struct mt7915_phy *phy)
1118 {
1119 struct mt7915_dev *dev = phy->dev;
1120 int i;
1121
1122 for (i = 0; i < 4; i++) {
1123 mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
1124 mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i));
1125 }
1126
1127 i = 0;
1128 phy->mt76->survey_time = ktime_get_boottime();
1129 if (phy->band_idx)
1130 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
1131
1132 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
1133
1134 /* reset airtime counters */
1135 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->band_idx),
1136 MT_WF_RMAC_MIB_RXTIME_CLR);
1137
1138 mt7915_mcu_get_chan_mib_info(phy, true);
1139 }
1140
mt7915_mac_set_timing(struct mt7915_phy * phy)1141 void mt7915_mac_set_timing(struct mt7915_phy *phy)
1142 {
1143 s16 coverage_class = phy->coverage_class;
1144 struct mt7915_dev *dev = phy->dev;
1145 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
1146 u32 val, reg_offset;
1147 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1149 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1150 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1151 int eifs_ofdm = 360, sifs = 10, offset;
1152 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ);
1153
1154 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1155 return;
1156
1157 if (ext_phy)
1158 coverage_class = max_t(s16, dev->phy.coverage_class,
1159 ext_phy->coverage_class);
1160
1161 mt76_set(dev, MT_ARB_SCR(phy->band_idx),
1162 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1163 udelay(1);
1164
1165 offset = 3 * coverage_class;
1166 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1167 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1168
1169 if (!is_mt7915(&dev->mt76)) {
1170 if (!a_band) {
1171 mt76_wr(dev, MT_TMAC_ICR1(phy->band_idx),
1172 FIELD_PREP(MT_IFS_EIFS_CCK, 314));
1173 eifs_ofdm = 78;
1174 } else {
1175 eifs_ofdm = 84;
1176 }
1177 } else if (a_band) {
1178 sifs = 16;
1179 }
1180
1181 mt76_wr(dev, MT_TMAC_CDTR(phy->band_idx), cck + reg_offset);
1182 mt76_wr(dev, MT_TMAC_ODTR(phy->band_idx), ofdm + reg_offset);
1183 mt76_wr(dev, MT_TMAC_ICR0(phy->band_idx),
1184 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) |
1185 FIELD_PREP(MT_IFS_RIFS, 2) |
1186 FIELD_PREP(MT_IFS_SIFS, sifs) |
1187 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1188
1189 if (phy->slottime < 20 || a_band)
1190 val = MT7915_CFEND_RATE_DEFAULT;
1191 else
1192 val = MT7915_CFEND_RATE_11B;
1193
1194 mt76_rmw_field(dev, MT_AGG_ACR0(phy->band_idx), MT_AGG_ACR_CFEND_RATE, val);
1195 mt76_clear(dev, MT_ARB_SCR(phy->band_idx),
1196 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1197 }
1198
mt7915_mac_enable_nf(struct mt7915_dev * dev,bool ext_phy)1199 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy)
1200 {
1201 u32 reg;
1202
1203 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(ext_phy) :
1204 MT_WF_PHY_RXTD12_MT7916(ext_phy);
1205 mt76_set(dev, reg,
1206 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |
1207 MT_WF_PHY_RXTD12_IRPI_SW_CLR);
1208
1209 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(ext_phy) :
1210 MT_WF_PHY_RX_CTRL1_MT7916(ext_phy);
1211 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));
1212 }
1213
1214 static u8
mt7915_phy_get_nf(struct mt7915_phy * phy,int idx)1215 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx)
1216 {
1217 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1218 struct mt7915_dev *dev = phy->dev;
1219 u32 val, sum = 0, n = 0;
1220 int nss, i;
1221
1222 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) {
1223 u32 reg = is_mt7915(&dev->mt76) ?
1224 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) :
1225 MT_WF_IRPI_NSS_MT7916(idx, nss);
1226
1227 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1228 val = mt76_rr(dev, reg);
1229 sum += val * nf_power[i];
1230 n += val;
1231 }
1232 }
1233
1234 if (!n)
1235 return 0;
1236
1237 return sum / n;
1238 }
1239
mt7915_update_channel(struct mt76_phy * mphy)1240 void mt7915_update_channel(struct mt76_phy *mphy)
1241 {
1242 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv;
1243 struct mt76_channel_state *state = mphy->chan_state;
1244 int nf;
1245
1246 mt7915_mcu_get_chan_mib_info(phy, false);
1247
1248 nf = mt7915_phy_get_nf(phy, phy->band_idx);
1249 if (!phy->noise)
1250 phy->noise = nf << 4;
1251 else if (nf)
1252 phy->noise += nf - (phy->noise >> 4);
1253
1254 state->noise = -(phy->noise >> 4);
1255 }
1256
1257 static bool
mt7915_wait_reset_state(struct mt7915_dev * dev,u32 state)1258 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1259 {
1260 bool ret;
1261
1262 ret = wait_event_timeout(dev->reset_wait,
1263 (READ_ONCE(dev->reset_state) & state),
1264 MT7915_RESET_TIMEOUT);
1265
1266 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1267 return ret;
1268 }
1269
1270 static void
mt7915_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)1271 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1272 {
1273 struct ieee80211_hw *hw = priv;
1274
1275 switch (vif->type) {
1276 case NL80211_IFTYPE_MESH_POINT:
1277 case NL80211_IFTYPE_ADHOC:
1278 case NL80211_IFTYPE_AP:
1279 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon,
1280 BSS_CHANGED_BEACON_ENABLED);
1281 break;
1282 default:
1283 break;
1284 }
1285 }
1286
1287 static void
mt7915_update_beacons(struct mt7915_dev * dev)1288 mt7915_update_beacons(struct mt7915_dev *dev)
1289 {
1290 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1];
1291
1292 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1293 IEEE80211_IFACE_ITER_RESUME_ALL,
1294 mt7915_update_vif_beacon, dev->mt76.hw);
1295
1296 if (!mphy_ext)
1297 return;
1298
1299 ieee80211_iterate_active_interfaces(mphy_ext->hw,
1300 IEEE80211_IFACE_ITER_RESUME_ALL,
1301 mt7915_update_vif_beacon, mphy_ext->hw);
1302 }
1303
1304 static void
mt7915_dma_reset(struct mt7915_dev * dev)1305 mt7915_dma_reset(struct mt7915_dev *dev)
1306 {
1307 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1];
1308 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
1309 int i;
1310
1311 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1312 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1313 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1314
1315 if (is_mt7915(&dev->mt76))
1316 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1317 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1318 MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1319 if (dev->hif2) {
1320 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1321 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1322 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1323
1324 if (is_mt7915(&dev->mt76))
1325 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1326 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1327 MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1328 }
1329
1330 usleep_range(1000, 2000);
1331
1332 for (i = 0; i < __MT_TXQ_MAX; i++) {
1333 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1334 if (mphy_ext)
1335 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true);
1336 }
1337
1338 for (i = 0; i < __MT_MCUQ_MAX; i++)
1339 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
1340
1341 mt76_for_each_q_rx(&dev->mt76, i)
1342 mt76_queue_rx_reset(dev, i);
1343
1344 mt76_tx_status_check(&dev->mt76, true);
1345
1346 /* re-init prefetch settings after reset */
1347 mt7915_dma_prefetch(dev);
1348
1349 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1350 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1351 if (is_mt7915(&dev->mt76))
1352 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1353 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1354 MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1355 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1356 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
1357 if (dev->hif2) {
1358 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1359 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1360 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1361
1362 if (is_mt7915(&dev->mt76))
1363 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1364 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1365 MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1366 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1367 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
1368 }
1369 }
1370
mt7915_tx_token_put(struct mt7915_dev * dev)1371 void mt7915_tx_token_put(struct mt7915_dev *dev)
1372 {
1373 struct mt76_txwi_cache *txwi;
1374 int id;
1375
1376 spin_lock_bh(&dev->mt76.token_lock);
1377 idr_for_each_entry(&dev->mt76.token, txwi, id) {
1378 mt7915_txwi_free(dev, txwi, NULL, NULL);
1379 dev->mt76.token_count--;
1380 }
1381 spin_unlock_bh(&dev->mt76.token_lock);
1382 idr_destroy(&dev->mt76.token);
1383 }
1384
1385 /* system error recovery */
mt7915_mac_reset_work(struct work_struct * work)1386 void mt7915_mac_reset_work(struct work_struct *work)
1387 {
1388 struct mt7915_phy *phy2;
1389 struct mt76_phy *ext_phy;
1390 struct mt7915_dev *dev;
1391 int i;
1392
1393 dev = container_of(work, struct mt7915_dev, reset_work);
1394 ext_phy = dev->mt76.phys[MT_BAND1];
1395 phy2 = ext_phy ? ext_phy->priv : NULL;
1396
1397 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1398 return;
1399
1400 ieee80211_stop_queues(mt76_hw(dev));
1401 if (ext_phy)
1402 ieee80211_stop_queues(ext_phy->hw);
1403
1404 set_bit(MT76_RESET, &dev->mphy.state);
1405 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1406 wake_up(&dev->mt76.mcu.wait);
1407 cancel_delayed_work_sync(&dev->mphy.mac_work);
1408 if (phy2) {
1409 set_bit(MT76_RESET, &phy2->mt76->state);
1410 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1411 }
1412 mt76_worker_disable(&dev->mt76.tx_worker);
1413 mt76_for_each_q_rx(&dev->mt76, i)
1414 napi_disable(&dev->mt76.napi[i]);
1415 napi_disable(&dev->mt76.tx_napi);
1416
1417 mutex_lock(&dev->mt76.mutex);
1418
1419 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1420
1421 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1422 mt7915_dma_reset(dev);
1423
1424 mt7915_tx_token_put(dev);
1425 idr_init(&dev->mt76.token);
1426
1427 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1428 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1429 }
1430
1431 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1432 clear_bit(MT76_RESET, &dev->mphy.state);
1433 if (phy2)
1434 clear_bit(MT76_RESET, &phy2->mt76->state);
1435
1436 local_bh_disable();
1437 mt76_for_each_q_rx(&dev->mt76, i) {
1438 napi_enable(&dev->mt76.napi[i]);
1439 napi_schedule(&dev->mt76.napi[i]);
1440 }
1441 local_bh_enable();
1442
1443 tasklet_schedule(&dev->irq_tasklet);
1444
1445 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1446 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1447
1448 mt76_worker_enable(&dev->mt76.tx_worker);
1449
1450 local_bh_disable();
1451 napi_enable(&dev->mt76.tx_napi);
1452 napi_schedule(&dev->mt76.tx_napi);
1453 local_bh_enable();
1454
1455 ieee80211_wake_queues(mt76_hw(dev));
1456 if (ext_phy)
1457 ieee80211_wake_queues(ext_phy->hw);
1458
1459 mutex_unlock(&dev->mt76.mutex);
1460
1461 mt7915_update_beacons(dev);
1462
1463 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1464 MT7915_WATCHDOG_TIME);
1465 if (phy2)
1466 ieee80211_queue_delayed_work(ext_phy->hw,
1467 &phy2->mt76->mac_work,
1468 MT7915_WATCHDOG_TIME);
1469 }
1470
mt7915_mac_update_stats(struct mt7915_phy * phy)1471 void mt7915_mac_update_stats(struct mt7915_phy *phy)
1472 {
1473 struct mt7915_dev *dev = phy->dev;
1474 struct mib_stats *mib = &phy->mib;
1475 int i, aggr0, aggr1, cnt;
1476 u32 val;
1477
1478 cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx));
1479 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ?
1480 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
1481 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
1482
1483 cnt = mt76_rr(dev, MT_MIB_SDR4(phy->band_idx));
1484 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);
1485
1486 cnt = mt76_rr(dev, MT_MIB_SDR5(phy->band_idx));
1487 mib->rx_mpdu_cnt += cnt;
1488
1489 cnt = mt76_rr(dev, MT_MIB_SDR6(phy->band_idx));
1490 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt);
1491
1492 cnt = mt76_rr(dev, MT_MIB_SDR7(phy->band_idx));
1493 mib->rx_vector_mismatch_cnt +=
1494 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt);
1495
1496 cnt = mt76_rr(dev, MT_MIB_SDR8(phy->band_idx));
1497 mib->rx_delimiter_fail_cnt +=
1498 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt);
1499
1500 cnt = mt76_rr(dev, MT_MIB_SDR10(phy->band_idx));
1501 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ?
1502 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) :
1503 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt);
1504
1505 cnt = mt76_rr(dev, MT_MIB_SDR11(phy->band_idx));
1506 mib->rx_len_mismatch_cnt +=
1507 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt);
1508
1509 cnt = mt76_rr(dev, MT_MIB_SDR12(phy->band_idx));
1510 mib->tx_ampdu_cnt += cnt;
1511
1512 cnt = mt76_rr(dev, MT_MIB_SDR13(phy->band_idx));
1513 mib->tx_stop_q_empty_cnt +=
1514 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt);
1515
1516 cnt = mt76_rr(dev, MT_MIB_SDR14(phy->band_idx));
1517 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ?
1518 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) :
1519 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt);
1520
1521 cnt = mt76_rr(dev, MT_MIB_SDR15(phy->band_idx));
1522 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ?
1523 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) :
1524 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt);
1525
1526 cnt = mt76_rr(dev, MT_MIB_SDR16(phy->band_idx));
1527 mib->primary_cca_busy_time +=
1528 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt);
1529
1530 cnt = mt76_rr(dev, MT_MIB_SDR17(phy->band_idx));
1531 mib->secondary_cca_busy_time +=
1532 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt);
1533
1534 cnt = mt76_rr(dev, MT_MIB_SDR18(phy->band_idx));
1535 mib->primary_energy_detect_time +=
1536 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt);
1537
1538 cnt = mt76_rr(dev, MT_MIB_SDR19(phy->band_idx));
1539 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt);
1540
1541 cnt = mt76_rr(dev, MT_MIB_SDR20(phy->band_idx));
1542 mib->ofdm_mdrdy_time +=
1543 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt);
1544
1545 cnt = mt76_rr(dev, MT_MIB_SDR21(phy->band_idx));
1546 mib->green_mdrdy_time +=
1547 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt);
1548
1549 cnt = mt76_rr(dev, MT_MIB_SDR22(phy->band_idx));
1550 mib->rx_ampdu_cnt += cnt;
1551
1552 cnt = mt76_rr(dev, MT_MIB_SDR23(phy->band_idx));
1553 mib->rx_ampdu_bytes_cnt += cnt;
1554
1555 cnt = mt76_rr(dev, MT_MIB_SDR24(phy->band_idx));
1556 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ?
1557 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) :
1558 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt);
1559
1560 cnt = mt76_rr(dev, MT_MIB_SDR25(phy->band_idx));
1561 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;
1562
1563 cnt = mt76_rr(dev, MT_MIB_SDR27(phy->band_idx));
1564 mib->tx_rwp_fail_cnt +=
1565 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt);
1566
1567 cnt = mt76_rr(dev, MT_MIB_SDR28(phy->band_idx));
1568 mib->tx_rwp_need_cnt +=
1569 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt);
1570
1571 cnt = mt76_rr(dev, MT_MIB_SDR29(phy->band_idx));
1572 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ?
1573 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) :
1574 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt);
1575
1576 cnt = mt76_rr(dev, MT_MIB_SDRVEC(phy->band_idx));
1577 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ?
1578 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) :
1579 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt);
1580
1581 cnt = mt76_rr(dev, MT_MIB_SDR31(phy->band_idx));
1582 mib->rx_ba_cnt += cnt;
1583
1584 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(phy->band_idx));
1585 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
1586
1587 cnt = mt76_rr(dev, MT_MIB_DR8(phy->band_idx));
1588 mib->tx_mu_mpdu_cnt += cnt;
1589
1590 cnt = mt76_rr(dev, MT_MIB_DR9(phy->band_idx));
1591 mib->tx_mu_acked_mpdu_cnt += cnt;
1592
1593 cnt = mt76_rr(dev, MT_MIB_DR11(phy->band_idx));
1594 mib->tx_su_acked_mpdu_cnt += cnt;
1595
1596 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(phy->band_idx));
1597 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt);
1598 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt);
1599 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt);
1600
1601 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
1602 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
1603 mib->tx_amsdu[i] += cnt;
1604 mib->tx_amsdu_cnt += cnt;
1605 }
1606
1607 aggr0 = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1608 if (is_mt7915(&dev->mt76)) {
1609 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) {
1610 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 4)));
1611 mib->ba_miss_cnt +=
1612 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1613 mib->ack_fail_cnt +=
1614 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1615
1616 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 4)));
1617 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1618 mib->rts_retries_cnt +=
1619 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1620
1621 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
1622 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
1623 dev->mt76.aggr_stats[aggr0++] += val >> 16;
1624
1625 val = mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i));
1626 dev->mt76.aggr_stats[aggr1++] += val & 0xffff;
1627 dev->mt76.aggr_stats[aggr1++] += val >> 16;
1628 }
1629
1630 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
1631 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1632
1633 cnt = mt76_rr(dev, MT_MIB_SDR33(phy->band_idx));
1634 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt);
1635
1636 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx));
1637 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt);
1638 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt);
1639
1640 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx));
1641 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt);
1642 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt);
1643
1644 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx));
1645 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt);
1646 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt);
1647 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt);
1648 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt);
1649 } else {
1650 for (i = 0; i < 2; i++) {
1651 /* rts count */
1652 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 2)));
1653 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val);
1654 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val);
1655
1656 /* rts retry count */
1657 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 2)));
1658 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val);
1659 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val);
1660
1661 /* ba miss count */
1662 val = mt76_rr(dev, MT_MIB_MB_SDR2(phy->band_idx, (i << 2)));
1663 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val);
1664 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val);
1665
1666 /* ack fail count */
1667 val = mt76_rr(dev, MT_MIB_MB_BFTF(phy->band_idx, (i << 2)));
1668 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val);
1669 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val);
1670 }
1671
1672 for (i = 0; i < 8; i++) {
1673 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
1674 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val);
1675 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val);
1676 }
1677
1678 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
1679 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
1680 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
1681 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1682 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1683
1684 cnt = mt76_rr(dev, MT_MIB_BFCR7(phy->band_idx));
1685 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt);
1686
1687 cnt = mt76_rr(dev, MT_MIB_BFCR2(phy->band_idx));
1688 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt);
1689
1690 cnt = mt76_rr(dev, MT_MIB_BFCR0(phy->band_idx));
1691 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
1692 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
1693 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
1694 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
1695
1696 cnt = mt76_rr(dev, MT_MIB_BFCR1(phy->band_idx));
1697 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
1698 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
1699 }
1700 }
1701
mt7915_mac_severe_check(struct mt7915_phy * phy)1702 static void mt7915_mac_severe_check(struct mt7915_phy *phy)
1703 {
1704 struct mt7915_dev *dev = phy->dev;
1705 bool ext_phy = phy != &dev->phy;
1706 u32 trb;
1707
1708 if (!phy->omac_mask)
1709 return;
1710
1711 /* In rare cases, TRB pointers might be out of sync leads to RMAC
1712 * stopping Rx, so check status periodically to see if TRB hardware
1713 * requires minimal recovery.
1714 */
1715 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->band_idx));
1716
1717 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) !=
1718 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) &&
1719 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) !=
1720 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) &&
1721 trb == phy->trb_ts)
1722 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT,
1723 ext_phy);
1724
1725 phy->trb_ts = trb;
1726 }
1727
mt7915_mac_sta_rc_work(struct work_struct * work)1728 void mt7915_mac_sta_rc_work(struct work_struct *work)
1729 {
1730 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
1731 struct ieee80211_sta *sta;
1732 struct ieee80211_vif *vif;
1733 struct mt7915_sta *msta;
1734 u32 changed;
1735 LIST_HEAD(list);
1736
1737 spin_lock_bh(&dev->sta_poll_lock);
1738 list_splice_init(&dev->sta_rc_list, &list);
1739
1740 while (!list_empty(&list)) {
1741 msta = list_first_entry(&list, struct mt7915_sta, rc_list);
1742 list_del_init(&msta->rc_list);
1743 changed = msta->changed;
1744 msta->changed = 0;
1745 spin_unlock_bh(&dev->sta_poll_lock);
1746
1747 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
1748 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
1749
1750 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
1751 IEEE80211_RC_NSS_CHANGED |
1752 IEEE80211_RC_BW_CHANGED))
1753 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true);
1754
1755 if (changed & IEEE80211_RC_SMPS_CHANGED)
1756 mt7915_mcu_add_smps(dev, vif, sta);
1757
1758 spin_lock_bh(&dev->sta_poll_lock);
1759 }
1760
1761 spin_unlock_bh(&dev->sta_poll_lock);
1762 }
1763
mt7915_mac_work(struct work_struct * work)1764 void mt7915_mac_work(struct work_struct *work)
1765 {
1766 struct mt7915_phy *phy;
1767 struct mt76_phy *mphy;
1768
1769 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
1770 mac_work.work);
1771 phy = mphy->priv;
1772
1773 mutex_lock(&mphy->dev->mutex);
1774
1775 mt76_update_survey(mphy);
1776 if (++mphy->mac_work_count == 5) {
1777 mphy->mac_work_count = 0;
1778
1779 mt7915_mac_update_stats(phy);
1780 mt7915_mac_severe_check(phy);
1781 }
1782
1783 mutex_unlock(&mphy->dev->mutex);
1784
1785 mt76_tx_status_check(mphy->dev, false);
1786
1787 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
1788 MT7915_WATCHDOG_TIME);
1789 }
1790
mt7915_dfs_stop_radar_detector(struct mt7915_phy * phy)1791 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
1792 {
1793 struct mt7915_dev *dev = phy->dev;
1794
1795 if (phy->rdd_state & BIT(0))
1796 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0,
1797 MT_RX_SEL0, 0);
1798 if (phy->rdd_state & BIT(1))
1799 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1,
1800 MT_RX_SEL0, 0);
1801 }
1802
mt7915_dfs_start_rdd(struct mt7915_dev * dev,int chain)1803 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
1804 {
1805 int err, region;
1806
1807 switch (dev->mt76.region) {
1808 case NL80211_DFS_ETSI:
1809 region = 0;
1810 break;
1811 case NL80211_DFS_JP:
1812 region = 2;
1813 break;
1814 case NL80211_DFS_FCC:
1815 default:
1816 region = 1;
1817 break;
1818 }
1819
1820 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain,
1821 MT_RX_SEL0, region);
1822 if (err < 0)
1823 return err;
1824
1825 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain,
1826 MT_RX_SEL0, 1);
1827 }
1828
mt7915_dfs_start_radar_detector(struct mt7915_phy * phy)1829 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
1830 {
1831 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1832 struct mt7915_dev *dev = phy->dev;
1833 int err;
1834
1835 /* start CAC */
1836 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, phy->band_idx,
1837 MT_RX_SEL0, 0);
1838 if (err < 0)
1839 return err;
1840
1841 err = mt7915_dfs_start_rdd(dev, phy->band_idx);
1842 if (err < 0)
1843 return err;
1844
1845 phy->rdd_state |= BIT(phy->band_idx);
1846
1847 if (!is_mt7915(&dev->mt76))
1848 return 0;
1849
1850 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1851 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1852 err = mt7915_dfs_start_rdd(dev, 1);
1853 if (err < 0)
1854 return err;
1855
1856 phy->rdd_state |= BIT(1);
1857 }
1858
1859 return 0;
1860 }
1861
1862 static int
mt7915_dfs_init_radar_specs(struct mt7915_phy * phy)1863 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
1864 {
1865 const struct mt7915_dfs_radar_spec *radar_specs;
1866 struct mt7915_dev *dev = phy->dev;
1867 int err, i;
1868
1869 switch (dev->mt76.region) {
1870 case NL80211_DFS_FCC:
1871 radar_specs = &fcc_radar_specs;
1872 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
1873 if (err < 0)
1874 return err;
1875 break;
1876 case NL80211_DFS_ETSI:
1877 radar_specs = &etsi_radar_specs;
1878 break;
1879 case NL80211_DFS_JP:
1880 radar_specs = &jp_radar_specs;
1881 break;
1882 default:
1883 return -EINVAL;
1884 }
1885
1886 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1887 err = mt7915_mcu_set_radar_th(dev, i,
1888 &radar_specs->radar_pattern[i]);
1889 if (err < 0)
1890 return err;
1891 }
1892
1893 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1894 }
1895
mt7915_dfs_init_radar_detector(struct mt7915_phy * phy)1896 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
1897 {
1898 struct mt7915_dev *dev = phy->dev;
1899 enum mt76_dfs_state dfs_state, prev_state;
1900 int err;
1901
1902 prev_state = phy->mt76->dfs_state;
1903 dfs_state = mt76_phy_dfs_state(phy->mt76);
1904
1905 if (prev_state == dfs_state)
1906 return 0;
1907
1908 if (prev_state == MT_DFS_STATE_UNKNOWN)
1909 mt7915_dfs_stop_radar_detector(phy);
1910
1911 if (dfs_state == MT_DFS_STATE_DISABLED)
1912 goto stop;
1913
1914 if (prev_state <= MT_DFS_STATE_DISABLED) {
1915 err = mt7915_dfs_init_radar_specs(phy);
1916 if (err < 0)
1917 return err;
1918
1919 err = mt7915_dfs_start_radar_detector(phy);
1920 if (err < 0)
1921 return err;
1922
1923 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
1924 }
1925
1926 if (dfs_state == MT_DFS_STATE_CAC)
1927 return 0;
1928
1929 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END,
1930 phy->band_idx, MT_RX_SEL0, 0);
1931 if (err < 0) {
1932 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
1933 return err;
1934 }
1935
1936 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
1937 return 0;
1938
1939 stop:
1940 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START,
1941 phy->band_idx, MT_RX_SEL0, 0);
1942 if (err < 0)
1943 return err;
1944
1945 mt7915_dfs_stop_radar_detector(phy);
1946 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
1947
1948 return 0;
1949 }
1950
1951 static int
mt7915_mac_twt_duration_align(int duration)1952 mt7915_mac_twt_duration_align(int duration)
1953 {
1954 return duration << 8;
1955 }
1956
1957 static u64
mt7915_mac_twt_sched_list_add(struct mt7915_dev * dev,struct mt7915_twt_flow * flow)1958 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev,
1959 struct mt7915_twt_flow *flow)
1960 {
1961 struct mt7915_twt_flow *iter, *iter_next;
1962 u32 duration = flow->duration << 8;
1963 u64 start_tsf;
1964
1965 iter = list_first_entry_or_null(&dev->twt_list,
1966 struct mt7915_twt_flow, list);
1967 if (!iter || !iter->sched || iter->start_tsf > duration) {
1968 /* add flow as first entry in the list */
1969 list_add(&flow->list, &dev->twt_list);
1970 return 0;
1971 }
1972
1973 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) {
1974 start_tsf = iter->start_tsf +
1975 mt7915_mac_twt_duration_align(iter->duration);
1976 if (list_is_last(&iter->list, &dev->twt_list))
1977 break;
1978
1979 if (!iter_next->sched ||
1980 iter_next->start_tsf > start_tsf + duration) {
1981 list_add(&flow->list, &iter->list);
1982 goto out;
1983 }
1984 }
1985
1986 /* add flow as last entry in the list */
1987 list_add_tail(&flow->list, &dev->twt_list);
1988 out:
1989 return start_tsf;
1990 }
1991
mt7915_mac_check_twt_req(struct ieee80211_twt_setup * twt)1992 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt)
1993 {
1994 struct ieee80211_twt_params *twt_agrt;
1995 u64 interval, duration;
1996 u16 mantissa;
1997 u8 exp;
1998
1999 /* only individual agreement supported */
2000 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST)
2001 return -EOPNOTSUPP;
2002
2003 /* only 256us unit supported */
2004 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT)
2005 return -EOPNOTSUPP;
2006
2007 twt_agrt = (struct ieee80211_twt_params *)twt->params;
2008
2009 /* explicit agreement not supported */
2010 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT)))
2011 return -EOPNOTSUPP;
2012
2013 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP,
2014 le16_to_cpu(twt_agrt->req_type));
2015 mantissa = le16_to_cpu(twt_agrt->mantissa);
2016 duration = twt_agrt->min_twt_dur << 8;
2017
2018 interval = (u64)mantissa << exp;
2019 if (interval < duration)
2020 return -EOPNOTSUPP;
2021
2022 return 0;
2023 }
2024
2025 static bool
mt7915_mac_twt_param_equal(struct mt7915_sta * msta,struct ieee80211_twt_params * twt_agrt)2026 mt7915_mac_twt_param_equal(struct mt7915_sta *msta,
2027 struct ieee80211_twt_params *twt_agrt)
2028 {
2029 u16 type = le16_to_cpu(twt_agrt->req_type);
2030 u8 exp;
2031 int i;
2032
2033 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type);
2034 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) {
2035 struct mt7915_twt_flow *f;
2036
2037 if (!(msta->twt.flowid_mask & BIT(i)))
2038 continue;
2039
2040 f = &msta->twt.flow[i];
2041 if (f->duration == twt_agrt->min_twt_dur &&
2042 f->mantissa == twt_agrt->mantissa &&
2043 f->exp == exp &&
2044 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) &&
2045 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) &&
2046 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER))
2047 return true;
2048 }
2049
2050 return false;
2051 }
2052
mt7915_mac_add_twt_setup(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct ieee80211_twt_setup * twt)2053 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
2054 struct ieee80211_sta *sta,
2055 struct ieee80211_twt_setup *twt)
2056 {
2057 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT;
2058 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2059 struct ieee80211_twt_params *twt_agrt = (void *)twt->params;
2060 u16 req_type = le16_to_cpu(twt_agrt->req_type);
2061 enum ieee80211_twt_setup_cmd sta_setup_cmd;
2062 struct mt7915_dev *dev = mt7915_hw_dev(hw);
2063 struct mt7915_twt_flow *flow;
2064 int flowid, table_id;
2065 u8 exp;
2066
2067 if (mt7915_mac_check_twt_req(twt))
2068 goto out;
2069
2070 mutex_lock(&dev->mt76.mutex);
2071
2072 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT)
2073 goto unlock;
2074
2075 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow))
2076 goto unlock;
2077
2078 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) {
2079 setup_cmd = TWT_SETUP_CMD_DICTATE;
2080 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR;
2081 goto unlock;
2082 }
2083
2084 flowid = ffs(~msta->twt.flowid_mask) - 1;
2085 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID);
2086 twt_agrt->req_type |= le16_encode_bits(flowid,
2087 IEEE80211_TWT_REQTYPE_FLOWID);
2088
2089 table_id = ffs(~dev->twt.table_mask) - 1;
2090 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type);
2091 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type);
2092
2093 if (mt7915_mac_twt_param_equal(msta, twt_agrt))
2094 goto unlock;
2095
2096 flow = &msta->twt.flow[flowid];
2097 memset(flow, 0, sizeof(*flow));
2098 INIT_LIST_HEAD(&flow->list);
2099 flow->wcid = msta->wcid.idx;
2100 flow->table_id = table_id;
2101 flow->id = flowid;
2102 flow->duration = twt_agrt->min_twt_dur;
2103 flow->mantissa = twt_agrt->mantissa;
2104 flow->exp = exp;
2105 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION);
2106 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE);
2107 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER);
2108
2109 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST ||
2110 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) {
2111 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp;
2112 u64 flow_tsf, curr_tsf;
2113 u32 rem;
2114
2115 flow->sched = true;
2116 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow);
2117 curr_tsf = __mt7915_get_tsf(hw, msta->vif);
2118 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem);
2119 flow_tsf = curr_tsf + interval - rem;
2120 twt_agrt->twt = cpu_to_le64(flow_tsf);
2121 } else {
2122 list_add_tail(&flow->list, &dev->twt_list);
2123 }
2124 flow->tsf = le64_to_cpu(twt_agrt->twt);
2125
2126 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD))
2127 goto unlock;
2128
2129 setup_cmd = TWT_SETUP_CMD_ACCEPT;
2130 dev->twt.table_mask |= BIT(table_id);
2131 msta->twt.flowid_mask |= BIT(flowid);
2132 dev->twt.n_agrt++;
2133
2134 unlock:
2135 mutex_unlock(&dev->mt76.mutex);
2136 out:
2137 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD);
2138 twt_agrt->req_type |=
2139 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD);
2140 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) |
2141 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED);
2142 }
2143
mt7915_mac_twt_teardown_flow(struct mt7915_dev * dev,struct mt7915_sta * msta,u8 flowid)2144 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
2145 struct mt7915_sta *msta,
2146 u8 flowid)
2147 {
2148 struct mt7915_twt_flow *flow;
2149
2150 lockdep_assert_held(&dev->mt76.mutex);
2151
2152 if (flowid >= ARRAY_SIZE(msta->twt.flow))
2153 return;
2154
2155 if (!(msta->twt.flowid_mask & BIT(flowid)))
2156 return;
2157
2158 flow = &msta->twt.flow[flowid];
2159 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow,
2160 MCU_TWT_AGRT_DELETE))
2161 return;
2162
2163 list_del_init(&flow->list);
2164 msta->twt.flowid_mask &= ~BIT(flowid);
2165 dev->twt.table_mask &= ~BIT(flow->table_id);
2166 dev->twt.n_agrt--;
2167 }
2168