1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
33 #include <net/dsa.h>
34
35 #include "chip.h"
36 #include "devlink.h"
37 #include "global1.h"
38 #include "global2.h"
39 #include "hwtstamp.h"
40 #include "phy.h"
41 #include "port.h"
42 #include "ptp.h"
43 #include "serdes.h"
44 #include "smi.h"
45
assert_reg_lock(struct mv88e6xxx_chip * chip)46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 {
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52 }
53
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55 {
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68 }
69
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71 {
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84 }
85
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88 {
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121 }
122
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125 {
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128 }
129
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131 {
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
135 list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140 }
141
mv88e6xxx_g1_irq_mask(struct irq_data * d)142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143 {
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148 }
149
mv88e6xxx_g1_irq_unmask(struct irq_data * d)150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151 {
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156 }
157
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159 {
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189 unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196 out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198 }
199
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201 {
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205 }
206
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208 {
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212 }
213
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215 {
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232 out:
233 mv88e6xxx_reg_unlock(chip);
234 }
235
236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242 };
243
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247 {
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255 }
256
257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260 };
261
262 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264 {
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278 }
279
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281 {
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291 }
292
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294 {
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328 out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332 out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341 }
342
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344 {
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372 }
373
mv88e6xxx_irq_poll(struct kthread_work * work)374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
375 {
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383 }
384
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386 {
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404 }
405
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407 {
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414 }
415
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418 {
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436 }
437
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441 {
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466 restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471 }
472
mv88e6xxx_phy_is_internal(struct dsa_switch * ds,int port)473 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
474 {
475 struct mv88e6xxx_chip *chip = ds->priv;
476
477 return port < chip->info->num_internal_phys;
478 }
479
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481 {
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return port < chip->info->num_internal_phys;
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500 }
501
mv88e6xxx_serdes_pcs_get_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)502 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
503 struct phylink_link_state *state)
504 {
505 struct mv88e6xxx_chip *chip = ds->priv;
506 int lane;
507 int err;
508
509 mv88e6xxx_reg_lock(chip);
510 lane = mv88e6xxx_serdes_get_lane(chip, port);
511 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
512 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
513 state);
514 else
515 err = -EOPNOTSUPP;
516 mv88e6xxx_reg_unlock(chip);
517
518 return err;
519 }
520
mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip * chip,int port,unsigned int mode,phy_interface_t interface,const unsigned long * advertise)521 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
522 unsigned int mode,
523 phy_interface_t interface,
524 const unsigned long *advertise)
525 {
526 const struct mv88e6xxx_ops *ops = chip->info->ops;
527 int lane;
528
529 if (ops->serdes_pcs_config) {
530 lane = mv88e6xxx_serdes_get_lane(chip, port);
531 if (lane >= 0)
532 return ops->serdes_pcs_config(chip, port, lane, mode,
533 interface, advertise);
534 }
535
536 return 0;
537 }
538
mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch * ds,int port)539 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
540 {
541 struct mv88e6xxx_chip *chip = ds->priv;
542 const struct mv88e6xxx_ops *ops;
543 int err = 0;
544 int lane;
545
546 ops = chip->info->ops;
547
548 if (ops->serdes_pcs_an_restart) {
549 mv88e6xxx_reg_lock(chip);
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane >= 0)
552 err = ops->serdes_pcs_an_restart(chip, port, lane);
553 mv88e6xxx_reg_unlock(chip);
554
555 if (err)
556 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
557 }
558 }
559
mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip * chip,int port,unsigned int mode,int speed,int duplex)560 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
561 unsigned int mode,
562 int speed, int duplex)
563 {
564 const struct mv88e6xxx_ops *ops = chip->info->ops;
565 int lane;
566
567 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
568 lane = mv88e6xxx_serdes_get_lane(chip, port);
569 if (lane >= 0)
570 return ops->serdes_pcs_link_up(chip, port, lane,
571 speed, duplex);
572 }
573
574 return 0;
575 }
576
577 static const u8 mv88e6185_phy_interface_modes[] = {
578 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
579 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
580 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
581 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
582 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
583 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
584 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
585 };
586
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)587 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
588 struct phylink_config *config)
589 {
590 u8 cmode = chip->ports[port].cmode;
591
592 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
593
594 if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
595 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
596 } else {
597 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
598 mv88e6185_phy_interface_modes[cmode])
599 __set_bit(mv88e6185_phy_interface_modes[cmode],
600 config->supported_interfaces);
601
602 config->mac_capabilities |= MAC_1000FD;
603 }
604 }
605
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)606 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
607 struct phylink_config *config)
608 {
609 u8 cmode = chip->ports[port].cmode;
610
611 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
612 mv88e6185_phy_interface_modes[cmode])
613 __set_bit(mv88e6185_phy_interface_modes[cmode],
614 config->supported_interfaces);
615
616 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
617 MAC_1000FD;
618 }
619
620 static const u8 mv88e6xxx_phy_interface_modes[] = {
621 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII,
622 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
623 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
624 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII,
625 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
626 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
627 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
628 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
629 /* higher interface modes are not needed here, since ports supporting
630 * them are writable, and so the supported interfaces are filled in the
631 * corresponding .phylink_set_interfaces() implementation below
632 */
633 };
634
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)635 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
636 {
637 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
638 mv88e6xxx_phy_interface_modes[cmode])
639 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
640 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
641 phy_interface_set_rgmii(supported);
642 }
643
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)644 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
645 struct phylink_config *config)
646 {
647 unsigned long *supported = config->supported_interfaces;
648
649 /* Translate the default cmode */
650 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
651
652 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
653 }
654
mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip * chip)655 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
656 {
657 u16 reg, val;
658 int err;
659
660 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
661 if (err)
662 return err;
663
664 /* If PHY_DETECT is zero, then we are not in auto-media mode */
665 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
666 return 0xf;
667
668 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
669 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
670 if (err)
671 return err;
672
673 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
674 if (err)
675 return err;
676
677 /* Restore PHY_DETECT value */
678 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
679 if (err)
680 return err;
681
682 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
683 }
684
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)685 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
686 struct phylink_config *config)
687 {
688 unsigned long *supported = config->supported_interfaces;
689 int err, cmode;
690
691 /* Translate the default cmode */
692 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
693
694 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
695 MAC_1000FD;
696
697 /* Port 4 supports automedia if the serdes is associated with it. */
698 if (port == 4) {
699 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
700 if (err < 0)
701 dev_err(chip->dev, "p%d: failed to read scratch\n",
702 port);
703 if (err <= 0)
704 return;
705
706 cmode = mv88e6352_get_port4_serdes_cmode(chip);
707 if (cmode < 0)
708 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
709 port);
710 else
711 mv88e6xxx_translate_cmode(cmode, supported);
712 }
713 }
714
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)715 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
716 struct phylink_config *config)
717 {
718 unsigned long *supported = config->supported_interfaces;
719
720 /* Translate the default cmode */
721 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
722
723 /* No ethtool bits for 200Mbps */
724 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
725 MAC_1000FD;
726
727 /* The C_Mode field is programmable on port 5 */
728 if (port == 5) {
729 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
730 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
731 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
732
733 config->mac_capabilities |= MAC_2500FD;
734 }
735 }
736
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)737 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
738 struct phylink_config *config)
739 {
740 unsigned long *supported = config->supported_interfaces;
741
742 /* Translate the default cmode */
743 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
744
745 /* No ethtool bits for 200Mbps */
746 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
747 MAC_1000FD;
748
749 /* The C_Mode field is programmable on ports 9 and 10 */
750 if (port == 9 || port == 10) {
751 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
752 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
753 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
754
755 config->mac_capabilities |= MAC_2500FD;
756 }
757 }
758
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)759 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
760 struct phylink_config *config)
761 {
762 unsigned long *supported = config->supported_interfaces;
763
764 mv88e6390_phylink_get_caps(chip, port, config);
765
766 /* For the 6x90X, ports 2-7 can be in automedia mode.
767 * (Note that 6x90 doesn't support RXAUI nor XAUI).
768 *
769 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
770 * configured for 1000BASE-X, SGMII or 2500BASE-X.
771 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
772 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
773 *
774 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
775 * configured for 1000BASE-X, SGMII or 2500BASE-X.
776 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
777 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
778 *
779 * For now, be permissive (as the old code was) and allow 1000BASE-X
780 * on ports 2..7.
781 */
782 if (port >= 2 && port <= 7)
783 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
784
785 /* The C_Mode field can also be programmed for 10G speeds */
786 if (port == 9 || port == 10) {
787 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
788 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
789
790 config->mac_capabilities |= MAC_10000FD;
791 }
792 }
793
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)794 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
795 struct phylink_config *config)
796 {
797 unsigned long *supported = config->supported_interfaces;
798 bool is_6191x =
799 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
800
801 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
802
803 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
804 MAC_1000FD;
805
806 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
807 if (port == 0 || port == 9 || port == 10) {
808 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
809 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
810
811 /* 6191X supports >1G modes only on port 10 */
812 if (!is_6191x || port == 10) {
813 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
814 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
815 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
816 /* FIXME: USXGMII is not supported yet */
817 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
818
819 config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
820 MAC_10000FD;
821 }
822 }
823
824 if (port == 0) {
825 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
826 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
827 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
828 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
829 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
830 }
831 }
832
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)833 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
834 struct phylink_config *config)
835 {
836 struct mv88e6xxx_chip *chip = ds->priv;
837
838 mv88e6xxx_reg_lock(chip);
839 chip->info->ops->phylink_get_caps(chip, port, config);
840 mv88e6xxx_reg_unlock(chip);
841
842 if (mv88e6xxx_phy_is_internal(ds, port)) {
843 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
844 config->supported_interfaces);
845 /* Internal ports with no phy-mode need GMII for PHYLIB */
846 __set_bit(PHY_INTERFACE_MODE_GMII,
847 config->supported_interfaces);
848 }
849 }
850
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)851 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
852 unsigned int mode,
853 const struct phylink_link_state *state)
854 {
855 struct mv88e6xxx_chip *chip = ds->priv;
856 struct mv88e6xxx_port *p;
857 int err = 0;
858
859 p = &chip->ports[port];
860
861 mv88e6xxx_reg_lock(chip);
862
863 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
864 /* In inband mode, the link may come up at any time while the
865 * link is not forced down. Force the link down while we
866 * reconfigure the interface mode.
867 */
868 if (mode == MLO_AN_INBAND &&
869 p->interface != state->interface &&
870 chip->info->ops->port_set_link)
871 chip->info->ops->port_set_link(chip, port,
872 LINK_FORCED_DOWN);
873
874 err = mv88e6xxx_port_config_interface(chip, port,
875 state->interface);
876 if (err && err != -EOPNOTSUPP)
877 goto err_unlock;
878
879 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
880 state->interface,
881 state->advertising);
882 /* FIXME: we should restart negotiation if something changed -
883 * which is something we get if we convert to using phylinks
884 * PCS operations.
885 */
886 if (err > 0)
887 err = 0;
888 }
889
890 /* Undo the forced down state above after completing configuration
891 * irrespective of its state on entry, which allows the link to come
892 * up in the in-band case where there is no separate SERDES. Also
893 * ensure that the link can come up if the PPU is in use and we are
894 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
895 */
896 if (chip->info->ops->port_set_link &&
897 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
898 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
899 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
900
901 p->interface = state->interface;
902
903 err_unlock:
904 mv88e6xxx_reg_unlock(chip);
905
906 if (err && err != -EOPNOTSUPP)
907 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
908 }
909
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)910 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
911 unsigned int mode,
912 phy_interface_t interface)
913 {
914 struct mv88e6xxx_chip *chip = ds->priv;
915 const struct mv88e6xxx_ops *ops;
916 int err = 0;
917
918 ops = chip->info->ops;
919
920 mv88e6xxx_reg_lock(chip);
921 /* Force the link down if we know the port may not be automatically
922 * updated by the switch or if we are using fixed-link mode.
923 */
924 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
925 mode == MLO_AN_FIXED) && ops->port_sync_link)
926 err = ops->port_sync_link(chip, port, mode, false);
927
928 if (!err && ops->port_set_speed_duplex)
929 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
930 DUPLEX_UNFORCED);
931 mv88e6xxx_reg_unlock(chip);
932
933 if (err)
934 dev_err(chip->dev,
935 "p%d: failed to force MAC link down\n", port);
936 }
937
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)938 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
939 unsigned int mode, phy_interface_t interface,
940 struct phy_device *phydev,
941 int speed, int duplex,
942 bool tx_pause, bool rx_pause)
943 {
944 struct mv88e6xxx_chip *chip = ds->priv;
945 const struct mv88e6xxx_ops *ops;
946 int err = 0;
947
948 ops = chip->info->ops;
949
950 mv88e6xxx_reg_lock(chip);
951 /* Configure and force the link up if we know that the port may not
952 * automatically updated by the switch or if we are using fixed-link
953 * mode.
954 */
955 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
956 mode == MLO_AN_FIXED) {
957 /* FIXME: for an automedia port, should we force the link
958 * down here - what if the link comes up due to "other" media
959 * while we're bringing the port up, how is the exclusivity
960 * handled in the Marvell hardware? E.g. port 2 on 88E6390
961 * shared between internal PHY and Serdes.
962 */
963 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
964 duplex);
965 if (err)
966 goto error;
967
968 if (ops->port_set_speed_duplex) {
969 err = ops->port_set_speed_duplex(chip, port,
970 speed, duplex);
971 if (err && err != -EOPNOTSUPP)
972 goto error;
973 }
974
975 if (ops->port_sync_link)
976 err = ops->port_sync_link(chip, port, mode, true);
977 }
978 error:
979 mv88e6xxx_reg_unlock(chip);
980
981 if (err && err != -EOPNOTSUPP)
982 dev_err(ds->dev,
983 "p%d: failed to configure MAC link up\n", port);
984 }
985
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)986 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
987 {
988 if (!chip->info->ops->stats_snapshot)
989 return -EOPNOTSUPP;
990
991 return chip->info->ops->stats_snapshot(chip, port);
992 }
993
994 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
995 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
996 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
997 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
998 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
999 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
1000 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
1001 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
1002 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
1003 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
1004 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
1005 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
1006 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1007 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1008 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1009 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1010 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1011 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1012 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1013 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1014 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1015 { "single", 4, 0x14, STATS_TYPE_BANK0, },
1016 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1017 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1018 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1019 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1020 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1021 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1022 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1023 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1024 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1025 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1026 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1027 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1028 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1029 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1030 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1031 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1032 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1033 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1034 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1035 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1036 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1037 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1038 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1039 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1040 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1041 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1042 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1043 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1044 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1045 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1046 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1047 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1048 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1049 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1050 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1051 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1052 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1053 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1054 };
1055
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1056 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1057 struct mv88e6xxx_hw_stat *s,
1058 int port, u16 bank1_select,
1059 u16 histogram)
1060 {
1061 u32 low;
1062 u32 high = 0;
1063 u16 reg = 0;
1064 int err;
1065 u64 value;
1066
1067 switch (s->type) {
1068 case STATS_TYPE_PORT:
1069 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1070 if (err)
1071 return U64_MAX;
1072
1073 low = reg;
1074 if (s->size == 4) {
1075 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1076 if (err)
1077 return U64_MAX;
1078 low |= ((u32)reg) << 16;
1079 }
1080 break;
1081 case STATS_TYPE_BANK1:
1082 reg = bank1_select;
1083 fallthrough;
1084 case STATS_TYPE_BANK0:
1085 reg |= s->reg | histogram;
1086 mv88e6xxx_g1_stats_read(chip, reg, &low);
1087 if (s->size == 8)
1088 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1089 break;
1090 default:
1091 return U64_MAX;
1092 }
1093 value = (((u64)high) << 32) | low;
1094 return value;
1095 }
1096
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)1097 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1098 uint8_t *data, int types)
1099 {
1100 struct mv88e6xxx_hw_stat *stat;
1101 int i, j;
1102
1103 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1104 stat = &mv88e6xxx_hw_stats[i];
1105 if (stat->type & types) {
1106 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1107 ETH_GSTRING_LEN);
1108 j++;
1109 }
1110 }
1111
1112 return j;
1113 }
1114
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1115 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1116 uint8_t *data)
1117 {
1118 return mv88e6xxx_stats_get_strings(chip, data,
1119 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1120 }
1121
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1122 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1123 uint8_t *data)
1124 {
1125 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1126 }
1127
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1128 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1129 uint8_t *data)
1130 {
1131 return mv88e6xxx_stats_get_strings(chip, data,
1132 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1133 }
1134
1135 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1136 "atu_member_violation",
1137 "atu_miss_violation",
1138 "atu_full_violation",
1139 "vtu_member_violation",
1140 "vtu_miss_violation",
1141 };
1142
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)1143 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1144 {
1145 unsigned int i;
1146
1147 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1148 strscpy(data + i * ETH_GSTRING_LEN,
1149 mv88e6xxx_atu_vtu_stats_strings[i],
1150 ETH_GSTRING_LEN);
1151 }
1152
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1153 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1154 u32 stringset, uint8_t *data)
1155 {
1156 struct mv88e6xxx_chip *chip = ds->priv;
1157 int count = 0;
1158
1159 if (stringset != ETH_SS_STATS)
1160 return;
1161
1162 mv88e6xxx_reg_lock(chip);
1163
1164 if (chip->info->ops->stats_get_strings)
1165 count = chip->info->ops->stats_get_strings(chip, data);
1166
1167 if (chip->info->ops->serdes_get_strings) {
1168 data += count * ETH_GSTRING_LEN;
1169 count = chip->info->ops->serdes_get_strings(chip, port, data);
1170 }
1171
1172 data += count * ETH_GSTRING_LEN;
1173 mv88e6xxx_atu_vtu_get_strings(data);
1174
1175 mv88e6xxx_reg_unlock(chip);
1176 }
1177
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1178 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1179 int types)
1180 {
1181 struct mv88e6xxx_hw_stat *stat;
1182 int i, j;
1183
1184 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1185 stat = &mv88e6xxx_hw_stats[i];
1186 if (stat->type & types)
1187 j++;
1188 }
1189 return j;
1190 }
1191
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1192 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1193 {
1194 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1195 STATS_TYPE_PORT);
1196 }
1197
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1198 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1199 {
1200 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1201 }
1202
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1203 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1204 {
1205 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1206 STATS_TYPE_BANK1);
1207 }
1208
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1209 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1210 {
1211 struct mv88e6xxx_chip *chip = ds->priv;
1212 int serdes_count = 0;
1213 int count = 0;
1214
1215 if (sset != ETH_SS_STATS)
1216 return 0;
1217
1218 mv88e6xxx_reg_lock(chip);
1219 if (chip->info->ops->stats_get_sset_count)
1220 count = chip->info->ops->stats_get_sset_count(chip);
1221 if (count < 0)
1222 goto out;
1223
1224 if (chip->info->ops->serdes_get_sset_count)
1225 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1226 port);
1227 if (serdes_count < 0) {
1228 count = serdes_count;
1229 goto out;
1230 }
1231 count += serdes_count;
1232 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1233
1234 out:
1235 mv88e6xxx_reg_unlock(chip);
1236
1237 return count;
1238 }
1239
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1240 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1241 uint64_t *data, int types,
1242 u16 bank1_select, u16 histogram)
1243 {
1244 struct mv88e6xxx_hw_stat *stat;
1245 int i, j;
1246
1247 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1248 stat = &mv88e6xxx_hw_stats[i];
1249 if (stat->type & types) {
1250 mv88e6xxx_reg_lock(chip);
1251 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1252 bank1_select,
1253 histogram);
1254 mv88e6xxx_reg_unlock(chip);
1255
1256 j++;
1257 }
1258 }
1259 return j;
1260 }
1261
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1262 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1263 uint64_t *data)
1264 {
1265 return mv88e6xxx_stats_get_stats(chip, port, data,
1266 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1267 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1268 }
1269
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1270 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1271 uint64_t *data)
1272 {
1273 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1274 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1275 }
1276
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1277 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1278 uint64_t *data)
1279 {
1280 return mv88e6xxx_stats_get_stats(chip, port, data,
1281 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1282 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1283 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1284 }
1285
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1286 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1287 uint64_t *data)
1288 {
1289 return mv88e6xxx_stats_get_stats(chip, port, data,
1290 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1291 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1292 0);
1293 }
1294
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1295 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1296 uint64_t *data)
1297 {
1298 *data++ = chip->ports[port].atu_member_violation;
1299 *data++ = chip->ports[port].atu_miss_violation;
1300 *data++ = chip->ports[port].atu_full_violation;
1301 *data++ = chip->ports[port].vtu_member_violation;
1302 *data++ = chip->ports[port].vtu_miss_violation;
1303 }
1304
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1305 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1306 uint64_t *data)
1307 {
1308 int count = 0;
1309
1310 if (chip->info->ops->stats_get_stats)
1311 count = chip->info->ops->stats_get_stats(chip, port, data);
1312
1313 mv88e6xxx_reg_lock(chip);
1314 if (chip->info->ops->serdes_get_stats) {
1315 data += count;
1316 count = chip->info->ops->serdes_get_stats(chip, port, data);
1317 }
1318 data += count;
1319 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1320 mv88e6xxx_reg_unlock(chip);
1321 }
1322
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1323 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1324 uint64_t *data)
1325 {
1326 struct mv88e6xxx_chip *chip = ds->priv;
1327 int ret;
1328
1329 mv88e6xxx_reg_lock(chip);
1330
1331 ret = mv88e6xxx_stats_snapshot(chip, port);
1332 mv88e6xxx_reg_unlock(chip);
1333
1334 if (ret < 0)
1335 return;
1336
1337 mv88e6xxx_get_stats(chip, port, data);
1338
1339 }
1340
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1341 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1342 {
1343 struct mv88e6xxx_chip *chip = ds->priv;
1344 int len;
1345
1346 len = 32 * sizeof(u16);
1347 if (chip->info->ops->serdes_get_regs_len)
1348 len += chip->info->ops->serdes_get_regs_len(chip, port);
1349
1350 return len;
1351 }
1352
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1353 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1354 struct ethtool_regs *regs, void *_p)
1355 {
1356 struct mv88e6xxx_chip *chip = ds->priv;
1357 int err;
1358 u16 reg;
1359 u16 *p = _p;
1360 int i;
1361
1362 regs->version = chip->info->prod_num;
1363
1364 memset(p, 0xff, 32 * sizeof(u16));
1365
1366 mv88e6xxx_reg_lock(chip);
1367
1368 for (i = 0; i < 32; i++) {
1369
1370 err = mv88e6xxx_port_read(chip, port, i, ®);
1371 if (!err)
1372 p[i] = reg;
1373 }
1374
1375 if (chip->info->ops->serdes_get_regs)
1376 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1377
1378 mv88e6xxx_reg_unlock(chip);
1379 }
1380
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1381 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1382 struct ethtool_eee *e)
1383 {
1384 /* Nothing to do on the port's MAC */
1385 return 0;
1386 }
1387
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1388 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1389 struct ethtool_eee *e)
1390 {
1391 /* Nothing to do on the port's MAC */
1392 return 0;
1393 }
1394
1395 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1396 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1397 {
1398 struct dsa_switch *ds = chip->ds;
1399 struct dsa_switch_tree *dst = ds->dst;
1400 struct dsa_port *dp, *other_dp;
1401 bool found = false;
1402 u16 pvlan;
1403
1404 /* dev is a physical switch */
1405 if (dev <= dst->last_switch) {
1406 list_for_each_entry(dp, &dst->ports, list) {
1407 if (dp->ds->index == dev && dp->index == port) {
1408 /* dp might be a DSA link or a user port, so it
1409 * might or might not have a bridge.
1410 * Use the "found" variable for both cases.
1411 */
1412 found = true;
1413 break;
1414 }
1415 }
1416 /* dev is a virtual bridge */
1417 } else {
1418 list_for_each_entry(dp, &dst->ports, list) {
1419 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1420
1421 if (!bridge_num)
1422 continue;
1423
1424 if (bridge_num + dst->last_switch != dev)
1425 continue;
1426
1427 found = true;
1428 break;
1429 }
1430 }
1431
1432 /* Prevent frames from unknown switch or virtual bridge */
1433 if (!found)
1434 return 0;
1435
1436 /* Frames from DSA links and CPU ports can egress any local port */
1437 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1438 return mv88e6xxx_port_mask(chip);
1439
1440 pvlan = 0;
1441
1442 /* Frames from standalone user ports can only egress on the
1443 * upstream port.
1444 */
1445 if (!dsa_port_bridge_dev_get(dp))
1446 return BIT(dsa_switch_upstream_port(ds));
1447
1448 /* Frames from bridged user ports can egress any local DSA
1449 * links and CPU ports, as well as any local member of their
1450 * bridge group.
1451 */
1452 dsa_switch_for_each_port(other_dp, ds)
1453 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1454 other_dp->type == DSA_PORT_TYPE_DSA ||
1455 dsa_port_bridge_same(dp, other_dp))
1456 pvlan |= BIT(other_dp->index);
1457
1458 return pvlan;
1459 }
1460
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1461 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1462 {
1463 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1464
1465 /* prevent frames from going back out of the port they came in on */
1466 output_ports &= ~BIT(port);
1467
1468 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1469 }
1470
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1471 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1472 u8 state)
1473 {
1474 struct mv88e6xxx_chip *chip = ds->priv;
1475 int err;
1476
1477 mv88e6xxx_reg_lock(chip);
1478 err = mv88e6xxx_port_set_state(chip, port, state);
1479 mv88e6xxx_reg_unlock(chip);
1480
1481 if (err)
1482 dev_err(ds->dev, "p%d: failed to update state\n", port);
1483 }
1484
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1485 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1486 {
1487 int err;
1488
1489 if (chip->info->ops->ieee_pri_map) {
1490 err = chip->info->ops->ieee_pri_map(chip);
1491 if (err)
1492 return err;
1493 }
1494
1495 if (chip->info->ops->ip_pri_map) {
1496 err = chip->info->ops->ip_pri_map(chip);
1497 if (err)
1498 return err;
1499 }
1500
1501 return 0;
1502 }
1503
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1504 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1505 {
1506 struct dsa_switch *ds = chip->ds;
1507 int target, port;
1508 int err;
1509
1510 if (!chip->info->global2_addr)
1511 return 0;
1512
1513 /* Initialize the routing port to the 32 possible target devices */
1514 for (target = 0; target < 32; target++) {
1515 port = dsa_routing_port(ds, target);
1516 if (port == ds->num_ports)
1517 port = 0x1f;
1518
1519 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1520 if (err)
1521 return err;
1522 }
1523
1524 if (chip->info->ops->set_cascade_port) {
1525 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1526 err = chip->info->ops->set_cascade_port(chip, port);
1527 if (err)
1528 return err;
1529 }
1530
1531 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1532 if (err)
1533 return err;
1534
1535 return 0;
1536 }
1537
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1538 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1539 {
1540 /* Clear all trunk masks and mapping */
1541 if (chip->info->global2_addr)
1542 return mv88e6xxx_g2_trunk_clear(chip);
1543
1544 return 0;
1545 }
1546
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1547 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1548 {
1549 if (chip->info->ops->rmu_disable)
1550 return chip->info->ops->rmu_disable(chip);
1551
1552 return 0;
1553 }
1554
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1555 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1556 {
1557 if (chip->info->ops->pot_clear)
1558 return chip->info->ops->pot_clear(chip);
1559
1560 return 0;
1561 }
1562
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1563 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1564 {
1565 if (chip->info->ops->mgmt_rsvd2cpu)
1566 return chip->info->ops->mgmt_rsvd2cpu(chip);
1567
1568 return 0;
1569 }
1570
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1571 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1572 {
1573 int err;
1574
1575 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1576 if (err)
1577 return err;
1578
1579 /* The chips that have a "learn2all" bit in Global1, ATU
1580 * Control are precisely those whose port registers have a
1581 * Message Port bit in Port Control 1 and hence implement
1582 * ->port_setup_message_port.
1583 */
1584 if (chip->info->ops->port_setup_message_port) {
1585 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1586 if (err)
1587 return err;
1588 }
1589
1590 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1591 }
1592
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1593 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1594 {
1595 int port;
1596 int err;
1597
1598 if (!chip->info->ops->irl_init_all)
1599 return 0;
1600
1601 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1602 /* Disable ingress rate limiting by resetting all per port
1603 * ingress rate limit resources to their initial state.
1604 */
1605 err = chip->info->ops->irl_init_all(chip, port);
1606 if (err)
1607 return err;
1608 }
1609
1610 return 0;
1611 }
1612
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1613 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1614 {
1615 if (chip->info->ops->set_switch_mac) {
1616 u8 addr[ETH_ALEN];
1617
1618 eth_random_addr(addr);
1619
1620 return chip->info->ops->set_switch_mac(chip, addr);
1621 }
1622
1623 return 0;
1624 }
1625
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1626 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1627 {
1628 struct dsa_switch_tree *dst = chip->ds->dst;
1629 struct dsa_switch *ds;
1630 struct dsa_port *dp;
1631 u16 pvlan = 0;
1632
1633 if (!mv88e6xxx_has_pvt(chip))
1634 return 0;
1635
1636 /* Skip the local source device, which uses in-chip port VLAN */
1637 if (dev != chip->ds->index) {
1638 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1639
1640 ds = dsa_switch_find(dst->index, dev);
1641 dp = ds ? dsa_to_port(ds, port) : NULL;
1642 if (dp && dp->lag) {
1643 /* As the PVT is used to limit flooding of
1644 * FORWARD frames, which use the LAG ID as the
1645 * source port, we must translate dev/port to
1646 * the special "LAG device" in the PVT, using
1647 * the LAG ID (one-based) as the port number
1648 * (zero-based).
1649 */
1650 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1651 port = dsa_port_lag_id_get(dp) - 1;
1652 }
1653 }
1654
1655 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1656 }
1657
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1658 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1659 {
1660 int dev, port;
1661 int err;
1662
1663 if (!mv88e6xxx_has_pvt(chip))
1664 return 0;
1665
1666 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1667 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1668 */
1669 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1670 if (err)
1671 return err;
1672
1673 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1674 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1675 err = mv88e6xxx_pvt_map(chip, dev, port);
1676 if (err)
1677 return err;
1678 }
1679 }
1680
1681 return 0;
1682 }
1683
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1684 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1685 u16 fid)
1686 {
1687 if (dsa_to_port(chip->ds, port)->lag)
1688 /* Hardware is incapable of fast-aging a LAG through a
1689 * regular ATU move operation. Until we have something
1690 * more fancy in place this is a no-op.
1691 */
1692 return -EOPNOTSUPP;
1693
1694 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1695 }
1696
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1697 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1698 {
1699 struct mv88e6xxx_chip *chip = ds->priv;
1700 int err;
1701
1702 mv88e6xxx_reg_lock(chip);
1703 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1704 mv88e6xxx_reg_unlock(chip);
1705
1706 if (err)
1707 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1708 port, err);
1709 }
1710
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1711 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1712 {
1713 if (!mv88e6xxx_max_vid(chip))
1714 return 0;
1715
1716 return mv88e6xxx_g1_vtu_flush(chip);
1717 }
1718
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1719 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1720 struct mv88e6xxx_vtu_entry *entry)
1721 {
1722 int err;
1723
1724 if (!chip->info->ops->vtu_getnext)
1725 return -EOPNOTSUPP;
1726
1727 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1728 entry->valid = false;
1729
1730 err = chip->info->ops->vtu_getnext(chip, entry);
1731
1732 if (entry->vid != vid)
1733 entry->valid = false;
1734
1735 return err;
1736 }
1737
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1738 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1739 int (*cb)(struct mv88e6xxx_chip *chip,
1740 const struct mv88e6xxx_vtu_entry *entry,
1741 void *priv),
1742 void *priv)
1743 {
1744 struct mv88e6xxx_vtu_entry entry = {
1745 .vid = mv88e6xxx_max_vid(chip),
1746 .valid = false,
1747 };
1748 int err;
1749
1750 if (!chip->info->ops->vtu_getnext)
1751 return -EOPNOTSUPP;
1752
1753 do {
1754 err = chip->info->ops->vtu_getnext(chip, &entry);
1755 if (err)
1756 return err;
1757
1758 if (!entry.valid)
1759 break;
1760
1761 err = cb(chip, &entry, priv);
1762 if (err)
1763 return err;
1764 } while (entry.vid < mv88e6xxx_max_vid(chip));
1765
1766 return 0;
1767 }
1768
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1769 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1770 struct mv88e6xxx_vtu_entry *entry)
1771 {
1772 if (!chip->info->ops->vtu_loadpurge)
1773 return -EOPNOTSUPP;
1774
1775 return chip->info->ops->vtu_loadpurge(chip, entry);
1776 }
1777
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1778 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1779 const struct mv88e6xxx_vtu_entry *entry,
1780 void *_fid_bitmap)
1781 {
1782 unsigned long *fid_bitmap = _fid_bitmap;
1783
1784 set_bit(entry->fid, fid_bitmap);
1785 return 0;
1786 }
1787
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1788 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1789 {
1790 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1791
1792 /* Every FID has an associated VID, so walking the VTU
1793 * will discover the full set of FIDs in use.
1794 */
1795 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1796 }
1797
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1798 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1799 {
1800 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1801 int err;
1802
1803 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1804 if (err)
1805 return err;
1806
1807 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1808 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1809 return -ENOSPC;
1810
1811 /* Clear the database */
1812 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1813 }
1814
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)1815 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1816 struct mv88e6xxx_stu_entry *entry)
1817 {
1818 if (!chip->info->ops->stu_loadpurge)
1819 return -EOPNOTSUPP;
1820
1821 return chip->info->ops->stu_loadpurge(chip, entry);
1822 }
1823
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)1824 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1825 {
1826 struct mv88e6xxx_stu_entry stu = {
1827 .valid = true,
1828 .sid = 0
1829 };
1830
1831 if (!mv88e6xxx_has_stu(chip))
1832 return 0;
1833
1834 /* Make sure that SID 0 is always valid. This is used by VTU
1835 * entries that do not make use of the STU, e.g. when creating
1836 * a VLAN upper on a port that is also part of a VLAN
1837 * filtering bridge.
1838 */
1839 return mv88e6xxx_stu_loadpurge(chip, &stu);
1840 }
1841
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1842 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1843 {
1844 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1845 struct mv88e6xxx_mst *mst;
1846
1847 __set_bit(0, busy);
1848
1849 list_for_each_entry(mst, &chip->msts, node)
1850 __set_bit(mst->stu.sid, busy);
1851
1852 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1853
1854 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1855 }
1856
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)1857 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1858 {
1859 struct mv88e6xxx_mst *mst, *tmp;
1860 int err;
1861
1862 if (!sid)
1863 return 0;
1864
1865 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1866 if (mst->stu.sid != sid)
1867 continue;
1868
1869 if (!refcount_dec_and_test(&mst->refcnt))
1870 return 0;
1871
1872 mst->stu.valid = false;
1873 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1874 if (err) {
1875 refcount_set(&mst->refcnt, 1);
1876 return err;
1877 }
1878
1879 list_del(&mst->node);
1880 kfree(mst);
1881 return 0;
1882 }
1883
1884 return -ENOENT;
1885 }
1886
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)1887 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1888 u16 msti, u8 *sid)
1889 {
1890 struct mv88e6xxx_mst *mst;
1891 int err, i;
1892
1893 if (!mv88e6xxx_has_stu(chip)) {
1894 err = -EOPNOTSUPP;
1895 goto err;
1896 }
1897
1898 if (!msti) {
1899 *sid = 0;
1900 return 0;
1901 }
1902
1903 list_for_each_entry(mst, &chip->msts, node) {
1904 if (mst->br == br && mst->msti == msti) {
1905 refcount_inc(&mst->refcnt);
1906 *sid = mst->stu.sid;
1907 return 0;
1908 }
1909 }
1910
1911 err = mv88e6xxx_sid_get(chip, sid);
1912 if (err)
1913 goto err;
1914
1915 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1916 if (!mst) {
1917 err = -ENOMEM;
1918 goto err;
1919 }
1920
1921 INIT_LIST_HEAD(&mst->node);
1922 refcount_set(&mst->refcnt, 1);
1923 mst->br = br;
1924 mst->msti = msti;
1925 mst->stu.valid = true;
1926 mst->stu.sid = *sid;
1927
1928 /* The bridge starts out all ports in the disabled state. But
1929 * a STU state of disabled means to go by the port-global
1930 * state. So we set all user port's initial state to blocking,
1931 * to match the bridge's behavior.
1932 */
1933 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1934 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1935 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1936 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1937
1938 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1939 if (err)
1940 goto err_free;
1941
1942 list_add_tail(&mst->node, &chip->msts);
1943 return 0;
1944
1945 err_free:
1946 kfree(mst);
1947 err:
1948 return err;
1949 }
1950
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)1951 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1952 const struct switchdev_mst_state *st)
1953 {
1954 struct dsa_port *dp = dsa_to_port(ds, port);
1955 struct mv88e6xxx_chip *chip = ds->priv;
1956 struct mv88e6xxx_mst *mst;
1957 u8 state;
1958 int err;
1959
1960 if (!mv88e6xxx_has_stu(chip))
1961 return -EOPNOTSUPP;
1962
1963 switch (st->state) {
1964 case BR_STATE_DISABLED:
1965 case BR_STATE_BLOCKING:
1966 case BR_STATE_LISTENING:
1967 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1968 break;
1969 case BR_STATE_LEARNING:
1970 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1971 break;
1972 case BR_STATE_FORWARDING:
1973 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1974 break;
1975 default:
1976 return -EINVAL;
1977 }
1978
1979 list_for_each_entry(mst, &chip->msts, node) {
1980 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1981 mst->msti == st->msti) {
1982 if (mst->stu.state[port] == state)
1983 return 0;
1984
1985 mst->stu.state[port] = state;
1986 mv88e6xxx_reg_lock(chip);
1987 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1988 mv88e6xxx_reg_unlock(chip);
1989 return err;
1990 }
1991 }
1992
1993 return -ENOENT;
1994 }
1995
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)1996 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1997 u16 vid)
1998 {
1999 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2000 struct mv88e6xxx_chip *chip = ds->priv;
2001 struct mv88e6xxx_vtu_entry vlan;
2002 int err;
2003
2004 /* DSA and CPU ports have to be members of multiple vlans */
2005 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2006 return 0;
2007
2008 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2009 if (err)
2010 return err;
2011
2012 if (!vlan.valid)
2013 return 0;
2014
2015 dsa_switch_for_each_user_port(other_dp, ds) {
2016 struct net_device *other_br;
2017
2018 if (vlan.member[other_dp->index] ==
2019 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2020 continue;
2021
2022 if (dsa_port_bridge_same(dp, other_dp))
2023 break; /* same bridge, check next VLAN */
2024
2025 other_br = dsa_port_bridge_dev_get(other_dp);
2026 if (!other_br)
2027 continue;
2028
2029 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2030 port, vlan.vid, other_dp->index, netdev_name(other_br));
2031 return -EOPNOTSUPP;
2032 }
2033
2034 return 0;
2035 }
2036
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)2037 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2038 {
2039 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2040 struct net_device *br = dsa_port_bridge_dev_get(dp);
2041 struct mv88e6xxx_port *p = &chip->ports[port];
2042 u16 pvid = MV88E6XXX_VID_STANDALONE;
2043 bool drop_untagged = false;
2044 int err;
2045
2046 if (br) {
2047 if (br_vlan_enabled(br)) {
2048 pvid = p->bridge_pvid.vid;
2049 drop_untagged = !p->bridge_pvid.valid;
2050 } else {
2051 pvid = MV88E6XXX_VID_BRIDGED;
2052 }
2053 }
2054
2055 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2056 if (err)
2057 return err;
2058
2059 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2060 }
2061
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2062 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2063 bool vlan_filtering,
2064 struct netlink_ext_ack *extack)
2065 {
2066 struct mv88e6xxx_chip *chip = ds->priv;
2067 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2068 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2069 int err;
2070
2071 if (!mv88e6xxx_max_vid(chip))
2072 return -EOPNOTSUPP;
2073
2074 mv88e6xxx_reg_lock(chip);
2075
2076 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2077 if (err)
2078 goto unlock;
2079
2080 err = mv88e6xxx_port_commit_pvid(chip, port);
2081 if (err)
2082 goto unlock;
2083
2084 unlock:
2085 mv88e6xxx_reg_unlock(chip);
2086
2087 return err;
2088 }
2089
2090 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2091 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2092 const struct switchdev_obj_port_vlan *vlan)
2093 {
2094 struct mv88e6xxx_chip *chip = ds->priv;
2095 int err;
2096
2097 if (!mv88e6xxx_max_vid(chip))
2098 return -EOPNOTSUPP;
2099
2100 /* If the requested port doesn't belong to the same bridge as the VLAN
2101 * members, do not support it (yet) and fallback to software VLAN.
2102 */
2103 mv88e6xxx_reg_lock(chip);
2104 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2105 mv88e6xxx_reg_unlock(chip);
2106
2107 return err;
2108 }
2109
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2110 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2111 const unsigned char *addr, u16 vid,
2112 u8 state)
2113 {
2114 struct mv88e6xxx_atu_entry entry;
2115 struct mv88e6xxx_vtu_entry vlan;
2116 u16 fid;
2117 int err;
2118
2119 /* Ports have two private address databases: one for when the port is
2120 * standalone and one for when the port is under a bridge and the
2121 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2122 * address database to remain 100% empty, so we never load an ATU entry
2123 * into a standalone port's database. Therefore, translate the null
2124 * VLAN ID into the port's database used for VLAN-unaware bridging.
2125 */
2126 if (vid == 0) {
2127 fid = MV88E6XXX_FID_BRIDGED;
2128 } else {
2129 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2130 if (err)
2131 return err;
2132
2133 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2134 if (!vlan.valid)
2135 return -EOPNOTSUPP;
2136
2137 fid = vlan.fid;
2138 }
2139
2140 entry.state = 0;
2141 ether_addr_copy(entry.mac, addr);
2142 eth_addr_dec(entry.mac);
2143
2144 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2145 if (err)
2146 return err;
2147
2148 /* Initialize a fresh ATU entry if it isn't found */
2149 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2150 memset(&entry, 0, sizeof(entry));
2151 ether_addr_copy(entry.mac, addr);
2152 }
2153
2154 /* Purge the ATU entry only if no port is using it anymore */
2155 if (!state) {
2156 entry.portvec &= ~BIT(port);
2157 if (!entry.portvec)
2158 entry.state = 0;
2159 } else {
2160 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2161 entry.portvec = BIT(port);
2162 else
2163 entry.portvec |= BIT(port);
2164
2165 entry.state = state;
2166 }
2167
2168 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2169 }
2170
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2171 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2172 const struct mv88e6xxx_policy *policy)
2173 {
2174 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2175 enum mv88e6xxx_policy_action action = policy->action;
2176 const u8 *addr = policy->addr;
2177 u16 vid = policy->vid;
2178 u8 state;
2179 int err;
2180 int id;
2181
2182 if (!chip->info->ops->port_set_policy)
2183 return -EOPNOTSUPP;
2184
2185 switch (mapping) {
2186 case MV88E6XXX_POLICY_MAPPING_DA:
2187 case MV88E6XXX_POLICY_MAPPING_SA:
2188 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2189 state = 0; /* Dissociate the port and address */
2190 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2191 is_multicast_ether_addr(addr))
2192 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2193 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2194 is_unicast_ether_addr(addr))
2195 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2196 else
2197 return -EOPNOTSUPP;
2198
2199 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2200 state);
2201 if (err)
2202 return err;
2203 break;
2204 default:
2205 return -EOPNOTSUPP;
2206 }
2207
2208 /* Skip the port's policy clearing if the mapping is still in use */
2209 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2210 idr_for_each_entry(&chip->policies, policy, id)
2211 if (policy->port == port &&
2212 policy->mapping == mapping &&
2213 policy->action != action)
2214 return 0;
2215
2216 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2217 }
2218
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2219 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2220 struct ethtool_rx_flow_spec *fs)
2221 {
2222 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2223 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2224 enum mv88e6xxx_policy_mapping mapping;
2225 enum mv88e6xxx_policy_action action;
2226 struct mv88e6xxx_policy *policy;
2227 u16 vid = 0;
2228 u8 *addr;
2229 int err;
2230 int id;
2231
2232 if (fs->location != RX_CLS_LOC_ANY)
2233 return -EINVAL;
2234
2235 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2236 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2237 else
2238 return -EOPNOTSUPP;
2239
2240 switch (fs->flow_type & ~FLOW_EXT) {
2241 case ETHER_FLOW:
2242 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2243 is_zero_ether_addr(mac_mask->h_source)) {
2244 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2245 addr = mac_entry->h_dest;
2246 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2247 !is_zero_ether_addr(mac_mask->h_source)) {
2248 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2249 addr = mac_entry->h_source;
2250 } else {
2251 /* Cannot support DA and SA mapping in the same rule */
2252 return -EOPNOTSUPP;
2253 }
2254 break;
2255 default:
2256 return -EOPNOTSUPP;
2257 }
2258
2259 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2260 if (fs->m_ext.vlan_tci != htons(0xffff))
2261 return -EOPNOTSUPP;
2262 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2263 }
2264
2265 idr_for_each_entry(&chip->policies, policy, id) {
2266 if (policy->port == port && policy->mapping == mapping &&
2267 policy->action == action && policy->vid == vid &&
2268 ether_addr_equal(policy->addr, addr))
2269 return -EEXIST;
2270 }
2271
2272 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2273 if (!policy)
2274 return -ENOMEM;
2275
2276 fs->location = 0;
2277 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2278 GFP_KERNEL);
2279 if (err) {
2280 devm_kfree(chip->dev, policy);
2281 return err;
2282 }
2283
2284 memcpy(&policy->fs, fs, sizeof(*fs));
2285 ether_addr_copy(policy->addr, addr);
2286 policy->mapping = mapping;
2287 policy->action = action;
2288 policy->port = port;
2289 policy->vid = vid;
2290
2291 err = mv88e6xxx_policy_apply(chip, port, policy);
2292 if (err) {
2293 idr_remove(&chip->policies, fs->location);
2294 devm_kfree(chip->dev, policy);
2295 return err;
2296 }
2297
2298 return 0;
2299 }
2300
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2301 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2302 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2303 {
2304 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2305 struct mv88e6xxx_chip *chip = ds->priv;
2306 struct mv88e6xxx_policy *policy;
2307 int err;
2308 int id;
2309
2310 mv88e6xxx_reg_lock(chip);
2311
2312 switch (rxnfc->cmd) {
2313 case ETHTOOL_GRXCLSRLCNT:
2314 rxnfc->data = 0;
2315 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2316 rxnfc->rule_cnt = 0;
2317 idr_for_each_entry(&chip->policies, policy, id)
2318 if (policy->port == port)
2319 rxnfc->rule_cnt++;
2320 err = 0;
2321 break;
2322 case ETHTOOL_GRXCLSRULE:
2323 err = -ENOENT;
2324 policy = idr_find(&chip->policies, fs->location);
2325 if (policy) {
2326 memcpy(fs, &policy->fs, sizeof(*fs));
2327 err = 0;
2328 }
2329 break;
2330 case ETHTOOL_GRXCLSRLALL:
2331 rxnfc->data = 0;
2332 rxnfc->rule_cnt = 0;
2333 idr_for_each_entry(&chip->policies, policy, id)
2334 if (policy->port == port)
2335 rule_locs[rxnfc->rule_cnt++] = id;
2336 err = 0;
2337 break;
2338 default:
2339 err = -EOPNOTSUPP;
2340 break;
2341 }
2342
2343 mv88e6xxx_reg_unlock(chip);
2344
2345 return err;
2346 }
2347
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2348 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2349 struct ethtool_rxnfc *rxnfc)
2350 {
2351 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2352 struct mv88e6xxx_chip *chip = ds->priv;
2353 struct mv88e6xxx_policy *policy;
2354 int err;
2355
2356 mv88e6xxx_reg_lock(chip);
2357
2358 switch (rxnfc->cmd) {
2359 case ETHTOOL_SRXCLSRLINS:
2360 err = mv88e6xxx_policy_insert(chip, port, fs);
2361 break;
2362 case ETHTOOL_SRXCLSRLDEL:
2363 err = -ENOENT;
2364 policy = idr_remove(&chip->policies, fs->location);
2365 if (policy) {
2366 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2367 err = mv88e6xxx_policy_apply(chip, port, policy);
2368 devm_kfree(chip->dev, policy);
2369 }
2370 break;
2371 default:
2372 err = -EOPNOTSUPP;
2373 break;
2374 }
2375
2376 mv88e6xxx_reg_unlock(chip);
2377
2378 return err;
2379 }
2380
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2381 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2382 u16 vid)
2383 {
2384 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2385 u8 broadcast[ETH_ALEN];
2386
2387 eth_broadcast_addr(broadcast);
2388
2389 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2390 }
2391
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2392 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2393 {
2394 int port;
2395 int err;
2396
2397 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2398 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2399 struct net_device *brport;
2400
2401 if (dsa_is_unused_port(chip->ds, port))
2402 continue;
2403
2404 brport = dsa_port_to_bridge_port(dp);
2405 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2406 /* Skip bridged user ports where broadcast
2407 * flooding is disabled.
2408 */
2409 continue;
2410
2411 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2412 if (err)
2413 return err;
2414 }
2415
2416 return 0;
2417 }
2418
2419 struct mv88e6xxx_port_broadcast_sync_ctx {
2420 int port;
2421 bool flood;
2422 };
2423
2424 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2425 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2426 const struct mv88e6xxx_vtu_entry *vlan,
2427 void *_ctx)
2428 {
2429 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2430 u8 broadcast[ETH_ALEN];
2431 u8 state;
2432
2433 if (ctx->flood)
2434 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2435 else
2436 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2437
2438 eth_broadcast_addr(broadcast);
2439
2440 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2441 vlan->vid, state);
2442 }
2443
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2444 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2445 bool flood)
2446 {
2447 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2448 .port = port,
2449 .flood = flood,
2450 };
2451 struct mv88e6xxx_vtu_entry vid0 = {
2452 .vid = 0,
2453 };
2454 int err;
2455
2456 /* Update the port's private database... */
2457 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2458 if (err)
2459 return err;
2460
2461 /* ...and the database for all VLANs. */
2462 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2463 &ctx);
2464 }
2465
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2466 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2467 u16 vid, u8 member, bool warn)
2468 {
2469 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2470 struct mv88e6xxx_vtu_entry vlan;
2471 int i, err;
2472
2473 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2474 if (err)
2475 return err;
2476
2477 if (!vlan.valid) {
2478 memset(&vlan, 0, sizeof(vlan));
2479
2480 if (vid == MV88E6XXX_VID_STANDALONE)
2481 vlan.policy = true;
2482
2483 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2484 if (err)
2485 return err;
2486
2487 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2488 if (i == port)
2489 vlan.member[i] = member;
2490 else
2491 vlan.member[i] = non_member;
2492
2493 vlan.vid = vid;
2494 vlan.valid = true;
2495
2496 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2497 if (err)
2498 return err;
2499
2500 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2501 if (err)
2502 return err;
2503 } else if (vlan.member[port] != member) {
2504 vlan.member[port] = member;
2505
2506 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2507 if (err)
2508 return err;
2509 } else if (warn) {
2510 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2511 port, vid);
2512 }
2513
2514 return 0;
2515 }
2516
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2517 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2518 const struct switchdev_obj_port_vlan *vlan,
2519 struct netlink_ext_ack *extack)
2520 {
2521 struct mv88e6xxx_chip *chip = ds->priv;
2522 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2523 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2524 struct mv88e6xxx_port *p = &chip->ports[port];
2525 bool warn;
2526 u8 member;
2527 int err;
2528
2529 if (!vlan->vid)
2530 return 0;
2531
2532 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2533 if (err)
2534 return err;
2535
2536 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2537 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2538 else if (untagged)
2539 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2540 else
2541 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2542
2543 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2544 * and then the CPU port. Do not warn for duplicates for the CPU port.
2545 */
2546 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2547
2548 mv88e6xxx_reg_lock(chip);
2549
2550 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2551 if (err) {
2552 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2553 vlan->vid, untagged ? 'u' : 't');
2554 goto out;
2555 }
2556
2557 if (pvid) {
2558 p->bridge_pvid.vid = vlan->vid;
2559 p->bridge_pvid.valid = true;
2560
2561 err = mv88e6xxx_port_commit_pvid(chip, port);
2562 if (err)
2563 goto out;
2564 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2565 /* The old pvid was reinstalled as a non-pvid VLAN */
2566 p->bridge_pvid.valid = false;
2567
2568 err = mv88e6xxx_port_commit_pvid(chip, port);
2569 if (err)
2570 goto out;
2571 }
2572
2573 out:
2574 mv88e6xxx_reg_unlock(chip);
2575
2576 return err;
2577 }
2578
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2579 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2580 int port, u16 vid)
2581 {
2582 struct mv88e6xxx_vtu_entry vlan;
2583 int i, err;
2584
2585 if (!vid)
2586 return 0;
2587
2588 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2589 if (err)
2590 return err;
2591
2592 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2593 * tell switchdev that this VLAN is likely handled in software.
2594 */
2595 if (!vlan.valid ||
2596 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2597 return -EOPNOTSUPP;
2598
2599 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2600
2601 /* keep the VLAN unless all ports are excluded */
2602 vlan.valid = false;
2603 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2604 if (vlan.member[i] !=
2605 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2606 vlan.valid = true;
2607 break;
2608 }
2609 }
2610
2611 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2612 if (err)
2613 return err;
2614
2615 if (!vlan.valid) {
2616 err = mv88e6xxx_mst_put(chip, vlan.sid);
2617 if (err)
2618 return err;
2619 }
2620
2621 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2622 }
2623
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2624 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2625 const struct switchdev_obj_port_vlan *vlan)
2626 {
2627 struct mv88e6xxx_chip *chip = ds->priv;
2628 struct mv88e6xxx_port *p = &chip->ports[port];
2629 int err = 0;
2630 u16 pvid;
2631
2632 if (!mv88e6xxx_max_vid(chip))
2633 return -EOPNOTSUPP;
2634
2635 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2636 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2637 * switchdev workqueue to ensure that all FDB entries are deleted
2638 * before we remove the VLAN.
2639 */
2640 dsa_flush_workqueue();
2641
2642 mv88e6xxx_reg_lock(chip);
2643
2644 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2645 if (err)
2646 goto unlock;
2647
2648 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2649 if (err)
2650 goto unlock;
2651
2652 if (vlan->vid == pvid) {
2653 p->bridge_pvid.valid = false;
2654
2655 err = mv88e6xxx_port_commit_pvid(chip, port);
2656 if (err)
2657 goto unlock;
2658 }
2659
2660 unlock:
2661 mv88e6xxx_reg_unlock(chip);
2662
2663 return err;
2664 }
2665
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2666 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2667 {
2668 struct mv88e6xxx_chip *chip = ds->priv;
2669 struct mv88e6xxx_vtu_entry vlan;
2670 int err;
2671
2672 mv88e6xxx_reg_lock(chip);
2673
2674 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2675 if (err)
2676 goto unlock;
2677
2678 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2679
2680 unlock:
2681 mv88e6xxx_reg_unlock(chip);
2682
2683 return err;
2684 }
2685
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2686 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2687 struct dsa_bridge bridge,
2688 const struct switchdev_vlan_msti *msti)
2689 {
2690 struct mv88e6xxx_chip *chip = ds->priv;
2691 struct mv88e6xxx_vtu_entry vlan;
2692 u8 old_sid, new_sid;
2693 int err;
2694
2695 if (!mv88e6xxx_has_stu(chip))
2696 return -EOPNOTSUPP;
2697
2698 mv88e6xxx_reg_lock(chip);
2699
2700 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2701 if (err)
2702 goto unlock;
2703
2704 if (!vlan.valid) {
2705 err = -EINVAL;
2706 goto unlock;
2707 }
2708
2709 old_sid = vlan.sid;
2710
2711 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2712 if (err)
2713 goto unlock;
2714
2715 if (new_sid != old_sid) {
2716 vlan.sid = new_sid;
2717
2718 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2719 if (err) {
2720 mv88e6xxx_mst_put(chip, new_sid);
2721 goto unlock;
2722 }
2723 }
2724
2725 err = mv88e6xxx_mst_put(chip, old_sid);
2726
2727 unlock:
2728 mv88e6xxx_reg_unlock(chip);
2729 return err;
2730 }
2731
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2732 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2733 const unsigned char *addr, u16 vid,
2734 struct dsa_db db)
2735 {
2736 struct mv88e6xxx_chip *chip = ds->priv;
2737 int err;
2738
2739 mv88e6xxx_reg_lock(chip);
2740 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2741 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2742 mv88e6xxx_reg_unlock(chip);
2743
2744 return err;
2745 }
2746
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2747 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2748 const unsigned char *addr, u16 vid,
2749 struct dsa_db db)
2750 {
2751 struct mv88e6xxx_chip *chip = ds->priv;
2752 int err;
2753
2754 mv88e6xxx_reg_lock(chip);
2755 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2756 mv88e6xxx_reg_unlock(chip);
2757
2758 return err;
2759 }
2760
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2761 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2762 u16 fid, u16 vid, int port,
2763 dsa_fdb_dump_cb_t *cb, void *data)
2764 {
2765 struct mv88e6xxx_atu_entry addr;
2766 bool is_static;
2767 int err;
2768
2769 addr.state = 0;
2770 eth_broadcast_addr(addr.mac);
2771
2772 do {
2773 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2774 if (err)
2775 return err;
2776
2777 if (!addr.state)
2778 break;
2779
2780 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2781 continue;
2782
2783 if (!is_unicast_ether_addr(addr.mac))
2784 continue;
2785
2786 is_static = (addr.state ==
2787 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2788 err = cb(addr.mac, vid, is_static, data);
2789 if (err)
2790 return err;
2791 } while (!is_broadcast_ether_addr(addr.mac));
2792
2793 return err;
2794 }
2795
2796 struct mv88e6xxx_port_db_dump_vlan_ctx {
2797 int port;
2798 dsa_fdb_dump_cb_t *cb;
2799 void *data;
2800 };
2801
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2802 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2803 const struct mv88e6xxx_vtu_entry *entry,
2804 void *_data)
2805 {
2806 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2807
2808 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2809 ctx->port, ctx->cb, ctx->data);
2810 }
2811
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2812 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2813 dsa_fdb_dump_cb_t *cb, void *data)
2814 {
2815 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2816 .port = port,
2817 .cb = cb,
2818 .data = data,
2819 };
2820 u16 fid;
2821 int err;
2822
2823 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2824 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2825 if (err)
2826 return err;
2827
2828 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2829 if (err)
2830 return err;
2831
2832 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2833 }
2834
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2835 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2836 dsa_fdb_dump_cb_t *cb, void *data)
2837 {
2838 struct mv88e6xxx_chip *chip = ds->priv;
2839 int err;
2840
2841 mv88e6xxx_reg_lock(chip);
2842 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2843 mv88e6xxx_reg_unlock(chip);
2844
2845 return err;
2846 }
2847
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)2848 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2849 struct dsa_bridge bridge)
2850 {
2851 struct dsa_switch *ds = chip->ds;
2852 struct dsa_switch_tree *dst = ds->dst;
2853 struct dsa_port *dp;
2854 int err;
2855
2856 list_for_each_entry(dp, &dst->ports, list) {
2857 if (dsa_port_offloads_bridge(dp, &bridge)) {
2858 if (dp->ds == ds) {
2859 /* This is a local bridge group member,
2860 * remap its Port VLAN Map.
2861 */
2862 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2863 if (err)
2864 return err;
2865 } else {
2866 /* This is an external bridge group member,
2867 * remap its cross-chip Port VLAN Table entry.
2868 */
2869 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2870 dp->index);
2871 if (err)
2872 return err;
2873 }
2874 }
2875 }
2876
2877 return 0;
2878 }
2879
2880 /* Treat the software bridge as a virtual single-port switch behind the
2881 * CPU and map in the PVT. First dst->last_switch elements are taken by
2882 * physical switches, so start from beyond that range.
2883 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)2884 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2885 unsigned int bridge_num)
2886 {
2887 u8 dev = bridge_num + ds->dst->last_switch;
2888 struct mv88e6xxx_chip *chip = ds->priv;
2889
2890 return mv88e6xxx_pvt_map(chip, dev, 0);
2891 }
2892
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2893 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2894 struct dsa_bridge bridge,
2895 bool *tx_fwd_offload,
2896 struct netlink_ext_ack *extack)
2897 {
2898 struct mv88e6xxx_chip *chip = ds->priv;
2899 int err;
2900
2901 mv88e6xxx_reg_lock(chip);
2902
2903 err = mv88e6xxx_bridge_map(chip, bridge);
2904 if (err)
2905 goto unlock;
2906
2907 err = mv88e6xxx_port_set_map_da(chip, port, true);
2908 if (err)
2909 goto unlock;
2910
2911 err = mv88e6xxx_port_commit_pvid(chip, port);
2912 if (err)
2913 goto unlock;
2914
2915 if (mv88e6xxx_has_pvt(chip)) {
2916 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2917 if (err)
2918 goto unlock;
2919
2920 *tx_fwd_offload = true;
2921 }
2922
2923 unlock:
2924 mv88e6xxx_reg_unlock(chip);
2925
2926 return err;
2927 }
2928
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2929 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2930 struct dsa_bridge bridge)
2931 {
2932 struct mv88e6xxx_chip *chip = ds->priv;
2933 int err;
2934
2935 mv88e6xxx_reg_lock(chip);
2936
2937 if (bridge.tx_fwd_offload &&
2938 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2939 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2940
2941 if (mv88e6xxx_bridge_map(chip, bridge) ||
2942 mv88e6xxx_port_vlan_map(chip, port))
2943 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2944
2945 err = mv88e6xxx_port_set_map_da(chip, port, false);
2946 if (err)
2947 dev_err(ds->dev,
2948 "port %d failed to restore map-DA: %pe\n",
2949 port, ERR_PTR(err));
2950
2951 err = mv88e6xxx_port_commit_pvid(chip, port);
2952 if (err)
2953 dev_err(ds->dev,
2954 "port %d failed to restore standalone pvid: %pe\n",
2955 port, ERR_PTR(err));
2956
2957 mv88e6xxx_reg_unlock(chip);
2958 }
2959
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)2960 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2961 int tree_index, int sw_index,
2962 int port, struct dsa_bridge bridge,
2963 struct netlink_ext_ack *extack)
2964 {
2965 struct mv88e6xxx_chip *chip = ds->priv;
2966 int err;
2967
2968 if (tree_index != ds->dst->index)
2969 return 0;
2970
2971 mv88e6xxx_reg_lock(chip);
2972 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2973 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2974 mv88e6xxx_reg_unlock(chip);
2975
2976 return err;
2977 }
2978
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)2979 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2980 int tree_index, int sw_index,
2981 int port, struct dsa_bridge bridge)
2982 {
2983 struct mv88e6xxx_chip *chip = ds->priv;
2984
2985 if (tree_index != ds->dst->index)
2986 return;
2987
2988 mv88e6xxx_reg_lock(chip);
2989 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2990 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2991 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2992 mv88e6xxx_reg_unlock(chip);
2993 }
2994
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)2995 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2996 {
2997 if (chip->info->ops->reset)
2998 return chip->info->ops->reset(chip);
2999
3000 return 0;
3001 }
3002
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3003 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3004 {
3005 struct gpio_desc *gpiod = chip->reset;
3006
3007 /* If there is a GPIO connected to the reset pin, toggle it */
3008 if (gpiod) {
3009 /* If the switch has just been reset and not yet completed
3010 * loading EEPROM, the reset may interrupt the I2C transaction
3011 * mid-byte, causing the first EEPROM read after the reset
3012 * from the wrong location resulting in the switch booting
3013 * to wrong mode and inoperable.
3014 */
3015 if (chip->info->ops->get_eeprom)
3016 mv88e6xxx_g2_eeprom_wait(chip);
3017
3018 gpiod_set_value_cansleep(gpiod, 1);
3019 usleep_range(10000, 20000);
3020 gpiod_set_value_cansleep(gpiod, 0);
3021 usleep_range(10000, 20000);
3022
3023 if (chip->info->ops->get_eeprom)
3024 mv88e6xxx_g2_eeprom_wait(chip);
3025 }
3026 }
3027
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)3028 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3029 {
3030 int i, err;
3031
3032 /* Set all ports to the Disabled state */
3033 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3034 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3035 if (err)
3036 return err;
3037 }
3038
3039 /* Wait for transmit queues to drain,
3040 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3041 */
3042 usleep_range(2000, 4000);
3043
3044 return 0;
3045 }
3046
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3047 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3048 {
3049 int err;
3050
3051 err = mv88e6xxx_disable_ports(chip);
3052 if (err)
3053 return err;
3054
3055 mv88e6xxx_hardware_reset(chip);
3056
3057 return mv88e6xxx_software_reset(chip);
3058 }
3059
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)3060 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3061 enum mv88e6xxx_frame_mode frame,
3062 enum mv88e6xxx_egress_mode egress, u16 etype)
3063 {
3064 int err;
3065
3066 if (!chip->info->ops->port_set_frame_mode)
3067 return -EOPNOTSUPP;
3068
3069 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3070 if (err)
3071 return err;
3072
3073 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3074 if (err)
3075 return err;
3076
3077 if (chip->info->ops->port_set_ether_type)
3078 return chip->info->ops->port_set_ether_type(chip, port, etype);
3079
3080 return 0;
3081 }
3082
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)3083 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3084 {
3085 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3086 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3087 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3088 }
3089
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)3090 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3091 {
3092 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3093 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3094 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3095 }
3096
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)3097 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3098 {
3099 return mv88e6xxx_set_port_mode(chip, port,
3100 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3101 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3102 ETH_P_EDSA);
3103 }
3104
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)3105 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3106 {
3107 if (dsa_is_dsa_port(chip->ds, port))
3108 return mv88e6xxx_set_port_mode_dsa(chip, port);
3109
3110 if (dsa_is_user_port(chip->ds, port))
3111 return mv88e6xxx_set_port_mode_normal(chip, port);
3112
3113 /* Setup CPU port mode depending on its supported tag format */
3114 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3115 return mv88e6xxx_set_port_mode_dsa(chip, port);
3116
3117 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3118 return mv88e6xxx_set_port_mode_edsa(chip, port);
3119
3120 return -EINVAL;
3121 }
3122
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3123 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3124 {
3125 bool message = dsa_is_dsa_port(chip->ds, port);
3126
3127 return mv88e6xxx_port_set_message_port(chip, port, message);
3128 }
3129
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3130 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3131 {
3132 int err;
3133
3134 if (chip->info->ops->port_set_ucast_flood) {
3135 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3136 if (err)
3137 return err;
3138 }
3139 if (chip->info->ops->port_set_mcast_flood) {
3140 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3141 if (err)
3142 return err;
3143 }
3144
3145 return 0;
3146 }
3147
mv88e6xxx_serdes_irq_thread_fn(int irq,void * dev_id)3148 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
3149 {
3150 struct mv88e6xxx_port *mvp = dev_id;
3151 struct mv88e6xxx_chip *chip = mvp->chip;
3152 irqreturn_t ret = IRQ_NONE;
3153 int port = mvp->port;
3154 int lane;
3155
3156 mv88e6xxx_reg_lock(chip);
3157 lane = mv88e6xxx_serdes_get_lane(chip, port);
3158 if (lane >= 0)
3159 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
3160 mv88e6xxx_reg_unlock(chip);
3161
3162 return ret;
3163 }
3164
mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip * chip,int port,int lane)3165 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
3166 int lane)
3167 {
3168 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3169 unsigned int irq;
3170 int err;
3171
3172 /* Nothing to request if this SERDES port has no IRQ */
3173 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
3174 if (!irq)
3175 return 0;
3176
3177 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
3178 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
3179
3180 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
3181 mv88e6xxx_reg_unlock(chip);
3182 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
3183 IRQF_ONESHOT, dev_id->serdes_irq_name,
3184 dev_id);
3185 mv88e6xxx_reg_lock(chip);
3186 if (err)
3187 return err;
3188
3189 dev_id->serdes_irq = irq;
3190
3191 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
3192 }
3193
mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip * chip,int port,int lane)3194 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
3195 int lane)
3196 {
3197 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3198 unsigned int irq = dev_id->serdes_irq;
3199 int err;
3200
3201 /* Nothing to free if no IRQ has been requested */
3202 if (!irq)
3203 return 0;
3204
3205 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
3206
3207 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
3208 mv88e6xxx_reg_unlock(chip);
3209 free_irq(irq, dev_id);
3210 mv88e6xxx_reg_lock(chip);
3211
3212 dev_id->serdes_irq = 0;
3213
3214 return err;
3215 }
3216
mv88e6xxx_serdes_power(struct mv88e6xxx_chip * chip,int port,bool on)3217 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
3218 bool on)
3219 {
3220 int lane;
3221 int err;
3222
3223 lane = mv88e6xxx_serdes_get_lane(chip, port);
3224 if (lane < 0)
3225 return 0;
3226
3227 if (on) {
3228 err = mv88e6xxx_serdes_power_up(chip, port, lane);
3229 if (err)
3230 return err;
3231
3232 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
3233 } else {
3234 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
3235 if (err)
3236 return err;
3237
3238 err = mv88e6xxx_serdes_power_down(chip, port, lane);
3239 }
3240
3241 return err;
3242 }
3243
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)3244 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3245 enum mv88e6xxx_egress_direction direction,
3246 int port)
3247 {
3248 int err;
3249
3250 if (!chip->info->ops->set_egress_port)
3251 return -EOPNOTSUPP;
3252
3253 err = chip->info->ops->set_egress_port(chip, direction, port);
3254 if (err)
3255 return err;
3256
3257 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3258 chip->ingress_dest_port = port;
3259 else
3260 chip->egress_dest_port = port;
3261
3262 return 0;
3263 }
3264
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3265 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3266 {
3267 struct dsa_switch *ds = chip->ds;
3268 int upstream_port;
3269 int err;
3270
3271 upstream_port = dsa_upstream_port(ds, port);
3272 if (chip->info->ops->port_set_upstream_port) {
3273 err = chip->info->ops->port_set_upstream_port(chip, port,
3274 upstream_port);
3275 if (err)
3276 return err;
3277 }
3278
3279 if (port == upstream_port) {
3280 if (chip->info->ops->set_cpu_port) {
3281 err = chip->info->ops->set_cpu_port(chip,
3282 upstream_port);
3283 if (err)
3284 return err;
3285 }
3286
3287 err = mv88e6xxx_set_egress_port(chip,
3288 MV88E6XXX_EGRESS_DIR_INGRESS,
3289 upstream_port);
3290 if (err && err != -EOPNOTSUPP)
3291 return err;
3292
3293 err = mv88e6xxx_set_egress_port(chip,
3294 MV88E6XXX_EGRESS_DIR_EGRESS,
3295 upstream_port);
3296 if (err && err != -EOPNOTSUPP)
3297 return err;
3298 }
3299
3300 return 0;
3301 }
3302
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3303 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3304 {
3305 struct device_node *phy_handle = NULL;
3306 struct dsa_switch *ds = chip->ds;
3307 phy_interface_t mode;
3308 struct dsa_port *dp;
3309 int tx_amp, speed;
3310 int err;
3311 u16 reg;
3312
3313 chip->ports[port].chip = chip;
3314 chip->ports[port].port = port;
3315
3316 dp = dsa_to_port(ds, port);
3317
3318 /* MAC Forcing register: don't force link, speed, duplex or flow control
3319 * state to any particular values on physical ports, but force the CPU
3320 * port and all DSA ports to their maximum bandwidth and full duplex.
3321 */
3322 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
3323 struct phylink_config pl_config = {};
3324 unsigned long caps;
3325
3326 chip->info->ops->phylink_get_caps(chip, port, &pl_config);
3327
3328 caps = pl_config.mac_capabilities;
3329
3330 if (chip->info->ops->port_max_speed_mode)
3331 mode = chip->info->ops->port_max_speed_mode(port);
3332 else
3333 mode = PHY_INTERFACE_MODE_NA;
3334
3335 if (caps & MAC_10000FD)
3336 speed = SPEED_10000;
3337 else if (caps & MAC_5000FD)
3338 speed = SPEED_5000;
3339 else if (caps & MAC_2500FD)
3340 speed = SPEED_2500;
3341 else if (caps & MAC_1000)
3342 speed = SPEED_1000;
3343 else if (caps & MAC_100)
3344 speed = SPEED_100;
3345 else
3346 speed = SPEED_10;
3347
3348 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
3349 speed, DUPLEX_FULL,
3350 PAUSE_OFF, mode);
3351 } else {
3352 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3353 SPEED_UNFORCED, DUPLEX_UNFORCED,
3354 PAUSE_ON,
3355 PHY_INTERFACE_MODE_NA);
3356 }
3357 if (err)
3358 return err;
3359
3360 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3361 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3362 * tunneling, determine priority by looking at 802.1p and IP
3363 * priority fields (IP prio has precedence), and set STP state
3364 * to Forwarding.
3365 *
3366 * If this is the CPU link, use DSA or EDSA tagging depending
3367 * on which tagging mode was configured.
3368 *
3369 * If this is a link to another switch, use DSA tagging mode.
3370 *
3371 * If this is the upstream port for this switch, enable
3372 * forwarding of unknown unicasts and multicasts.
3373 */
3374 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3375 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3376 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3377 * by a USER port to the CPU port to allow snooping.
3378 */
3379 if (dsa_is_user_port(ds, port))
3380 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3381
3382 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3383 if (err)
3384 return err;
3385
3386 err = mv88e6xxx_setup_port_mode(chip, port);
3387 if (err)
3388 return err;
3389
3390 err = mv88e6xxx_setup_egress_floods(chip, port);
3391 if (err)
3392 return err;
3393
3394 /* Port Control 2: don't force a good FCS, set the MTU size to
3395 * 10222 bytes, disable 802.1q tags checking, don't discard
3396 * tagged or untagged frames on this port, skip destination
3397 * address lookup on user ports, disable ARP mirroring and don't
3398 * send a copy of all transmitted/received frames on this port
3399 * to the CPU.
3400 */
3401 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3402 if (err)
3403 return err;
3404
3405 err = mv88e6xxx_setup_upstream_port(chip, port);
3406 if (err)
3407 return err;
3408
3409 /* On chips that support it, set all downstream DSA ports'
3410 * VLAN policy to TRAP. In combination with loading
3411 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3412 * provides a better isolation barrier between standalone
3413 * ports, as the ATU is bypassed on any intermediate switches
3414 * between the incoming port and the CPU.
3415 */
3416 if (dsa_is_downstream_port(ds, port) &&
3417 chip->info->ops->port_set_policy) {
3418 err = chip->info->ops->port_set_policy(chip, port,
3419 MV88E6XXX_POLICY_MAPPING_VTU,
3420 MV88E6XXX_POLICY_ACTION_TRAP);
3421 if (err)
3422 return err;
3423 }
3424
3425 /* User ports start out in standalone mode and 802.1Q is
3426 * therefore disabled. On DSA ports, all valid VIDs are always
3427 * loaded in the VTU - therefore, enable 802.1Q in order to take
3428 * advantage of VLAN policy on chips that supports it.
3429 */
3430 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3431 dsa_is_user_port(ds, port) ?
3432 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3433 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3434 if (err)
3435 return err;
3436
3437 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3438 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3439 * the first free FID. This will be used as the private PVID for
3440 * unbridged ports. Shared (DSA and CPU) ports must also be
3441 * members of this VID, in order to trap all frames assigned to
3442 * it to the CPU.
3443 */
3444 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3445 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3446 false);
3447 if (err)
3448 return err;
3449
3450 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3451 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3452 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3453 * as the private PVID on ports under a VLAN-unaware bridge.
3454 * Shared (DSA and CPU) ports must also be members of it, to translate
3455 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3456 * relying on their port default FID.
3457 */
3458 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3459 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3460 false);
3461 if (err)
3462 return err;
3463
3464 if (chip->info->ops->port_set_jumbo_size) {
3465 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3466 if (err)
3467 return err;
3468 }
3469
3470 /* Port Association Vector: disable automatic address learning
3471 * on all user ports since they start out in standalone
3472 * mode. When joining a bridge, learning will be configured to
3473 * match the bridge port settings. Enable learning on all
3474 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3475 * learning process.
3476 *
3477 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3478 * and RefreshLocked. I.e. setup standard automatic learning.
3479 */
3480 if (dsa_is_user_port(ds, port))
3481 reg = 0;
3482 else
3483 reg = 1 << port;
3484
3485 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3486 reg);
3487 if (err)
3488 return err;
3489
3490 /* Egress rate control 2: disable egress rate control. */
3491 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3492 0x0000);
3493 if (err)
3494 return err;
3495
3496 if (chip->info->ops->port_pause_limit) {
3497 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3498 if (err)
3499 return err;
3500 }
3501
3502 if (chip->info->ops->port_disable_learn_limit) {
3503 err = chip->info->ops->port_disable_learn_limit(chip, port);
3504 if (err)
3505 return err;
3506 }
3507
3508 if (chip->info->ops->port_disable_pri_override) {
3509 err = chip->info->ops->port_disable_pri_override(chip, port);
3510 if (err)
3511 return err;
3512 }
3513
3514 if (chip->info->ops->port_tag_remap) {
3515 err = chip->info->ops->port_tag_remap(chip, port);
3516 if (err)
3517 return err;
3518 }
3519
3520 if (chip->info->ops->port_egress_rate_limiting) {
3521 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3522 if (err)
3523 return err;
3524 }
3525
3526 if (chip->info->ops->port_setup_message_port) {
3527 err = chip->info->ops->port_setup_message_port(chip, port);
3528 if (err)
3529 return err;
3530 }
3531
3532 if (chip->info->ops->serdes_set_tx_amplitude) {
3533 if (dp)
3534 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3535
3536 if (phy_handle && !of_property_read_u32(phy_handle,
3537 "tx-p2p-microvolt",
3538 &tx_amp))
3539 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3540 port, tx_amp);
3541 if (phy_handle) {
3542 of_node_put(phy_handle);
3543 if (err)
3544 return err;
3545 }
3546 }
3547
3548 /* Port based VLAN map: give each port the same default address
3549 * database, and allow bidirectional communication between the
3550 * CPU and DSA port(s), and the other ports.
3551 */
3552 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3553 if (err)
3554 return err;
3555
3556 err = mv88e6xxx_port_vlan_map(chip, port);
3557 if (err)
3558 return err;
3559
3560 /* Default VLAN ID and priority: don't set a default VLAN
3561 * ID, and set the default packet priority to zero.
3562 */
3563 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3564 }
3565
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3566 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3567 {
3568 struct mv88e6xxx_chip *chip = ds->priv;
3569
3570 if (chip->info->ops->port_set_jumbo_size)
3571 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3572 else if (chip->info->ops->set_max_frame_size)
3573 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3574 return ETH_DATA_LEN;
3575 }
3576
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3577 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3578 {
3579 struct mv88e6xxx_chip *chip = ds->priv;
3580 int ret = 0;
3581
3582 /* For families where we don't know how to alter the MTU,
3583 * just accept any value up to ETH_DATA_LEN
3584 */
3585 if (!chip->info->ops->port_set_jumbo_size &&
3586 !chip->info->ops->set_max_frame_size) {
3587 if (new_mtu > ETH_DATA_LEN)
3588 return -EINVAL;
3589
3590 return 0;
3591 }
3592
3593 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3594 new_mtu += EDSA_HLEN;
3595
3596 mv88e6xxx_reg_lock(chip);
3597 if (chip->info->ops->port_set_jumbo_size)
3598 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3599 else if (chip->info->ops->set_max_frame_size)
3600 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3601 mv88e6xxx_reg_unlock(chip);
3602
3603 return ret;
3604 }
3605
mv88e6xxx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)3606 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3607 struct phy_device *phydev)
3608 {
3609 struct mv88e6xxx_chip *chip = ds->priv;
3610 int err;
3611
3612 mv88e6xxx_reg_lock(chip);
3613 err = mv88e6xxx_serdes_power(chip, port, true);
3614 mv88e6xxx_reg_unlock(chip);
3615
3616 return err;
3617 }
3618
mv88e6xxx_port_disable(struct dsa_switch * ds,int port)3619 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3620 {
3621 struct mv88e6xxx_chip *chip = ds->priv;
3622
3623 mv88e6xxx_reg_lock(chip);
3624 if (mv88e6xxx_serdes_power(chip, port, false))
3625 dev_err(chip->dev, "failed to power off SERDES\n");
3626 mv88e6xxx_reg_unlock(chip);
3627 }
3628
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3629 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3630 unsigned int ageing_time)
3631 {
3632 struct mv88e6xxx_chip *chip = ds->priv;
3633 int err;
3634
3635 mv88e6xxx_reg_lock(chip);
3636 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3637 mv88e6xxx_reg_unlock(chip);
3638
3639 return err;
3640 }
3641
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3642 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3643 {
3644 int err;
3645
3646 /* Initialize the statistics unit */
3647 if (chip->info->ops->stats_set_histogram) {
3648 err = chip->info->ops->stats_set_histogram(chip);
3649 if (err)
3650 return err;
3651 }
3652
3653 return mv88e6xxx_g1_stats_clear(chip);
3654 }
3655
3656 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3657 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3658 {
3659 int port;
3660 int err;
3661 u16 val;
3662
3663 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3664 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3665 if (err) {
3666 dev_err(chip->dev,
3667 "Error reading hidden register: %d\n", err);
3668 return false;
3669 }
3670 if (val != 0x01c0)
3671 return false;
3672 }
3673
3674 return true;
3675 }
3676
3677 /* The 6390 copper ports have an errata which require poking magic
3678 * values into undocumented hidden registers and then performing a
3679 * software reset.
3680 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3681 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3682 {
3683 int port;
3684 int err;
3685
3686 if (mv88e6390_setup_errata_applied(chip))
3687 return 0;
3688
3689 /* Set the ports into blocking mode */
3690 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3691 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3692 if (err)
3693 return err;
3694 }
3695
3696 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3697 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3698 if (err)
3699 return err;
3700 }
3701
3702 return mv88e6xxx_software_reset(chip);
3703 }
3704
mv88e6xxx_teardown(struct dsa_switch * ds)3705 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3706 {
3707 mv88e6xxx_teardown_devlink_params(ds);
3708 dsa_devlink_resources_unregister(ds);
3709 mv88e6xxx_teardown_devlink_regions_global(ds);
3710 }
3711
mv88e6xxx_setup(struct dsa_switch * ds)3712 static int mv88e6xxx_setup(struct dsa_switch *ds)
3713 {
3714 struct mv88e6xxx_chip *chip = ds->priv;
3715 u8 cmode;
3716 int err;
3717 int i;
3718
3719 chip->ds = ds;
3720 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3721
3722 /* Since virtual bridges are mapped in the PVT, the number we support
3723 * depends on the physical switch topology. We need to let DSA figure
3724 * that out and therefore we cannot set this at dsa_register_switch()
3725 * time.
3726 */
3727 if (mv88e6xxx_has_pvt(chip))
3728 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3729 ds->dst->last_switch - 1;
3730
3731 mv88e6xxx_reg_lock(chip);
3732
3733 if (chip->info->ops->setup_errata) {
3734 err = chip->info->ops->setup_errata(chip);
3735 if (err)
3736 goto unlock;
3737 }
3738
3739 /* Cache the cmode of each port. */
3740 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3741 if (chip->info->ops->port_get_cmode) {
3742 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3743 if (err)
3744 goto unlock;
3745
3746 chip->ports[i].cmode = cmode;
3747 }
3748 }
3749
3750 err = mv88e6xxx_vtu_setup(chip);
3751 if (err)
3752 goto unlock;
3753
3754 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3755 * VTU, thereby also flushing the STU).
3756 */
3757 err = mv88e6xxx_stu_setup(chip);
3758 if (err)
3759 goto unlock;
3760
3761 /* Setup Switch Port Registers */
3762 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3763 if (dsa_is_unused_port(ds, i))
3764 continue;
3765
3766 /* Prevent the use of an invalid port. */
3767 if (mv88e6xxx_is_invalid_port(chip, i)) {
3768 dev_err(chip->dev, "port %d is invalid\n", i);
3769 err = -EINVAL;
3770 goto unlock;
3771 }
3772
3773 err = mv88e6xxx_setup_port(chip, i);
3774 if (err)
3775 goto unlock;
3776 }
3777
3778 err = mv88e6xxx_irl_setup(chip);
3779 if (err)
3780 goto unlock;
3781
3782 err = mv88e6xxx_mac_setup(chip);
3783 if (err)
3784 goto unlock;
3785
3786 err = mv88e6xxx_phy_setup(chip);
3787 if (err)
3788 goto unlock;
3789
3790 err = mv88e6xxx_pvt_setup(chip);
3791 if (err)
3792 goto unlock;
3793
3794 err = mv88e6xxx_atu_setup(chip);
3795 if (err)
3796 goto unlock;
3797
3798 err = mv88e6xxx_broadcast_setup(chip, 0);
3799 if (err)
3800 goto unlock;
3801
3802 err = mv88e6xxx_pot_setup(chip);
3803 if (err)
3804 goto unlock;
3805
3806 err = mv88e6xxx_rmu_setup(chip);
3807 if (err)
3808 goto unlock;
3809
3810 err = mv88e6xxx_rsvd2cpu_setup(chip);
3811 if (err)
3812 goto unlock;
3813
3814 err = mv88e6xxx_trunk_setup(chip);
3815 if (err)
3816 goto unlock;
3817
3818 err = mv88e6xxx_devmap_setup(chip);
3819 if (err)
3820 goto unlock;
3821
3822 err = mv88e6xxx_pri_setup(chip);
3823 if (err)
3824 goto unlock;
3825
3826 /* Setup PTP Hardware Clock and timestamping */
3827 if (chip->info->ptp_support) {
3828 err = mv88e6xxx_ptp_setup(chip);
3829 if (err)
3830 goto unlock;
3831
3832 err = mv88e6xxx_hwtstamp_setup(chip);
3833 if (err)
3834 goto unlock;
3835 }
3836
3837 err = mv88e6xxx_stats_setup(chip);
3838 if (err)
3839 goto unlock;
3840
3841 unlock:
3842 mv88e6xxx_reg_unlock(chip);
3843
3844 if (err)
3845 return err;
3846
3847 /* Have to be called without holding the register lock, since
3848 * they take the devlink lock, and we later take the locks in
3849 * the reverse order when getting/setting parameters or
3850 * resource occupancy.
3851 */
3852 err = mv88e6xxx_setup_devlink_resources(ds);
3853 if (err)
3854 return err;
3855
3856 err = mv88e6xxx_setup_devlink_params(ds);
3857 if (err)
3858 goto out_resources;
3859
3860 err = mv88e6xxx_setup_devlink_regions_global(ds);
3861 if (err)
3862 goto out_params;
3863
3864 return 0;
3865
3866 out_params:
3867 mv88e6xxx_teardown_devlink_params(ds);
3868 out_resources:
3869 dsa_devlink_resources_unregister(ds);
3870
3871 return err;
3872 }
3873
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)3874 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3875 {
3876 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3877 }
3878
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)3879 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3880 {
3881 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3882 }
3883
3884 /* prod_id for switch families which do not have a PHY model number */
3885 static const u16 family_prod_id_table[] = {
3886 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3887 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3888 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3889 };
3890
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3891 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3892 {
3893 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3894 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3895 u16 prod_id;
3896 u16 val;
3897 int err;
3898
3899 if (!chip->info->ops->phy_read)
3900 return -EOPNOTSUPP;
3901
3902 mv88e6xxx_reg_lock(chip);
3903 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3904 mv88e6xxx_reg_unlock(chip);
3905
3906 /* Some internal PHYs don't have a model number. */
3907 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3908 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3909 prod_id = family_prod_id_table[chip->info->family];
3910 if (prod_id)
3911 val |= prod_id >> 4;
3912 }
3913
3914 return err ? err : val;
3915 }
3916
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3917 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3918 {
3919 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3920 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3921 int err;
3922
3923 if (!chip->info->ops->phy_write)
3924 return -EOPNOTSUPP;
3925
3926 mv88e6xxx_reg_lock(chip);
3927 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3928 mv88e6xxx_reg_unlock(chip);
3929
3930 return err;
3931 }
3932
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3933 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3934 struct device_node *np,
3935 bool external)
3936 {
3937 static int index;
3938 struct mv88e6xxx_mdio_bus *mdio_bus;
3939 struct mii_bus *bus;
3940 int err;
3941
3942 if (external) {
3943 mv88e6xxx_reg_lock(chip);
3944 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3945 mv88e6xxx_reg_unlock(chip);
3946
3947 if (err)
3948 return err;
3949 }
3950
3951 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3952 if (!bus)
3953 return -ENOMEM;
3954
3955 mdio_bus = bus->priv;
3956 mdio_bus->bus = bus;
3957 mdio_bus->chip = chip;
3958 INIT_LIST_HEAD(&mdio_bus->list);
3959 mdio_bus->external = external;
3960
3961 if (np) {
3962 bus->name = np->full_name;
3963 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3964 } else {
3965 bus->name = "mv88e6xxx SMI";
3966 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3967 }
3968
3969 bus->read = mv88e6xxx_mdio_read;
3970 bus->write = mv88e6xxx_mdio_write;
3971 bus->parent = chip->dev;
3972
3973 if (!external) {
3974 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3975 if (err)
3976 goto out;
3977 }
3978
3979 err = of_mdiobus_register(bus, np);
3980 if (err) {
3981 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3982 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3983 goto out;
3984 }
3985
3986 if (external)
3987 list_add_tail(&mdio_bus->list, &chip->mdios);
3988 else
3989 list_add(&mdio_bus->list, &chip->mdios);
3990
3991 return 0;
3992
3993 out:
3994 mdiobus_free(bus);
3995 return err;
3996 }
3997
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3998 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3999
4000 {
4001 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
4002 struct mii_bus *bus;
4003
4004 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
4005 bus = mdio_bus->bus;
4006
4007 if (!mdio_bus->external)
4008 mv88e6xxx_g2_irq_mdio_free(chip, bus);
4009
4010 mdiobus_unregister(bus);
4011 mdiobus_free(bus);
4012 }
4013 }
4014
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip,struct device_node * np)4015 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
4016 struct device_node *np)
4017 {
4018 struct device_node *child;
4019 int err;
4020
4021 /* Always register one mdio bus for the internal/default mdio
4022 * bus. This maybe represented in the device tree, but is
4023 * optional.
4024 */
4025 child = of_get_child_by_name(np, "mdio");
4026 err = mv88e6xxx_mdio_register(chip, child, false);
4027 of_node_put(child);
4028 if (err)
4029 return err;
4030
4031 /* Walk the device tree, and see if there are any other nodes
4032 * which say they are compatible with the external mdio
4033 * bus.
4034 */
4035 for_each_available_child_of_node(np, child) {
4036 if (of_device_is_compatible(
4037 child, "marvell,mv88e6xxx-mdio-external")) {
4038 err = mv88e6xxx_mdio_register(chip, child, true);
4039 if (err) {
4040 mv88e6xxx_mdios_unregister(chip);
4041 of_node_put(child);
4042 return err;
4043 }
4044 }
4045 }
4046
4047 return 0;
4048 }
4049
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)4050 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4051 {
4052 struct mv88e6xxx_chip *chip = ds->priv;
4053
4054 return chip->eeprom_len;
4055 }
4056
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4057 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4058 struct ethtool_eeprom *eeprom, u8 *data)
4059 {
4060 struct mv88e6xxx_chip *chip = ds->priv;
4061 int err;
4062
4063 if (!chip->info->ops->get_eeprom)
4064 return -EOPNOTSUPP;
4065
4066 mv88e6xxx_reg_lock(chip);
4067 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4068 mv88e6xxx_reg_unlock(chip);
4069
4070 if (err)
4071 return err;
4072
4073 eeprom->magic = 0xc3ec4951;
4074
4075 return 0;
4076 }
4077
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4078 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4079 struct ethtool_eeprom *eeprom, u8 *data)
4080 {
4081 struct mv88e6xxx_chip *chip = ds->priv;
4082 int err;
4083
4084 if (!chip->info->ops->set_eeprom)
4085 return -EOPNOTSUPP;
4086
4087 if (eeprom->magic != 0xc3ec4951)
4088 return -EINVAL;
4089
4090 mv88e6xxx_reg_lock(chip);
4091 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4092 mv88e6xxx_reg_unlock(chip);
4093
4094 return err;
4095 }
4096
4097 static const struct mv88e6xxx_ops mv88e6085_ops = {
4098 /* MV88E6XXX_FAMILY_6097 */
4099 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4100 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4101 .irl_init_all = mv88e6352_g2_irl_init_all,
4102 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4103 .phy_read = mv88e6185_phy_ppu_read,
4104 .phy_write = mv88e6185_phy_ppu_write,
4105 .port_set_link = mv88e6xxx_port_set_link,
4106 .port_sync_link = mv88e6xxx_port_sync_link,
4107 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4108 .port_tag_remap = mv88e6095_port_tag_remap,
4109 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4110 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4111 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4112 .port_set_ether_type = mv88e6351_port_set_ether_type,
4113 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4114 .port_pause_limit = mv88e6097_port_pause_limit,
4115 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4116 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4117 .port_get_cmode = mv88e6185_port_get_cmode,
4118 .port_setup_message_port = mv88e6xxx_setup_message_port,
4119 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4120 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4121 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4122 .stats_get_strings = mv88e6095_stats_get_strings,
4123 .stats_get_stats = mv88e6095_stats_get_stats,
4124 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4125 .set_egress_port = mv88e6095_g1_set_egress_port,
4126 .watchdog_ops = &mv88e6097_watchdog_ops,
4127 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4128 .pot_clear = mv88e6xxx_g2_pot_clear,
4129 .ppu_enable = mv88e6185_g1_ppu_enable,
4130 .ppu_disable = mv88e6185_g1_ppu_disable,
4131 .reset = mv88e6185_g1_reset,
4132 .rmu_disable = mv88e6085_g1_rmu_disable,
4133 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4134 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4135 .stu_getnext = mv88e6352_g1_stu_getnext,
4136 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4137 .phylink_get_caps = mv88e6185_phylink_get_caps,
4138 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4139 };
4140
4141 static const struct mv88e6xxx_ops mv88e6095_ops = {
4142 /* MV88E6XXX_FAMILY_6095 */
4143 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4144 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4145 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4146 .phy_read = mv88e6185_phy_ppu_read,
4147 .phy_write = mv88e6185_phy_ppu_write,
4148 .port_set_link = mv88e6xxx_port_set_link,
4149 .port_sync_link = mv88e6185_port_sync_link,
4150 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4151 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4152 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4153 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4154 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4155 .port_get_cmode = mv88e6185_port_get_cmode,
4156 .port_setup_message_port = mv88e6xxx_setup_message_port,
4157 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4158 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4159 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4160 .stats_get_strings = mv88e6095_stats_get_strings,
4161 .stats_get_stats = mv88e6095_stats_get_stats,
4162 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4163 .serdes_power = mv88e6185_serdes_power,
4164 .serdes_get_lane = mv88e6185_serdes_get_lane,
4165 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4166 .ppu_enable = mv88e6185_g1_ppu_enable,
4167 .ppu_disable = mv88e6185_g1_ppu_disable,
4168 .reset = mv88e6185_g1_reset,
4169 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4170 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4171 .phylink_get_caps = mv88e6095_phylink_get_caps,
4172 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4173 };
4174
4175 static const struct mv88e6xxx_ops mv88e6097_ops = {
4176 /* MV88E6XXX_FAMILY_6097 */
4177 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4178 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4179 .irl_init_all = mv88e6352_g2_irl_init_all,
4180 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4181 .phy_read = mv88e6xxx_g2_smi_phy_read,
4182 .phy_write = mv88e6xxx_g2_smi_phy_write,
4183 .port_set_link = mv88e6xxx_port_set_link,
4184 .port_sync_link = mv88e6185_port_sync_link,
4185 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4186 .port_tag_remap = mv88e6095_port_tag_remap,
4187 .port_set_policy = mv88e6352_port_set_policy,
4188 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4189 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4190 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4191 .port_set_ether_type = mv88e6351_port_set_ether_type,
4192 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4193 .port_pause_limit = mv88e6097_port_pause_limit,
4194 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4196 .port_get_cmode = mv88e6185_port_get_cmode,
4197 .port_setup_message_port = mv88e6xxx_setup_message_port,
4198 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4199 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4200 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4201 .stats_get_strings = mv88e6095_stats_get_strings,
4202 .stats_get_stats = mv88e6095_stats_get_stats,
4203 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4204 .set_egress_port = mv88e6095_g1_set_egress_port,
4205 .watchdog_ops = &mv88e6097_watchdog_ops,
4206 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4207 .serdes_power = mv88e6185_serdes_power,
4208 .serdes_get_lane = mv88e6185_serdes_get_lane,
4209 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4210 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4211 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
4212 .serdes_irq_status = mv88e6097_serdes_irq_status,
4213 .pot_clear = mv88e6xxx_g2_pot_clear,
4214 .reset = mv88e6352_g1_reset,
4215 .rmu_disable = mv88e6085_g1_rmu_disable,
4216 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4217 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4218 .phylink_get_caps = mv88e6095_phylink_get_caps,
4219 .stu_getnext = mv88e6352_g1_stu_getnext,
4220 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4221 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4222 };
4223
4224 static const struct mv88e6xxx_ops mv88e6123_ops = {
4225 /* MV88E6XXX_FAMILY_6165 */
4226 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4227 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4228 .irl_init_all = mv88e6352_g2_irl_init_all,
4229 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4230 .phy_read = mv88e6xxx_g2_smi_phy_read,
4231 .phy_write = mv88e6xxx_g2_smi_phy_write,
4232 .port_set_link = mv88e6xxx_port_set_link,
4233 .port_sync_link = mv88e6xxx_port_sync_link,
4234 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4235 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4236 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4237 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4238 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4239 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4240 .port_get_cmode = mv88e6185_port_get_cmode,
4241 .port_setup_message_port = mv88e6xxx_setup_message_port,
4242 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4243 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4244 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4245 .stats_get_strings = mv88e6095_stats_get_strings,
4246 .stats_get_stats = mv88e6095_stats_get_stats,
4247 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4248 .set_egress_port = mv88e6095_g1_set_egress_port,
4249 .watchdog_ops = &mv88e6097_watchdog_ops,
4250 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4251 .pot_clear = mv88e6xxx_g2_pot_clear,
4252 .reset = mv88e6352_g1_reset,
4253 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4254 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4255 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4256 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4257 .stu_getnext = mv88e6352_g1_stu_getnext,
4258 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4259 .phylink_get_caps = mv88e6185_phylink_get_caps,
4260 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4261 };
4262
4263 static const struct mv88e6xxx_ops mv88e6131_ops = {
4264 /* MV88E6XXX_FAMILY_6185 */
4265 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4266 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4267 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4268 .phy_read = mv88e6185_phy_ppu_read,
4269 .phy_write = mv88e6185_phy_ppu_write,
4270 .port_set_link = mv88e6xxx_port_set_link,
4271 .port_sync_link = mv88e6xxx_port_sync_link,
4272 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4273 .port_tag_remap = mv88e6095_port_tag_remap,
4274 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4275 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4276 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4277 .port_set_ether_type = mv88e6351_port_set_ether_type,
4278 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4279 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4280 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4281 .port_pause_limit = mv88e6097_port_pause_limit,
4282 .port_set_pause = mv88e6185_port_set_pause,
4283 .port_get_cmode = mv88e6185_port_get_cmode,
4284 .port_setup_message_port = mv88e6xxx_setup_message_port,
4285 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4286 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4287 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4288 .stats_get_strings = mv88e6095_stats_get_strings,
4289 .stats_get_stats = mv88e6095_stats_get_stats,
4290 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4291 .set_egress_port = mv88e6095_g1_set_egress_port,
4292 .watchdog_ops = &mv88e6097_watchdog_ops,
4293 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4294 .ppu_enable = mv88e6185_g1_ppu_enable,
4295 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4296 .ppu_disable = mv88e6185_g1_ppu_disable,
4297 .reset = mv88e6185_g1_reset,
4298 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4299 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4300 .phylink_get_caps = mv88e6185_phylink_get_caps,
4301 };
4302
4303 static const struct mv88e6xxx_ops mv88e6141_ops = {
4304 /* MV88E6XXX_FAMILY_6341 */
4305 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4306 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4307 .irl_init_all = mv88e6352_g2_irl_init_all,
4308 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4309 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4310 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4311 .phy_read = mv88e6xxx_g2_smi_phy_read,
4312 .phy_write = mv88e6xxx_g2_smi_phy_write,
4313 .port_set_link = mv88e6xxx_port_set_link,
4314 .port_sync_link = mv88e6xxx_port_sync_link,
4315 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4316 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4317 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4318 .port_tag_remap = mv88e6095_port_tag_remap,
4319 .port_set_policy = mv88e6352_port_set_policy,
4320 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4321 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4322 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4323 .port_set_ether_type = mv88e6351_port_set_ether_type,
4324 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4325 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4326 .port_pause_limit = mv88e6097_port_pause_limit,
4327 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4328 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4329 .port_get_cmode = mv88e6352_port_get_cmode,
4330 .port_set_cmode = mv88e6341_port_set_cmode,
4331 .port_setup_message_port = mv88e6xxx_setup_message_port,
4332 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4333 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4334 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4335 .stats_get_strings = mv88e6320_stats_get_strings,
4336 .stats_get_stats = mv88e6390_stats_get_stats,
4337 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4338 .set_egress_port = mv88e6390_g1_set_egress_port,
4339 .watchdog_ops = &mv88e6390_watchdog_ops,
4340 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4341 .pot_clear = mv88e6xxx_g2_pot_clear,
4342 .reset = mv88e6352_g1_reset,
4343 .rmu_disable = mv88e6390_g1_rmu_disable,
4344 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4345 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4346 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4347 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4348 .stu_getnext = mv88e6352_g1_stu_getnext,
4349 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4350 .serdes_power = mv88e6390_serdes_power,
4351 .serdes_get_lane = mv88e6341_serdes_get_lane,
4352 /* Check status register pause & lpa register */
4353 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4354 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4355 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4356 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4357 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4358 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4359 .serdes_irq_status = mv88e6390_serdes_irq_status,
4360 .gpio_ops = &mv88e6352_gpio_ops,
4361 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4362 .serdes_get_strings = mv88e6390_serdes_get_strings,
4363 .serdes_get_stats = mv88e6390_serdes_get_stats,
4364 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4365 .serdes_get_regs = mv88e6390_serdes_get_regs,
4366 .phylink_get_caps = mv88e6341_phylink_get_caps,
4367 };
4368
4369 static const struct mv88e6xxx_ops mv88e6161_ops = {
4370 /* MV88E6XXX_FAMILY_6165 */
4371 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4372 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4373 .irl_init_all = mv88e6352_g2_irl_init_all,
4374 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4375 .phy_read = mv88e6xxx_g2_smi_phy_read,
4376 .phy_write = mv88e6xxx_g2_smi_phy_write,
4377 .port_set_link = mv88e6xxx_port_set_link,
4378 .port_sync_link = mv88e6xxx_port_sync_link,
4379 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4380 .port_tag_remap = mv88e6095_port_tag_remap,
4381 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4382 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4383 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4384 .port_set_ether_type = mv88e6351_port_set_ether_type,
4385 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4386 .port_pause_limit = mv88e6097_port_pause_limit,
4387 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4388 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4389 .port_get_cmode = mv88e6185_port_get_cmode,
4390 .port_setup_message_port = mv88e6xxx_setup_message_port,
4391 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4392 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4393 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4394 .stats_get_strings = mv88e6095_stats_get_strings,
4395 .stats_get_stats = mv88e6095_stats_get_stats,
4396 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4397 .set_egress_port = mv88e6095_g1_set_egress_port,
4398 .watchdog_ops = &mv88e6097_watchdog_ops,
4399 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4400 .pot_clear = mv88e6xxx_g2_pot_clear,
4401 .reset = mv88e6352_g1_reset,
4402 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4403 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4404 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4405 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4406 .stu_getnext = mv88e6352_g1_stu_getnext,
4407 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4408 .avb_ops = &mv88e6165_avb_ops,
4409 .ptp_ops = &mv88e6165_ptp_ops,
4410 .phylink_get_caps = mv88e6185_phylink_get_caps,
4411 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4412 };
4413
4414 static const struct mv88e6xxx_ops mv88e6165_ops = {
4415 /* MV88E6XXX_FAMILY_6165 */
4416 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4417 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4418 .irl_init_all = mv88e6352_g2_irl_init_all,
4419 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4420 .phy_read = mv88e6165_phy_read,
4421 .phy_write = mv88e6165_phy_write,
4422 .port_set_link = mv88e6xxx_port_set_link,
4423 .port_sync_link = mv88e6xxx_port_sync_link,
4424 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4425 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4426 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4427 .port_get_cmode = mv88e6185_port_get_cmode,
4428 .port_setup_message_port = mv88e6xxx_setup_message_port,
4429 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4431 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4432 .stats_get_strings = mv88e6095_stats_get_strings,
4433 .stats_get_stats = mv88e6095_stats_get_stats,
4434 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4435 .set_egress_port = mv88e6095_g1_set_egress_port,
4436 .watchdog_ops = &mv88e6097_watchdog_ops,
4437 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4438 .pot_clear = mv88e6xxx_g2_pot_clear,
4439 .reset = mv88e6352_g1_reset,
4440 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4441 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4442 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4443 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4444 .stu_getnext = mv88e6352_g1_stu_getnext,
4445 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4446 .avb_ops = &mv88e6165_avb_ops,
4447 .ptp_ops = &mv88e6165_ptp_ops,
4448 .phylink_get_caps = mv88e6185_phylink_get_caps,
4449 };
4450
4451 static const struct mv88e6xxx_ops mv88e6171_ops = {
4452 /* MV88E6XXX_FAMILY_6351 */
4453 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4454 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4455 .irl_init_all = mv88e6352_g2_irl_init_all,
4456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4457 .phy_read = mv88e6xxx_g2_smi_phy_read,
4458 .phy_write = mv88e6xxx_g2_smi_phy_write,
4459 .port_set_link = mv88e6xxx_port_set_link,
4460 .port_sync_link = mv88e6xxx_port_sync_link,
4461 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4462 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4463 .port_tag_remap = mv88e6095_port_tag_remap,
4464 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4465 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4466 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4467 .port_set_ether_type = mv88e6351_port_set_ether_type,
4468 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4469 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4470 .port_pause_limit = mv88e6097_port_pause_limit,
4471 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4472 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4473 .port_get_cmode = mv88e6352_port_get_cmode,
4474 .port_setup_message_port = mv88e6xxx_setup_message_port,
4475 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4476 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4477 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4478 .stats_get_strings = mv88e6095_stats_get_strings,
4479 .stats_get_stats = mv88e6095_stats_get_stats,
4480 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4481 .set_egress_port = mv88e6095_g1_set_egress_port,
4482 .watchdog_ops = &mv88e6097_watchdog_ops,
4483 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4484 .pot_clear = mv88e6xxx_g2_pot_clear,
4485 .reset = mv88e6352_g1_reset,
4486 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4487 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4488 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4489 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4490 .stu_getnext = mv88e6352_g1_stu_getnext,
4491 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4492 .phylink_get_caps = mv88e6185_phylink_get_caps,
4493 };
4494
4495 static const struct mv88e6xxx_ops mv88e6172_ops = {
4496 /* MV88E6XXX_FAMILY_6352 */
4497 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4498 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4499 .irl_init_all = mv88e6352_g2_irl_init_all,
4500 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4501 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4502 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4503 .phy_read = mv88e6xxx_g2_smi_phy_read,
4504 .phy_write = mv88e6xxx_g2_smi_phy_write,
4505 .port_set_link = mv88e6xxx_port_set_link,
4506 .port_sync_link = mv88e6xxx_port_sync_link,
4507 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4508 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4509 .port_tag_remap = mv88e6095_port_tag_remap,
4510 .port_set_policy = mv88e6352_port_set_policy,
4511 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4512 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4513 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4514 .port_set_ether_type = mv88e6351_port_set_ether_type,
4515 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4516 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4517 .port_pause_limit = mv88e6097_port_pause_limit,
4518 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4519 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4520 .port_get_cmode = mv88e6352_port_get_cmode,
4521 .port_setup_message_port = mv88e6xxx_setup_message_port,
4522 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4523 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4524 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4525 .stats_get_strings = mv88e6095_stats_get_strings,
4526 .stats_get_stats = mv88e6095_stats_get_stats,
4527 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4528 .set_egress_port = mv88e6095_g1_set_egress_port,
4529 .watchdog_ops = &mv88e6097_watchdog_ops,
4530 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4531 .pot_clear = mv88e6xxx_g2_pot_clear,
4532 .reset = mv88e6352_g1_reset,
4533 .rmu_disable = mv88e6352_g1_rmu_disable,
4534 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4535 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4536 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4537 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4538 .stu_getnext = mv88e6352_g1_stu_getnext,
4539 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4540 .serdes_get_lane = mv88e6352_serdes_get_lane,
4541 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4542 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4543 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4544 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4545 .serdes_power = mv88e6352_serdes_power,
4546 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4547 .serdes_get_regs = mv88e6352_serdes_get_regs,
4548 .gpio_ops = &mv88e6352_gpio_ops,
4549 .phylink_get_caps = mv88e6352_phylink_get_caps,
4550 };
4551
4552 static const struct mv88e6xxx_ops mv88e6175_ops = {
4553 /* MV88E6XXX_FAMILY_6351 */
4554 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4555 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4556 .irl_init_all = mv88e6352_g2_irl_init_all,
4557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4558 .phy_read = mv88e6xxx_g2_smi_phy_read,
4559 .phy_write = mv88e6xxx_g2_smi_phy_write,
4560 .port_set_link = mv88e6xxx_port_set_link,
4561 .port_sync_link = mv88e6xxx_port_sync_link,
4562 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4563 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4564 .port_tag_remap = mv88e6095_port_tag_remap,
4565 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4566 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4567 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4568 .port_set_ether_type = mv88e6351_port_set_ether_type,
4569 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4570 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4571 .port_pause_limit = mv88e6097_port_pause_limit,
4572 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4573 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4574 .port_get_cmode = mv88e6352_port_get_cmode,
4575 .port_setup_message_port = mv88e6xxx_setup_message_port,
4576 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4577 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4578 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4579 .stats_get_strings = mv88e6095_stats_get_strings,
4580 .stats_get_stats = mv88e6095_stats_get_stats,
4581 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4582 .set_egress_port = mv88e6095_g1_set_egress_port,
4583 .watchdog_ops = &mv88e6097_watchdog_ops,
4584 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4585 .pot_clear = mv88e6xxx_g2_pot_clear,
4586 .reset = mv88e6352_g1_reset,
4587 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4588 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4589 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4591 .stu_getnext = mv88e6352_g1_stu_getnext,
4592 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4593 .phylink_get_caps = mv88e6185_phylink_get_caps,
4594 };
4595
4596 static const struct mv88e6xxx_ops mv88e6176_ops = {
4597 /* MV88E6XXX_FAMILY_6352 */
4598 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4599 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4600 .irl_init_all = mv88e6352_g2_irl_init_all,
4601 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4602 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4603 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4604 .phy_read = mv88e6xxx_g2_smi_phy_read,
4605 .phy_write = mv88e6xxx_g2_smi_phy_write,
4606 .port_set_link = mv88e6xxx_port_set_link,
4607 .port_sync_link = mv88e6xxx_port_sync_link,
4608 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4609 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4610 .port_tag_remap = mv88e6095_port_tag_remap,
4611 .port_set_policy = mv88e6352_port_set_policy,
4612 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4613 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4614 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4615 .port_set_ether_type = mv88e6351_port_set_ether_type,
4616 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4617 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4618 .port_pause_limit = mv88e6097_port_pause_limit,
4619 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4620 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4621 .port_get_cmode = mv88e6352_port_get_cmode,
4622 .port_setup_message_port = mv88e6xxx_setup_message_port,
4623 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4624 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4625 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4626 .stats_get_strings = mv88e6095_stats_get_strings,
4627 .stats_get_stats = mv88e6095_stats_get_stats,
4628 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4629 .set_egress_port = mv88e6095_g1_set_egress_port,
4630 .watchdog_ops = &mv88e6097_watchdog_ops,
4631 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4632 .pot_clear = mv88e6xxx_g2_pot_clear,
4633 .reset = mv88e6352_g1_reset,
4634 .rmu_disable = mv88e6352_g1_rmu_disable,
4635 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4636 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4637 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4639 .stu_getnext = mv88e6352_g1_stu_getnext,
4640 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4641 .serdes_get_lane = mv88e6352_serdes_get_lane,
4642 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4643 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4644 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4645 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4646 .serdes_power = mv88e6352_serdes_power,
4647 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4648 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4649 .serdes_irq_status = mv88e6352_serdes_irq_status,
4650 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4651 .serdes_get_regs = mv88e6352_serdes_get_regs,
4652 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4653 .gpio_ops = &mv88e6352_gpio_ops,
4654 .phylink_get_caps = mv88e6352_phylink_get_caps,
4655 };
4656
4657 static const struct mv88e6xxx_ops mv88e6185_ops = {
4658 /* MV88E6XXX_FAMILY_6185 */
4659 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4660 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4661 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4662 .phy_read = mv88e6185_phy_ppu_read,
4663 .phy_write = mv88e6185_phy_ppu_write,
4664 .port_set_link = mv88e6xxx_port_set_link,
4665 .port_sync_link = mv88e6185_port_sync_link,
4666 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4667 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4668 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4669 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4670 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4671 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4672 .port_set_pause = mv88e6185_port_set_pause,
4673 .port_get_cmode = mv88e6185_port_get_cmode,
4674 .port_setup_message_port = mv88e6xxx_setup_message_port,
4675 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4676 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4677 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4678 .stats_get_strings = mv88e6095_stats_get_strings,
4679 .stats_get_stats = mv88e6095_stats_get_stats,
4680 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4681 .set_egress_port = mv88e6095_g1_set_egress_port,
4682 .watchdog_ops = &mv88e6097_watchdog_ops,
4683 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4684 .serdes_power = mv88e6185_serdes_power,
4685 .serdes_get_lane = mv88e6185_serdes_get_lane,
4686 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4687 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4688 .ppu_enable = mv88e6185_g1_ppu_enable,
4689 .ppu_disable = mv88e6185_g1_ppu_disable,
4690 .reset = mv88e6185_g1_reset,
4691 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4692 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4693 .phylink_get_caps = mv88e6185_phylink_get_caps,
4694 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4695 };
4696
4697 static const struct mv88e6xxx_ops mv88e6190_ops = {
4698 /* MV88E6XXX_FAMILY_6390 */
4699 .setup_errata = mv88e6390_setup_errata,
4700 .irl_init_all = mv88e6390_g2_irl_init_all,
4701 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4702 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4703 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4704 .phy_read = mv88e6xxx_g2_smi_phy_read,
4705 .phy_write = mv88e6xxx_g2_smi_phy_write,
4706 .port_set_link = mv88e6xxx_port_set_link,
4707 .port_sync_link = mv88e6xxx_port_sync_link,
4708 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4709 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4710 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4711 .port_tag_remap = mv88e6390_port_tag_remap,
4712 .port_set_policy = mv88e6352_port_set_policy,
4713 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4714 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4715 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4716 .port_set_ether_type = mv88e6351_port_set_ether_type,
4717 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4718 .port_pause_limit = mv88e6390_port_pause_limit,
4719 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4720 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4721 .port_get_cmode = mv88e6352_port_get_cmode,
4722 .port_set_cmode = mv88e6390_port_set_cmode,
4723 .port_setup_message_port = mv88e6xxx_setup_message_port,
4724 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4725 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4726 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4727 .stats_get_strings = mv88e6320_stats_get_strings,
4728 .stats_get_stats = mv88e6390_stats_get_stats,
4729 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4730 .set_egress_port = mv88e6390_g1_set_egress_port,
4731 .watchdog_ops = &mv88e6390_watchdog_ops,
4732 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4733 .pot_clear = mv88e6xxx_g2_pot_clear,
4734 .reset = mv88e6352_g1_reset,
4735 .rmu_disable = mv88e6390_g1_rmu_disable,
4736 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4737 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4738 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4739 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4740 .stu_getnext = mv88e6390_g1_stu_getnext,
4741 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4742 .serdes_power = mv88e6390_serdes_power,
4743 .serdes_get_lane = mv88e6390_serdes_get_lane,
4744 /* Check status register pause & lpa register */
4745 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4746 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4747 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4748 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4749 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4750 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4751 .serdes_irq_status = mv88e6390_serdes_irq_status,
4752 .serdes_get_strings = mv88e6390_serdes_get_strings,
4753 .serdes_get_stats = mv88e6390_serdes_get_stats,
4754 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4755 .serdes_get_regs = mv88e6390_serdes_get_regs,
4756 .gpio_ops = &mv88e6352_gpio_ops,
4757 .phylink_get_caps = mv88e6390_phylink_get_caps,
4758 };
4759
4760 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4761 /* MV88E6XXX_FAMILY_6390 */
4762 .setup_errata = mv88e6390_setup_errata,
4763 .irl_init_all = mv88e6390_g2_irl_init_all,
4764 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4765 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4767 .phy_read = mv88e6xxx_g2_smi_phy_read,
4768 .phy_write = mv88e6xxx_g2_smi_phy_write,
4769 .port_set_link = mv88e6xxx_port_set_link,
4770 .port_sync_link = mv88e6xxx_port_sync_link,
4771 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4772 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4773 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4774 .port_tag_remap = mv88e6390_port_tag_remap,
4775 .port_set_policy = mv88e6352_port_set_policy,
4776 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4777 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4778 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4779 .port_set_ether_type = mv88e6351_port_set_ether_type,
4780 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4781 .port_pause_limit = mv88e6390_port_pause_limit,
4782 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4783 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4784 .port_get_cmode = mv88e6352_port_get_cmode,
4785 .port_set_cmode = mv88e6390x_port_set_cmode,
4786 .port_setup_message_port = mv88e6xxx_setup_message_port,
4787 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4788 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4789 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4790 .stats_get_strings = mv88e6320_stats_get_strings,
4791 .stats_get_stats = mv88e6390_stats_get_stats,
4792 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4793 .set_egress_port = mv88e6390_g1_set_egress_port,
4794 .watchdog_ops = &mv88e6390_watchdog_ops,
4795 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4796 .pot_clear = mv88e6xxx_g2_pot_clear,
4797 .reset = mv88e6352_g1_reset,
4798 .rmu_disable = mv88e6390_g1_rmu_disable,
4799 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4800 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4801 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4802 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4803 .stu_getnext = mv88e6390_g1_stu_getnext,
4804 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4805 .serdes_power = mv88e6390_serdes_power,
4806 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4807 /* Check status register pause & lpa register */
4808 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4809 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4810 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4811 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4812 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4813 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4814 .serdes_irq_status = mv88e6390_serdes_irq_status,
4815 .serdes_get_strings = mv88e6390_serdes_get_strings,
4816 .serdes_get_stats = mv88e6390_serdes_get_stats,
4817 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4818 .serdes_get_regs = mv88e6390_serdes_get_regs,
4819 .gpio_ops = &mv88e6352_gpio_ops,
4820 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4821 };
4822
4823 static const struct mv88e6xxx_ops mv88e6191_ops = {
4824 /* MV88E6XXX_FAMILY_6390 */
4825 .setup_errata = mv88e6390_setup_errata,
4826 .irl_init_all = mv88e6390_g2_irl_init_all,
4827 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4828 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4829 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4830 .phy_read = mv88e6xxx_g2_smi_phy_read,
4831 .phy_write = mv88e6xxx_g2_smi_phy_write,
4832 .port_set_link = mv88e6xxx_port_set_link,
4833 .port_sync_link = mv88e6xxx_port_sync_link,
4834 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4835 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4836 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4837 .port_tag_remap = mv88e6390_port_tag_remap,
4838 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4839 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4840 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4841 .port_set_ether_type = mv88e6351_port_set_ether_type,
4842 .port_pause_limit = mv88e6390_port_pause_limit,
4843 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4844 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4845 .port_get_cmode = mv88e6352_port_get_cmode,
4846 .port_set_cmode = mv88e6390_port_set_cmode,
4847 .port_setup_message_port = mv88e6xxx_setup_message_port,
4848 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4849 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4850 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4851 .stats_get_strings = mv88e6320_stats_get_strings,
4852 .stats_get_stats = mv88e6390_stats_get_stats,
4853 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4854 .set_egress_port = mv88e6390_g1_set_egress_port,
4855 .watchdog_ops = &mv88e6390_watchdog_ops,
4856 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4857 .pot_clear = mv88e6xxx_g2_pot_clear,
4858 .reset = mv88e6352_g1_reset,
4859 .rmu_disable = mv88e6390_g1_rmu_disable,
4860 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4861 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4862 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4863 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4864 .stu_getnext = mv88e6390_g1_stu_getnext,
4865 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4866 .serdes_power = mv88e6390_serdes_power,
4867 .serdes_get_lane = mv88e6390_serdes_get_lane,
4868 /* Check status register pause & lpa register */
4869 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4870 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4871 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4872 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4873 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4874 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4875 .serdes_irq_status = mv88e6390_serdes_irq_status,
4876 .serdes_get_strings = mv88e6390_serdes_get_strings,
4877 .serdes_get_stats = mv88e6390_serdes_get_stats,
4878 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4879 .serdes_get_regs = mv88e6390_serdes_get_regs,
4880 .avb_ops = &mv88e6390_avb_ops,
4881 .ptp_ops = &mv88e6352_ptp_ops,
4882 .phylink_get_caps = mv88e6390_phylink_get_caps,
4883 };
4884
4885 static const struct mv88e6xxx_ops mv88e6240_ops = {
4886 /* MV88E6XXX_FAMILY_6352 */
4887 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4888 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4889 .irl_init_all = mv88e6352_g2_irl_init_all,
4890 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4891 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4892 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4893 .phy_read = mv88e6xxx_g2_smi_phy_read,
4894 .phy_write = mv88e6xxx_g2_smi_phy_write,
4895 .port_set_link = mv88e6xxx_port_set_link,
4896 .port_sync_link = mv88e6xxx_port_sync_link,
4897 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4898 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4899 .port_tag_remap = mv88e6095_port_tag_remap,
4900 .port_set_policy = mv88e6352_port_set_policy,
4901 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4902 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4903 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4904 .port_set_ether_type = mv88e6351_port_set_ether_type,
4905 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4906 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4907 .port_pause_limit = mv88e6097_port_pause_limit,
4908 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4909 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4910 .port_get_cmode = mv88e6352_port_get_cmode,
4911 .port_setup_message_port = mv88e6xxx_setup_message_port,
4912 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4913 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4914 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4915 .stats_get_strings = mv88e6095_stats_get_strings,
4916 .stats_get_stats = mv88e6095_stats_get_stats,
4917 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4918 .set_egress_port = mv88e6095_g1_set_egress_port,
4919 .watchdog_ops = &mv88e6097_watchdog_ops,
4920 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4921 .pot_clear = mv88e6xxx_g2_pot_clear,
4922 .reset = mv88e6352_g1_reset,
4923 .rmu_disable = mv88e6352_g1_rmu_disable,
4924 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4925 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4926 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4927 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4928 .stu_getnext = mv88e6352_g1_stu_getnext,
4929 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4930 .serdes_get_lane = mv88e6352_serdes_get_lane,
4931 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4932 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4933 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4934 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4935 .serdes_power = mv88e6352_serdes_power,
4936 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4937 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4938 .serdes_irq_status = mv88e6352_serdes_irq_status,
4939 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4940 .serdes_get_regs = mv88e6352_serdes_get_regs,
4941 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4942 .gpio_ops = &mv88e6352_gpio_ops,
4943 .avb_ops = &mv88e6352_avb_ops,
4944 .ptp_ops = &mv88e6352_ptp_ops,
4945 .phylink_get_caps = mv88e6352_phylink_get_caps,
4946 };
4947
4948 static const struct mv88e6xxx_ops mv88e6250_ops = {
4949 /* MV88E6XXX_FAMILY_6250 */
4950 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4951 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4952 .irl_init_all = mv88e6352_g2_irl_init_all,
4953 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4954 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4955 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4956 .phy_read = mv88e6xxx_g2_smi_phy_read,
4957 .phy_write = mv88e6xxx_g2_smi_phy_write,
4958 .port_set_link = mv88e6xxx_port_set_link,
4959 .port_sync_link = mv88e6xxx_port_sync_link,
4960 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4961 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4962 .port_tag_remap = mv88e6095_port_tag_remap,
4963 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4964 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4965 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4966 .port_set_ether_type = mv88e6351_port_set_ether_type,
4967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4968 .port_pause_limit = mv88e6097_port_pause_limit,
4969 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4970 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4971 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4972 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4973 .stats_get_strings = mv88e6250_stats_get_strings,
4974 .stats_get_stats = mv88e6250_stats_get_stats,
4975 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4976 .set_egress_port = mv88e6095_g1_set_egress_port,
4977 .watchdog_ops = &mv88e6250_watchdog_ops,
4978 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4979 .pot_clear = mv88e6xxx_g2_pot_clear,
4980 .reset = mv88e6250_g1_reset,
4981 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4982 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4983 .avb_ops = &mv88e6352_avb_ops,
4984 .ptp_ops = &mv88e6250_ptp_ops,
4985 .phylink_get_caps = mv88e6250_phylink_get_caps,
4986 };
4987
4988 static const struct mv88e6xxx_ops mv88e6290_ops = {
4989 /* MV88E6XXX_FAMILY_6390 */
4990 .setup_errata = mv88e6390_setup_errata,
4991 .irl_init_all = mv88e6390_g2_irl_init_all,
4992 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4993 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4994 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4995 .phy_read = mv88e6xxx_g2_smi_phy_read,
4996 .phy_write = mv88e6xxx_g2_smi_phy_write,
4997 .port_set_link = mv88e6xxx_port_set_link,
4998 .port_sync_link = mv88e6xxx_port_sync_link,
4999 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5000 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5001 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5002 .port_tag_remap = mv88e6390_port_tag_remap,
5003 .port_set_policy = mv88e6352_port_set_policy,
5004 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5005 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5006 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5007 .port_set_ether_type = mv88e6351_port_set_ether_type,
5008 .port_pause_limit = mv88e6390_port_pause_limit,
5009 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5010 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5011 .port_get_cmode = mv88e6352_port_get_cmode,
5012 .port_set_cmode = mv88e6390_port_set_cmode,
5013 .port_setup_message_port = mv88e6xxx_setup_message_port,
5014 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5015 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5016 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5017 .stats_get_strings = mv88e6320_stats_get_strings,
5018 .stats_get_stats = mv88e6390_stats_get_stats,
5019 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5020 .set_egress_port = mv88e6390_g1_set_egress_port,
5021 .watchdog_ops = &mv88e6390_watchdog_ops,
5022 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5023 .pot_clear = mv88e6xxx_g2_pot_clear,
5024 .reset = mv88e6352_g1_reset,
5025 .rmu_disable = mv88e6390_g1_rmu_disable,
5026 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5027 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5028 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5029 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5030 .stu_getnext = mv88e6390_g1_stu_getnext,
5031 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5032 .serdes_power = mv88e6390_serdes_power,
5033 .serdes_get_lane = mv88e6390_serdes_get_lane,
5034 /* Check status register pause & lpa register */
5035 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5036 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5037 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5038 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5039 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5040 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5041 .serdes_irq_status = mv88e6390_serdes_irq_status,
5042 .serdes_get_strings = mv88e6390_serdes_get_strings,
5043 .serdes_get_stats = mv88e6390_serdes_get_stats,
5044 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5045 .serdes_get_regs = mv88e6390_serdes_get_regs,
5046 .gpio_ops = &mv88e6352_gpio_ops,
5047 .avb_ops = &mv88e6390_avb_ops,
5048 .ptp_ops = &mv88e6352_ptp_ops,
5049 .phylink_get_caps = mv88e6390_phylink_get_caps,
5050 };
5051
5052 static const struct mv88e6xxx_ops mv88e6320_ops = {
5053 /* MV88E6XXX_FAMILY_6320 */
5054 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5055 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5056 .irl_init_all = mv88e6352_g2_irl_init_all,
5057 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5058 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5059 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5060 .phy_read = mv88e6xxx_g2_smi_phy_read,
5061 .phy_write = mv88e6xxx_g2_smi_phy_write,
5062 .port_set_link = mv88e6xxx_port_set_link,
5063 .port_sync_link = mv88e6xxx_port_sync_link,
5064 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5065 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5066 .port_tag_remap = mv88e6095_port_tag_remap,
5067 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5068 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5069 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5070 .port_set_ether_type = mv88e6351_port_set_ether_type,
5071 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5072 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5073 .port_pause_limit = mv88e6097_port_pause_limit,
5074 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5075 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5076 .port_get_cmode = mv88e6352_port_get_cmode,
5077 .port_setup_message_port = mv88e6xxx_setup_message_port,
5078 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5079 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5080 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5081 .stats_get_strings = mv88e6320_stats_get_strings,
5082 .stats_get_stats = mv88e6320_stats_get_stats,
5083 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5084 .set_egress_port = mv88e6095_g1_set_egress_port,
5085 .watchdog_ops = &mv88e6390_watchdog_ops,
5086 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5087 .pot_clear = mv88e6xxx_g2_pot_clear,
5088 .reset = mv88e6352_g1_reset,
5089 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5090 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5091 .gpio_ops = &mv88e6352_gpio_ops,
5092 .avb_ops = &mv88e6352_avb_ops,
5093 .ptp_ops = &mv88e6352_ptp_ops,
5094 .phylink_get_caps = mv88e6185_phylink_get_caps,
5095 };
5096
5097 static const struct mv88e6xxx_ops mv88e6321_ops = {
5098 /* MV88E6XXX_FAMILY_6320 */
5099 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5100 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5101 .irl_init_all = mv88e6352_g2_irl_init_all,
5102 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5103 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5104 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5105 .phy_read = mv88e6xxx_g2_smi_phy_read,
5106 .phy_write = mv88e6xxx_g2_smi_phy_write,
5107 .port_set_link = mv88e6xxx_port_set_link,
5108 .port_sync_link = mv88e6xxx_port_sync_link,
5109 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5110 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5111 .port_tag_remap = mv88e6095_port_tag_remap,
5112 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5113 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5114 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5115 .port_set_ether_type = mv88e6351_port_set_ether_type,
5116 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5117 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5118 .port_pause_limit = mv88e6097_port_pause_limit,
5119 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5120 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5121 .port_get_cmode = mv88e6352_port_get_cmode,
5122 .port_setup_message_port = mv88e6xxx_setup_message_port,
5123 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5124 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5125 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5126 .stats_get_strings = mv88e6320_stats_get_strings,
5127 .stats_get_stats = mv88e6320_stats_get_stats,
5128 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5129 .set_egress_port = mv88e6095_g1_set_egress_port,
5130 .watchdog_ops = &mv88e6390_watchdog_ops,
5131 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5132 .reset = mv88e6352_g1_reset,
5133 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5134 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5135 .gpio_ops = &mv88e6352_gpio_ops,
5136 .avb_ops = &mv88e6352_avb_ops,
5137 .ptp_ops = &mv88e6352_ptp_ops,
5138 .phylink_get_caps = mv88e6185_phylink_get_caps,
5139 };
5140
5141 static const struct mv88e6xxx_ops mv88e6341_ops = {
5142 /* MV88E6XXX_FAMILY_6341 */
5143 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5144 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5145 .irl_init_all = mv88e6352_g2_irl_init_all,
5146 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5147 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5148 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5149 .phy_read = mv88e6xxx_g2_smi_phy_read,
5150 .phy_write = mv88e6xxx_g2_smi_phy_write,
5151 .port_set_link = mv88e6xxx_port_set_link,
5152 .port_sync_link = mv88e6xxx_port_sync_link,
5153 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5154 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5155 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5156 .port_tag_remap = mv88e6095_port_tag_remap,
5157 .port_set_policy = mv88e6352_port_set_policy,
5158 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5159 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5160 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5161 .port_set_ether_type = mv88e6351_port_set_ether_type,
5162 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5163 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5164 .port_pause_limit = mv88e6097_port_pause_limit,
5165 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5166 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5167 .port_get_cmode = mv88e6352_port_get_cmode,
5168 .port_set_cmode = mv88e6341_port_set_cmode,
5169 .port_setup_message_port = mv88e6xxx_setup_message_port,
5170 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5171 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5172 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5173 .stats_get_strings = mv88e6320_stats_get_strings,
5174 .stats_get_stats = mv88e6390_stats_get_stats,
5175 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5176 .set_egress_port = mv88e6390_g1_set_egress_port,
5177 .watchdog_ops = &mv88e6390_watchdog_ops,
5178 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5179 .pot_clear = mv88e6xxx_g2_pot_clear,
5180 .reset = mv88e6352_g1_reset,
5181 .rmu_disable = mv88e6390_g1_rmu_disable,
5182 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5183 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5184 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5185 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5186 .stu_getnext = mv88e6352_g1_stu_getnext,
5187 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5188 .serdes_power = mv88e6390_serdes_power,
5189 .serdes_get_lane = mv88e6341_serdes_get_lane,
5190 /* Check status register pause & lpa register */
5191 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5192 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5193 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5194 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5195 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5196 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5197 .serdes_irq_status = mv88e6390_serdes_irq_status,
5198 .gpio_ops = &mv88e6352_gpio_ops,
5199 .avb_ops = &mv88e6390_avb_ops,
5200 .ptp_ops = &mv88e6352_ptp_ops,
5201 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5202 .serdes_get_strings = mv88e6390_serdes_get_strings,
5203 .serdes_get_stats = mv88e6390_serdes_get_stats,
5204 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5205 .serdes_get_regs = mv88e6390_serdes_get_regs,
5206 .phylink_get_caps = mv88e6341_phylink_get_caps,
5207 };
5208
5209 static const struct mv88e6xxx_ops mv88e6350_ops = {
5210 /* MV88E6XXX_FAMILY_6351 */
5211 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5212 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5213 .irl_init_all = mv88e6352_g2_irl_init_all,
5214 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5215 .phy_read = mv88e6xxx_g2_smi_phy_read,
5216 .phy_write = mv88e6xxx_g2_smi_phy_write,
5217 .port_set_link = mv88e6xxx_port_set_link,
5218 .port_sync_link = mv88e6xxx_port_sync_link,
5219 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5220 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5221 .port_tag_remap = mv88e6095_port_tag_remap,
5222 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5223 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5224 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5225 .port_set_ether_type = mv88e6351_port_set_ether_type,
5226 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5227 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5228 .port_pause_limit = mv88e6097_port_pause_limit,
5229 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5230 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5231 .port_get_cmode = mv88e6352_port_get_cmode,
5232 .port_setup_message_port = mv88e6xxx_setup_message_port,
5233 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5234 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5236 .stats_get_strings = mv88e6095_stats_get_strings,
5237 .stats_get_stats = mv88e6095_stats_get_stats,
5238 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5239 .set_egress_port = mv88e6095_g1_set_egress_port,
5240 .watchdog_ops = &mv88e6097_watchdog_ops,
5241 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5242 .pot_clear = mv88e6xxx_g2_pot_clear,
5243 .reset = mv88e6352_g1_reset,
5244 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5245 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5246 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5247 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5248 .stu_getnext = mv88e6352_g1_stu_getnext,
5249 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5250 .phylink_get_caps = mv88e6185_phylink_get_caps,
5251 };
5252
5253 static const struct mv88e6xxx_ops mv88e6351_ops = {
5254 /* MV88E6XXX_FAMILY_6351 */
5255 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5256 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5257 .irl_init_all = mv88e6352_g2_irl_init_all,
5258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5259 .phy_read = mv88e6xxx_g2_smi_phy_read,
5260 .phy_write = mv88e6xxx_g2_smi_phy_write,
5261 .port_set_link = mv88e6xxx_port_set_link,
5262 .port_sync_link = mv88e6xxx_port_sync_link,
5263 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5264 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5265 .port_tag_remap = mv88e6095_port_tag_remap,
5266 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5267 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5268 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5269 .port_set_ether_type = mv88e6351_port_set_ether_type,
5270 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5271 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5272 .port_pause_limit = mv88e6097_port_pause_limit,
5273 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5274 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5275 .port_get_cmode = mv88e6352_port_get_cmode,
5276 .port_setup_message_port = mv88e6xxx_setup_message_port,
5277 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5278 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5279 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5280 .stats_get_strings = mv88e6095_stats_get_strings,
5281 .stats_get_stats = mv88e6095_stats_get_stats,
5282 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5283 .set_egress_port = mv88e6095_g1_set_egress_port,
5284 .watchdog_ops = &mv88e6097_watchdog_ops,
5285 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5286 .pot_clear = mv88e6xxx_g2_pot_clear,
5287 .reset = mv88e6352_g1_reset,
5288 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5289 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5290 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5291 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5292 .stu_getnext = mv88e6352_g1_stu_getnext,
5293 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5294 .avb_ops = &mv88e6352_avb_ops,
5295 .ptp_ops = &mv88e6352_ptp_ops,
5296 .phylink_get_caps = mv88e6185_phylink_get_caps,
5297 };
5298
5299 static const struct mv88e6xxx_ops mv88e6352_ops = {
5300 /* MV88E6XXX_FAMILY_6352 */
5301 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5302 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5303 .irl_init_all = mv88e6352_g2_irl_init_all,
5304 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5305 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5306 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5307 .phy_read = mv88e6xxx_g2_smi_phy_read,
5308 .phy_write = mv88e6xxx_g2_smi_phy_write,
5309 .port_set_link = mv88e6xxx_port_set_link,
5310 .port_sync_link = mv88e6xxx_port_sync_link,
5311 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5312 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5313 .port_tag_remap = mv88e6095_port_tag_remap,
5314 .port_set_policy = mv88e6352_port_set_policy,
5315 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5316 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5317 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5318 .port_set_ether_type = mv88e6351_port_set_ether_type,
5319 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5320 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5321 .port_pause_limit = mv88e6097_port_pause_limit,
5322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5324 .port_get_cmode = mv88e6352_port_get_cmode,
5325 .port_setup_message_port = mv88e6xxx_setup_message_port,
5326 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5327 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5328 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5329 .stats_get_strings = mv88e6095_stats_get_strings,
5330 .stats_get_stats = mv88e6095_stats_get_stats,
5331 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5332 .set_egress_port = mv88e6095_g1_set_egress_port,
5333 .watchdog_ops = &mv88e6097_watchdog_ops,
5334 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5335 .pot_clear = mv88e6xxx_g2_pot_clear,
5336 .reset = mv88e6352_g1_reset,
5337 .rmu_disable = mv88e6352_g1_rmu_disable,
5338 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5339 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5340 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5341 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5342 .stu_getnext = mv88e6352_g1_stu_getnext,
5343 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5344 .serdes_get_lane = mv88e6352_serdes_get_lane,
5345 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
5346 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
5347 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
5348 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
5349 .serdes_power = mv88e6352_serdes_power,
5350 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5351 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
5352 .serdes_irq_status = mv88e6352_serdes_irq_status,
5353 .gpio_ops = &mv88e6352_gpio_ops,
5354 .avb_ops = &mv88e6352_avb_ops,
5355 .ptp_ops = &mv88e6352_ptp_ops,
5356 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5357 .serdes_get_strings = mv88e6352_serdes_get_strings,
5358 .serdes_get_stats = mv88e6352_serdes_get_stats,
5359 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5360 .serdes_get_regs = mv88e6352_serdes_get_regs,
5361 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5362 .phylink_get_caps = mv88e6352_phylink_get_caps,
5363 };
5364
5365 static const struct mv88e6xxx_ops mv88e6390_ops = {
5366 /* MV88E6XXX_FAMILY_6390 */
5367 .setup_errata = mv88e6390_setup_errata,
5368 .irl_init_all = mv88e6390_g2_irl_init_all,
5369 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5370 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5371 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5372 .phy_read = mv88e6xxx_g2_smi_phy_read,
5373 .phy_write = mv88e6xxx_g2_smi_phy_write,
5374 .port_set_link = mv88e6xxx_port_set_link,
5375 .port_sync_link = mv88e6xxx_port_sync_link,
5376 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5377 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5378 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5379 .port_tag_remap = mv88e6390_port_tag_remap,
5380 .port_set_policy = mv88e6352_port_set_policy,
5381 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5382 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5383 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5384 .port_set_ether_type = mv88e6351_port_set_ether_type,
5385 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5386 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5387 .port_pause_limit = mv88e6390_port_pause_limit,
5388 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5389 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5390 .port_get_cmode = mv88e6352_port_get_cmode,
5391 .port_set_cmode = mv88e6390_port_set_cmode,
5392 .port_setup_message_port = mv88e6xxx_setup_message_port,
5393 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5394 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5395 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5396 .stats_get_strings = mv88e6320_stats_get_strings,
5397 .stats_get_stats = mv88e6390_stats_get_stats,
5398 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5399 .set_egress_port = mv88e6390_g1_set_egress_port,
5400 .watchdog_ops = &mv88e6390_watchdog_ops,
5401 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5402 .pot_clear = mv88e6xxx_g2_pot_clear,
5403 .reset = mv88e6352_g1_reset,
5404 .rmu_disable = mv88e6390_g1_rmu_disable,
5405 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5406 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5407 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5408 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5409 .stu_getnext = mv88e6390_g1_stu_getnext,
5410 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5411 .serdes_power = mv88e6390_serdes_power,
5412 .serdes_get_lane = mv88e6390_serdes_get_lane,
5413 /* Check status register pause & lpa register */
5414 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5415 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5416 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5417 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5418 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5419 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5420 .serdes_irq_status = mv88e6390_serdes_irq_status,
5421 .gpio_ops = &mv88e6352_gpio_ops,
5422 .avb_ops = &mv88e6390_avb_ops,
5423 .ptp_ops = &mv88e6352_ptp_ops,
5424 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5425 .serdes_get_strings = mv88e6390_serdes_get_strings,
5426 .serdes_get_stats = mv88e6390_serdes_get_stats,
5427 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5428 .serdes_get_regs = mv88e6390_serdes_get_regs,
5429 .phylink_get_caps = mv88e6390_phylink_get_caps,
5430 };
5431
5432 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5433 /* MV88E6XXX_FAMILY_6390 */
5434 .setup_errata = mv88e6390_setup_errata,
5435 .irl_init_all = mv88e6390_g2_irl_init_all,
5436 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5437 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5438 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5439 .phy_read = mv88e6xxx_g2_smi_phy_read,
5440 .phy_write = mv88e6xxx_g2_smi_phy_write,
5441 .port_set_link = mv88e6xxx_port_set_link,
5442 .port_sync_link = mv88e6xxx_port_sync_link,
5443 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5444 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5445 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5446 .port_tag_remap = mv88e6390_port_tag_remap,
5447 .port_set_policy = mv88e6352_port_set_policy,
5448 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5449 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5450 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5451 .port_set_ether_type = mv88e6351_port_set_ether_type,
5452 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5453 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5454 .port_pause_limit = mv88e6390_port_pause_limit,
5455 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5456 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5457 .port_get_cmode = mv88e6352_port_get_cmode,
5458 .port_set_cmode = mv88e6390x_port_set_cmode,
5459 .port_setup_message_port = mv88e6xxx_setup_message_port,
5460 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5461 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5462 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5463 .stats_get_strings = mv88e6320_stats_get_strings,
5464 .stats_get_stats = mv88e6390_stats_get_stats,
5465 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5466 .set_egress_port = mv88e6390_g1_set_egress_port,
5467 .watchdog_ops = &mv88e6390_watchdog_ops,
5468 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5469 .pot_clear = mv88e6xxx_g2_pot_clear,
5470 .reset = mv88e6352_g1_reset,
5471 .rmu_disable = mv88e6390_g1_rmu_disable,
5472 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5473 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5474 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5475 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5476 .stu_getnext = mv88e6390_g1_stu_getnext,
5477 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5478 .serdes_power = mv88e6390_serdes_power,
5479 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5480 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5481 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5482 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5483 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5484 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5485 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5486 .serdes_irq_status = mv88e6390_serdes_irq_status,
5487 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5488 .serdes_get_strings = mv88e6390_serdes_get_strings,
5489 .serdes_get_stats = mv88e6390_serdes_get_stats,
5490 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5491 .serdes_get_regs = mv88e6390_serdes_get_regs,
5492 .gpio_ops = &mv88e6352_gpio_ops,
5493 .avb_ops = &mv88e6390_avb_ops,
5494 .ptp_ops = &mv88e6352_ptp_ops,
5495 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5496 };
5497
5498 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5499 /* MV88E6XXX_FAMILY_6393 */
5500 .setup_errata = mv88e6393x_serdes_setup_errata,
5501 .irl_init_all = mv88e6390_g2_irl_init_all,
5502 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5503 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5504 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5505 .phy_read = mv88e6xxx_g2_smi_phy_read,
5506 .phy_write = mv88e6xxx_g2_smi_phy_write,
5507 .port_set_link = mv88e6xxx_port_set_link,
5508 .port_sync_link = mv88e6xxx_port_sync_link,
5509 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5510 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5511 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5512 .port_tag_remap = mv88e6390_port_tag_remap,
5513 .port_set_policy = mv88e6393x_port_set_policy,
5514 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5515 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5516 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5517 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5518 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5519 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5520 .port_pause_limit = mv88e6390_port_pause_limit,
5521 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5522 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5523 .port_get_cmode = mv88e6352_port_get_cmode,
5524 .port_set_cmode = mv88e6393x_port_set_cmode,
5525 .port_setup_message_port = mv88e6xxx_setup_message_port,
5526 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5527 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5528 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5529 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5530 .stats_get_strings = mv88e6320_stats_get_strings,
5531 .stats_get_stats = mv88e6390_stats_get_stats,
5532 /* .set_cpu_port is missing because this family does not support a global
5533 * CPU port, only per port CPU port which is set via
5534 * .port_set_upstream_port method.
5535 */
5536 .set_egress_port = mv88e6393x_set_egress_port,
5537 .watchdog_ops = &mv88e6393x_watchdog_ops,
5538 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5539 .pot_clear = mv88e6xxx_g2_pot_clear,
5540 .reset = mv88e6352_g1_reset,
5541 .rmu_disable = mv88e6390_g1_rmu_disable,
5542 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5543 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5544 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5545 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5546 .stu_getnext = mv88e6390_g1_stu_getnext,
5547 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5548 .serdes_power = mv88e6393x_serdes_power,
5549 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5550 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
5551 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5552 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5553 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5554 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5555 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
5556 .serdes_irq_status = mv88e6393x_serdes_irq_status,
5557 /* TODO: serdes stats */
5558 .gpio_ops = &mv88e6352_gpio_ops,
5559 .avb_ops = &mv88e6390_avb_ops,
5560 .ptp_ops = &mv88e6352_ptp_ops,
5561 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5562 };
5563
5564 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5565 [MV88E6085] = {
5566 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5567 .family = MV88E6XXX_FAMILY_6097,
5568 .name = "Marvell 88E6085",
5569 .num_databases = 4096,
5570 .num_macs = 8192,
5571 .num_ports = 10,
5572 .num_internal_phys = 5,
5573 .max_vid = 4095,
5574 .max_sid = 63,
5575 .port_base_addr = 0x10,
5576 .phy_base_addr = 0x0,
5577 .global1_addr = 0x1b,
5578 .global2_addr = 0x1c,
5579 .age_time_coeff = 15000,
5580 .g1_irqs = 8,
5581 .g2_irqs = 10,
5582 .atu_move_port_mask = 0xf,
5583 .pvt = true,
5584 .multi_chip = true,
5585 .ops = &mv88e6085_ops,
5586 },
5587
5588 [MV88E6095] = {
5589 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5590 .family = MV88E6XXX_FAMILY_6095,
5591 .name = "Marvell 88E6095/88E6095F",
5592 .num_databases = 256,
5593 .num_macs = 8192,
5594 .num_ports = 11,
5595 .num_internal_phys = 0,
5596 .max_vid = 4095,
5597 .port_base_addr = 0x10,
5598 .phy_base_addr = 0x0,
5599 .global1_addr = 0x1b,
5600 .global2_addr = 0x1c,
5601 .age_time_coeff = 15000,
5602 .g1_irqs = 8,
5603 .atu_move_port_mask = 0xf,
5604 .multi_chip = true,
5605 .ops = &mv88e6095_ops,
5606 },
5607
5608 [MV88E6097] = {
5609 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5610 .family = MV88E6XXX_FAMILY_6097,
5611 .name = "Marvell 88E6097/88E6097F",
5612 .num_databases = 4096,
5613 .num_macs = 8192,
5614 .num_ports = 11,
5615 .num_internal_phys = 8,
5616 .max_vid = 4095,
5617 .max_sid = 63,
5618 .port_base_addr = 0x10,
5619 .phy_base_addr = 0x0,
5620 .global1_addr = 0x1b,
5621 .global2_addr = 0x1c,
5622 .age_time_coeff = 15000,
5623 .g1_irqs = 8,
5624 .g2_irqs = 10,
5625 .atu_move_port_mask = 0xf,
5626 .pvt = true,
5627 .multi_chip = true,
5628 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5629 .ops = &mv88e6097_ops,
5630 },
5631
5632 [MV88E6123] = {
5633 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5634 .family = MV88E6XXX_FAMILY_6165,
5635 .name = "Marvell 88E6123",
5636 .num_databases = 4096,
5637 .num_macs = 1024,
5638 .num_ports = 3,
5639 .num_internal_phys = 5,
5640 .max_vid = 4095,
5641 .max_sid = 63,
5642 .port_base_addr = 0x10,
5643 .phy_base_addr = 0x0,
5644 .global1_addr = 0x1b,
5645 .global2_addr = 0x1c,
5646 .age_time_coeff = 15000,
5647 .g1_irqs = 9,
5648 .g2_irqs = 10,
5649 .atu_move_port_mask = 0xf,
5650 .pvt = true,
5651 .multi_chip = true,
5652 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5653 .ops = &mv88e6123_ops,
5654 },
5655
5656 [MV88E6131] = {
5657 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5658 .family = MV88E6XXX_FAMILY_6185,
5659 .name = "Marvell 88E6131",
5660 .num_databases = 256,
5661 .num_macs = 8192,
5662 .num_ports = 8,
5663 .num_internal_phys = 0,
5664 .max_vid = 4095,
5665 .port_base_addr = 0x10,
5666 .phy_base_addr = 0x0,
5667 .global1_addr = 0x1b,
5668 .global2_addr = 0x1c,
5669 .age_time_coeff = 15000,
5670 .g1_irqs = 9,
5671 .atu_move_port_mask = 0xf,
5672 .multi_chip = true,
5673 .ops = &mv88e6131_ops,
5674 },
5675
5676 [MV88E6141] = {
5677 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5678 .family = MV88E6XXX_FAMILY_6341,
5679 .name = "Marvell 88E6141",
5680 .num_databases = 4096,
5681 .num_macs = 2048,
5682 .num_ports = 6,
5683 .num_internal_phys = 5,
5684 .num_gpio = 11,
5685 .max_vid = 4095,
5686 .max_sid = 63,
5687 .port_base_addr = 0x10,
5688 .phy_base_addr = 0x10,
5689 .global1_addr = 0x1b,
5690 .global2_addr = 0x1c,
5691 .age_time_coeff = 3750,
5692 .atu_move_port_mask = 0x1f,
5693 .g1_irqs = 9,
5694 .g2_irqs = 10,
5695 .pvt = true,
5696 .multi_chip = true,
5697 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5698 .ops = &mv88e6141_ops,
5699 },
5700
5701 [MV88E6161] = {
5702 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5703 .family = MV88E6XXX_FAMILY_6165,
5704 .name = "Marvell 88E6161",
5705 .num_databases = 4096,
5706 .num_macs = 1024,
5707 .num_ports = 6,
5708 .num_internal_phys = 5,
5709 .max_vid = 4095,
5710 .max_sid = 63,
5711 .port_base_addr = 0x10,
5712 .phy_base_addr = 0x0,
5713 .global1_addr = 0x1b,
5714 .global2_addr = 0x1c,
5715 .age_time_coeff = 15000,
5716 .g1_irqs = 9,
5717 .g2_irqs = 10,
5718 .atu_move_port_mask = 0xf,
5719 .pvt = true,
5720 .multi_chip = true,
5721 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5722 .ptp_support = true,
5723 .ops = &mv88e6161_ops,
5724 },
5725
5726 [MV88E6165] = {
5727 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5728 .family = MV88E6XXX_FAMILY_6165,
5729 .name = "Marvell 88E6165",
5730 .num_databases = 4096,
5731 .num_macs = 8192,
5732 .num_ports = 6,
5733 .num_internal_phys = 0,
5734 .max_vid = 4095,
5735 .max_sid = 63,
5736 .port_base_addr = 0x10,
5737 .phy_base_addr = 0x0,
5738 .global1_addr = 0x1b,
5739 .global2_addr = 0x1c,
5740 .age_time_coeff = 15000,
5741 .g1_irqs = 9,
5742 .g2_irqs = 10,
5743 .atu_move_port_mask = 0xf,
5744 .pvt = true,
5745 .multi_chip = true,
5746 .ptp_support = true,
5747 .ops = &mv88e6165_ops,
5748 },
5749
5750 [MV88E6171] = {
5751 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5752 .family = MV88E6XXX_FAMILY_6351,
5753 .name = "Marvell 88E6171",
5754 .num_databases = 4096,
5755 .num_macs = 8192,
5756 .num_ports = 7,
5757 .num_internal_phys = 5,
5758 .max_vid = 4095,
5759 .max_sid = 63,
5760 .port_base_addr = 0x10,
5761 .phy_base_addr = 0x0,
5762 .global1_addr = 0x1b,
5763 .global2_addr = 0x1c,
5764 .age_time_coeff = 15000,
5765 .g1_irqs = 9,
5766 .g2_irqs = 10,
5767 .atu_move_port_mask = 0xf,
5768 .pvt = true,
5769 .multi_chip = true,
5770 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5771 .ops = &mv88e6171_ops,
5772 },
5773
5774 [MV88E6172] = {
5775 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5776 .family = MV88E6XXX_FAMILY_6352,
5777 .name = "Marvell 88E6172",
5778 .num_databases = 4096,
5779 .num_macs = 8192,
5780 .num_ports = 7,
5781 .num_internal_phys = 5,
5782 .num_gpio = 15,
5783 .max_vid = 4095,
5784 .max_sid = 63,
5785 .port_base_addr = 0x10,
5786 .phy_base_addr = 0x0,
5787 .global1_addr = 0x1b,
5788 .global2_addr = 0x1c,
5789 .age_time_coeff = 15000,
5790 .g1_irqs = 9,
5791 .g2_irqs = 10,
5792 .atu_move_port_mask = 0xf,
5793 .pvt = true,
5794 .multi_chip = true,
5795 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5796 .ops = &mv88e6172_ops,
5797 },
5798
5799 [MV88E6175] = {
5800 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5801 .family = MV88E6XXX_FAMILY_6351,
5802 .name = "Marvell 88E6175",
5803 .num_databases = 4096,
5804 .num_macs = 8192,
5805 .num_ports = 7,
5806 .num_internal_phys = 5,
5807 .max_vid = 4095,
5808 .max_sid = 63,
5809 .port_base_addr = 0x10,
5810 .phy_base_addr = 0x0,
5811 .global1_addr = 0x1b,
5812 .global2_addr = 0x1c,
5813 .age_time_coeff = 15000,
5814 .g1_irqs = 9,
5815 .g2_irqs = 10,
5816 .atu_move_port_mask = 0xf,
5817 .pvt = true,
5818 .multi_chip = true,
5819 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5820 .ops = &mv88e6175_ops,
5821 },
5822
5823 [MV88E6176] = {
5824 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5825 .family = MV88E6XXX_FAMILY_6352,
5826 .name = "Marvell 88E6176",
5827 .num_databases = 4096,
5828 .num_macs = 8192,
5829 .num_ports = 7,
5830 .num_internal_phys = 5,
5831 .num_gpio = 15,
5832 .max_vid = 4095,
5833 .max_sid = 63,
5834 .port_base_addr = 0x10,
5835 .phy_base_addr = 0x0,
5836 .global1_addr = 0x1b,
5837 .global2_addr = 0x1c,
5838 .age_time_coeff = 15000,
5839 .g1_irqs = 9,
5840 .g2_irqs = 10,
5841 .atu_move_port_mask = 0xf,
5842 .pvt = true,
5843 .multi_chip = true,
5844 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5845 .ops = &mv88e6176_ops,
5846 },
5847
5848 [MV88E6185] = {
5849 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5850 .family = MV88E6XXX_FAMILY_6185,
5851 .name = "Marvell 88E6185",
5852 .num_databases = 256,
5853 .num_macs = 8192,
5854 .num_ports = 10,
5855 .num_internal_phys = 0,
5856 .max_vid = 4095,
5857 .port_base_addr = 0x10,
5858 .phy_base_addr = 0x0,
5859 .global1_addr = 0x1b,
5860 .global2_addr = 0x1c,
5861 .age_time_coeff = 15000,
5862 .g1_irqs = 8,
5863 .atu_move_port_mask = 0xf,
5864 .multi_chip = true,
5865 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5866 .ops = &mv88e6185_ops,
5867 },
5868
5869 [MV88E6190] = {
5870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5871 .family = MV88E6XXX_FAMILY_6390,
5872 .name = "Marvell 88E6190",
5873 .num_databases = 4096,
5874 .num_macs = 16384,
5875 .num_ports = 11, /* 10 + Z80 */
5876 .num_internal_phys = 9,
5877 .num_gpio = 16,
5878 .max_vid = 8191,
5879 .max_sid = 63,
5880 .port_base_addr = 0x0,
5881 .phy_base_addr = 0x0,
5882 .global1_addr = 0x1b,
5883 .global2_addr = 0x1c,
5884 .age_time_coeff = 3750,
5885 .g1_irqs = 9,
5886 .g2_irqs = 14,
5887 .pvt = true,
5888 .multi_chip = true,
5889 .atu_move_port_mask = 0x1f,
5890 .ops = &mv88e6190_ops,
5891 },
5892
5893 [MV88E6190X] = {
5894 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5895 .family = MV88E6XXX_FAMILY_6390,
5896 .name = "Marvell 88E6190X",
5897 .num_databases = 4096,
5898 .num_macs = 16384,
5899 .num_ports = 11, /* 10 + Z80 */
5900 .num_internal_phys = 9,
5901 .num_gpio = 16,
5902 .max_vid = 8191,
5903 .max_sid = 63,
5904 .port_base_addr = 0x0,
5905 .phy_base_addr = 0x0,
5906 .global1_addr = 0x1b,
5907 .global2_addr = 0x1c,
5908 .age_time_coeff = 3750,
5909 .g1_irqs = 9,
5910 .g2_irqs = 14,
5911 .atu_move_port_mask = 0x1f,
5912 .pvt = true,
5913 .multi_chip = true,
5914 .ops = &mv88e6190x_ops,
5915 },
5916
5917 [MV88E6191] = {
5918 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5919 .family = MV88E6XXX_FAMILY_6390,
5920 .name = "Marvell 88E6191",
5921 .num_databases = 4096,
5922 .num_macs = 16384,
5923 .num_ports = 11, /* 10 + Z80 */
5924 .num_internal_phys = 9,
5925 .max_vid = 8191,
5926 .max_sid = 63,
5927 .port_base_addr = 0x0,
5928 .phy_base_addr = 0x0,
5929 .global1_addr = 0x1b,
5930 .global2_addr = 0x1c,
5931 .age_time_coeff = 3750,
5932 .g1_irqs = 9,
5933 .g2_irqs = 14,
5934 .atu_move_port_mask = 0x1f,
5935 .pvt = true,
5936 .multi_chip = true,
5937 .ptp_support = true,
5938 .ops = &mv88e6191_ops,
5939 },
5940
5941 [MV88E6191X] = {
5942 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5943 .family = MV88E6XXX_FAMILY_6393,
5944 .name = "Marvell 88E6191X",
5945 .num_databases = 4096,
5946 .num_ports = 11, /* 10 + Z80 */
5947 .num_internal_phys = 9,
5948 .max_vid = 8191,
5949 .max_sid = 63,
5950 .port_base_addr = 0x0,
5951 .phy_base_addr = 0x0,
5952 .global1_addr = 0x1b,
5953 .global2_addr = 0x1c,
5954 .age_time_coeff = 3750,
5955 .g1_irqs = 10,
5956 .g2_irqs = 14,
5957 .atu_move_port_mask = 0x1f,
5958 .pvt = true,
5959 .multi_chip = true,
5960 .ptp_support = true,
5961 .ops = &mv88e6393x_ops,
5962 },
5963
5964 [MV88E6193X] = {
5965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5966 .family = MV88E6XXX_FAMILY_6393,
5967 .name = "Marvell 88E6193X",
5968 .num_databases = 4096,
5969 .num_ports = 11, /* 10 + Z80 */
5970 .num_internal_phys = 9,
5971 .max_vid = 8191,
5972 .max_sid = 63,
5973 .port_base_addr = 0x0,
5974 .phy_base_addr = 0x0,
5975 .global1_addr = 0x1b,
5976 .global2_addr = 0x1c,
5977 .age_time_coeff = 3750,
5978 .g1_irqs = 10,
5979 .g2_irqs = 14,
5980 .atu_move_port_mask = 0x1f,
5981 .pvt = true,
5982 .multi_chip = true,
5983 .ptp_support = true,
5984 .ops = &mv88e6393x_ops,
5985 },
5986
5987 [MV88E6220] = {
5988 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5989 .family = MV88E6XXX_FAMILY_6250,
5990 .name = "Marvell 88E6220",
5991 .num_databases = 64,
5992
5993 /* Ports 2-4 are not routed to pins
5994 * => usable ports 0, 1, 5, 6
5995 */
5996 .num_ports = 7,
5997 .num_internal_phys = 2,
5998 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5999 .max_vid = 4095,
6000 .port_base_addr = 0x08,
6001 .phy_base_addr = 0x00,
6002 .global1_addr = 0x0f,
6003 .global2_addr = 0x07,
6004 .age_time_coeff = 15000,
6005 .g1_irqs = 9,
6006 .g2_irqs = 10,
6007 .atu_move_port_mask = 0xf,
6008 .dual_chip = true,
6009 .ptp_support = true,
6010 .ops = &mv88e6250_ops,
6011 },
6012
6013 [MV88E6240] = {
6014 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6015 .family = MV88E6XXX_FAMILY_6352,
6016 .name = "Marvell 88E6240",
6017 .num_databases = 4096,
6018 .num_macs = 8192,
6019 .num_ports = 7,
6020 .num_internal_phys = 5,
6021 .num_gpio = 15,
6022 .max_vid = 4095,
6023 .max_sid = 63,
6024 .port_base_addr = 0x10,
6025 .phy_base_addr = 0x0,
6026 .global1_addr = 0x1b,
6027 .global2_addr = 0x1c,
6028 .age_time_coeff = 15000,
6029 .g1_irqs = 9,
6030 .g2_irqs = 10,
6031 .atu_move_port_mask = 0xf,
6032 .pvt = true,
6033 .multi_chip = true,
6034 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6035 .ptp_support = true,
6036 .ops = &mv88e6240_ops,
6037 },
6038
6039 [MV88E6250] = {
6040 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6041 .family = MV88E6XXX_FAMILY_6250,
6042 .name = "Marvell 88E6250",
6043 .num_databases = 64,
6044 .num_ports = 7,
6045 .num_internal_phys = 5,
6046 .max_vid = 4095,
6047 .port_base_addr = 0x08,
6048 .phy_base_addr = 0x00,
6049 .global1_addr = 0x0f,
6050 .global2_addr = 0x07,
6051 .age_time_coeff = 15000,
6052 .g1_irqs = 9,
6053 .g2_irqs = 10,
6054 .atu_move_port_mask = 0xf,
6055 .dual_chip = true,
6056 .ptp_support = true,
6057 .ops = &mv88e6250_ops,
6058 },
6059
6060 [MV88E6290] = {
6061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6062 .family = MV88E6XXX_FAMILY_6390,
6063 .name = "Marvell 88E6290",
6064 .num_databases = 4096,
6065 .num_ports = 11, /* 10 + Z80 */
6066 .num_internal_phys = 9,
6067 .num_gpio = 16,
6068 .max_vid = 8191,
6069 .max_sid = 63,
6070 .port_base_addr = 0x0,
6071 .phy_base_addr = 0x0,
6072 .global1_addr = 0x1b,
6073 .global2_addr = 0x1c,
6074 .age_time_coeff = 3750,
6075 .g1_irqs = 9,
6076 .g2_irqs = 14,
6077 .atu_move_port_mask = 0x1f,
6078 .pvt = true,
6079 .multi_chip = true,
6080 .ptp_support = true,
6081 .ops = &mv88e6290_ops,
6082 },
6083
6084 [MV88E6320] = {
6085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6086 .family = MV88E6XXX_FAMILY_6320,
6087 .name = "Marvell 88E6320",
6088 .num_databases = 4096,
6089 .num_macs = 8192,
6090 .num_ports = 7,
6091 .num_internal_phys = 5,
6092 .num_gpio = 15,
6093 .max_vid = 4095,
6094 .port_base_addr = 0x10,
6095 .phy_base_addr = 0x0,
6096 .global1_addr = 0x1b,
6097 .global2_addr = 0x1c,
6098 .age_time_coeff = 15000,
6099 .g1_irqs = 8,
6100 .g2_irqs = 10,
6101 .atu_move_port_mask = 0xf,
6102 .pvt = true,
6103 .multi_chip = true,
6104 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6105 .ptp_support = true,
6106 .ops = &mv88e6320_ops,
6107 },
6108
6109 [MV88E6321] = {
6110 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6111 .family = MV88E6XXX_FAMILY_6320,
6112 .name = "Marvell 88E6321",
6113 .num_databases = 4096,
6114 .num_macs = 8192,
6115 .num_ports = 7,
6116 .num_internal_phys = 5,
6117 .num_gpio = 15,
6118 .max_vid = 4095,
6119 .port_base_addr = 0x10,
6120 .phy_base_addr = 0x0,
6121 .global1_addr = 0x1b,
6122 .global2_addr = 0x1c,
6123 .age_time_coeff = 15000,
6124 .g1_irqs = 8,
6125 .g2_irqs = 10,
6126 .atu_move_port_mask = 0xf,
6127 .multi_chip = true,
6128 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6129 .ptp_support = true,
6130 .ops = &mv88e6321_ops,
6131 },
6132
6133 [MV88E6341] = {
6134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6135 .family = MV88E6XXX_FAMILY_6341,
6136 .name = "Marvell 88E6341",
6137 .num_databases = 4096,
6138 .num_macs = 2048,
6139 .num_internal_phys = 5,
6140 .num_ports = 6,
6141 .num_gpio = 11,
6142 .max_vid = 4095,
6143 .max_sid = 63,
6144 .port_base_addr = 0x10,
6145 .phy_base_addr = 0x10,
6146 .global1_addr = 0x1b,
6147 .global2_addr = 0x1c,
6148 .age_time_coeff = 3750,
6149 .atu_move_port_mask = 0x1f,
6150 .g1_irqs = 9,
6151 .g2_irqs = 10,
6152 .pvt = true,
6153 .multi_chip = true,
6154 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6155 .ptp_support = true,
6156 .ops = &mv88e6341_ops,
6157 },
6158
6159 [MV88E6350] = {
6160 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6161 .family = MV88E6XXX_FAMILY_6351,
6162 .name = "Marvell 88E6350",
6163 .num_databases = 4096,
6164 .num_macs = 8192,
6165 .num_ports = 7,
6166 .num_internal_phys = 5,
6167 .max_vid = 4095,
6168 .max_sid = 63,
6169 .port_base_addr = 0x10,
6170 .phy_base_addr = 0x0,
6171 .global1_addr = 0x1b,
6172 .global2_addr = 0x1c,
6173 .age_time_coeff = 15000,
6174 .g1_irqs = 9,
6175 .g2_irqs = 10,
6176 .atu_move_port_mask = 0xf,
6177 .pvt = true,
6178 .multi_chip = true,
6179 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6180 .ops = &mv88e6350_ops,
6181 },
6182
6183 [MV88E6351] = {
6184 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6185 .family = MV88E6XXX_FAMILY_6351,
6186 .name = "Marvell 88E6351",
6187 .num_databases = 4096,
6188 .num_macs = 8192,
6189 .num_ports = 7,
6190 .num_internal_phys = 5,
6191 .max_vid = 4095,
6192 .max_sid = 63,
6193 .port_base_addr = 0x10,
6194 .phy_base_addr = 0x0,
6195 .global1_addr = 0x1b,
6196 .global2_addr = 0x1c,
6197 .age_time_coeff = 15000,
6198 .g1_irqs = 9,
6199 .g2_irqs = 10,
6200 .atu_move_port_mask = 0xf,
6201 .pvt = true,
6202 .multi_chip = true,
6203 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6204 .ops = &mv88e6351_ops,
6205 },
6206
6207 [MV88E6352] = {
6208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6209 .family = MV88E6XXX_FAMILY_6352,
6210 .name = "Marvell 88E6352",
6211 .num_databases = 4096,
6212 .num_macs = 8192,
6213 .num_ports = 7,
6214 .num_internal_phys = 5,
6215 .num_gpio = 15,
6216 .max_vid = 4095,
6217 .max_sid = 63,
6218 .port_base_addr = 0x10,
6219 .phy_base_addr = 0x0,
6220 .global1_addr = 0x1b,
6221 .global2_addr = 0x1c,
6222 .age_time_coeff = 15000,
6223 .g1_irqs = 9,
6224 .g2_irqs = 10,
6225 .atu_move_port_mask = 0xf,
6226 .pvt = true,
6227 .multi_chip = true,
6228 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6229 .ptp_support = true,
6230 .ops = &mv88e6352_ops,
6231 },
6232 [MV88E6390] = {
6233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6234 .family = MV88E6XXX_FAMILY_6390,
6235 .name = "Marvell 88E6390",
6236 .num_databases = 4096,
6237 .num_macs = 16384,
6238 .num_ports = 11, /* 10 + Z80 */
6239 .num_internal_phys = 9,
6240 .num_gpio = 16,
6241 .max_vid = 8191,
6242 .max_sid = 63,
6243 .port_base_addr = 0x0,
6244 .phy_base_addr = 0x0,
6245 .global1_addr = 0x1b,
6246 .global2_addr = 0x1c,
6247 .age_time_coeff = 3750,
6248 .g1_irqs = 9,
6249 .g2_irqs = 14,
6250 .atu_move_port_mask = 0x1f,
6251 .pvt = true,
6252 .multi_chip = true,
6253 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6254 .ptp_support = true,
6255 .ops = &mv88e6390_ops,
6256 },
6257 [MV88E6390X] = {
6258 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6259 .family = MV88E6XXX_FAMILY_6390,
6260 .name = "Marvell 88E6390X",
6261 .num_databases = 4096,
6262 .num_macs = 16384,
6263 .num_ports = 11, /* 10 + Z80 */
6264 .num_internal_phys = 9,
6265 .num_gpio = 16,
6266 .max_vid = 8191,
6267 .max_sid = 63,
6268 .port_base_addr = 0x0,
6269 .phy_base_addr = 0x0,
6270 .global1_addr = 0x1b,
6271 .global2_addr = 0x1c,
6272 .age_time_coeff = 3750,
6273 .g1_irqs = 9,
6274 .g2_irqs = 14,
6275 .atu_move_port_mask = 0x1f,
6276 .pvt = true,
6277 .multi_chip = true,
6278 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6279 .ptp_support = true,
6280 .ops = &mv88e6390x_ops,
6281 },
6282
6283 [MV88E6393X] = {
6284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6285 .family = MV88E6XXX_FAMILY_6393,
6286 .name = "Marvell 88E6393X",
6287 .num_databases = 4096,
6288 .num_ports = 11, /* 10 + Z80 */
6289 .num_internal_phys = 9,
6290 .max_vid = 8191,
6291 .max_sid = 63,
6292 .port_base_addr = 0x0,
6293 .phy_base_addr = 0x0,
6294 .global1_addr = 0x1b,
6295 .global2_addr = 0x1c,
6296 .age_time_coeff = 3750,
6297 .g1_irqs = 10,
6298 .g2_irqs = 14,
6299 .atu_move_port_mask = 0x1f,
6300 .pvt = true,
6301 .multi_chip = true,
6302 .ptp_support = true,
6303 .ops = &mv88e6393x_ops,
6304 },
6305 };
6306
mv88e6xxx_lookup_info(unsigned int prod_num)6307 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6308 {
6309 int i;
6310
6311 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6312 if (mv88e6xxx_table[i].prod_num == prod_num)
6313 return &mv88e6xxx_table[i];
6314
6315 return NULL;
6316 }
6317
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6318 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6319 {
6320 const struct mv88e6xxx_info *info;
6321 unsigned int prod_num, rev;
6322 u16 id;
6323 int err;
6324
6325 mv88e6xxx_reg_lock(chip);
6326 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6327 mv88e6xxx_reg_unlock(chip);
6328 if (err)
6329 return err;
6330
6331 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6332 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6333
6334 info = mv88e6xxx_lookup_info(prod_num);
6335 if (!info)
6336 return -ENODEV;
6337
6338 /* Update the compatible info with the probed one */
6339 chip->info = info;
6340
6341 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6342 chip->info->prod_num, chip->info->name, rev);
6343
6344 return 0;
6345 }
6346
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)6347 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6348 struct mdio_device *mdiodev)
6349 {
6350 int err;
6351
6352 /* dual_chip takes precedence over single/multi-chip modes */
6353 if (chip->info->dual_chip)
6354 return -EINVAL;
6355
6356 /* If the mdio addr is 16 indicating the first port address of a switch
6357 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6358 * configured in single chip addressing mode. Setup the smi access as
6359 * single chip addressing mode and attempt to detect the model of the
6360 * switch, if this fails the device is not configured in single chip
6361 * addressing mode.
6362 */
6363 if (mdiodev->addr != 16)
6364 return -EINVAL;
6365
6366 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6367 if (err)
6368 return err;
6369
6370 return mv88e6xxx_detect(chip);
6371 }
6372
mv88e6xxx_alloc_chip(struct device * dev)6373 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6374 {
6375 struct mv88e6xxx_chip *chip;
6376
6377 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6378 if (!chip)
6379 return NULL;
6380
6381 chip->dev = dev;
6382
6383 mutex_init(&chip->reg_lock);
6384 INIT_LIST_HEAD(&chip->mdios);
6385 idr_init(&chip->policies);
6386 INIT_LIST_HEAD(&chip->msts);
6387
6388 return chip;
6389 }
6390
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)6391 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6392 int port,
6393 enum dsa_tag_protocol m)
6394 {
6395 struct mv88e6xxx_chip *chip = ds->priv;
6396
6397 return chip->tag_protocol;
6398 }
6399
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6400 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6401 enum dsa_tag_protocol proto)
6402 {
6403 struct mv88e6xxx_chip *chip = ds->priv;
6404 enum dsa_tag_protocol old_protocol;
6405 struct dsa_port *cpu_dp;
6406 int err;
6407
6408 switch (proto) {
6409 case DSA_TAG_PROTO_EDSA:
6410 switch (chip->info->edsa_support) {
6411 case MV88E6XXX_EDSA_UNSUPPORTED:
6412 return -EPROTONOSUPPORT;
6413 case MV88E6XXX_EDSA_UNDOCUMENTED:
6414 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6415 fallthrough;
6416 case MV88E6XXX_EDSA_SUPPORTED:
6417 break;
6418 }
6419 break;
6420 case DSA_TAG_PROTO_DSA:
6421 break;
6422 default:
6423 return -EPROTONOSUPPORT;
6424 }
6425
6426 old_protocol = chip->tag_protocol;
6427 chip->tag_protocol = proto;
6428
6429 mv88e6xxx_reg_lock(chip);
6430 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6431 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6432 if (err) {
6433 mv88e6xxx_reg_unlock(chip);
6434 goto unwind;
6435 }
6436 }
6437 mv88e6xxx_reg_unlock(chip);
6438
6439 return 0;
6440
6441 unwind:
6442 chip->tag_protocol = old_protocol;
6443
6444 mv88e6xxx_reg_lock(chip);
6445 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6446 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6447 mv88e6xxx_reg_unlock(chip);
6448
6449 return err;
6450 }
6451
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6452 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6453 const struct switchdev_obj_port_mdb *mdb,
6454 struct dsa_db db)
6455 {
6456 struct mv88e6xxx_chip *chip = ds->priv;
6457 int err;
6458
6459 mv88e6xxx_reg_lock(chip);
6460 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6461 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6462 mv88e6xxx_reg_unlock(chip);
6463
6464 return err;
6465 }
6466
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6467 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6468 const struct switchdev_obj_port_mdb *mdb,
6469 struct dsa_db db)
6470 {
6471 struct mv88e6xxx_chip *chip = ds->priv;
6472 int err;
6473
6474 mv88e6xxx_reg_lock(chip);
6475 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6476 mv88e6xxx_reg_unlock(chip);
6477
6478 return err;
6479 }
6480
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6481 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6482 struct dsa_mall_mirror_tc_entry *mirror,
6483 bool ingress,
6484 struct netlink_ext_ack *extack)
6485 {
6486 enum mv88e6xxx_egress_direction direction = ingress ?
6487 MV88E6XXX_EGRESS_DIR_INGRESS :
6488 MV88E6XXX_EGRESS_DIR_EGRESS;
6489 struct mv88e6xxx_chip *chip = ds->priv;
6490 bool other_mirrors = false;
6491 int i;
6492 int err;
6493
6494 mutex_lock(&chip->reg_lock);
6495 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6496 mirror->to_local_port) {
6497 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6498 other_mirrors |= ingress ?
6499 chip->ports[i].mirror_ingress :
6500 chip->ports[i].mirror_egress;
6501
6502 /* Can't change egress port when other mirror is active */
6503 if (other_mirrors) {
6504 err = -EBUSY;
6505 goto out;
6506 }
6507
6508 err = mv88e6xxx_set_egress_port(chip, direction,
6509 mirror->to_local_port);
6510 if (err)
6511 goto out;
6512 }
6513
6514 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6515 out:
6516 mutex_unlock(&chip->reg_lock);
6517
6518 return err;
6519 }
6520
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6521 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6522 struct dsa_mall_mirror_tc_entry *mirror)
6523 {
6524 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6525 MV88E6XXX_EGRESS_DIR_INGRESS :
6526 MV88E6XXX_EGRESS_DIR_EGRESS;
6527 struct mv88e6xxx_chip *chip = ds->priv;
6528 bool other_mirrors = false;
6529 int i;
6530
6531 mutex_lock(&chip->reg_lock);
6532 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6533 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6534
6535 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6536 other_mirrors |= mirror->ingress ?
6537 chip->ports[i].mirror_ingress :
6538 chip->ports[i].mirror_egress;
6539
6540 /* Reset egress port when no other mirror is active */
6541 if (!other_mirrors) {
6542 if (mv88e6xxx_set_egress_port(chip, direction,
6543 dsa_upstream_port(ds, port)))
6544 dev_err(ds->dev, "failed to set egress port\n");
6545 }
6546
6547 mutex_unlock(&chip->reg_lock);
6548 }
6549
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6550 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6551 struct switchdev_brport_flags flags,
6552 struct netlink_ext_ack *extack)
6553 {
6554 struct mv88e6xxx_chip *chip = ds->priv;
6555 const struct mv88e6xxx_ops *ops;
6556
6557 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6558 BR_BCAST_FLOOD | BR_PORT_LOCKED))
6559 return -EINVAL;
6560
6561 ops = chip->info->ops;
6562
6563 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6564 return -EINVAL;
6565
6566 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6567 return -EINVAL;
6568
6569 return 0;
6570 }
6571
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6572 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6573 struct switchdev_brport_flags flags,
6574 struct netlink_ext_ack *extack)
6575 {
6576 struct mv88e6xxx_chip *chip = ds->priv;
6577 int err = -EOPNOTSUPP;
6578
6579 mv88e6xxx_reg_lock(chip);
6580
6581 if (flags.mask & BR_LEARNING) {
6582 bool learning = !!(flags.val & BR_LEARNING);
6583 u16 pav = learning ? (1 << port) : 0;
6584
6585 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6586 if (err)
6587 goto out;
6588 }
6589
6590 if (flags.mask & BR_FLOOD) {
6591 bool unicast = !!(flags.val & BR_FLOOD);
6592
6593 err = chip->info->ops->port_set_ucast_flood(chip, port,
6594 unicast);
6595 if (err)
6596 goto out;
6597 }
6598
6599 if (flags.mask & BR_MCAST_FLOOD) {
6600 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6601
6602 err = chip->info->ops->port_set_mcast_flood(chip, port,
6603 multicast);
6604 if (err)
6605 goto out;
6606 }
6607
6608 if (flags.mask & BR_BCAST_FLOOD) {
6609 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6610
6611 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6612 if (err)
6613 goto out;
6614 }
6615
6616 if (flags.mask & BR_PORT_LOCKED) {
6617 bool locked = !!(flags.val & BR_PORT_LOCKED);
6618
6619 err = mv88e6xxx_port_set_lock(chip, port, locked);
6620 if (err)
6621 goto out;
6622 }
6623 out:
6624 mv88e6xxx_reg_unlock(chip);
6625
6626 return err;
6627 }
6628
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6629 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6630 struct dsa_lag lag,
6631 struct netdev_lag_upper_info *info,
6632 struct netlink_ext_ack *extack)
6633 {
6634 struct mv88e6xxx_chip *chip = ds->priv;
6635 struct dsa_port *dp;
6636 int members = 0;
6637
6638 if (!mv88e6xxx_has_lag(chip)) {
6639 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6640 return false;
6641 }
6642
6643 if (!lag.id)
6644 return false;
6645
6646 dsa_lag_foreach_port(dp, ds->dst, &lag)
6647 /* Includes the port joining the LAG */
6648 members++;
6649
6650 if (members > 8) {
6651 NL_SET_ERR_MSG_MOD(extack,
6652 "Cannot offload more than 8 LAG ports");
6653 return false;
6654 }
6655
6656 /* We could potentially relax this to include active
6657 * backup in the future.
6658 */
6659 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6660 NL_SET_ERR_MSG_MOD(extack,
6661 "Can only offload LAG using hash TX type");
6662 return false;
6663 }
6664
6665 /* Ideally we would also validate that the hash type matches
6666 * the hardware. Alas, this is always set to unknown on team
6667 * interfaces.
6668 */
6669 return true;
6670 }
6671
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6672 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6673 {
6674 struct mv88e6xxx_chip *chip = ds->priv;
6675 struct dsa_port *dp;
6676 u16 map = 0;
6677 int id;
6678
6679 /* DSA LAG IDs are one-based, hardware is zero-based */
6680 id = lag.id - 1;
6681
6682 /* Build the map of all ports to distribute flows destined for
6683 * this LAG. This can be either a local user port, or a DSA
6684 * port if the LAG port is on a remote chip.
6685 */
6686 dsa_lag_foreach_port(dp, ds->dst, &lag)
6687 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6688
6689 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6690 }
6691
6692 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6693 /* Row number corresponds to the number of active members in a
6694 * LAG. Each column states which of the eight hash buckets are
6695 * mapped to the column:th port in the LAG.
6696 *
6697 * Example: In a LAG with three active ports, the second port
6698 * ([2][1]) would be selected for traffic mapped to buckets
6699 * 3,4,5 (0x38).
6700 */
6701 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6702 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6703 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6704 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6705 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6706 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6707 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6708 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6709 };
6710
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6711 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6712 int num_tx, int nth)
6713 {
6714 u8 active = 0;
6715 int i;
6716
6717 num_tx = num_tx <= 8 ? num_tx : 8;
6718 if (nth < num_tx)
6719 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6720
6721 for (i = 0; i < 8; i++) {
6722 if (BIT(i) & active)
6723 mask[i] |= BIT(port);
6724 }
6725 }
6726
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6727 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6728 {
6729 struct mv88e6xxx_chip *chip = ds->priv;
6730 unsigned int id, num_tx;
6731 struct dsa_port *dp;
6732 struct dsa_lag *lag;
6733 int i, err, nth;
6734 u16 mask[8];
6735 u16 ivec;
6736
6737 /* Assume no port is a member of any LAG. */
6738 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6739
6740 /* Disable all masks for ports that _are_ members of a LAG. */
6741 dsa_switch_for_each_port(dp, ds) {
6742 if (!dp->lag)
6743 continue;
6744
6745 ivec &= ~BIT(dp->index);
6746 }
6747
6748 for (i = 0; i < 8; i++)
6749 mask[i] = ivec;
6750
6751 /* Enable the correct subset of masks for all LAG ports that
6752 * are in the Tx set.
6753 */
6754 dsa_lags_foreach_id(id, ds->dst) {
6755 lag = dsa_lag_by_id(ds->dst, id);
6756 if (!lag)
6757 continue;
6758
6759 num_tx = 0;
6760 dsa_lag_foreach_port(dp, ds->dst, lag) {
6761 if (dp->lag_tx_enabled)
6762 num_tx++;
6763 }
6764
6765 if (!num_tx)
6766 continue;
6767
6768 nth = 0;
6769 dsa_lag_foreach_port(dp, ds->dst, lag) {
6770 if (!dp->lag_tx_enabled)
6771 continue;
6772
6773 if (dp->ds == ds)
6774 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6775 num_tx, nth);
6776
6777 nth++;
6778 }
6779 }
6780
6781 for (i = 0; i < 8; i++) {
6782 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6783 if (err)
6784 return err;
6785 }
6786
6787 return 0;
6788 }
6789
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)6790 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6791 struct dsa_lag lag)
6792 {
6793 int err;
6794
6795 err = mv88e6xxx_lag_sync_masks(ds);
6796
6797 if (!err)
6798 err = mv88e6xxx_lag_sync_map(ds, lag);
6799
6800 return err;
6801 }
6802
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)6803 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6804 {
6805 struct mv88e6xxx_chip *chip = ds->priv;
6806 int err;
6807
6808 mv88e6xxx_reg_lock(chip);
6809 err = mv88e6xxx_lag_sync_masks(ds);
6810 mv88e6xxx_reg_unlock(chip);
6811 return err;
6812 }
6813
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6814 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6815 struct dsa_lag lag,
6816 struct netdev_lag_upper_info *info,
6817 struct netlink_ext_ack *extack)
6818 {
6819 struct mv88e6xxx_chip *chip = ds->priv;
6820 int err, id;
6821
6822 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6823 return -EOPNOTSUPP;
6824
6825 /* DSA LAG IDs are one-based */
6826 id = lag.id - 1;
6827
6828 mv88e6xxx_reg_lock(chip);
6829
6830 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6831 if (err)
6832 goto err_unlock;
6833
6834 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6835 if (err)
6836 goto err_clear_trunk;
6837
6838 mv88e6xxx_reg_unlock(chip);
6839 return 0;
6840
6841 err_clear_trunk:
6842 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6843 err_unlock:
6844 mv88e6xxx_reg_unlock(chip);
6845 return err;
6846 }
6847
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)6848 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6849 struct dsa_lag lag)
6850 {
6851 struct mv88e6xxx_chip *chip = ds->priv;
6852 int err_sync, err_trunk;
6853
6854 mv88e6xxx_reg_lock(chip);
6855 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6856 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6857 mv88e6xxx_reg_unlock(chip);
6858 return err_sync ? : err_trunk;
6859 }
6860
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)6861 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6862 int port)
6863 {
6864 struct mv88e6xxx_chip *chip = ds->priv;
6865 int err;
6866
6867 mv88e6xxx_reg_lock(chip);
6868 err = mv88e6xxx_lag_sync_masks(ds);
6869 mv88e6xxx_reg_unlock(chip);
6870 return err;
6871 }
6872
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6873 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6874 int port, struct dsa_lag lag,
6875 struct netdev_lag_upper_info *info,
6876 struct netlink_ext_ack *extack)
6877 {
6878 struct mv88e6xxx_chip *chip = ds->priv;
6879 int err;
6880
6881 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6882 return -EOPNOTSUPP;
6883
6884 mv88e6xxx_reg_lock(chip);
6885
6886 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6887 if (err)
6888 goto unlock;
6889
6890 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6891
6892 unlock:
6893 mv88e6xxx_reg_unlock(chip);
6894 return err;
6895 }
6896
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)6897 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6898 int port, struct dsa_lag lag)
6899 {
6900 struct mv88e6xxx_chip *chip = ds->priv;
6901 int err_sync, err_pvt;
6902
6903 mv88e6xxx_reg_lock(chip);
6904 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6905 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6906 mv88e6xxx_reg_unlock(chip);
6907 return err_sync ? : err_pvt;
6908 }
6909
6910 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6911 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6912 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6913 .setup = mv88e6xxx_setup,
6914 .teardown = mv88e6xxx_teardown,
6915 .port_setup = mv88e6xxx_port_setup,
6916 .port_teardown = mv88e6xxx_port_teardown,
6917 .phylink_get_caps = mv88e6xxx_get_caps,
6918 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6919 .phylink_mac_config = mv88e6xxx_mac_config,
6920 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6921 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6922 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6923 .get_strings = mv88e6xxx_get_strings,
6924 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6925 .get_sset_count = mv88e6xxx_get_sset_count,
6926 .port_enable = mv88e6xxx_port_enable,
6927 .port_disable = mv88e6xxx_port_disable,
6928 .port_max_mtu = mv88e6xxx_get_max_mtu,
6929 .port_change_mtu = mv88e6xxx_change_mtu,
6930 .get_mac_eee = mv88e6xxx_get_mac_eee,
6931 .set_mac_eee = mv88e6xxx_set_mac_eee,
6932 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6933 .get_eeprom = mv88e6xxx_get_eeprom,
6934 .set_eeprom = mv88e6xxx_set_eeprom,
6935 .get_regs_len = mv88e6xxx_get_regs_len,
6936 .get_regs = mv88e6xxx_get_regs,
6937 .get_rxnfc = mv88e6xxx_get_rxnfc,
6938 .set_rxnfc = mv88e6xxx_set_rxnfc,
6939 .set_ageing_time = mv88e6xxx_set_ageing_time,
6940 .port_bridge_join = mv88e6xxx_port_bridge_join,
6941 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6942 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6943 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6944 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6945 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6946 .port_fast_age = mv88e6xxx_port_fast_age,
6947 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6948 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6949 .port_vlan_add = mv88e6xxx_port_vlan_add,
6950 .port_vlan_del = mv88e6xxx_port_vlan_del,
6951 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6952 .port_fdb_add = mv88e6xxx_port_fdb_add,
6953 .port_fdb_del = mv88e6xxx_port_fdb_del,
6954 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6955 .port_mdb_add = mv88e6xxx_port_mdb_add,
6956 .port_mdb_del = mv88e6xxx_port_mdb_del,
6957 .port_mirror_add = mv88e6xxx_port_mirror_add,
6958 .port_mirror_del = mv88e6xxx_port_mirror_del,
6959 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6960 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6961 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6962 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6963 .port_txtstamp = mv88e6xxx_port_txtstamp,
6964 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6965 .get_ts_info = mv88e6xxx_get_ts_info,
6966 .devlink_param_get = mv88e6xxx_devlink_param_get,
6967 .devlink_param_set = mv88e6xxx_devlink_param_set,
6968 .devlink_info_get = mv88e6xxx_devlink_info_get,
6969 .port_lag_change = mv88e6xxx_port_lag_change,
6970 .port_lag_join = mv88e6xxx_port_lag_join,
6971 .port_lag_leave = mv88e6xxx_port_lag_leave,
6972 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6973 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6974 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6975 };
6976
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)6977 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6978 {
6979 struct device *dev = chip->dev;
6980 struct dsa_switch *ds;
6981
6982 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6983 if (!ds)
6984 return -ENOMEM;
6985
6986 ds->dev = dev;
6987 ds->num_ports = mv88e6xxx_num_ports(chip);
6988 ds->priv = chip;
6989 ds->dev = dev;
6990 ds->ops = &mv88e6xxx_switch_ops;
6991 ds->ageing_time_min = chip->info->age_time_coeff;
6992 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6993
6994 /* Some chips support up to 32, but that requires enabling the
6995 * 5-bit port mode, which we do not support. 640k^W16 ought to
6996 * be enough for anyone.
6997 */
6998 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6999
7000 dev_set_drvdata(dev, ds);
7001
7002 return dsa_register_switch(ds);
7003 }
7004
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7005 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7006 {
7007 dsa_unregister_switch(chip->ds);
7008 }
7009
pdata_device_get_match_data(struct device * dev)7010 static const void *pdata_device_get_match_data(struct device *dev)
7011 {
7012 const struct of_device_id *matches = dev->driver->of_match_table;
7013 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7014
7015 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7016 matches++) {
7017 if (!strcmp(pdata->compatible, matches->compatible))
7018 return matches->data;
7019 }
7020 return NULL;
7021 }
7022
7023 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7024 * would be lost after a power cycle so prevent it to be suspended.
7025 */
mv88e6xxx_suspend(struct device * dev)7026 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7027 {
7028 return -EOPNOTSUPP;
7029 }
7030
mv88e6xxx_resume(struct device * dev)7031 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7032 {
7033 return 0;
7034 }
7035
7036 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7037
mv88e6xxx_probe(struct mdio_device * mdiodev)7038 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7039 {
7040 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7041 const struct mv88e6xxx_info *compat_info = NULL;
7042 struct device *dev = &mdiodev->dev;
7043 struct device_node *np = dev->of_node;
7044 struct mv88e6xxx_chip *chip;
7045 int port;
7046 int err;
7047
7048 if (!np && !pdata)
7049 return -EINVAL;
7050
7051 if (np)
7052 compat_info = of_device_get_match_data(dev);
7053
7054 if (pdata) {
7055 compat_info = pdata_device_get_match_data(dev);
7056
7057 if (!pdata->netdev)
7058 return -EINVAL;
7059
7060 for (port = 0; port < DSA_MAX_PORTS; port++) {
7061 if (!(pdata->enabled_ports & (1 << port)))
7062 continue;
7063 if (strcmp(pdata->cd.port_names[port], "cpu"))
7064 continue;
7065 pdata->cd.netdev[port] = &pdata->netdev->dev;
7066 break;
7067 }
7068 }
7069
7070 if (!compat_info)
7071 return -EINVAL;
7072
7073 chip = mv88e6xxx_alloc_chip(dev);
7074 if (!chip) {
7075 err = -ENOMEM;
7076 goto out;
7077 }
7078
7079 chip->info = compat_info;
7080
7081 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7082 if (IS_ERR(chip->reset)) {
7083 err = PTR_ERR(chip->reset);
7084 goto out;
7085 }
7086 if (chip->reset)
7087 usleep_range(10000, 20000);
7088
7089 /* Detect if the device is configured in single chip addressing mode,
7090 * otherwise continue with address specific smi init/detection.
7091 */
7092 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7093 if (err) {
7094 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7095 if (err)
7096 goto out;
7097
7098 err = mv88e6xxx_detect(chip);
7099 if (err)
7100 goto out;
7101 }
7102
7103 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7104 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7105 else
7106 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7107
7108 mv88e6xxx_phy_init(chip);
7109
7110 if (chip->info->ops->get_eeprom) {
7111 if (np)
7112 of_property_read_u32(np, "eeprom-length",
7113 &chip->eeprom_len);
7114 else
7115 chip->eeprom_len = pdata->eeprom_len;
7116 }
7117
7118 mv88e6xxx_reg_lock(chip);
7119 err = mv88e6xxx_switch_reset(chip);
7120 mv88e6xxx_reg_unlock(chip);
7121 if (err)
7122 goto out;
7123
7124 if (np) {
7125 chip->irq = of_irq_get(np, 0);
7126 if (chip->irq == -EPROBE_DEFER) {
7127 err = chip->irq;
7128 goto out;
7129 }
7130 }
7131
7132 if (pdata)
7133 chip->irq = pdata->irq;
7134
7135 /* Has to be performed before the MDIO bus is created, because
7136 * the PHYs will link their interrupts to these interrupt
7137 * controllers
7138 */
7139 mv88e6xxx_reg_lock(chip);
7140 if (chip->irq > 0)
7141 err = mv88e6xxx_g1_irq_setup(chip);
7142 else
7143 err = mv88e6xxx_irq_poll_setup(chip);
7144 mv88e6xxx_reg_unlock(chip);
7145
7146 if (err)
7147 goto out;
7148
7149 if (chip->info->g2_irqs > 0) {
7150 err = mv88e6xxx_g2_irq_setup(chip);
7151 if (err)
7152 goto out_g1_irq;
7153 }
7154
7155 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7156 if (err)
7157 goto out_g2_irq;
7158
7159 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7160 if (err)
7161 goto out_g1_atu_prob_irq;
7162
7163 err = mv88e6xxx_mdios_register(chip, np);
7164 if (err)
7165 goto out_g1_vtu_prob_irq;
7166
7167 err = mv88e6xxx_register_switch(chip);
7168 if (err)
7169 goto out_mdio;
7170
7171 return 0;
7172
7173 out_mdio:
7174 mv88e6xxx_mdios_unregister(chip);
7175 out_g1_vtu_prob_irq:
7176 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7177 out_g1_atu_prob_irq:
7178 mv88e6xxx_g1_atu_prob_irq_free(chip);
7179 out_g2_irq:
7180 if (chip->info->g2_irqs > 0)
7181 mv88e6xxx_g2_irq_free(chip);
7182 out_g1_irq:
7183 if (chip->irq > 0)
7184 mv88e6xxx_g1_irq_free(chip);
7185 else
7186 mv88e6xxx_irq_poll_free(chip);
7187 out:
7188 if (pdata)
7189 dev_put(pdata->netdev);
7190
7191 return err;
7192 }
7193
mv88e6xxx_remove(struct mdio_device * mdiodev)7194 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7195 {
7196 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7197 struct mv88e6xxx_chip *chip;
7198
7199 if (!ds)
7200 return;
7201
7202 chip = ds->priv;
7203
7204 if (chip->info->ptp_support) {
7205 mv88e6xxx_hwtstamp_free(chip);
7206 mv88e6xxx_ptp_free(chip);
7207 }
7208
7209 mv88e6xxx_phy_destroy(chip);
7210 mv88e6xxx_unregister_switch(chip);
7211 mv88e6xxx_mdios_unregister(chip);
7212
7213 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7214 mv88e6xxx_g1_atu_prob_irq_free(chip);
7215
7216 if (chip->info->g2_irqs > 0)
7217 mv88e6xxx_g2_irq_free(chip);
7218
7219 if (chip->irq > 0)
7220 mv88e6xxx_g1_irq_free(chip);
7221 else
7222 mv88e6xxx_irq_poll_free(chip);
7223 }
7224
mv88e6xxx_shutdown(struct mdio_device * mdiodev)7225 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7226 {
7227 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7228
7229 if (!ds)
7230 return;
7231
7232 dsa_switch_shutdown(ds);
7233
7234 dev_set_drvdata(&mdiodev->dev, NULL);
7235 }
7236
7237 static const struct of_device_id mv88e6xxx_of_match[] = {
7238 {
7239 .compatible = "marvell,mv88e6085",
7240 .data = &mv88e6xxx_table[MV88E6085],
7241 },
7242 {
7243 .compatible = "marvell,mv88e6190",
7244 .data = &mv88e6xxx_table[MV88E6190],
7245 },
7246 {
7247 .compatible = "marvell,mv88e6250",
7248 .data = &mv88e6xxx_table[MV88E6250],
7249 },
7250 { /* sentinel */ },
7251 };
7252
7253 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7254
7255 static struct mdio_driver mv88e6xxx_driver = {
7256 .probe = mv88e6xxx_probe,
7257 .remove = mv88e6xxx_remove,
7258 .shutdown = mv88e6xxx_shutdown,
7259 .mdiodrv.driver = {
7260 .name = "mv88e6085",
7261 .of_match_table = mv88e6xxx_of_match,
7262 .pm = &mv88e6xxx_pm_ops,
7263 },
7264 };
7265
7266 mdio_module_driver(mv88e6xxx_driver);
7267
7268 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7269 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7270 MODULE_LICENSE("GPL");
7271