1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/phy.h>
29 #include <linux/phylink.h>
30 #include <linux/phy/phy.h>
31 #include <linux/ptp_classify.h>
32 #include <linux/clk.h>
33 #include <linux/hrtimer.h>
34 #include <linux/ktime.h>
35 #include <linux/regmap.h>
36 #include <uapi/linux/ppp_defs.h>
37 #include <net/ip.h>
38 #include <net/ipv6.h>
39 #include <net/tso.h>
40 #include <linux/bpf_trace.h>
41
42 #include "mvpp2.h"
43 #include "mvpp2_prs.h"
44 #include "mvpp2_cls.h"
45
46 enum mvpp2_bm_pool_log_num {
47 MVPP2_BM_SHORT,
48 MVPP2_BM_LONG,
49 MVPP2_BM_JUMBO,
50 MVPP2_BM_POOLS_NUM
51 };
52
53 static struct {
54 int pkt_size;
55 int buf_num;
56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
57
58 /* The prototype is added here to be used in start_dev when using ACPI. This
59 * will be removed once phylink is used for all modes (dt+ACPI).
60 */
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
62
63 /* Queue modes */
64 #define MVPP2_QDIST_SINGLE_MODE 0
65 #define MVPP2_QDIST_MULTI_MODE 1
66
67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
68
69 module_param(queue_mode, int, 0444);
70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
71
72 /* Utility/helper methods */
73
mvpp2_write(struct mvpp2 * priv,u32 offset,u32 data)74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
75 {
76 writel(data, priv->swth_base[0] + offset);
77 }
78
mvpp2_read(struct mvpp2 * priv,u32 offset)79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
80 {
81 return readl(priv->swth_base[0] + offset);
82 }
83
mvpp2_read_relaxed(struct mvpp2 * priv,u32 offset)84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
85 {
86 return readl_relaxed(priv->swth_base[0] + offset);
87 }
88
mvpp2_cpu_to_thread(struct mvpp2 * priv,int cpu)89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
90 {
91 return cpu % priv->nthreads;
92 }
93
mvpp2_cm3_write(struct mvpp2 * priv,u32 offset,u32 data)94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
95 {
96 writel(data, priv->cm3_base + offset);
97 }
98
mvpp2_cm3_read(struct mvpp2 * priv,u32 offset)99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
100 {
101 return readl(priv->cm3_base + offset);
102 }
103
104 static struct page_pool *
mvpp2_create_page_pool(struct device * dev,int num,int len,enum dma_data_direction dma_dir)105 mvpp2_create_page_pool(struct device *dev, int num, int len,
106 enum dma_data_direction dma_dir)
107 {
108 struct page_pool_params pp_params = {
109 /* internal DMA mapping in page_pool */
110 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
111 .pool_size = num,
112 .nid = NUMA_NO_NODE,
113 .dev = dev,
114 .dma_dir = dma_dir,
115 .offset = MVPP2_SKB_HEADROOM,
116 .max_len = len,
117 };
118
119 return page_pool_create(&pp_params);
120 }
121
122 /* These accessors should be used to access:
123 *
124 * - per-thread registers, where each thread has its own copy of the
125 * register.
126 *
127 * MVPP2_BM_VIRT_ALLOC_REG
128 * MVPP2_BM_ADDR_HIGH_ALLOC
129 * MVPP22_BM_ADDR_HIGH_RLS_REG
130 * MVPP2_BM_VIRT_RLS_REG
131 * MVPP2_ISR_RX_TX_CAUSE_REG
132 * MVPP2_ISR_RX_TX_MASK_REG
133 * MVPP2_TXQ_NUM_REG
134 * MVPP2_AGGR_TXQ_UPDATE_REG
135 * MVPP2_TXQ_RSVD_REQ_REG
136 * MVPP2_TXQ_RSVD_RSLT_REG
137 * MVPP2_TXQ_SENT_REG
138 * MVPP2_RXQ_NUM_REG
139 *
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
142 * register
143 *
144 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
145 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
146 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
147 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
148 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
149 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
150 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
151 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
152 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
153 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
154 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
155 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
156 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
157 */
mvpp2_thread_write(struct mvpp2 * priv,unsigned int thread,u32 offset,u32 data)158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
159 u32 offset, u32 data)
160 {
161 writel(data, priv->swth_base[thread] + offset);
162 }
163
mvpp2_thread_read(struct mvpp2 * priv,unsigned int thread,u32 offset)164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
165 u32 offset)
166 {
167 return readl(priv->swth_base[thread] + offset);
168 }
169
mvpp2_thread_write_relaxed(struct mvpp2 * priv,unsigned int thread,u32 offset,u32 data)170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
171 u32 offset, u32 data)
172 {
173 writel_relaxed(data, priv->swth_base[thread] + offset);
174 }
175
mvpp2_thread_read_relaxed(struct mvpp2 * priv,unsigned int thread,u32 offset)176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
177 u32 offset)
178 {
179 return readl_relaxed(priv->swth_base[thread] + offset);
180 }
181
mvpp2_txdesc_dma_addr_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
183 struct mvpp2_tx_desc *tx_desc)
184 {
185 if (port->priv->hw_version == MVPP21)
186 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
187 else
188 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
189 MVPP2_DESC_DMA_MASK;
190 }
191
mvpp2_txdesc_dma_addr_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,dma_addr_t dma_addr)192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
193 struct mvpp2_tx_desc *tx_desc,
194 dma_addr_t dma_addr)
195 {
196 dma_addr_t addr, offset;
197
198 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
199 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
200
201 if (port->priv->hw_version == MVPP21) {
202 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
203 tx_desc->pp21.packet_offset = offset;
204 } else {
205 __le64 val = cpu_to_le64(addr);
206
207 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
208 tx_desc->pp22.buf_dma_addr_ptp |= val;
209 tx_desc->pp22.packet_offset = offset;
210 }
211 }
212
mvpp2_txdesc_size_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
214 struct mvpp2_tx_desc *tx_desc)
215 {
216 if (port->priv->hw_version == MVPP21)
217 return le16_to_cpu(tx_desc->pp21.data_size);
218 else
219 return le16_to_cpu(tx_desc->pp22.data_size);
220 }
221
mvpp2_txdesc_size_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,size_t size)222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
223 struct mvpp2_tx_desc *tx_desc,
224 size_t size)
225 {
226 if (port->priv->hw_version == MVPP21)
227 tx_desc->pp21.data_size = cpu_to_le16(size);
228 else
229 tx_desc->pp22.data_size = cpu_to_le16(size);
230 }
231
mvpp2_txdesc_txq_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,unsigned int txq)232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
233 struct mvpp2_tx_desc *tx_desc,
234 unsigned int txq)
235 {
236 if (port->priv->hw_version == MVPP21)
237 tx_desc->pp21.phys_txq = txq;
238 else
239 tx_desc->pp22.phys_txq = txq;
240 }
241
mvpp2_txdesc_cmd_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,unsigned int command)242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
243 struct mvpp2_tx_desc *tx_desc,
244 unsigned int command)
245 {
246 if (port->priv->hw_version == MVPP21)
247 tx_desc->pp21.command = cpu_to_le32(command);
248 else
249 tx_desc->pp22.command = cpu_to_le32(command);
250 }
251
mvpp2_txdesc_offset_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
253 struct mvpp2_tx_desc *tx_desc)
254 {
255 if (port->priv->hw_version == MVPP21)
256 return tx_desc->pp21.packet_offset;
257 else
258 return tx_desc->pp22.packet_offset;
259 }
260
mvpp2_rxdesc_dma_addr_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
262 struct mvpp2_rx_desc *rx_desc)
263 {
264 if (port->priv->hw_version == MVPP21)
265 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
266 else
267 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
268 MVPP2_DESC_DMA_MASK;
269 }
270
mvpp2_rxdesc_cookie_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
272 struct mvpp2_rx_desc *rx_desc)
273 {
274 if (port->priv->hw_version == MVPP21)
275 return le32_to_cpu(rx_desc->pp21.buf_cookie);
276 else
277 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
278 MVPP2_DESC_DMA_MASK;
279 }
280
mvpp2_rxdesc_size_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
282 struct mvpp2_rx_desc *rx_desc)
283 {
284 if (port->priv->hw_version == MVPP21)
285 return le16_to_cpu(rx_desc->pp21.data_size);
286 else
287 return le16_to_cpu(rx_desc->pp22.data_size);
288 }
289
mvpp2_rxdesc_status_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
291 struct mvpp2_rx_desc *rx_desc)
292 {
293 if (port->priv->hw_version == MVPP21)
294 return le32_to_cpu(rx_desc->pp21.status);
295 else
296 return le32_to_cpu(rx_desc->pp22.status);
297 }
298
mvpp2_txq_inc_get(struct mvpp2_txq_pcpu * txq_pcpu)299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
300 {
301 txq_pcpu->txq_get_index++;
302 if (txq_pcpu->txq_get_index == txq_pcpu->size)
303 txq_pcpu->txq_get_index = 0;
304 }
305
mvpp2_txq_inc_put(struct mvpp2_port * port,struct mvpp2_txq_pcpu * txq_pcpu,void * data,struct mvpp2_tx_desc * tx_desc,enum mvpp2_tx_buf_type buf_type)306 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
307 struct mvpp2_txq_pcpu *txq_pcpu,
308 void *data,
309 struct mvpp2_tx_desc *tx_desc,
310 enum mvpp2_tx_buf_type buf_type)
311 {
312 struct mvpp2_txq_pcpu_buf *tx_buf =
313 txq_pcpu->buffs + txq_pcpu->txq_put_index;
314 tx_buf->type = buf_type;
315 if (buf_type == MVPP2_TYPE_SKB)
316 tx_buf->skb = data;
317 else
318 tx_buf->xdpf = data;
319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
321 mvpp2_txdesc_offset_get(port, tx_desc);
322 txq_pcpu->txq_put_index++;
323 if (txq_pcpu->txq_put_index == txq_pcpu->size)
324 txq_pcpu->txq_put_index = 0;
325 }
326
327 /* Get number of maximum RXQ */
mvpp2_get_nrxqs(struct mvpp2 * priv)328 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
329 {
330 unsigned int nrxqs;
331
332 if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
333 return 1;
334
335 /* According to the PPv2.2 datasheet and our experiments on
336 * PPv2.1, RX queues have an allocation granularity of 4 (when
337 * more than a single one on PPv2.2).
338 * Round up to nearest multiple of 4.
339 */
340 nrxqs = (num_possible_cpus() + 3) & ~0x3;
341 if (nrxqs > MVPP2_PORT_MAX_RXQ)
342 nrxqs = MVPP2_PORT_MAX_RXQ;
343
344 return nrxqs;
345 }
346
347 /* Get number of physical egress port */
mvpp2_egress_port(struct mvpp2_port * port)348 static inline int mvpp2_egress_port(struct mvpp2_port *port)
349 {
350 return MVPP2_MAX_TCONT + port->id;
351 }
352
353 /* Get number of physical TXQ */
mvpp2_txq_phys(int port,int txq)354 static inline int mvpp2_txq_phys(int port, int txq)
355 {
356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
357 }
358
359 /* Returns a struct page if page_pool is set, otherwise a buffer */
mvpp2_frag_alloc(const struct mvpp2_bm_pool * pool,struct page_pool * page_pool)360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
361 struct page_pool *page_pool)
362 {
363 if (page_pool)
364 return page_pool_dev_alloc_pages(page_pool);
365
366 if (likely(pool->frag_size <= PAGE_SIZE))
367 return netdev_alloc_frag(pool->frag_size);
368
369 return kmalloc(pool->frag_size, GFP_ATOMIC);
370 }
371
mvpp2_frag_free(const struct mvpp2_bm_pool * pool,struct page_pool * page_pool,void * data)372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
373 struct page_pool *page_pool, void *data)
374 {
375 if (page_pool)
376 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
377 else if (likely(pool->frag_size <= PAGE_SIZE))
378 skb_free_frag(data);
379 else
380 kfree(data);
381 }
382
383 /* Buffer Manager configuration routines */
384
385 /* Create pool */
mvpp2_bm_pool_create(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int size)386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
387 struct mvpp2_bm_pool *bm_pool, int size)
388 {
389 u32 val;
390
391 /* Number of buffer pointers must be a multiple of 16, as per
392 * hardware constraints
393 */
394 if (!IS_ALIGNED(size, 16))
395 return -EINVAL;
396
397 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
398 * bytes per buffer pointer
399 */
400 if (priv->hw_version == MVPP21)
401 bm_pool->size_bytes = 2 * sizeof(u32) * size;
402 else
403 bm_pool->size_bytes = 2 * sizeof(u64) * size;
404
405 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
406 &bm_pool->dma_addr,
407 GFP_KERNEL);
408 if (!bm_pool->virt_addr)
409 return -ENOMEM;
410
411 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
412 MVPP2_BM_POOL_PTR_ALIGN)) {
413 dma_free_coherent(dev, bm_pool->size_bytes,
414 bm_pool->virt_addr, bm_pool->dma_addr);
415 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
417 return -ENOMEM;
418 }
419
420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
421 lower_32_bits(bm_pool->dma_addr));
422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
423
424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
425 val |= MVPP2_BM_START_MASK;
426
427 val &= ~MVPP2_BM_LOW_THRESH_MASK;
428 val &= ~MVPP2_BM_HIGH_THRESH_MASK;
429
430 /* Set 8 Pools BPPI threshold for MVPP23 */
431 if (priv->hw_version == MVPP23) {
432 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
433 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
434 } else {
435 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
436 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
437 }
438
439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
440
441 bm_pool->size = size;
442 bm_pool->pkt_size = 0;
443 bm_pool->buf_num = 0;
444
445 return 0;
446 }
447
448 /* Set pool buffer size */
mvpp2_bm_pool_bufsize_set(struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int buf_size)449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
450 struct mvpp2_bm_pool *bm_pool,
451 int buf_size)
452 {
453 u32 val;
454
455 bm_pool->buf_size = buf_size;
456
457 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
459 }
460
mvpp2_bm_bufs_get_addrs(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,dma_addr_t * dma_addr,phys_addr_t * phys_addr)461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
462 struct mvpp2_bm_pool *bm_pool,
463 dma_addr_t *dma_addr,
464 phys_addr_t *phys_addr)
465 {
466 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
467
468 *dma_addr = mvpp2_thread_read(priv, thread,
469 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
470 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
471
472 if (priv->hw_version >= MVPP22) {
473 u32 val;
474 u32 dma_addr_highbits, phys_addr_highbits;
475
476 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
477 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
478 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
479 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
480
481 if (sizeof(dma_addr_t) == 8)
482 *dma_addr |= (u64)dma_addr_highbits << 32;
483
484 if (sizeof(phys_addr_t) == 8)
485 *phys_addr |= (u64)phys_addr_highbits << 32;
486 }
487
488 put_cpu();
489 }
490
491 /* Free all buffers from the pool */
mvpp2_bm_bufs_free(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int buf_num)492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
493 struct mvpp2_bm_pool *bm_pool, int buf_num)
494 {
495 struct page_pool *pp = NULL;
496 int i;
497
498 if (buf_num > bm_pool->buf_num) {
499 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
500 bm_pool->id, buf_num);
501 buf_num = bm_pool->buf_num;
502 }
503
504 if (priv->percpu_pools)
505 pp = priv->page_pool[bm_pool->id];
506
507 for (i = 0; i < buf_num; i++) {
508 dma_addr_t buf_dma_addr;
509 phys_addr_t buf_phys_addr;
510 void *data;
511
512 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
513 &buf_dma_addr, &buf_phys_addr);
514
515 if (!pp)
516 dma_unmap_single(dev, buf_dma_addr,
517 bm_pool->buf_size, DMA_FROM_DEVICE);
518
519 data = (void *)phys_to_virt(buf_phys_addr);
520 if (!data)
521 break;
522
523 mvpp2_frag_free(bm_pool, pp, data);
524 }
525
526 /* Update BM driver with number of buffers removed from pool */
527 bm_pool->buf_num -= i;
528 }
529
530 /* Check number of buffers in BM pool */
mvpp2_check_hw_buf_num(struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool)531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
532 {
533 int buf_num = 0;
534
535 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
536 MVPP22_BM_POOL_PTRS_NUM_MASK;
537 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
538 MVPP2_BM_BPPI_PTR_NUM_MASK;
539
540 /* HW has one buffer ready which is not reflected in the counters */
541 if (buf_num)
542 buf_num += 1;
543
544 return buf_num;
545 }
546
547 /* Cleanup pool */
mvpp2_bm_pool_destroy(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool)548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
549 struct mvpp2_bm_pool *bm_pool)
550 {
551 int buf_num;
552 u32 val;
553
554 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
555 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
556
557 /* Check buffer counters after free */
558 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
559 if (buf_num) {
560 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
561 bm_pool->id, bm_pool->buf_num);
562 return 0;
563 }
564
565 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
566 val |= MVPP2_BM_STOP_MASK;
567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
568
569 if (priv->percpu_pools) {
570 page_pool_destroy(priv->page_pool[bm_pool->id]);
571 priv->page_pool[bm_pool->id] = NULL;
572 }
573
574 dma_free_coherent(dev, bm_pool->size_bytes,
575 bm_pool->virt_addr,
576 bm_pool->dma_addr);
577 return 0;
578 }
579
mvpp2_bm_pools_init(struct device * dev,struct mvpp2 * priv)580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
581 {
582 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
583 struct mvpp2_bm_pool *bm_pool;
584
585 if (priv->percpu_pools)
586 poolnum = mvpp2_get_nrxqs(priv) * 2;
587
588 /* Create all pools with maximum size */
589 size = MVPP2_BM_POOL_SIZE_MAX;
590 for (i = 0; i < poolnum; i++) {
591 bm_pool = &priv->bm_pools[i];
592 bm_pool->id = i;
593 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
594 if (err)
595 goto err_unroll_pools;
596 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
597 }
598 return 0;
599
600 err_unroll_pools:
601 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
602 for (i = i - 1; i >= 0; i--)
603 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
604 return err;
605 }
606
607 /* Routine enable PPv23 8 pool mode */
mvpp23_bm_set_8pool_mode(struct mvpp2 * priv)608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
609 {
610 int val;
611
612 val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
613 val |= MVPP23_BM_8POOL_MODE;
614 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
615 }
616
617 /* Cleanup pool before actual initialization in the OS */
mvpp2_bm_pool_cleanup(struct mvpp2 * priv,int pool_id)618 static void mvpp2_bm_pool_cleanup(struct mvpp2 *priv, int pool_id)
619 {
620 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
621 u32 val;
622 int i;
623
624 /* Drain the BM from all possible residues left by firmware */
625 for (i = 0; i < MVPP2_BM_POOL_SIZE_MAX; i++)
626 mvpp2_thread_read(priv, thread, MVPP2_BM_PHY_ALLOC_REG(pool_id));
627
628 put_cpu();
629
630 /* Stop the BM pool */
631 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id));
632 val |= MVPP2_BM_STOP_MASK;
633 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val);
634 }
635
mvpp2_bm_init(struct device * dev,struct mvpp2 * priv)636 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
637 {
638 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
639 int i, err, poolnum = MVPP2_BM_POOLS_NUM;
640 struct mvpp2_port *port;
641
642 if (priv->percpu_pools)
643 poolnum = mvpp2_get_nrxqs(priv) * 2;
644
645 /* Clean up the pool state in case it contains stale state */
646 for (i = 0; i < poolnum; i++)
647 mvpp2_bm_pool_cleanup(priv, i);
648
649 if (priv->percpu_pools) {
650 for (i = 0; i < priv->port_count; i++) {
651 port = priv->port_list[i];
652 if (port->xdp_prog) {
653 dma_dir = DMA_BIDIRECTIONAL;
654 break;
655 }
656 }
657
658 for (i = 0; i < poolnum; i++) {
659 /* the pool in use */
660 int pn = i / (poolnum / 2);
661
662 priv->page_pool[i] =
663 mvpp2_create_page_pool(dev,
664 mvpp2_pools[pn].buf_num,
665 mvpp2_pools[pn].pkt_size,
666 dma_dir);
667 if (IS_ERR(priv->page_pool[i])) {
668 int j;
669
670 for (j = 0; j < i; j++) {
671 page_pool_destroy(priv->page_pool[j]);
672 priv->page_pool[j] = NULL;
673 }
674 return PTR_ERR(priv->page_pool[i]);
675 }
676 }
677 }
678
679 dev_info(dev, "using %d %s buffers\n", poolnum,
680 priv->percpu_pools ? "per-cpu" : "shared");
681
682 for (i = 0; i < poolnum; i++) {
683 /* Mask BM all interrupts */
684 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
685 /* Clear BM cause register */
686 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
687 }
688
689 /* Allocate and initialize BM pools */
690 priv->bm_pools = devm_kcalloc(dev, poolnum,
691 sizeof(*priv->bm_pools), GFP_KERNEL);
692 if (!priv->bm_pools)
693 return -ENOMEM;
694
695 if (priv->hw_version == MVPP23)
696 mvpp23_bm_set_8pool_mode(priv);
697
698 err = mvpp2_bm_pools_init(dev, priv);
699 if (err < 0)
700 return err;
701 return 0;
702 }
703
mvpp2_setup_bm_pool(void)704 static void mvpp2_setup_bm_pool(void)
705 {
706 /* Short pool */
707 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
708 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
709
710 /* Long pool */
711 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
712 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
713
714 /* Jumbo pool */
715 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
716 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
717 }
718
719 /* Attach long pool to rxq */
mvpp2_rxq_long_pool_set(struct mvpp2_port * port,int lrxq,int long_pool)720 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
721 int lrxq, int long_pool)
722 {
723 u32 val, mask;
724 int prxq;
725
726 /* Get queue physical ID */
727 prxq = port->rxqs[lrxq]->id;
728
729 if (port->priv->hw_version == MVPP21)
730 mask = MVPP21_RXQ_POOL_LONG_MASK;
731 else
732 mask = MVPP22_RXQ_POOL_LONG_MASK;
733
734 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
735 val &= ~mask;
736 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
737 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
738 }
739
740 /* Attach short pool to rxq */
mvpp2_rxq_short_pool_set(struct mvpp2_port * port,int lrxq,int short_pool)741 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
742 int lrxq, int short_pool)
743 {
744 u32 val, mask;
745 int prxq;
746
747 /* Get queue physical ID */
748 prxq = port->rxqs[lrxq]->id;
749
750 if (port->priv->hw_version == MVPP21)
751 mask = MVPP21_RXQ_POOL_SHORT_MASK;
752 else
753 mask = MVPP22_RXQ_POOL_SHORT_MASK;
754
755 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
756 val &= ~mask;
757 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
758 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
759 }
760
mvpp2_buf_alloc(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,struct page_pool * page_pool,dma_addr_t * buf_dma_addr,phys_addr_t * buf_phys_addr,gfp_t gfp_mask)761 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
762 struct mvpp2_bm_pool *bm_pool,
763 struct page_pool *page_pool,
764 dma_addr_t *buf_dma_addr,
765 phys_addr_t *buf_phys_addr,
766 gfp_t gfp_mask)
767 {
768 dma_addr_t dma_addr;
769 struct page *page;
770 void *data;
771
772 data = mvpp2_frag_alloc(bm_pool, page_pool);
773 if (!data)
774 return NULL;
775
776 if (page_pool) {
777 page = (struct page *)data;
778 dma_addr = page_pool_get_dma_addr(page);
779 data = page_to_virt(page);
780 } else {
781 dma_addr = dma_map_single(port->dev->dev.parent, data,
782 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
783 DMA_FROM_DEVICE);
784 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
785 mvpp2_frag_free(bm_pool, NULL, data);
786 return NULL;
787 }
788 }
789 *buf_dma_addr = dma_addr;
790 *buf_phys_addr = virt_to_phys(data);
791
792 return data;
793 }
794
795 /* Routine enable flow control for RXQs condition */
mvpp2_rxq_enable_fc(struct mvpp2_port * port)796 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
797 {
798 int val, cm3_state, host_id, q;
799 int fq = port->first_rxq;
800 unsigned long flags;
801
802 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
803
804 /* Remove Flow control enable bit to prevent race between FW and Kernel
805 * If Flow control was enabled, it would be re-enabled.
806 */
807 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
808 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
809 val &= ~FLOW_CONTROL_ENABLE_BIT;
810 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
811
812 /* Set same Flow control for all RXQs */
813 for (q = 0; q < port->nrxqs; q++) {
814 /* Set stop and start Flow control RXQ thresholds */
815 val = MSS_THRESHOLD_START;
816 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
817 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
818
819 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
820 /* Set RXQ port ID */
821 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
822 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
823 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
824 + MSS_RXQ_ASS_HOSTID_OFFS));
825
826 /* Calculate RXQ host ID:
827 * In Single queue mode: Host ID equal to Host ID used for
828 * shared RX interrupt
829 * In Multi queue mode: Host ID equal to number of
830 * RXQ ID / number of CoS queues
831 * In Single resource mode: Host ID always equal to 0
832 */
833 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
834 host_id = port->nqvecs;
835 else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
836 host_id = q;
837 else
838 host_id = 0;
839
840 /* Set RXQ host ID */
841 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
842 + MSS_RXQ_ASS_HOSTID_OFFS));
843
844 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
845 }
846
847 /* Notify Firmware that Flow control config space ready for update */
848 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
849 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
850 val |= cm3_state;
851 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
852
853 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
854 }
855
856 /* Routine disable flow control for RXQs condition */
mvpp2_rxq_disable_fc(struct mvpp2_port * port)857 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
858 {
859 int val, cm3_state, q;
860 unsigned long flags;
861 int fq = port->first_rxq;
862
863 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
864
865 /* Remove Flow control enable bit to prevent race between FW and Kernel
866 * If Flow control was enabled, it would be re-enabled.
867 */
868 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
869 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
870 val &= ~FLOW_CONTROL_ENABLE_BIT;
871 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
872
873 /* Disable Flow control for all RXQs */
874 for (q = 0; q < port->nrxqs; q++) {
875 /* Set threshold 0 to disable Flow control */
876 val = 0;
877 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
878 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
879
880 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
881
882 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
883
884 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
885 + MSS_RXQ_ASS_HOSTID_OFFS));
886
887 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
888 }
889
890 /* Notify Firmware that Flow control config space ready for update */
891 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
892 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
893 val |= cm3_state;
894 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
895
896 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
897 }
898
899 /* Routine disable/enable flow control for BM pool condition */
mvpp2_bm_pool_update_fc(struct mvpp2_port * port,struct mvpp2_bm_pool * pool,bool en)900 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
901 struct mvpp2_bm_pool *pool,
902 bool en)
903 {
904 int val, cm3_state;
905 unsigned long flags;
906
907 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
908
909 /* Remove Flow control enable bit to prevent race between FW and Kernel
910 * If Flow control were enabled, it would be re-enabled.
911 */
912 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
913 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
914 val &= ~FLOW_CONTROL_ENABLE_BIT;
915 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
916
917 /* Check if BM pool should be enabled/disable */
918 if (en) {
919 /* Set BM pool start and stop thresholds per port */
920 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
921 val |= MSS_BUF_POOL_PORT_OFFS(port->id);
922 val &= ~MSS_BUF_POOL_START_MASK;
923 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
924 val &= ~MSS_BUF_POOL_STOP_MASK;
925 val |= MSS_THRESHOLD_STOP;
926 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
927 } else {
928 /* Remove BM pool from the port */
929 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
930 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
931
932 /* Zero BM pool start and stop thresholds to disable pool
933 * flow control if pool empty (not used by any port)
934 */
935 if (!pool->buf_num) {
936 val &= ~MSS_BUF_POOL_START_MASK;
937 val &= ~MSS_BUF_POOL_STOP_MASK;
938 }
939
940 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
941 }
942
943 /* Notify Firmware that Flow control config space ready for update */
944 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
945 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
946 val |= cm3_state;
947 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
948
949 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
950 }
951
952 /* disable/enable flow control for BM pool on all ports */
mvpp2_bm_pool_update_priv_fc(struct mvpp2 * priv,bool en)953 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
954 {
955 struct mvpp2_port *port;
956 int i;
957
958 for (i = 0; i < priv->port_count; i++) {
959 port = priv->port_list[i];
960 if (port->priv->percpu_pools) {
961 for (i = 0; i < port->nrxqs; i++)
962 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i],
963 port->tx_fc & en);
964 } else {
965 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
966 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en);
967 }
968 }
969 }
970
mvpp2_enable_global_fc(struct mvpp2 * priv)971 static int mvpp2_enable_global_fc(struct mvpp2 *priv)
972 {
973 int val, timeout = 0;
974
975 /* Enable global flow control. In this stage global
976 * flow control enabled, but still disabled per port.
977 */
978 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
979 val |= FLOW_CONTROL_ENABLE_BIT;
980 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
981
982 /* Check if Firmware running and disable FC if not*/
983 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
984 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
985
986 while (timeout < MSS_FC_MAX_TIMEOUT) {
987 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
988
989 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
990 return 0;
991 usleep_range(10, 20);
992 timeout++;
993 }
994
995 priv->global_tx_fc = false;
996 return -EOPNOTSUPP;
997 }
998
999 /* Release buffer to BM */
mvpp2_bm_pool_put(struct mvpp2_port * port,int pool,dma_addr_t buf_dma_addr,phys_addr_t buf_phys_addr)1000 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
1001 dma_addr_t buf_dma_addr,
1002 phys_addr_t buf_phys_addr)
1003 {
1004 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1005 unsigned long flags = 0;
1006
1007 if (test_bit(thread, &port->priv->lock_map))
1008 spin_lock_irqsave(&port->bm_lock[thread], flags);
1009
1010 if (port->priv->hw_version >= MVPP22) {
1011 u32 val = 0;
1012
1013 if (sizeof(dma_addr_t) == 8)
1014 val |= upper_32_bits(buf_dma_addr) &
1015 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
1016
1017 if (sizeof(phys_addr_t) == 8)
1018 val |= (upper_32_bits(buf_phys_addr)
1019 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
1020 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
1021
1022 mvpp2_thread_write_relaxed(port->priv, thread,
1023 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
1024 }
1025
1026 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
1027 * returned in the "cookie" field of the RX
1028 * descriptor. Instead of storing the virtual address, we
1029 * store the physical address
1030 */
1031 mvpp2_thread_write_relaxed(port->priv, thread,
1032 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1033 mvpp2_thread_write_relaxed(port->priv, thread,
1034 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
1035
1036 if (test_bit(thread, &port->priv->lock_map))
1037 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
1038
1039 put_cpu();
1040 }
1041
1042 /* Allocate buffers for the pool */
mvpp2_bm_bufs_add(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,int buf_num)1043 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
1044 struct mvpp2_bm_pool *bm_pool, int buf_num)
1045 {
1046 int i, buf_size, total_size;
1047 dma_addr_t dma_addr;
1048 phys_addr_t phys_addr;
1049 struct page_pool *pp = NULL;
1050 void *buf;
1051
1052 if (port->priv->percpu_pools &&
1053 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1054 netdev_err(port->dev,
1055 "attempted to use jumbo frames with per-cpu pools");
1056 return 0;
1057 }
1058
1059 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
1060 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
1061
1062 if (buf_num < 0 ||
1063 (buf_num + bm_pool->buf_num > bm_pool->size)) {
1064 netdev_err(port->dev,
1065 "cannot allocate %d buffers for pool %d\n",
1066 buf_num, bm_pool->id);
1067 return 0;
1068 }
1069
1070 if (port->priv->percpu_pools)
1071 pp = port->priv->page_pool[bm_pool->id];
1072 for (i = 0; i < buf_num; i++) {
1073 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
1074 &phys_addr, GFP_KERNEL);
1075 if (!buf)
1076 break;
1077
1078 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
1079 phys_addr);
1080 }
1081
1082 /* Update BM driver with number of buffers added to pool */
1083 bm_pool->buf_num += i;
1084
1085 netdev_dbg(port->dev,
1086 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
1087 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
1088
1089 netdev_dbg(port->dev,
1090 "pool %d: %d of %d buffers added\n",
1091 bm_pool->id, i, buf_num);
1092 return i;
1093 }
1094
1095 /* Notify the driver that BM pool is being used as specific type and return the
1096 * pool pointer on success
1097 */
1098 static struct mvpp2_bm_pool *
mvpp2_bm_pool_use(struct mvpp2_port * port,unsigned pool,int pkt_size)1099 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
1100 {
1101 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1102 int num;
1103
1104 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
1105 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
1106 netdev_err(port->dev, "Invalid pool %d\n", pool);
1107 return NULL;
1108 }
1109
1110 /* Allocate buffers in case BM pool is used as long pool, but packet
1111 * size doesn't match MTU or BM pool hasn't being used yet
1112 */
1113 if (new_pool->pkt_size == 0) {
1114 int pkts_num;
1115
1116 /* Set default buffer number or free all the buffers in case
1117 * the pool is not empty
1118 */
1119 pkts_num = new_pool->buf_num;
1120 if (pkts_num == 0) {
1121 if (port->priv->percpu_pools) {
1122 if (pool < port->nrxqs)
1123 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
1124 else
1125 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
1126 } else {
1127 pkts_num = mvpp2_pools[pool].buf_num;
1128 }
1129 } else {
1130 mvpp2_bm_bufs_free(port->dev->dev.parent,
1131 port->priv, new_pool, pkts_num);
1132 }
1133
1134 new_pool->pkt_size = pkt_size;
1135 new_pool->frag_size =
1136 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1137 MVPP2_SKB_SHINFO_SIZE;
1138
1139 /* Allocate buffers for this pool */
1140 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1141 if (num != pkts_num) {
1142 WARN(1, "pool %d: %d of %d allocated\n",
1143 new_pool->id, num, pkts_num);
1144 return NULL;
1145 }
1146 }
1147
1148 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1149 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1150
1151 return new_pool;
1152 }
1153
1154 static struct mvpp2_bm_pool *
mvpp2_bm_pool_use_percpu(struct mvpp2_port * port,int type,unsigned int pool,int pkt_size)1155 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
1156 unsigned int pool, int pkt_size)
1157 {
1158 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1159 int num;
1160
1161 if (pool > port->nrxqs * 2) {
1162 netdev_err(port->dev, "Invalid pool %d\n", pool);
1163 return NULL;
1164 }
1165
1166 /* Allocate buffers in case BM pool is used as long pool, but packet
1167 * size doesn't match MTU or BM pool hasn't being used yet
1168 */
1169 if (new_pool->pkt_size == 0) {
1170 int pkts_num;
1171
1172 /* Set default buffer number or free all the buffers in case
1173 * the pool is not empty
1174 */
1175 pkts_num = new_pool->buf_num;
1176 if (pkts_num == 0)
1177 pkts_num = mvpp2_pools[type].buf_num;
1178 else
1179 mvpp2_bm_bufs_free(port->dev->dev.parent,
1180 port->priv, new_pool, pkts_num);
1181
1182 new_pool->pkt_size = pkt_size;
1183 new_pool->frag_size =
1184 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1185 MVPP2_SKB_SHINFO_SIZE;
1186
1187 /* Allocate buffers for this pool */
1188 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1189 if (num != pkts_num) {
1190 WARN(1, "pool %d: %d of %d allocated\n",
1191 new_pool->id, num, pkts_num);
1192 return NULL;
1193 }
1194 }
1195
1196 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1197 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1198
1199 return new_pool;
1200 }
1201
1202 /* Initialize pools for swf, shared buffers variant */
mvpp2_swf_bm_pool_init_shared(struct mvpp2_port * port)1203 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
1204 {
1205 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
1206 int rxq;
1207
1208 /* If port pkt_size is higher than 1518B:
1209 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1210 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1211 */
1212 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1213 long_log_pool = MVPP2_BM_JUMBO;
1214 short_log_pool = MVPP2_BM_LONG;
1215 } else {
1216 long_log_pool = MVPP2_BM_LONG;
1217 short_log_pool = MVPP2_BM_SHORT;
1218 }
1219
1220 if (!port->pool_long) {
1221 port->pool_long =
1222 mvpp2_bm_pool_use(port, long_log_pool,
1223 mvpp2_pools[long_log_pool].pkt_size);
1224 if (!port->pool_long)
1225 return -ENOMEM;
1226
1227 port->pool_long->port_map |= BIT(port->id);
1228
1229 for (rxq = 0; rxq < port->nrxqs; rxq++)
1230 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
1231 }
1232
1233 if (!port->pool_short) {
1234 port->pool_short =
1235 mvpp2_bm_pool_use(port, short_log_pool,
1236 mvpp2_pools[short_log_pool].pkt_size);
1237 if (!port->pool_short)
1238 return -ENOMEM;
1239
1240 port->pool_short->port_map |= BIT(port->id);
1241
1242 for (rxq = 0; rxq < port->nrxqs; rxq++)
1243 mvpp2_rxq_short_pool_set(port, rxq,
1244 port->pool_short->id);
1245 }
1246
1247 return 0;
1248 }
1249
1250 /* Initialize pools for swf, percpu buffers variant */
mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port * port)1251 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
1252 {
1253 struct mvpp2_bm_pool *bm_pool;
1254 int i;
1255
1256 for (i = 0; i < port->nrxqs; i++) {
1257 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
1258 mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
1259 if (!bm_pool)
1260 return -ENOMEM;
1261
1262 bm_pool->port_map |= BIT(port->id);
1263 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1264 }
1265
1266 for (i = 0; i < port->nrxqs; i++) {
1267 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1268 mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1269 if (!bm_pool)
1270 return -ENOMEM;
1271
1272 bm_pool->port_map |= BIT(port->id);
1273 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1274 }
1275
1276 port->pool_long = NULL;
1277 port->pool_short = NULL;
1278
1279 return 0;
1280 }
1281
mvpp2_swf_bm_pool_init(struct mvpp2_port * port)1282 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1283 {
1284 if (port->priv->percpu_pools)
1285 return mvpp2_swf_bm_pool_init_percpu(port);
1286 else
1287 return mvpp2_swf_bm_pool_init_shared(port);
1288 }
1289
mvpp2_set_hw_csum(struct mvpp2_port * port,enum mvpp2_bm_pool_log_num new_long_pool)1290 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1291 enum mvpp2_bm_pool_log_num new_long_pool)
1292 {
1293 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1294
1295 /* Update L4 checksum when jumbo enable/disable on port.
1296 * Only port 0 supports hardware checksum offload due to
1297 * the Tx FIFO size limitation.
1298 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1299 * has 7 bits, so the maximum L3 offset is 128.
1300 */
1301 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1302 port->dev->features &= ~csums;
1303 port->dev->hw_features &= ~csums;
1304 } else {
1305 port->dev->features |= csums;
1306 port->dev->hw_features |= csums;
1307 }
1308 }
1309
mvpp2_bm_update_mtu(struct net_device * dev,int mtu)1310 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1311 {
1312 struct mvpp2_port *port = netdev_priv(dev);
1313 enum mvpp2_bm_pool_log_num new_long_pool;
1314 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1315
1316 if (port->priv->percpu_pools)
1317 goto out_set;
1318
1319 /* If port MTU is higher than 1518B:
1320 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1321 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1322 */
1323 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1324 new_long_pool = MVPP2_BM_JUMBO;
1325 else
1326 new_long_pool = MVPP2_BM_LONG;
1327
1328 if (new_long_pool != port->pool_long->id) {
1329 if (port->tx_fc) {
1330 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1331 mvpp2_bm_pool_update_fc(port,
1332 port->pool_short,
1333 false);
1334 else
1335 mvpp2_bm_pool_update_fc(port, port->pool_long,
1336 false);
1337 }
1338
1339 /* Remove port from old short & long pool */
1340 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1341 port->pool_long->pkt_size);
1342 port->pool_long->port_map &= ~BIT(port->id);
1343 port->pool_long = NULL;
1344
1345 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1346 port->pool_short->pkt_size);
1347 port->pool_short->port_map &= ~BIT(port->id);
1348 port->pool_short = NULL;
1349
1350 port->pkt_size = pkt_size;
1351
1352 /* Add port to new short & long pool */
1353 mvpp2_swf_bm_pool_init(port);
1354
1355 mvpp2_set_hw_csum(port, new_long_pool);
1356
1357 if (port->tx_fc) {
1358 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1359 mvpp2_bm_pool_update_fc(port, port->pool_long,
1360 true);
1361 else
1362 mvpp2_bm_pool_update_fc(port, port->pool_short,
1363 true);
1364 }
1365
1366 /* Update L4 checksum when jumbo enable/disable on port */
1367 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1368 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1369 dev->hw_features &= ~(NETIF_F_IP_CSUM |
1370 NETIF_F_IPV6_CSUM);
1371 } else {
1372 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1373 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1374 }
1375 }
1376
1377 out_set:
1378 dev->mtu = mtu;
1379 dev->wanted_features = dev->features;
1380
1381 netdev_update_features(dev);
1382 return 0;
1383 }
1384
mvpp2_interrupts_enable(struct mvpp2_port * port)1385 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1386 {
1387 int i, sw_thread_mask = 0;
1388
1389 for (i = 0; i < port->nqvecs; i++)
1390 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1391
1392 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1393 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1394 }
1395
mvpp2_interrupts_disable(struct mvpp2_port * port)1396 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1397 {
1398 int i, sw_thread_mask = 0;
1399
1400 for (i = 0; i < port->nqvecs; i++)
1401 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1402
1403 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1404 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1405 }
1406
mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector * qvec)1407 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1408 {
1409 struct mvpp2_port *port = qvec->port;
1410
1411 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1412 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1413 }
1414
mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector * qvec)1415 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1416 {
1417 struct mvpp2_port *port = qvec->port;
1418
1419 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1420 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1421 }
1422
1423 /* Mask the current thread's Rx/Tx interrupts
1424 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1425 * using smp_processor_id() is OK.
1426 */
mvpp2_interrupts_mask(void * arg)1427 static void mvpp2_interrupts_mask(void *arg)
1428 {
1429 struct mvpp2_port *port = arg;
1430 int cpu = smp_processor_id();
1431 u32 thread;
1432
1433 /* If the thread isn't used, don't do anything */
1434 if (cpu > port->priv->nthreads)
1435 return;
1436
1437 thread = mvpp2_cpu_to_thread(port->priv, cpu);
1438
1439 mvpp2_thread_write(port->priv, thread,
1440 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1441 mvpp2_thread_write(port->priv, thread,
1442 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
1443 }
1444
1445 /* Unmask the current thread's Rx/Tx interrupts.
1446 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1447 * using smp_processor_id() is OK.
1448 */
mvpp2_interrupts_unmask(void * arg)1449 static void mvpp2_interrupts_unmask(void *arg)
1450 {
1451 struct mvpp2_port *port = arg;
1452 int cpu = smp_processor_id();
1453 u32 val, thread;
1454
1455 /* If the thread isn't used, don't do anything */
1456 if (cpu >= port->priv->nthreads)
1457 return;
1458
1459 thread = mvpp2_cpu_to_thread(port->priv, cpu);
1460
1461 val = MVPP2_CAUSE_MISC_SUM_MASK |
1462 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1463 if (port->has_tx_irqs)
1464 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1465
1466 mvpp2_thread_write(port->priv, thread,
1467 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1468 mvpp2_thread_write(port->priv, thread,
1469 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1470 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1471 }
1472
1473 static void
mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port * port,bool mask)1474 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1475 {
1476 u32 val;
1477 int i;
1478
1479 if (port->priv->hw_version == MVPP21)
1480 return;
1481
1482 if (mask)
1483 val = 0;
1484 else
1485 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1486
1487 for (i = 0; i < port->nqvecs; i++) {
1488 struct mvpp2_queue_vector *v = port->qvecs + i;
1489
1490 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1491 continue;
1492
1493 mvpp2_thread_write(port->priv, v->sw_thread_id,
1494 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1495 mvpp2_thread_write(port->priv, v->sw_thread_id,
1496 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1497 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1498 }
1499 }
1500
1501 /* Only GOP port 0 has an XLG MAC */
mvpp2_port_supports_xlg(struct mvpp2_port * port)1502 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1503 {
1504 return port->gop_id == 0;
1505 }
1506
mvpp2_port_supports_rgmii(struct mvpp2_port * port)1507 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1508 {
1509 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
1510 }
1511
1512 /* Port configuration routines */
mvpp2_is_xlg(phy_interface_t interface)1513 static bool mvpp2_is_xlg(phy_interface_t interface)
1514 {
1515 return interface == PHY_INTERFACE_MODE_10GBASER ||
1516 interface == PHY_INTERFACE_MODE_5GBASER ||
1517 interface == PHY_INTERFACE_MODE_XAUI;
1518 }
1519
mvpp2_modify(void __iomem * ptr,u32 mask,u32 set)1520 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1521 {
1522 u32 old, val;
1523
1524 old = val = readl(ptr);
1525 val &= ~mask;
1526 val |= set;
1527 if (old != val)
1528 writel(val, ptr);
1529 }
1530
mvpp22_gop_init_rgmii(struct mvpp2_port * port)1531 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1532 {
1533 struct mvpp2 *priv = port->priv;
1534 u32 val;
1535
1536 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1537 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1538 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1539
1540 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1541 if (port->gop_id == 2)
1542 val |= GENCONF_CTRL0_PORT2_RGMII;
1543 else if (port->gop_id == 3)
1544 val |= GENCONF_CTRL0_PORT3_RGMII_MII;
1545 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1546 }
1547
mvpp22_gop_init_sgmii(struct mvpp2_port * port)1548 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1549 {
1550 struct mvpp2 *priv = port->priv;
1551 u32 val;
1552
1553 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1554 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1555 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1556 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1557
1558 if (port->gop_id > 1) {
1559 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1560 if (port->gop_id == 2)
1561 val &= ~GENCONF_CTRL0_PORT2_RGMII;
1562 else if (port->gop_id == 3)
1563 val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
1564 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1565 }
1566 }
1567
mvpp22_gop_init_10gkr(struct mvpp2_port * port)1568 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1569 {
1570 struct mvpp2 *priv = port->priv;
1571 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1572 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1573 u32 val;
1574
1575 val = readl(xpcs + MVPP22_XPCS_CFG0);
1576 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1577 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1578 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1579 writel(val, xpcs + MVPP22_XPCS_CFG0);
1580
1581 val = readl(mpcs + MVPP22_MPCS_CTRL);
1582 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1583 writel(val, mpcs + MVPP22_MPCS_CTRL);
1584
1585 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1586 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1587 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1588 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1589 }
1590
mvpp22_gop_fca_enable_periodic(struct mvpp2_port * port,bool en)1591 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
1592 {
1593 struct mvpp2 *priv = port->priv;
1594 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1595 u32 val;
1596
1597 val = readl(fca + MVPP22_FCA_CONTROL_REG);
1598 val &= ~MVPP22_FCA_ENABLE_PERIODIC;
1599 if (en)
1600 val |= MVPP22_FCA_ENABLE_PERIODIC;
1601 writel(val, fca + MVPP22_FCA_CONTROL_REG);
1602 }
1603
mvpp22_gop_fca_set_timer(struct mvpp2_port * port,u32 timer)1604 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
1605 {
1606 struct mvpp2 *priv = port->priv;
1607 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1608 u32 lsb, msb;
1609
1610 lsb = timer & MVPP22_FCA_REG_MASK;
1611 msb = timer >> MVPP22_FCA_REG_SIZE;
1612
1613 writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
1614 writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
1615 }
1616
1617 /* Set Flow Control timer x100 faster than pause quanta to ensure that link
1618 * partner won't send traffic if port is in XOFF mode.
1619 */
mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port * port)1620 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
1621 {
1622 u32 timer;
1623
1624 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
1625 * FC_QUANTA;
1626
1627 mvpp22_gop_fca_enable_periodic(port, false);
1628
1629 mvpp22_gop_fca_set_timer(port, timer);
1630
1631 mvpp22_gop_fca_enable_periodic(port, true);
1632 }
1633
mvpp22_gop_init(struct mvpp2_port * port,phy_interface_t interface)1634 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface)
1635 {
1636 struct mvpp2 *priv = port->priv;
1637 u32 val;
1638
1639 if (!priv->sysctrl_base)
1640 return 0;
1641
1642 switch (interface) {
1643 case PHY_INTERFACE_MODE_RGMII:
1644 case PHY_INTERFACE_MODE_RGMII_ID:
1645 case PHY_INTERFACE_MODE_RGMII_RXID:
1646 case PHY_INTERFACE_MODE_RGMII_TXID:
1647 if (!mvpp2_port_supports_rgmii(port))
1648 goto invalid_conf;
1649 mvpp22_gop_init_rgmii(port);
1650 break;
1651 case PHY_INTERFACE_MODE_SGMII:
1652 case PHY_INTERFACE_MODE_1000BASEX:
1653 case PHY_INTERFACE_MODE_2500BASEX:
1654 mvpp22_gop_init_sgmii(port);
1655 break;
1656 case PHY_INTERFACE_MODE_5GBASER:
1657 case PHY_INTERFACE_MODE_10GBASER:
1658 if (!mvpp2_port_supports_xlg(port))
1659 goto invalid_conf;
1660 mvpp22_gop_init_10gkr(port);
1661 break;
1662 default:
1663 goto unsupported_conf;
1664 }
1665
1666 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1667 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1668 GENCONF_PORT_CTRL1_EN(port->gop_id);
1669 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1670
1671 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1672 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1673 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1674
1675 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1676 val |= GENCONF_SOFT_RESET1_GOP;
1677 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1678
1679 mvpp22_gop_fca_set_periodic_timer(port);
1680
1681 unsupported_conf:
1682 return 0;
1683
1684 invalid_conf:
1685 netdev_err(port->dev, "Invalid port configuration\n");
1686 return -EINVAL;
1687 }
1688
mvpp22_gop_unmask_irq(struct mvpp2_port * port)1689 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1690 {
1691 u32 val;
1692
1693 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1694 phy_interface_mode_is_8023z(port->phy_interface) ||
1695 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1696 /* Enable the GMAC link status irq for this port */
1697 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1698 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1699 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1700 }
1701
1702 if (mvpp2_port_supports_xlg(port)) {
1703 /* Enable the XLG/GIG irqs for this port */
1704 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1705 if (mvpp2_is_xlg(port->phy_interface))
1706 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1707 else
1708 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1709 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1710 }
1711 }
1712
mvpp22_gop_mask_irq(struct mvpp2_port * port)1713 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1714 {
1715 u32 val;
1716
1717 if (mvpp2_port_supports_xlg(port)) {
1718 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1719 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1720 MVPP22_XLG_EXT_INT_MASK_GIG);
1721 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1722 }
1723
1724 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1725 phy_interface_mode_is_8023z(port->phy_interface) ||
1726 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1727 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1728 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1729 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1730 }
1731 }
1732
mvpp22_gop_setup_irq(struct mvpp2_port * port)1733 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1734 {
1735 u32 val;
1736
1737 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1738 MVPP22_GMAC_INT_SUM_MASK_PTP,
1739 MVPP22_GMAC_INT_SUM_MASK_PTP);
1740
1741 if (port->phylink ||
1742 phy_interface_mode_is_rgmii(port->phy_interface) ||
1743 phy_interface_mode_is_8023z(port->phy_interface) ||
1744 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1745 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1746 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1747 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1748 }
1749
1750 if (mvpp2_port_supports_xlg(port)) {
1751 val = readl(port->base + MVPP22_XLG_INT_MASK);
1752 val |= MVPP22_XLG_INT_MASK_LINK;
1753 writel(val, port->base + MVPP22_XLG_INT_MASK);
1754
1755 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1756 MVPP22_XLG_EXT_INT_MASK_PTP,
1757 MVPP22_XLG_EXT_INT_MASK_PTP);
1758 }
1759
1760 mvpp22_gop_unmask_irq(port);
1761 }
1762
1763 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1764 *
1765 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1766 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1767 * differ.
1768 *
1769 * The COMPHY configures the serdes lanes regardless of the actual use of the
1770 * lanes by the physical layer. This is why configurations like
1771 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1772 */
mvpp22_comphy_init(struct mvpp2_port * port,phy_interface_t interface)1773 static int mvpp22_comphy_init(struct mvpp2_port *port,
1774 phy_interface_t interface)
1775 {
1776 int ret;
1777
1778 if (!port->comphy)
1779 return 0;
1780
1781 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface);
1782 if (ret)
1783 return ret;
1784
1785 return phy_power_on(port->comphy);
1786 }
1787
mvpp2_port_enable(struct mvpp2_port * port)1788 static void mvpp2_port_enable(struct mvpp2_port *port)
1789 {
1790 u32 val;
1791
1792 if (mvpp2_port_supports_xlg(port) &&
1793 mvpp2_is_xlg(port->phy_interface)) {
1794 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1795 val |= MVPP22_XLG_CTRL0_PORT_EN;
1796 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1797 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1798 } else {
1799 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1800 val |= MVPP2_GMAC_PORT_EN_MASK;
1801 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1802 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1803 }
1804 }
1805
mvpp2_port_disable(struct mvpp2_port * port)1806 static void mvpp2_port_disable(struct mvpp2_port *port)
1807 {
1808 u32 val;
1809
1810 if (mvpp2_port_supports_xlg(port) &&
1811 mvpp2_is_xlg(port->phy_interface)) {
1812 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1813 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1814 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1815 }
1816
1817 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1818 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1819 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1820 }
1821
1822 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
mvpp2_port_periodic_xon_disable(struct mvpp2_port * port)1823 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1824 {
1825 u32 val;
1826
1827 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1828 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1829 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1830 }
1831
1832 /* Configure loopback port */
mvpp2_port_loopback_set(struct mvpp2_port * port,const struct phylink_link_state * state)1833 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1834 const struct phylink_link_state *state)
1835 {
1836 u32 val;
1837
1838 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1839
1840 if (state->speed == 1000)
1841 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1842 else
1843 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1844
1845 if (phy_interface_mode_is_8023z(state->interface) ||
1846 state->interface == PHY_INTERFACE_MODE_SGMII)
1847 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1848 else
1849 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1850
1851 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1852 }
1853
1854 enum {
1855 ETHTOOL_XDP_REDIRECT,
1856 ETHTOOL_XDP_PASS,
1857 ETHTOOL_XDP_DROP,
1858 ETHTOOL_XDP_TX,
1859 ETHTOOL_XDP_TX_ERR,
1860 ETHTOOL_XDP_XMIT,
1861 ETHTOOL_XDP_XMIT_ERR,
1862 };
1863
1864 struct mvpp2_ethtool_counter {
1865 unsigned int offset;
1866 const char string[ETH_GSTRING_LEN];
1867 bool reg_is_64b;
1868 };
1869
mvpp2_read_count(struct mvpp2_port * port,const struct mvpp2_ethtool_counter * counter)1870 static u64 mvpp2_read_count(struct mvpp2_port *port,
1871 const struct mvpp2_ethtool_counter *counter)
1872 {
1873 u64 val;
1874
1875 val = readl(port->stats_base + counter->offset);
1876 if (counter->reg_is_64b)
1877 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1878
1879 return val;
1880 }
1881
1882 /* Some counters are accessed indirectly by first writing an index to
1883 * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1884 * register we access, it can be a hit counter for some classification tables,
1885 * a counter specific to a rxq, a txq or a buffer pool.
1886 */
mvpp2_read_index(struct mvpp2 * priv,u32 index,u32 reg)1887 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1888 {
1889 mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1890 return mvpp2_read(priv, reg);
1891 }
1892
1893 /* Due to the fact that software statistics and hardware statistics are, by
1894 * design, incremented at different moments in the chain of packet processing,
1895 * it is very likely that incoming packets could have been dropped after being
1896 * counted by hardware but before reaching software statistics (most probably
1897 * multicast packets), and in the opposite way, during transmission, FCS bytes
1898 * are added in between as well as TSO skb will be split and header bytes added.
1899 * Hence, statistics gathered from userspace with ifconfig (software) and
1900 * ethtool (hardware) cannot be compared.
1901 */
1902 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1903 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1904 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1905 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1906 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1907 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1908 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1909 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1910 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1911 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1912 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1913 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1914 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1915 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1916 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1917 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1918 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1919 { MVPP2_MIB_FC_SENT, "fc_sent" },
1920 { MVPP2_MIB_FC_RCVD, "fc_received" },
1921 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1922 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1923 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1924 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1925 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1926 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1927 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1928 { MVPP2_MIB_COLLISION, "collision" },
1929 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1930 };
1931
1932 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1933 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1934 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1935 };
1936
1937 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1938 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1939 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1940 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1941 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1942 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1943 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1944 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1945 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1946 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1947 };
1948
1949 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1950 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1951 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1952 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1953 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1954 };
1955
1956 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1957 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1958 { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1959 { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1960 { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1961 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1962 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1963 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1964 };
1965
1966 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1967 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1968 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1969 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1970 ARRAY_SIZE(mvpp2_ethtool_xdp))
1971
mvpp2_ethtool_get_strings(struct net_device * netdev,u32 sset,u8 * data)1972 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1973 u8 *data)
1974 {
1975 struct mvpp2_port *port = netdev_priv(netdev);
1976 int i, q;
1977
1978 if (sset != ETH_SS_STATS)
1979 return;
1980
1981 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1982 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1983 ETH_GSTRING_LEN);
1984 data += ETH_GSTRING_LEN;
1985 }
1986
1987 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1988 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1989 ETH_GSTRING_LEN);
1990 data += ETH_GSTRING_LEN;
1991 }
1992
1993 for (q = 0; q < port->ntxqs; q++) {
1994 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1995 snprintf(data, ETH_GSTRING_LEN,
1996 mvpp2_ethtool_txq_regs[i].string, q);
1997 data += ETH_GSTRING_LEN;
1998 }
1999 }
2000
2001 for (q = 0; q < port->nrxqs; q++) {
2002 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
2003 snprintf(data, ETH_GSTRING_LEN,
2004 mvpp2_ethtool_rxq_regs[i].string,
2005 q);
2006 data += ETH_GSTRING_LEN;
2007 }
2008 }
2009
2010 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
2011 strscpy(data, mvpp2_ethtool_xdp[i].string,
2012 ETH_GSTRING_LEN);
2013 data += ETH_GSTRING_LEN;
2014 }
2015 }
2016
2017 static void
mvpp2_get_xdp_stats(struct mvpp2_port * port,struct mvpp2_pcpu_stats * xdp_stats)2018 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
2019 {
2020 unsigned int start;
2021 unsigned int cpu;
2022
2023 /* Gather XDP Statistics */
2024 for_each_possible_cpu(cpu) {
2025 struct mvpp2_pcpu_stats *cpu_stats;
2026 u64 xdp_redirect;
2027 u64 xdp_pass;
2028 u64 xdp_drop;
2029 u64 xdp_xmit;
2030 u64 xdp_xmit_err;
2031 u64 xdp_tx;
2032 u64 xdp_tx_err;
2033
2034 cpu_stats = per_cpu_ptr(port->stats, cpu);
2035 do {
2036 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
2037 xdp_redirect = cpu_stats->xdp_redirect;
2038 xdp_pass = cpu_stats->xdp_pass;
2039 xdp_drop = cpu_stats->xdp_drop;
2040 xdp_xmit = cpu_stats->xdp_xmit;
2041 xdp_xmit_err = cpu_stats->xdp_xmit_err;
2042 xdp_tx = cpu_stats->xdp_tx;
2043 xdp_tx_err = cpu_stats->xdp_tx_err;
2044 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
2045
2046 xdp_stats->xdp_redirect += xdp_redirect;
2047 xdp_stats->xdp_pass += xdp_pass;
2048 xdp_stats->xdp_drop += xdp_drop;
2049 xdp_stats->xdp_xmit += xdp_xmit;
2050 xdp_stats->xdp_xmit_err += xdp_xmit_err;
2051 xdp_stats->xdp_tx += xdp_tx;
2052 xdp_stats->xdp_tx_err += xdp_tx_err;
2053 }
2054 }
2055
mvpp2_read_stats(struct mvpp2_port * port)2056 static void mvpp2_read_stats(struct mvpp2_port *port)
2057 {
2058 struct mvpp2_pcpu_stats xdp_stats = {};
2059 const struct mvpp2_ethtool_counter *s;
2060 u64 *pstats;
2061 int i, q;
2062
2063 pstats = port->ethtool_stats;
2064
2065 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
2066 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
2067
2068 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
2069 *pstats++ += mvpp2_read(port->priv,
2070 mvpp2_ethtool_port_regs[i].offset +
2071 4 * port->id);
2072
2073 for (q = 0; q < port->ntxqs; q++)
2074 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
2075 *pstats++ += mvpp2_read_index(port->priv,
2076 MVPP22_CTRS_TX_CTR(port->id, q),
2077 mvpp2_ethtool_txq_regs[i].offset);
2078
2079 /* Rxqs are numbered from 0 from the user standpoint, but not from the
2080 * driver's. We need to add the port->first_rxq offset.
2081 */
2082 for (q = 0; q < port->nrxqs; q++)
2083 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
2084 *pstats++ += mvpp2_read_index(port->priv,
2085 port->first_rxq + q,
2086 mvpp2_ethtool_rxq_regs[i].offset);
2087
2088 /* Gather XDP Statistics */
2089 mvpp2_get_xdp_stats(port, &xdp_stats);
2090
2091 for (i = 0, s = mvpp2_ethtool_xdp;
2092 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
2093 s++, i++) {
2094 switch (s->offset) {
2095 case ETHTOOL_XDP_REDIRECT:
2096 *pstats++ = xdp_stats.xdp_redirect;
2097 break;
2098 case ETHTOOL_XDP_PASS:
2099 *pstats++ = xdp_stats.xdp_pass;
2100 break;
2101 case ETHTOOL_XDP_DROP:
2102 *pstats++ = xdp_stats.xdp_drop;
2103 break;
2104 case ETHTOOL_XDP_TX:
2105 *pstats++ = xdp_stats.xdp_tx;
2106 break;
2107 case ETHTOOL_XDP_TX_ERR:
2108 *pstats++ = xdp_stats.xdp_tx_err;
2109 break;
2110 case ETHTOOL_XDP_XMIT:
2111 *pstats++ = xdp_stats.xdp_xmit;
2112 break;
2113 case ETHTOOL_XDP_XMIT_ERR:
2114 *pstats++ = xdp_stats.xdp_xmit_err;
2115 break;
2116 }
2117 }
2118 }
2119
mvpp2_gather_hw_statistics(struct work_struct * work)2120 static void mvpp2_gather_hw_statistics(struct work_struct *work)
2121 {
2122 struct delayed_work *del_work = to_delayed_work(work);
2123 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
2124 stats_work);
2125
2126 mutex_lock(&port->gather_stats_lock);
2127
2128 mvpp2_read_stats(port);
2129
2130 /* No need to read again the counters right after this function if it
2131 * was called asynchronously by the user (ie. use of ethtool).
2132 */
2133 cancel_delayed_work(&port->stats_work);
2134 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
2135 MVPP2_MIB_COUNTERS_STATS_DELAY);
2136
2137 mutex_unlock(&port->gather_stats_lock);
2138 }
2139
mvpp2_ethtool_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2140 static void mvpp2_ethtool_get_stats(struct net_device *dev,
2141 struct ethtool_stats *stats, u64 *data)
2142 {
2143 struct mvpp2_port *port = netdev_priv(dev);
2144
2145 /* Update statistics for the given port, then take the lock to avoid
2146 * concurrent accesses on the ethtool_stats structure during its copy.
2147 */
2148 mvpp2_gather_hw_statistics(&port->stats_work.work);
2149
2150 mutex_lock(&port->gather_stats_lock);
2151 memcpy(data, port->ethtool_stats,
2152 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
2153 mutex_unlock(&port->gather_stats_lock);
2154 }
2155
mvpp2_ethtool_get_sset_count(struct net_device * dev,int sset)2156 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
2157 {
2158 struct mvpp2_port *port = netdev_priv(dev);
2159
2160 if (sset == ETH_SS_STATS)
2161 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
2162
2163 return -EOPNOTSUPP;
2164 }
2165
mvpp2_mac_reset_assert(struct mvpp2_port * port)2166 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
2167 {
2168 u32 val;
2169
2170 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
2171 MVPP2_GMAC_PORT_RESET_MASK;
2172 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2173
2174 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
2175 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
2176 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
2177 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
2178 }
2179 }
2180
mvpp22_pcs_reset_assert(struct mvpp2_port * port)2181 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
2182 {
2183 struct mvpp2 *priv = port->priv;
2184 void __iomem *mpcs, *xpcs;
2185 u32 val;
2186
2187 if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2188 return;
2189
2190 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2191 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2192
2193 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2194 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
2195 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
2196 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2197
2198 val = readl(xpcs + MVPP22_XPCS_CFG0);
2199 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2200 }
2201
mvpp22_pcs_reset_deassert(struct mvpp2_port * port,phy_interface_t interface)2202 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port,
2203 phy_interface_t interface)
2204 {
2205 struct mvpp2 *priv = port->priv;
2206 void __iomem *mpcs, *xpcs;
2207 u32 val;
2208
2209 if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2210 return;
2211
2212 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2213 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2214
2215 switch (interface) {
2216 case PHY_INTERFACE_MODE_5GBASER:
2217 case PHY_INTERFACE_MODE_10GBASER:
2218 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2219 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
2220 MAC_CLK_RESET_SD_TX;
2221 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
2222 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2223 break;
2224 case PHY_INTERFACE_MODE_XAUI:
2225 case PHY_INTERFACE_MODE_RXAUI:
2226 val = readl(xpcs + MVPP22_XPCS_CFG0);
2227 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2228 break;
2229 default:
2230 break;
2231 }
2232 }
2233
2234 /* Change maximum receive size of the port */
mvpp2_gmac_max_rx_size_set(struct mvpp2_port * port)2235 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2236 {
2237 u32 val;
2238
2239 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2240 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2241 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2242 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2243 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2244 }
2245
2246 /* Change maximum receive size of the port */
mvpp2_xlg_max_rx_size_set(struct mvpp2_port * port)2247 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
2248 {
2249 u32 val;
2250
2251 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
2252 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
2253 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2254 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
2255 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
2256 }
2257
2258 /* Set defaults to the MVPP2 port */
mvpp2_defaults_set(struct mvpp2_port * port)2259 static void mvpp2_defaults_set(struct mvpp2_port *port)
2260 {
2261 int tx_port_num, val, queue, lrxq;
2262
2263 if (port->priv->hw_version == MVPP21) {
2264 /* Update TX FIFO MIN Threshold */
2265 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2266 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2267 /* Min. TX threshold must be less than minimal packet length */
2268 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2269 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2270 }
2271
2272 /* Disable Legacy WRR, Disable EJP, Release from reset */
2273 tx_port_num = mvpp2_egress_port(port);
2274 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2275 tx_port_num);
2276 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2277
2278 /* Set TXQ scheduling to Round-Robin */
2279 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
2280
2281 /* Close bandwidth for all queues */
2282 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
2283 mvpp2_write(port->priv,
2284 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
2285
2286 /* Set refill period to 1 usec, refill tokens
2287 * and bucket size to maximum
2288 */
2289 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
2290 port->priv->tclk / USEC_PER_SEC);
2291 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2292 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2293 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2294 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2295 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2296 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2297 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2298
2299 /* Set MaximumLowLatencyPacketSize value to 256 */
2300 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2301 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2302 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2303
2304 /* Enable Rx cache snoop */
2305 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2306 queue = port->rxqs[lrxq]->id;
2307 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2308 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2309 MVPP2_SNOOP_BUF_HDR_MASK;
2310 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2311 }
2312
2313 /* At default, mask all interrupts to all present cpus */
2314 mvpp2_interrupts_disable(port);
2315 }
2316
2317 /* Enable/disable receiving packets */
mvpp2_ingress_enable(struct mvpp2_port * port)2318 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2319 {
2320 u32 val;
2321 int lrxq, queue;
2322
2323 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2324 queue = port->rxqs[lrxq]->id;
2325 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2326 val &= ~MVPP2_RXQ_DISABLE_MASK;
2327 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2328 }
2329 }
2330
mvpp2_ingress_disable(struct mvpp2_port * port)2331 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2332 {
2333 u32 val;
2334 int lrxq, queue;
2335
2336 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2337 queue = port->rxqs[lrxq]->id;
2338 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2339 val |= MVPP2_RXQ_DISABLE_MASK;
2340 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2341 }
2342 }
2343
2344 /* Enable transmit via physical egress queue
2345 * - HW starts take descriptors from DRAM
2346 */
mvpp2_egress_enable(struct mvpp2_port * port)2347 static void mvpp2_egress_enable(struct mvpp2_port *port)
2348 {
2349 u32 qmap;
2350 int queue;
2351 int tx_port_num = mvpp2_egress_port(port);
2352
2353 /* Enable all initialized TXs. */
2354 qmap = 0;
2355 for (queue = 0; queue < port->ntxqs; queue++) {
2356 struct mvpp2_tx_queue *txq = port->txqs[queue];
2357
2358 if (txq->descs)
2359 qmap |= (1 << queue);
2360 }
2361
2362 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2363 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2364 }
2365
2366 /* Disable transmit via physical egress queue
2367 * - HW doesn't take descriptors from DRAM
2368 */
mvpp2_egress_disable(struct mvpp2_port * port)2369 static void mvpp2_egress_disable(struct mvpp2_port *port)
2370 {
2371 u32 reg_data;
2372 int delay;
2373 int tx_port_num = mvpp2_egress_port(port);
2374
2375 /* Issue stop command for active channels only */
2376 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2377 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2378 MVPP2_TXP_SCHED_ENQ_MASK;
2379 if (reg_data != 0)
2380 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2381 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2382
2383 /* Wait for all Tx activity to terminate. */
2384 delay = 0;
2385 do {
2386 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2387 netdev_warn(port->dev,
2388 "Tx stop timed out, status=0x%08x\n",
2389 reg_data);
2390 break;
2391 }
2392 mdelay(1);
2393 delay++;
2394
2395 /* Check port TX Command register that all
2396 * Tx queues are stopped
2397 */
2398 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2399 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2400 }
2401
2402 /* Rx descriptors helper methods */
2403
2404 /* Get number of Rx descriptors occupied by received packets */
2405 static inline int
mvpp2_rxq_received(struct mvpp2_port * port,int rxq_id)2406 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2407 {
2408 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2409
2410 return val & MVPP2_RXQ_OCCUPIED_MASK;
2411 }
2412
2413 /* Update Rx queue status with the number of occupied and available
2414 * Rx descriptor slots.
2415 */
2416 static inline void
mvpp2_rxq_status_update(struct mvpp2_port * port,int rxq_id,int used_count,int free_count)2417 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2418 int used_count, int free_count)
2419 {
2420 /* Decrement the number of used descriptors and increment count
2421 * increment the number of free descriptors.
2422 */
2423 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2424
2425 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2426 }
2427
2428 /* Get pointer to next RX descriptor to be processed by SW */
2429 static inline struct mvpp2_rx_desc *
mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue * rxq)2430 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2431 {
2432 int rx_desc = rxq->next_desc_to_proc;
2433
2434 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2435 prefetch(rxq->descs + rxq->next_desc_to_proc);
2436 return rxq->descs + rx_desc;
2437 }
2438
2439 /* Set rx queue offset */
mvpp2_rxq_offset_set(struct mvpp2_port * port,int prxq,int offset)2440 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2441 int prxq, int offset)
2442 {
2443 u32 val;
2444
2445 /* Convert offset from bytes to units of 32 bytes */
2446 offset = offset >> 5;
2447
2448 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2449 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2450
2451 /* Offset is in */
2452 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2453 MVPP2_RXQ_PACKET_OFFSET_MASK);
2454
2455 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2456 }
2457
2458 /* Tx descriptors helper methods */
2459
2460 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2461 static struct mvpp2_tx_desc *
mvpp2_txq_next_desc_get(struct mvpp2_tx_queue * txq)2462 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2463 {
2464 int tx_desc = txq->next_desc_to_proc;
2465
2466 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2467 return txq->descs + tx_desc;
2468 }
2469
2470 /* Update HW with number of aggregated Tx descriptors to be sent
2471 *
2472 * Called only from mvpp2_tx(), so migration is disabled, using
2473 * smp_processor_id() is OK.
2474 */
mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port * port,int pending)2475 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2476 {
2477 /* aggregated access - relevant TXQ number is written in TX desc */
2478 mvpp2_thread_write(port->priv,
2479 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2480 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2481 }
2482
2483 /* Check if there are enough free descriptors in aggregated txq.
2484 * If not, update the number of occupied descriptors and repeat the check.
2485 *
2486 * Called only from mvpp2_tx(), so migration is disabled, using
2487 * smp_processor_id() is OK.
2488 */
mvpp2_aggr_desc_num_check(struct mvpp2_port * port,struct mvpp2_tx_queue * aggr_txq,int num)2489 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2490 struct mvpp2_tx_queue *aggr_txq, int num)
2491 {
2492 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2493 /* Update number of occupied aggregated Tx descriptors */
2494 unsigned int thread =
2495 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2496 u32 val = mvpp2_read_relaxed(port->priv,
2497 MVPP2_AGGR_TXQ_STATUS_REG(thread));
2498
2499 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2500
2501 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2502 return -ENOMEM;
2503 }
2504 return 0;
2505 }
2506
2507 /* Reserved Tx descriptors allocation request
2508 *
2509 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2510 * only by mvpp2_tx(), so migration is disabled, using
2511 * smp_processor_id() is OK.
2512 */
mvpp2_txq_alloc_reserved_desc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,int num)2513 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2514 struct mvpp2_tx_queue *txq, int num)
2515 {
2516 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2517 struct mvpp2 *priv = port->priv;
2518 u32 val;
2519
2520 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2521 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2522
2523 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2524
2525 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2526 }
2527
2528 /* Check if there are enough reserved descriptors for transmission.
2529 * If not, request chunk of reserved descriptors and check again.
2530 */
mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu,int num)2531 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2532 struct mvpp2_tx_queue *txq,
2533 struct mvpp2_txq_pcpu *txq_pcpu,
2534 int num)
2535 {
2536 int req, desc_count;
2537 unsigned int thread;
2538
2539 if (txq_pcpu->reserved_num >= num)
2540 return 0;
2541
2542 /* Not enough descriptors reserved! Update the reserved descriptor
2543 * count and check again.
2544 */
2545
2546 desc_count = 0;
2547 /* Compute total of used descriptors */
2548 for (thread = 0; thread < port->priv->nthreads; thread++) {
2549 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2550
2551 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2552 desc_count += txq_pcpu_aux->count;
2553 desc_count += txq_pcpu_aux->reserved_num;
2554 }
2555
2556 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2557 desc_count += req;
2558
2559 if (desc_count >
2560 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2561 return -ENOMEM;
2562
2563 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2564
2565 /* OK, the descriptor could have been updated: check again. */
2566 if (txq_pcpu->reserved_num < num)
2567 return -ENOMEM;
2568 return 0;
2569 }
2570
2571 /* Release the last allocated Tx descriptor. Useful to handle DMA
2572 * mapping failures in the Tx path.
2573 */
mvpp2_txq_desc_put(struct mvpp2_tx_queue * txq)2574 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2575 {
2576 if (txq->next_desc_to_proc == 0)
2577 txq->next_desc_to_proc = txq->last_desc - 1;
2578 else
2579 txq->next_desc_to_proc--;
2580 }
2581
2582 /* Set Tx descriptors fields relevant for CSUM calculation */
mvpp2_txq_desc_csum(int l3_offs,__be16 l3_proto,int ip_hdr_len,int l4_proto)2583 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2584 int ip_hdr_len, int l4_proto)
2585 {
2586 u32 command;
2587
2588 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2589 * G_L4_chk, L4_type required only for checksum calculation
2590 */
2591 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2592 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2593 command |= MVPP2_TXD_IP_CSUM_DISABLE;
2594
2595 if (l3_proto == htons(ETH_P_IP)) {
2596 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
2597 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
2598 } else {
2599 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
2600 }
2601
2602 if (l4_proto == IPPROTO_TCP) {
2603 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
2604 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2605 } else if (l4_proto == IPPROTO_UDP) {
2606 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
2607 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2608 } else {
2609 command |= MVPP2_TXD_L4_CSUM_NOT;
2610 }
2611
2612 return command;
2613 }
2614
2615 /* Get number of sent descriptors and decrement counter.
2616 * The number of sent descriptors is returned.
2617 * Per-thread access
2618 *
2619 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2620 * (migration disabled) and from the TX completion tasklet (migration
2621 * disabled) so using smp_processor_id() is OK.
2622 */
mvpp2_txq_sent_desc_proc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)2623 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2624 struct mvpp2_tx_queue *txq)
2625 {
2626 u32 val;
2627
2628 /* Reading status reg resets transmitted descriptor counter */
2629 val = mvpp2_thread_read_relaxed(port->priv,
2630 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2631 MVPP2_TXQ_SENT_REG(txq->id));
2632
2633 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2634 MVPP2_TRANSMITTED_COUNT_OFFSET;
2635 }
2636
2637 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2638 * disabled, therefore using smp_processor_id() is OK.
2639 */
mvpp2_txq_sent_counter_clear(void * arg)2640 static void mvpp2_txq_sent_counter_clear(void *arg)
2641 {
2642 struct mvpp2_port *port = arg;
2643 int queue;
2644
2645 /* If the thread isn't used, don't do anything */
2646 if (smp_processor_id() >= port->priv->nthreads)
2647 return;
2648
2649 for (queue = 0; queue < port->ntxqs; queue++) {
2650 int id = port->txqs[queue]->id;
2651
2652 mvpp2_thread_read(port->priv,
2653 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2654 MVPP2_TXQ_SENT_REG(id));
2655 }
2656 }
2657
2658 /* Set max sizes for Tx queues */
mvpp2_txp_max_tx_size_set(struct mvpp2_port * port)2659 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2660 {
2661 u32 val, size, mtu;
2662 int txq, tx_port_num;
2663
2664 mtu = port->pkt_size * 8;
2665 if (mtu > MVPP2_TXP_MTU_MAX)
2666 mtu = MVPP2_TXP_MTU_MAX;
2667
2668 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2669 mtu = 3 * mtu;
2670
2671 /* Indirect access to registers */
2672 tx_port_num = mvpp2_egress_port(port);
2673 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2674
2675 /* Set MTU */
2676 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2677 val &= ~MVPP2_TXP_MTU_MAX;
2678 val |= mtu;
2679 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2680
2681 /* TXP token size and all TXQs token size must be larger that MTU */
2682 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2683 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2684 if (size < mtu) {
2685 size = mtu;
2686 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2687 val |= size;
2688 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2689 }
2690
2691 for (txq = 0; txq < port->ntxqs; txq++) {
2692 val = mvpp2_read(port->priv,
2693 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2694 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2695
2696 if (size < mtu) {
2697 size = mtu;
2698 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2699 val |= size;
2700 mvpp2_write(port->priv,
2701 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2702 val);
2703 }
2704 }
2705 }
2706
2707 /* Set the number of non-occupied descriptors threshold */
mvpp2_set_rxq_free_tresh(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2708 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
2709 struct mvpp2_rx_queue *rxq)
2710 {
2711 u32 val;
2712
2713 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2714
2715 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
2716 val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
2717 val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
2718 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
2719 }
2720
2721 /* Set the number of packets that will be received before Rx interrupt
2722 * will be generated by HW.
2723 */
mvpp2_rx_pkts_coal_set(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2724 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2725 struct mvpp2_rx_queue *rxq)
2726 {
2727 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2728
2729 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2730 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2731
2732 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2733 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2734 rxq->pkts_coal);
2735
2736 put_cpu();
2737 }
2738
2739 /* For some reason in the LSP this is done on each CPU. Why ? */
mvpp2_tx_pkts_coal_set(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)2740 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2741 struct mvpp2_tx_queue *txq)
2742 {
2743 unsigned int thread;
2744 u32 val;
2745
2746 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2747 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2748
2749 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2750 /* PKT-coalescing registers are per-queue + per-thread */
2751 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2752 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2753 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2754 }
2755 }
2756
mvpp2_usec_to_cycles(u32 usec,unsigned long clk_hz)2757 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2758 {
2759 u64 tmp = (u64)clk_hz * usec;
2760
2761 do_div(tmp, USEC_PER_SEC);
2762
2763 return tmp > U32_MAX ? U32_MAX : tmp;
2764 }
2765
mvpp2_cycles_to_usec(u32 cycles,unsigned long clk_hz)2766 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2767 {
2768 u64 tmp = (u64)cycles * USEC_PER_SEC;
2769
2770 do_div(tmp, clk_hz);
2771
2772 return tmp > U32_MAX ? U32_MAX : tmp;
2773 }
2774
2775 /* Set the time delay in usec before Rx interrupt */
mvpp2_rx_time_coal_set(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2776 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2777 struct mvpp2_rx_queue *rxq)
2778 {
2779 unsigned long freq = port->priv->tclk;
2780 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2781
2782 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2783 rxq->time_coal =
2784 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2785
2786 /* re-evaluate to get actual register value */
2787 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2788 }
2789
2790 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2791 }
2792
mvpp2_tx_time_coal_set(struct mvpp2_port * port)2793 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2794 {
2795 unsigned long freq = port->priv->tclk;
2796 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2797
2798 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2799 port->tx_time_coal =
2800 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2801
2802 /* re-evaluate to get actual register value */
2803 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2804 }
2805
2806 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2807 }
2808
2809 /* Free Tx queue skbuffs */
mvpp2_txq_bufs_free(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu,int num)2810 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2811 struct mvpp2_tx_queue *txq,
2812 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2813 {
2814 struct xdp_frame_bulk bq;
2815 int i;
2816
2817 xdp_frame_bulk_init(&bq);
2818
2819 rcu_read_lock(); /* need for xdp_return_frame_bulk */
2820
2821 for (i = 0; i < num; i++) {
2822 struct mvpp2_txq_pcpu_buf *tx_buf =
2823 txq_pcpu->buffs + txq_pcpu->txq_get_index;
2824
2825 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2826 tx_buf->type != MVPP2_TYPE_XDP_TX)
2827 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2828 tx_buf->size, DMA_TO_DEVICE);
2829 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2830 dev_kfree_skb_any(tx_buf->skb);
2831 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2832 tx_buf->type == MVPP2_TYPE_XDP_NDO)
2833 xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2834
2835 mvpp2_txq_inc_get(txq_pcpu);
2836 }
2837 xdp_flush_frame_bulk(&bq);
2838
2839 rcu_read_unlock();
2840 }
2841
mvpp2_get_rx_queue(struct mvpp2_port * port,u32 cause)2842 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2843 u32 cause)
2844 {
2845 int queue = fls(cause) - 1;
2846
2847 return port->rxqs[queue];
2848 }
2849
mvpp2_get_tx_queue(struct mvpp2_port * port,u32 cause)2850 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2851 u32 cause)
2852 {
2853 int queue = fls(cause) - 1;
2854
2855 return port->txqs[queue];
2856 }
2857
2858 /* Handle end of transmission */
mvpp2_txq_done(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu)2859 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2860 struct mvpp2_txq_pcpu *txq_pcpu)
2861 {
2862 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2863 int tx_done;
2864
2865 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2866 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2867
2868 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2869 if (!tx_done)
2870 return;
2871 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2872
2873 txq_pcpu->count -= tx_done;
2874
2875 if (netif_tx_queue_stopped(nq))
2876 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2877 netif_tx_wake_queue(nq);
2878 }
2879
mvpp2_tx_done(struct mvpp2_port * port,u32 cause,unsigned int thread)2880 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2881 unsigned int thread)
2882 {
2883 struct mvpp2_tx_queue *txq;
2884 struct mvpp2_txq_pcpu *txq_pcpu;
2885 unsigned int tx_todo = 0;
2886
2887 while (cause) {
2888 txq = mvpp2_get_tx_queue(port, cause);
2889 if (!txq)
2890 break;
2891
2892 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2893
2894 if (txq_pcpu->count) {
2895 mvpp2_txq_done(port, txq, txq_pcpu);
2896 tx_todo += txq_pcpu->count;
2897 }
2898
2899 cause &= ~(1 << txq->log_id);
2900 }
2901 return tx_todo;
2902 }
2903
2904 /* Rx/Tx queue initialization/cleanup methods */
2905
2906 /* Allocate and initialize descriptors for aggr TXQ */
mvpp2_aggr_txq_init(struct platform_device * pdev,struct mvpp2_tx_queue * aggr_txq,unsigned int thread,struct mvpp2 * priv)2907 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2908 struct mvpp2_tx_queue *aggr_txq,
2909 unsigned int thread, struct mvpp2 *priv)
2910 {
2911 u32 txq_dma;
2912
2913 /* Allocate memory for TX descriptors */
2914 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2915 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2916 &aggr_txq->descs_dma, GFP_KERNEL);
2917 if (!aggr_txq->descs)
2918 return -ENOMEM;
2919
2920 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2921
2922 /* Aggr TXQ no reset WA */
2923 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2924 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2925
2926 /* Set Tx descriptors queue starting address indirect
2927 * access
2928 */
2929 if (priv->hw_version == MVPP21)
2930 txq_dma = aggr_txq->descs_dma;
2931 else
2932 txq_dma = aggr_txq->descs_dma >>
2933 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2934
2935 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2936 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2937 MVPP2_AGGR_TXQ_SIZE);
2938
2939 return 0;
2940 }
2941
2942 /* Create a specified Rx queue */
mvpp2_rxq_init(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2943 static int mvpp2_rxq_init(struct mvpp2_port *port,
2944 struct mvpp2_rx_queue *rxq)
2945 {
2946 struct mvpp2 *priv = port->priv;
2947 unsigned int thread;
2948 u32 rxq_dma;
2949 int err;
2950
2951 rxq->size = port->rx_ring_size;
2952
2953 /* Allocate memory for RX descriptors */
2954 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2955 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2956 &rxq->descs_dma, GFP_KERNEL);
2957 if (!rxq->descs)
2958 return -ENOMEM;
2959
2960 rxq->last_desc = rxq->size - 1;
2961
2962 /* Zero occupied and non-occupied counters - direct access */
2963 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2964
2965 /* Set Rx descriptors queue starting address - indirect access */
2966 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2967 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2968 if (port->priv->hw_version == MVPP21)
2969 rxq_dma = rxq->descs_dma;
2970 else
2971 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2972 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2973 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2974 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2975 put_cpu();
2976
2977 /* Set Offset */
2978 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2979
2980 /* Set coalescing pkts and time */
2981 mvpp2_rx_pkts_coal_set(port, rxq);
2982 mvpp2_rx_time_coal_set(port, rxq);
2983
2984 /* Set the number of non occupied descriptors threshold */
2985 mvpp2_set_rxq_free_tresh(port, rxq);
2986
2987 /* Add number of descriptors ready for receiving packets */
2988 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2989
2990 if (priv->percpu_pools) {
2991 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0);
2992 if (err < 0)
2993 goto err_free_dma;
2994
2995 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0);
2996 if (err < 0)
2997 goto err_unregister_rxq_short;
2998
2999 /* Every RXQ has a pool for short and another for long packets */
3000 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
3001 MEM_TYPE_PAGE_POOL,
3002 priv->page_pool[rxq->logic_rxq]);
3003 if (err < 0)
3004 goto err_unregister_rxq_long;
3005
3006 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
3007 MEM_TYPE_PAGE_POOL,
3008 priv->page_pool[rxq->logic_rxq +
3009 port->nrxqs]);
3010 if (err < 0)
3011 goto err_unregister_mem_rxq_short;
3012 }
3013
3014 return 0;
3015
3016 err_unregister_mem_rxq_short:
3017 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
3018 err_unregister_rxq_long:
3019 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3020 err_unregister_rxq_short:
3021 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3022 err_free_dma:
3023 dma_free_coherent(port->dev->dev.parent,
3024 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3025 rxq->descs, rxq->descs_dma);
3026 return err;
3027 }
3028
3029 /* Push packets received by the RXQ to BM pool */
mvpp2_rxq_drop_pkts(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)3030 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3031 struct mvpp2_rx_queue *rxq)
3032 {
3033 int rx_received, i;
3034
3035 rx_received = mvpp2_rxq_received(port, rxq->id);
3036 if (!rx_received)
3037 return;
3038
3039 for (i = 0; i < rx_received; i++) {
3040 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3041 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3042 int pool;
3043
3044 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3045 MVPP2_RXD_BM_POOL_ID_OFFS;
3046
3047 mvpp2_bm_pool_put(port, pool,
3048 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3049 mvpp2_rxdesc_cookie_get(port, rx_desc));
3050 }
3051 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3052 }
3053
3054 /* Cleanup Rx queue */
mvpp2_rxq_deinit(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)3055 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3056 struct mvpp2_rx_queue *rxq)
3057 {
3058 unsigned int thread;
3059
3060 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
3061 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3062
3063 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
3064 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3065
3066 mvpp2_rxq_drop_pkts(port, rxq);
3067
3068 if (rxq->descs)
3069 dma_free_coherent(port->dev->dev.parent,
3070 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3071 rxq->descs,
3072 rxq->descs_dma);
3073
3074 rxq->descs = NULL;
3075 rxq->last_desc = 0;
3076 rxq->next_desc_to_proc = 0;
3077 rxq->descs_dma = 0;
3078
3079 /* Clear Rx descriptors queue starting address and size;
3080 * free descriptor number
3081 */
3082 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3083 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3084 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
3085 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
3086 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
3087 put_cpu();
3088 }
3089
3090 /* Create and initialize a Tx queue */
mvpp2_txq_init(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3091 static int mvpp2_txq_init(struct mvpp2_port *port,
3092 struct mvpp2_tx_queue *txq)
3093 {
3094 u32 val;
3095 unsigned int thread;
3096 int desc, desc_per_txq, tx_port_num;
3097 struct mvpp2_txq_pcpu *txq_pcpu;
3098
3099 txq->size = port->tx_ring_size;
3100
3101 /* Allocate memory for Tx descriptors */
3102 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
3103 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3104 &txq->descs_dma, GFP_KERNEL);
3105 if (!txq->descs)
3106 return -ENOMEM;
3107
3108 txq->last_desc = txq->size - 1;
3109
3110 /* Set Tx descriptors queue starting address - indirect access */
3111 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3112 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3113 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
3114 txq->descs_dma);
3115 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
3116 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
3117 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
3118 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
3119 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3120 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3121 val &= ~MVPP2_TXQ_PENDING_MASK;
3122 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3123
3124 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3125 * for each existing TXQ.
3126 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3127 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3128 */
3129 desc_per_txq = 16;
3130 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3131 (txq->log_id * desc_per_txq);
3132
3133 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
3134 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3135 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3136 put_cpu();
3137
3138 /* WRR / EJP configuration - indirect access */
3139 tx_port_num = mvpp2_egress_port(port);
3140 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3141
3142 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3143 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3144 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3145 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3146 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3147
3148 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3149 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3150 val);
3151
3152 for (thread = 0; thread < port->priv->nthreads; thread++) {
3153 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3154 txq_pcpu->size = txq->size;
3155 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
3156 sizeof(*txq_pcpu->buffs),
3157 GFP_KERNEL);
3158 if (!txq_pcpu->buffs)
3159 return -ENOMEM;
3160
3161 txq_pcpu->count = 0;
3162 txq_pcpu->reserved_num = 0;
3163 txq_pcpu->txq_put_index = 0;
3164 txq_pcpu->txq_get_index = 0;
3165 txq_pcpu->tso_headers = NULL;
3166
3167 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
3168 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
3169
3170 txq_pcpu->tso_headers =
3171 dma_alloc_coherent(port->dev->dev.parent,
3172 txq_pcpu->size * TSO_HEADER_SIZE,
3173 &txq_pcpu->tso_headers_dma,
3174 GFP_KERNEL);
3175 if (!txq_pcpu->tso_headers)
3176 return -ENOMEM;
3177 }
3178
3179 return 0;
3180 }
3181
3182 /* Free allocated TXQ resources */
mvpp2_txq_deinit(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3183 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3184 struct mvpp2_tx_queue *txq)
3185 {
3186 struct mvpp2_txq_pcpu *txq_pcpu;
3187 unsigned int thread;
3188
3189 for (thread = 0; thread < port->priv->nthreads; thread++) {
3190 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3191 kfree(txq_pcpu->buffs);
3192
3193 if (txq_pcpu->tso_headers)
3194 dma_free_coherent(port->dev->dev.parent,
3195 txq_pcpu->size * TSO_HEADER_SIZE,
3196 txq_pcpu->tso_headers,
3197 txq_pcpu->tso_headers_dma);
3198
3199 txq_pcpu->tso_headers = NULL;
3200 }
3201
3202 if (txq->descs)
3203 dma_free_coherent(port->dev->dev.parent,
3204 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3205 txq->descs, txq->descs_dma);
3206
3207 txq->descs = NULL;
3208 txq->last_desc = 0;
3209 txq->next_desc_to_proc = 0;
3210 txq->descs_dma = 0;
3211
3212 /* Set minimum bandwidth for disabled TXQs */
3213 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3214
3215 /* Set Tx descriptors queue starting address and size */
3216 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3217 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3218 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
3219 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
3220 put_cpu();
3221 }
3222
3223 /* Cleanup Tx ports */
mvpp2_txq_clean(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3224 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3225 {
3226 struct mvpp2_txq_pcpu *txq_pcpu;
3227 int delay, pending;
3228 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3229 u32 val;
3230
3231 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3232 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3233 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3234 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3235
3236 /* The napi queue has been stopped so wait for all packets
3237 * to be transmitted.
3238 */
3239 delay = 0;
3240 do {
3241 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3242 netdev_warn(port->dev,
3243 "port %d: cleaning queue %d timed out\n",
3244 port->id, txq->log_id);
3245 break;
3246 }
3247 mdelay(1);
3248 delay++;
3249
3250 pending = mvpp2_thread_read(port->priv, thread,
3251 MVPP2_TXQ_PENDING_REG);
3252 pending &= MVPP2_TXQ_PENDING_MASK;
3253 } while (pending);
3254
3255 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3256 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3257 put_cpu();
3258
3259 for (thread = 0; thread < port->priv->nthreads; thread++) {
3260 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3261
3262 /* Release all packets */
3263 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3264
3265 /* Reset queue */
3266 txq_pcpu->count = 0;
3267 txq_pcpu->txq_put_index = 0;
3268 txq_pcpu->txq_get_index = 0;
3269 }
3270 }
3271
3272 /* Cleanup all Tx queues */
mvpp2_cleanup_txqs(struct mvpp2_port * port)3273 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3274 {
3275 struct mvpp2_tx_queue *txq;
3276 int queue;
3277 u32 val;
3278
3279 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3280
3281 /* Reset Tx ports and delete Tx queues */
3282 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3283 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3284
3285 for (queue = 0; queue < port->ntxqs; queue++) {
3286 txq = port->txqs[queue];
3287 mvpp2_txq_clean(port, txq);
3288 mvpp2_txq_deinit(port, txq);
3289 }
3290
3291 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3292
3293 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3294 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3295 }
3296
3297 /* Cleanup all Rx queues */
mvpp2_cleanup_rxqs(struct mvpp2_port * port)3298 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3299 {
3300 int queue;
3301
3302 for (queue = 0; queue < port->nrxqs; queue++)
3303 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3304
3305 if (port->tx_fc)
3306 mvpp2_rxq_disable_fc(port);
3307 }
3308
3309 /* Init all Rx queues for port */
mvpp2_setup_rxqs(struct mvpp2_port * port)3310 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3311 {
3312 int queue, err;
3313
3314 for (queue = 0; queue < port->nrxqs; queue++) {
3315 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3316 if (err)
3317 goto err_cleanup;
3318 }
3319
3320 if (port->tx_fc)
3321 mvpp2_rxq_enable_fc(port);
3322
3323 return 0;
3324
3325 err_cleanup:
3326 mvpp2_cleanup_rxqs(port);
3327 return err;
3328 }
3329
3330 /* Init all tx queues for port */
mvpp2_setup_txqs(struct mvpp2_port * port)3331 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3332 {
3333 struct mvpp2_tx_queue *txq;
3334 int queue, err;
3335
3336 for (queue = 0; queue < port->ntxqs; queue++) {
3337 txq = port->txqs[queue];
3338 err = mvpp2_txq_init(port, txq);
3339 if (err)
3340 goto err_cleanup;
3341
3342 /* Assign this queue to a CPU */
3343 if (queue < num_possible_cpus())
3344 netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
3345 }
3346
3347 if (port->has_tx_irqs) {
3348 mvpp2_tx_time_coal_set(port);
3349 for (queue = 0; queue < port->ntxqs; queue++) {
3350 txq = port->txqs[queue];
3351 mvpp2_tx_pkts_coal_set(port, txq);
3352 }
3353 }
3354
3355 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3356 return 0;
3357
3358 err_cleanup:
3359 mvpp2_cleanup_txqs(port);
3360 return err;
3361 }
3362
3363 /* The callback for per-port interrupt */
mvpp2_isr(int irq,void * dev_id)3364 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
3365 {
3366 struct mvpp2_queue_vector *qv = dev_id;
3367
3368 mvpp2_qvec_interrupt_disable(qv);
3369
3370 napi_schedule(&qv->napi);
3371
3372 return IRQ_HANDLED;
3373 }
3374
mvpp2_isr_handle_ptp_queue(struct mvpp2_port * port,int nq)3375 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
3376 {
3377 struct skb_shared_hwtstamps shhwtstamps;
3378 struct mvpp2_hwtstamp_queue *queue;
3379 struct sk_buff *skb;
3380 void __iomem *ptp_q;
3381 unsigned int id;
3382 u32 r0, r1, r2;
3383
3384 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3385 if (nq)
3386 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3387
3388 queue = &port->tx_hwtstamp_queue[nq];
3389
3390 while (1) {
3391 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3392 if (!r0)
3393 break;
3394
3395 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3396 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3397
3398 id = (r0 >> 1) & 31;
3399
3400 skb = queue->skb[id];
3401 queue->skb[id] = NULL;
3402 if (skb) {
3403 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3404
3405 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3406 skb_tstamp_tx(skb, &shhwtstamps);
3407 dev_kfree_skb_any(skb);
3408 }
3409 }
3410 }
3411
mvpp2_isr_handle_ptp(struct mvpp2_port * port)3412 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3413 {
3414 void __iomem *ptp;
3415 u32 val;
3416
3417 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3418 val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3419 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3420 mvpp2_isr_handle_ptp_queue(port, 0);
3421 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3422 mvpp2_isr_handle_ptp_queue(port, 1);
3423 }
3424
mvpp2_isr_handle_link(struct mvpp2_port * port,bool link)3425 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3426 {
3427 struct net_device *dev = port->dev;
3428
3429 if (port->phylink) {
3430 phylink_mac_change(port->phylink, link);
3431 return;
3432 }
3433
3434 if (!netif_running(dev))
3435 return;
3436
3437 if (link) {
3438 mvpp2_interrupts_enable(port);
3439
3440 mvpp2_egress_enable(port);
3441 mvpp2_ingress_enable(port);
3442 netif_carrier_on(dev);
3443 netif_tx_wake_all_queues(dev);
3444 } else {
3445 netif_tx_stop_all_queues(dev);
3446 netif_carrier_off(dev);
3447 mvpp2_ingress_disable(port);
3448 mvpp2_egress_disable(port);
3449
3450 mvpp2_interrupts_disable(port);
3451 }
3452 }
3453
mvpp2_isr_handle_xlg(struct mvpp2_port * port)3454 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3455 {
3456 bool link;
3457 u32 val;
3458
3459 val = readl(port->base + MVPP22_XLG_INT_STAT);
3460 if (val & MVPP22_XLG_INT_STAT_LINK) {
3461 val = readl(port->base + MVPP22_XLG_STATUS);
3462 link = (val & MVPP22_XLG_STATUS_LINK_UP);
3463 mvpp2_isr_handle_link(port, link);
3464 }
3465 }
3466
mvpp2_isr_handle_gmac_internal(struct mvpp2_port * port)3467 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3468 {
3469 bool link;
3470 u32 val;
3471
3472 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3473 phy_interface_mode_is_8023z(port->phy_interface) ||
3474 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3475 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3476 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3477 val = readl(port->base + MVPP2_GMAC_STATUS0);
3478 link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3479 mvpp2_isr_handle_link(port, link);
3480 }
3481 }
3482 }
3483
3484 /* Per-port interrupt for link status changes */
mvpp2_port_isr(int irq,void * dev_id)3485 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3486 {
3487 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3488 u32 val;
3489
3490 mvpp22_gop_mask_irq(port);
3491
3492 if (mvpp2_port_supports_xlg(port) &&
3493 mvpp2_is_xlg(port->phy_interface)) {
3494 /* Check the external status register */
3495 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3496 if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3497 mvpp2_isr_handle_xlg(port);
3498 if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3499 mvpp2_isr_handle_ptp(port);
3500 } else {
3501 /* If it's not the XLG, we must be using the GMAC.
3502 * Check the summary status.
3503 */
3504 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3505 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3506 mvpp2_isr_handle_gmac_internal(port);
3507 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3508 mvpp2_isr_handle_ptp(port);
3509 }
3510
3511 mvpp22_gop_unmask_irq(port);
3512 return IRQ_HANDLED;
3513 }
3514
mvpp2_hr_timer_cb(struct hrtimer * timer)3515 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3516 {
3517 struct net_device *dev;
3518 struct mvpp2_port *port;
3519 struct mvpp2_port_pcpu *port_pcpu;
3520 unsigned int tx_todo, cause;
3521
3522 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3523 dev = port_pcpu->dev;
3524
3525 if (!netif_running(dev))
3526 return HRTIMER_NORESTART;
3527
3528 port_pcpu->timer_scheduled = false;
3529 port = netdev_priv(dev);
3530
3531 /* Process all the Tx queues */
3532 cause = (1 << port->ntxqs) - 1;
3533 tx_todo = mvpp2_tx_done(port, cause,
3534 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3535
3536 /* Set the timer in case not all the packets were processed */
3537 if (tx_todo && !port_pcpu->timer_scheduled) {
3538 port_pcpu->timer_scheduled = true;
3539 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3540 MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3541
3542 return HRTIMER_RESTART;
3543 }
3544 return HRTIMER_NORESTART;
3545 }
3546
3547 /* Main RX/TX processing routines */
3548
3549 /* Display more error info */
mvpp2_rx_error(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)3550 static void mvpp2_rx_error(struct mvpp2_port *port,
3551 struct mvpp2_rx_desc *rx_desc)
3552 {
3553 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3554 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3555 char *err_str = NULL;
3556
3557 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3558 case MVPP2_RXD_ERR_CRC:
3559 err_str = "crc";
3560 break;
3561 case MVPP2_RXD_ERR_OVERRUN:
3562 err_str = "overrun";
3563 break;
3564 case MVPP2_RXD_ERR_RESOURCE:
3565 err_str = "resource";
3566 break;
3567 }
3568 if (err_str && net_ratelimit())
3569 netdev_err(port->dev,
3570 "bad rx status %08x (%s error), size=%zu\n",
3571 status, err_str, sz);
3572 }
3573
3574 /* Handle RX checksum offload */
mvpp2_rx_csum(struct mvpp2_port * port,u32 status)3575 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status)
3576 {
3577 if (((status & MVPP2_RXD_L3_IP4) &&
3578 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3579 (status & MVPP2_RXD_L3_IP6))
3580 if (((status & MVPP2_RXD_L4_UDP) ||
3581 (status & MVPP2_RXD_L4_TCP)) &&
3582 (status & MVPP2_RXD_L4_CSUM_OK))
3583 return CHECKSUM_UNNECESSARY;
3584
3585 return CHECKSUM_NONE;
3586 }
3587
3588 /* Allocate a new skb and add it to BM pool */
mvpp2_rx_refill(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,struct page_pool * page_pool,int pool)3589 static int mvpp2_rx_refill(struct mvpp2_port *port,
3590 struct mvpp2_bm_pool *bm_pool,
3591 struct page_pool *page_pool, int pool)
3592 {
3593 dma_addr_t dma_addr;
3594 phys_addr_t phys_addr;
3595 void *buf;
3596
3597 buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3598 &dma_addr, &phys_addr, GFP_ATOMIC);
3599 if (!buf)
3600 return -ENOMEM;
3601
3602 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3603
3604 return 0;
3605 }
3606
3607 /* Handle tx checksum */
mvpp2_skb_tx_csum(struct mvpp2_port * port,struct sk_buff * skb)3608 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3609 {
3610 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3611 int ip_hdr_len = 0;
3612 u8 l4_proto;
3613 __be16 l3_proto = vlan_get_protocol(skb);
3614
3615 if (l3_proto == htons(ETH_P_IP)) {
3616 struct iphdr *ip4h = ip_hdr(skb);
3617
3618 /* Calculate IPv4 checksum and L4 checksum */
3619 ip_hdr_len = ip4h->ihl;
3620 l4_proto = ip4h->protocol;
3621 } else if (l3_proto == htons(ETH_P_IPV6)) {
3622 struct ipv6hdr *ip6h = ipv6_hdr(skb);
3623
3624 /* Read l4_protocol from one of IPv6 extra headers */
3625 if (skb_network_header_len(skb) > 0)
3626 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3627 l4_proto = ip6h->nexthdr;
3628 } else {
3629 return MVPP2_TXD_L4_CSUM_NOT;
3630 }
3631
3632 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3633 l3_proto, ip_hdr_len, l4_proto);
3634 }
3635
3636 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3637 }
3638
mvpp2_xdp_finish_tx(struct mvpp2_port * port,u16 txq_id,int nxmit,int nxmit_byte)3639 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3640 {
3641 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3642 struct mvpp2_tx_queue *aggr_txq;
3643 struct mvpp2_txq_pcpu *txq_pcpu;
3644 struct mvpp2_tx_queue *txq;
3645 struct netdev_queue *nq;
3646
3647 txq = port->txqs[txq_id];
3648 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3649 nq = netdev_get_tx_queue(port->dev, txq_id);
3650 aggr_txq = &port->priv->aggr_txqs[thread];
3651
3652 txq_pcpu->reserved_num -= nxmit;
3653 txq_pcpu->count += nxmit;
3654 aggr_txq->count += nxmit;
3655
3656 /* Enable transmit */
3657 wmb();
3658 mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3659
3660 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3661 netif_tx_stop_queue(nq);
3662
3663 /* Finalize TX processing */
3664 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3665 mvpp2_txq_done(port, txq, txq_pcpu);
3666 }
3667
3668 static int
mvpp2_xdp_submit_frame(struct mvpp2_port * port,u16 txq_id,struct xdp_frame * xdpf,bool dma_map)3669 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3670 struct xdp_frame *xdpf, bool dma_map)
3671 {
3672 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3673 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3674 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3675 enum mvpp2_tx_buf_type buf_type;
3676 struct mvpp2_txq_pcpu *txq_pcpu;
3677 struct mvpp2_tx_queue *aggr_txq;
3678 struct mvpp2_tx_desc *tx_desc;
3679 struct mvpp2_tx_queue *txq;
3680 int ret = MVPP2_XDP_TX;
3681 dma_addr_t dma_addr;
3682
3683 txq = port->txqs[txq_id];
3684 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3685 aggr_txq = &port->priv->aggr_txqs[thread];
3686
3687 /* Check number of available descriptors */
3688 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3689 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3690 ret = MVPP2_XDP_DROPPED;
3691 goto out;
3692 }
3693
3694 /* Get a descriptor for the first part of the packet */
3695 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3696 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3697 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3698
3699 if (dma_map) {
3700 /* XDP_REDIRECT or AF_XDP */
3701 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3702 xdpf->len, DMA_TO_DEVICE);
3703
3704 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3705 mvpp2_txq_desc_put(txq);
3706 ret = MVPP2_XDP_DROPPED;
3707 goto out;
3708 }
3709
3710 buf_type = MVPP2_TYPE_XDP_NDO;
3711 } else {
3712 /* XDP_TX */
3713 struct page *page = virt_to_page(xdpf->data);
3714
3715 dma_addr = page_pool_get_dma_addr(page) +
3716 sizeof(*xdpf) + xdpf->headroom;
3717 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3718 xdpf->len, DMA_BIDIRECTIONAL);
3719
3720 buf_type = MVPP2_TYPE_XDP_TX;
3721 }
3722
3723 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3724
3725 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3726 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3727
3728 out:
3729 return ret;
3730 }
3731
3732 static int
mvpp2_xdp_xmit_back(struct mvpp2_port * port,struct xdp_buff * xdp)3733 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3734 {
3735 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3736 struct xdp_frame *xdpf;
3737 u16 txq_id;
3738 int ret;
3739
3740 xdpf = xdp_convert_buff_to_frame(xdp);
3741 if (unlikely(!xdpf))
3742 return MVPP2_XDP_DROPPED;
3743
3744 /* The first of the TX queues are used for XPS,
3745 * the second half for XDP_TX
3746 */
3747 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3748
3749 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3750 if (ret == MVPP2_XDP_TX) {
3751 u64_stats_update_begin(&stats->syncp);
3752 stats->tx_bytes += xdpf->len;
3753 stats->tx_packets++;
3754 stats->xdp_tx++;
3755 u64_stats_update_end(&stats->syncp);
3756
3757 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3758 } else {
3759 u64_stats_update_begin(&stats->syncp);
3760 stats->xdp_tx_err++;
3761 u64_stats_update_end(&stats->syncp);
3762 }
3763
3764 return ret;
3765 }
3766
3767 static int
mvpp2_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)3768 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3769 struct xdp_frame **frames, u32 flags)
3770 {
3771 struct mvpp2_port *port = netdev_priv(dev);
3772 int i, nxmit_byte = 0, nxmit = 0;
3773 struct mvpp2_pcpu_stats *stats;
3774 u16 txq_id;
3775 u32 ret;
3776
3777 if (unlikely(test_bit(0, &port->state)))
3778 return -ENETDOWN;
3779
3780 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3781 return -EINVAL;
3782
3783 /* The first of the TX queues are used for XPS,
3784 * the second half for XDP_TX
3785 */
3786 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3787
3788 for (i = 0; i < num_frame; i++) {
3789 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3790 if (ret != MVPP2_XDP_TX)
3791 break;
3792
3793 nxmit_byte += frames[i]->len;
3794 nxmit++;
3795 }
3796
3797 if (likely(nxmit > 0))
3798 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3799
3800 stats = this_cpu_ptr(port->stats);
3801 u64_stats_update_begin(&stats->syncp);
3802 stats->tx_bytes += nxmit_byte;
3803 stats->tx_packets += nxmit;
3804 stats->xdp_xmit += nxmit;
3805 stats->xdp_xmit_err += num_frame - nxmit;
3806 u64_stats_update_end(&stats->syncp);
3807
3808 return nxmit;
3809 }
3810
3811 static int
mvpp2_run_xdp(struct mvpp2_port * port,struct bpf_prog * prog,struct xdp_buff * xdp,struct page_pool * pp,struct mvpp2_pcpu_stats * stats)3812 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog,
3813 struct xdp_buff *xdp, struct page_pool *pp,
3814 struct mvpp2_pcpu_stats *stats)
3815 {
3816 unsigned int len, sync, err;
3817 struct page *page;
3818 u32 ret, act;
3819
3820 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3821 act = bpf_prog_run_xdp(prog, xdp);
3822
3823 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3824 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3825 sync = max(sync, len);
3826
3827 switch (act) {
3828 case XDP_PASS:
3829 stats->xdp_pass++;
3830 ret = MVPP2_XDP_PASS;
3831 break;
3832 case XDP_REDIRECT:
3833 err = xdp_do_redirect(port->dev, xdp, prog);
3834 if (unlikely(err)) {
3835 ret = MVPP2_XDP_DROPPED;
3836 page = virt_to_head_page(xdp->data);
3837 page_pool_put_page(pp, page, sync, true);
3838 } else {
3839 ret = MVPP2_XDP_REDIR;
3840 stats->xdp_redirect++;
3841 }
3842 break;
3843 case XDP_TX:
3844 ret = mvpp2_xdp_xmit_back(port, xdp);
3845 if (ret != MVPP2_XDP_TX) {
3846 page = virt_to_head_page(xdp->data);
3847 page_pool_put_page(pp, page, sync, true);
3848 }
3849 break;
3850 default:
3851 bpf_warn_invalid_xdp_action(port->dev, prog, act);
3852 fallthrough;
3853 case XDP_ABORTED:
3854 trace_xdp_exception(port->dev, prog, act);
3855 fallthrough;
3856 case XDP_DROP:
3857 page = virt_to_head_page(xdp->data);
3858 page_pool_put_page(pp, page, sync, true);
3859 ret = MVPP2_XDP_DROPPED;
3860 stats->xdp_drop++;
3861 break;
3862 }
3863
3864 return ret;
3865 }
3866
mvpp2_buff_hdr_pool_put(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc,int pool,u32 rx_status)3867 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc,
3868 int pool, u32 rx_status)
3869 {
3870 phys_addr_t phys_addr, phys_addr_next;
3871 dma_addr_t dma_addr, dma_addr_next;
3872 struct mvpp2_buff_hdr *buff_hdr;
3873
3874 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3875 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3876
3877 do {
3878 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr);
3879
3880 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr);
3881 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr);
3882
3883 if (port->priv->hw_version >= MVPP22) {
3884 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32);
3885 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32);
3886 }
3887
3888 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3889
3890 phys_addr = phys_addr_next;
3891 dma_addr = dma_addr_next;
3892
3893 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info)));
3894 }
3895
3896 /* Main rx processing */
mvpp2_rx(struct mvpp2_port * port,struct napi_struct * napi,int rx_todo,struct mvpp2_rx_queue * rxq)3897 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3898 int rx_todo, struct mvpp2_rx_queue *rxq)
3899 {
3900 struct net_device *dev = port->dev;
3901 struct mvpp2_pcpu_stats ps = {};
3902 enum dma_data_direction dma_dir;
3903 struct bpf_prog *xdp_prog;
3904 struct xdp_buff xdp;
3905 int rx_received;
3906 int rx_done = 0;
3907 u32 xdp_ret = 0;
3908
3909 xdp_prog = READ_ONCE(port->xdp_prog);
3910
3911 /* Get number of received packets and clamp the to-do */
3912 rx_received = mvpp2_rxq_received(port, rxq->id);
3913 if (rx_todo > rx_received)
3914 rx_todo = rx_received;
3915
3916 while (rx_done < rx_todo) {
3917 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3918 struct mvpp2_bm_pool *bm_pool;
3919 struct page_pool *pp = NULL;
3920 struct sk_buff *skb;
3921 unsigned int frag_size;
3922 dma_addr_t dma_addr;
3923 phys_addr_t phys_addr;
3924 u32 rx_status, timestamp;
3925 int pool, rx_bytes, err, ret;
3926 struct page *page;
3927 void *data;
3928
3929 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3930 data = (void *)phys_to_virt(phys_addr);
3931 page = virt_to_page(data);
3932 prefetch(page);
3933
3934 rx_done++;
3935 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3936 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3937 rx_bytes -= MVPP2_MH_SIZE;
3938 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3939
3940 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3941 MVPP2_RXD_BM_POOL_ID_OFFS;
3942 bm_pool = &port->priv->bm_pools[pool];
3943
3944 if (port->priv->percpu_pools) {
3945 pp = port->priv->page_pool[pool];
3946 dma_dir = page_pool_get_dma_dir(pp);
3947 } else {
3948 dma_dir = DMA_FROM_DEVICE;
3949 }
3950
3951 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3952 rx_bytes + MVPP2_MH_SIZE,
3953 dma_dir);
3954
3955 /* Buffer header not supported */
3956 if (rx_status & MVPP2_RXD_BUF_HDR)
3957 goto err_drop_frame;
3958
3959 /* In case of an error, release the requested buffer pointer
3960 * to the Buffer Manager. This request process is controlled
3961 * by the hardware, and the information about the buffer is
3962 * comprised by the RX descriptor.
3963 */
3964 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3965 goto err_drop_frame;
3966
3967 /* Prefetch header */
3968 prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3969
3970 if (bm_pool->frag_size > PAGE_SIZE)
3971 frag_size = 0;
3972 else
3973 frag_size = bm_pool->frag_size;
3974
3975 if (xdp_prog) {
3976 struct xdp_rxq_info *xdp_rxq;
3977
3978 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3979 xdp_rxq = &rxq->xdp_rxq_short;
3980 else
3981 xdp_rxq = &rxq->xdp_rxq_long;
3982
3983 xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq);
3984 xdp_prepare_buff(&xdp, data,
3985 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM,
3986 rx_bytes, false);
3987
3988 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps);
3989
3990 if (ret) {
3991 xdp_ret |= ret;
3992 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3993 if (err) {
3994 netdev_err(port->dev, "failed to refill BM pools\n");
3995 goto err_drop_frame;
3996 }
3997
3998 ps.rx_packets++;
3999 ps.rx_bytes += rx_bytes;
4000 continue;
4001 }
4002 }
4003
4004 skb = build_skb(data, frag_size);
4005 if (!skb) {
4006 netdev_warn(port->dev, "skb build failed\n");
4007 goto err_drop_frame;
4008 }
4009
4010 /* If we have RX hardware timestamping enabled, grab the
4011 * timestamp from the queue and convert.
4012 */
4013 if (mvpp22_rx_hwtstamping(port)) {
4014 timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
4015 mvpp22_tai_tstamp(port->priv->tai, timestamp,
4016 skb_hwtstamps(skb));
4017 }
4018
4019 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
4020 if (err) {
4021 netdev_err(port->dev, "failed to refill BM pools\n");
4022 dev_kfree_skb_any(skb);
4023 goto err_drop_frame;
4024 }
4025
4026 if (pp)
4027 skb_mark_for_recycle(skb);
4028 else
4029 dma_unmap_single_attrs(dev->dev.parent, dma_addr,
4030 bm_pool->buf_size, DMA_FROM_DEVICE,
4031 DMA_ATTR_SKIP_CPU_SYNC);
4032
4033 ps.rx_packets++;
4034 ps.rx_bytes += rx_bytes;
4035
4036 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
4037 skb_put(skb, rx_bytes);
4038 skb->ip_summed = mvpp2_rx_csum(port, rx_status);
4039 skb->protocol = eth_type_trans(skb, dev);
4040
4041 napi_gro_receive(napi, skb);
4042 continue;
4043
4044 err_drop_frame:
4045 dev->stats.rx_errors++;
4046 mvpp2_rx_error(port, rx_desc);
4047 /* Return the buffer to the pool */
4048 if (rx_status & MVPP2_RXD_BUF_HDR)
4049 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status);
4050 else
4051 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
4052 }
4053
4054 if (xdp_ret & MVPP2_XDP_REDIR)
4055 xdp_do_flush_map();
4056
4057 if (ps.rx_packets) {
4058 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
4059
4060 u64_stats_update_begin(&stats->syncp);
4061 stats->rx_packets += ps.rx_packets;
4062 stats->rx_bytes += ps.rx_bytes;
4063 /* xdp */
4064 stats->xdp_redirect += ps.xdp_redirect;
4065 stats->xdp_pass += ps.xdp_pass;
4066 stats->xdp_drop += ps.xdp_drop;
4067 u64_stats_update_end(&stats->syncp);
4068 }
4069
4070 /* Update Rx queue management counters */
4071 wmb();
4072 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
4073
4074 return rx_todo;
4075 }
4076
4077 static inline void
tx_desc_unmap_put(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_tx_desc * desc)4078 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4079 struct mvpp2_tx_desc *desc)
4080 {
4081 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4082 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4083
4084 dma_addr_t buf_dma_addr =
4085 mvpp2_txdesc_dma_addr_get(port, desc);
4086 size_t buf_sz =
4087 mvpp2_txdesc_size_get(port, desc);
4088 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
4089 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
4090 buf_sz, DMA_TO_DEVICE);
4091 mvpp2_txq_desc_put(txq);
4092 }
4093
mvpp2_txdesc_clear_ptp(struct mvpp2_port * port,struct mvpp2_tx_desc * desc)4094 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
4095 struct mvpp2_tx_desc *desc)
4096 {
4097 /* We only need to clear the low bits */
4098 if (port->priv->hw_version >= MVPP22)
4099 desc->pp22.ptp_descriptor &=
4100 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4101 }
4102
mvpp2_tx_hw_tstamp(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,struct sk_buff * skb)4103 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
4104 struct mvpp2_tx_desc *tx_desc,
4105 struct sk_buff *skb)
4106 {
4107 struct mvpp2_hwtstamp_queue *queue;
4108 unsigned int mtype, type, i;
4109 struct ptp_header *hdr;
4110 u64 ptpdesc;
4111
4112 if (port->priv->hw_version == MVPP21 ||
4113 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
4114 return false;
4115
4116 type = ptp_classify_raw(skb);
4117 if (!type)
4118 return false;
4119
4120 hdr = ptp_parse_header(skb, type);
4121 if (!hdr)
4122 return false;
4123
4124 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4125
4126 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
4127 MVPP22_PTP_ACTION_CAPTURE;
4128 queue = &port->tx_hwtstamp_queue[0];
4129
4130 switch (type & PTP_CLASS_VMASK) {
4131 case PTP_CLASS_V1:
4132 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
4133 break;
4134
4135 case PTP_CLASS_V2:
4136 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
4137 mtype = hdr->tsmt & 15;
4138 /* Direct PTP Sync messages to queue 1 */
4139 if (mtype == 0) {
4140 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
4141 queue = &port->tx_hwtstamp_queue[1];
4142 }
4143 break;
4144 }
4145
4146 /* Take a reference on the skb and insert into our queue */
4147 i = queue->next;
4148 queue->next = (i + 1) & 31;
4149 if (queue->skb[i])
4150 dev_kfree_skb_any(queue->skb[i]);
4151 queue->skb[i] = skb_get(skb);
4152
4153 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
4154
4155 /*
4156 * 3:0 - PTPAction
4157 * 6:4 - PTPPacketFormat
4158 * 7 - PTP_CF_WraparoundCheckEn
4159 * 9:8 - IngressTimestampSeconds[1:0]
4160 * 10 - Reserved
4161 * 11 - MACTimestampingEn
4162 * 17:12 - PTP_TimestampQueueEntryID[5:0]
4163 * 18 - PTPTimestampQueueSelect
4164 * 19 - UDPChecksumUpdateEn
4165 * 27:20 - TimestampOffset
4166 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
4167 * NTPTs, Y.1731 - L3 to timestamp entry
4168 * 35:28 - UDP Checksum Offset
4169 *
4170 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
4171 */
4172 tx_desc->pp22.ptp_descriptor &=
4173 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4174 tx_desc->pp22.ptp_descriptor |=
4175 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
4176 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4177 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4178
4179 return true;
4180 }
4181
4182 /* Handle tx fragmentation processing */
mvpp2_tx_frag_process(struct mvpp2_port * port,struct sk_buff * skb,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_tx_queue * txq)4183 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
4184 struct mvpp2_tx_queue *aggr_txq,
4185 struct mvpp2_tx_queue *txq)
4186 {
4187 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4188 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4189 struct mvpp2_tx_desc *tx_desc;
4190 int i;
4191 dma_addr_t buf_dma_addr;
4192
4193 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4194 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4195 void *addr = skb_frag_address(frag);
4196
4197 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4198 mvpp2_txdesc_clear_ptp(port, tx_desc);
4199 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4200 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4201
4202 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
4203 skb_frag_size(frag),
4204 DMA_TO_DEVICE);
4205 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
4206 mvpp2_txq_desc_put(txq);
4207 goto cleanup;
4208 }
4209
4210 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4211
4212 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
4213 /* Last descriptor */
4214 mvpp2_txdesc_cmd_set(port, tx_desc,
4215 MVPP2_TXD_L_DESC);
4216 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4217 } else {
4218 /* Descriptor in the middle: Not First, Not Last */
4219 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4220 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4221 }
4222 }
4223
4224 return 0;
4225 cleanup:
4226 /* Release all descriptors that were used to map fragments of
4227 * this packet, as well as the corresponding DMA mappings
4228 */
4229 for (i = i - 1; i >= 0; i--) {
4230 tx_desc = txq->descs + i;
4231 tx_desc_unmap_put(port, txq, tx_desc);
4232 }
4233
4234 return -ENOMEM;
4235 }
4236
mvpp2_tso_put_hdr(struct sk_buff * skb,struct net_device * dev,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu,int hdr_sz)4237 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
4238 struct net_device *dev,
4239 struct mvpp2_tx_queue *txq,
4240 struct mvpp2_tx_queue *aggr_txq,
4241 struct mvpp2_txq_pcpu *txq_pcpu,
4242 int hdr_sz)
4243 {
4244 struct mvpp2_port *port = netdev_priv(dev);
4245 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4246 dma_addr_t addr;
4247
4248 mvpp2_txdesc_clear_ptp(port, tx_desc);
4249 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4250 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4251
4252 addr = txq_pcpu->tso_headers_dma +
4253 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4254 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4255
4256 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4257 MVPP2_TXD_F_DESC |
4258 MVPP2_TXD_PADDING_DISABLE);
4259 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4260 }
4261
mvpp2_tso_put_data(struct sk_buff * skb,struct net_device * dev,struct tso_t * tso,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu,int sz,bool left,bool last)4262 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
4263 struct net_device *dev, struct tso_t *tso,
4264 struct mvpp2_tx_queue *txq,
4265 struct mvpp2_tx_queue *aggr_txq,
4266 struct mvpp2_txq_pcpu *txq_pcpu,
4267 int sz, bool left, bool last)
4268 {
4269 struct mvpp2_port *port = netdev_priv(dev);
4270 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4271 dma_addr_t buf_dma_addr;
4272
4273 mvpp2_txdesc_clear_ptp(port, tx_desc);
4274 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4275 mvpp2_txdesc_size_set(port, tx_desc, sz);
4276
4277 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
4278 DMA_TO_DEVICE);
4279 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4280 mvpp2_txq_desc_put(txq);
4281 return -ENOMEM;
4282 }
4283
4284 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4285
4286 if (!left) {
4287 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4288 if (last) {
4289 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4290 return 0;
4291 }
4292 } else {
4293 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4294 }
4295
4296 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4297 return 0;
4298 }
4299
mvpp2_tx_tso(struct sk_buff * skb,struct net_device * dev,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu)4300 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
4301 struct mvpp2_tx_queue *txq,
4302 struct mvpp2_tx_queue *aggr_txq,
4303 struct mvpp2_txq_pcpu *txq_pcpu)
4304 {
4305 struct mvpp2_port *port = netdev_priv(dev);
4306 int hdr_sz, i, len, descs = 0;
4307 struct tso_t tso;
4308
4309 /* Check number of available descriptors */
4310 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
4311 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
4312 tso_count_descs(skb)))
4313 return 0;
4314
4315 hdr_sz = tso_start(skb, &tso);
4316
4317 len = skb->len - hdr_sz;
4318 while (len > 0) {
4319 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
4320 char *hdr = txq_pcpu->tso_headers +
4321 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4322
4323 len -= left;
4324 descs++;
4325
4326 tso_build_hdr(skb, hdr, &tso, left, len == 0);
4327 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
4328
4329 while (left > 0) {
4330 int sz = min_t(int, tso.size, left);
4331 left -= sz;
4332 descs++;
4333
4334 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
4335 txq_pcpu, sz, left, len == 0))
4336 goto release;
4337 tso_build_data(skb, &tso, sz);
4338 }
4339 }
4340
4341 return descs;
4342
4343 release:
4344 for (i = descs - 1; i >= 0; i--) {
4345 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4346 tx_desc_unmap_put(port, txq, tx_desc);
4347 }
4348 return 0;
4349 }
4350
4351 /* Main tx processing */
mvpp2_tx(struct sk_buff * skb,struct net_device * dev)4352 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
4353 {
4354 struct mvpp2_port *port = netdev_priv(dev);
4355 struct mvpp2_tx_queue *txq, *aggr_txq;
4356 struct mvpp2_txq_pcpu *txq_pcpu;
4357 struct mvpp2_tx_desc *tx_desc;
4358 dma_addr_t buf_dma_addr;
4359 unsigned long flags = 0;
4360 unsigned int thread;
4361 int frags = 0;
4362 u16 txq_id;
4363 u32 tx_cmd;
4364
4365 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4366
4367 txq_id = skb_get_queue_mapping(skb);
4368 txq = port->txqs[txq_id];
4369 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4370 aggr_txq = &port->priv->aggr_txqs[thread];
4371
4372 if (test_bit(thread, &port->priv->lock_map))
4373 spin_lock_irqsave(&port->tx_lock[thread], flags);
4374
4375 if (skb_is_gso(skb)) {
4376 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
4377 goto out;
4378 }
4379 frags = skb_shinfo(skb)->nr_frags + 1;
4380
4381 /* Check number of available descriptors */
4382 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
4383 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
4384 frags = 0;
4385 goto out;
4386 }
4387
4388 /* Get a descriptor for the first part of the packet */
4389 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4390 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
4391 !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4392 mvpp2_txdesc_clear_ptp(port, tx_desc);
4393 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4394 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4395
4396 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
4397 skb_headlen(skb), DMA_TO_DEVICE);
4398 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4399 mvpp2_txq_desc_put(txq);
4400 frags = 0;
4401 goto out;
4402 }
4403
4404 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4405
4406 tx_cmd = mvpp2_skb_tx_csum(port, skb);
4407
4408 if (frags == 1) {
4409 /* First and Last descriptor */
4410 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4411 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4412 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4413 } else {
4414 /* First but not Last */
4415 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4416 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4417 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4418
4419 /* Continue with other skb fragments */
4420 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4421 tx_desc_unmap_put(port, txq, tx_desc);
4422 frags = 0;
4423 }
4424 }
4425
4426 out:
4427 if (frags > 0) {
4428 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4429 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4430
4431 txq_pcpu->reserved_num -= frags;
4432 txq_pcpu->count += frags;
4433 aggr_txq->count += frags;
4434
4435 /* Enable transmit */
4436 wmb();
4437 mvpp2_aggr_txq_pend_desc_add(port, frags);
4438
4439 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4440 netif_tx_stop_queue(nq);
4441
4442 u64_stats_update_begin(&stats->syncp);
4443 stats->tx_packets++;
4444 stats->tx_bytes += skb->len;
4445 u64_stats_update_end(&stats->syncp);
4446 } else {
4447 dev->stats.tx_dropped++;
4448 dev_kfree_skb_any(skb);
4449 }
4450
4451 /* Finalize TX processing */
4452 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4453 mvpp2_txq_done(port, txq, txq_pcpu);
4454
4455 /* Set the timer in case not all frags were processed */
4456 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4457 txq_pcpu->count > 0) {
4458 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4459
4460 if (!port_pcpu->timer_scheduled) {
4461 port_pcpu->timer_scheduled = true;
4462 hrtimer_start(&port_pcpu->tx_done_timer,
4463 MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4464 HRTIMER_MODE_REL_PINNED_SOFT);
4465 }
4466 }
4467
4468 if (test_bit(thread, &port->priv->lock_map))
4469 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4470
4471 return NETDEV_TX_OK;
4472 }
4473
mvpp2_cause_error(struct net_device * dev,int cause)4474 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4475 {
4476 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4477 netdev_err(dev, "FCS error\n");
4478 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4479 netdev_err(dev, "rx fifo overrun error\n");
4480 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4481 netdev_err(dev, "tx fifo underrun error\n");
4482 }
4483
mvpp2_poll(struct napi_struct * napi,int budget)4484 static int mvpp2_poll(struct napi_struct *napi, int budget)
4485 {
4486 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4487 int rx_done = 0;
4488 struct mvpp2_port *port = netdev_priv(napi->dev);
4489 struct mvpp2_queue_vector *qv;
4490 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4491
4492 qv = container_of(napi, struct mvpp2_queue_vector, napi);
4493
4494 /* Rx/Tx cause register
4495 *
4496 * Bits 0-15: each bit indicates received packets on the Rx queue
4497 * (bit 0 is for Rx queue 0).
4498 *
4499 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4500 * (bit 16 is for Tx queue 0).
4501 *
4502 * Each CPU has its own Rx/Tx cause register
4503 */
4504 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4505 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4506
4507 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4508 if (cause_misc) {
4509 mvpp2_cause_error(port->dev, cause_misc);
4510
4511 /* Clear the cause register */
4512 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4513 mvpp2_thread_write(port->priv, thread,
4514 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4515 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4516 }
4517
4518 if (port->has_tx_irqs) {
4519 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4520 if (cause_tx) {
4521 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4522 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4523 }
4524 }
4525
4526 /* Process RX packets */
4527 cause_rx = cause_rx_tx &
4528 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4529 cause_rx <<= qv->first_rxq;
4530 cause_rx |= qv->pending_cause_rx;
4531 while (cause_rx && budget > 0) {
4532 int count;
4533 struct mvpp2_rx_queue *rxq;
4534
4535 rxq = mvpp2_get_rx_queue(port, cause_rx);
4536 if (!rxq)
4537 break;
4538
4539 count = mvpp2_rx(port, napi, budget, rxq);
4540 rx_done += count;
4541 budget -= count;
4542 if (budget > 0) {
4543 /* Clear the bit associated to this Rx queue
4544 * so that next iteration will continue from
4545 * the next Rx queue.
4546 */
4547 cause_rx &= ~(1 << rxq->logic_rxq);
4548 }
4549 }
4550
4551 if (budget > 0) {
4552 cause_rx = 0;
4553 napi_complete_done(napi, rx_done);
4554
4555 mvpp2_qvec_interrupt_enable(qv);
4556 }
4557 qv->pending_cause_rx = cause_rx;
4558 return rx_done;
4559 }
4560
mvpp22_mode_reconfigure(struct mvpp2_port * port,phy_interface_t interface)4561 static void mvpp22_mode_reconfigure(struct mvpp2_port *port,
4562 phy_interface_t interface)
4563 {
4564 u32 ctrl3;
4565
4566 /* Set the GMAC & XLG MAC in reset */
4567 mvpp2_mac_reset_assert(port);
4568
4569 /* Set the MPCS and XPCS in reset */
4570 mvpp22_pcs_reset_assert(port);
4571
4572 /* comphy reconfiguration */
4573 mvpp22_comphy_init(port, interface);
4574
4575 /* gop reconfiguration */
4576 mvpp22_gop_init(port, interface);
4577
4578 mvpp22_pcs_reset_deassert(port, interface);
4579
4580 if (mvpp2_port_supports_xlg(port)) {
4581 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4582 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4583
4584 if (mvpp2_is_xlg(interface))
4585 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4586 else
4587 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4588
4589 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4590 }
4591
4592 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface))
4593 mvpp2_xlg_max_rx_size_set(port);
4594 else
4595 mvpp2_gmac_max_rx_size_set(port);
4596 }
4597
4598 /* Set hw internals when starting port */
mvpp2_start_dev(struct mvpp2_port * port)4599 static void mvpp2_start_dev(struct mvpp2_port *port)
4600 {
4601 int i;
4602
4603 mvpp2_txp_max_tx_size_set(port);
4604
4605 for (i = 0; i < port->nqvecs; i++)
4606 napi_enable(&port->qvecs[i].napi);
4607
4608 /* Enable interrupts on all threads */
4609 mvpp2_interrupts_enable(port);
4610
4611 if (port->priv->hw_version >= MVPP22)
4612 mvpp22_mode_reconfigure(port, port->phy_interface);
4613
4614 if (port->phylink) {
4615 phylink_start(port->phylink);
4616 } else {
4617 mvpp2_acpi_start(port);
4618 }
4619
4620 netif_tx_start_all_queues(port->dev);
4621
4622 clear_bit(0, &port->state);
4623 }
4624
4625 /* Set hw internals when stopping port */
mvpp2_stop_dev(struct mvpp2_port * port)4626 static void mvpp2_stop_dev(struct mvpp2_port *port)
4627 {
4628 int i;
4629
4630 set_bit(0, &port->state);
4631
4632 /* Disable interrupts on all threads */
4633 mvpp2_interrupts_disable(port);
4634
4635 for (i = 0; i < port->nqvecs; i++)
4636 napi_disable(&port->qvecs[i].napi);
4637
4638 if (port->phylink)
4639 phylink_stop(port->phylink);
4640 phy_power_off(port->comphy);
4641 }
4642
mvpp2_check_ringparam_valid(struct net_device * dev,struct ethtool_ringparam * ring)4643 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4644 struct ethtool_ringparam *ring)
4645 {
4646 u16 new_rx_pending = ring->rx_pending;
4647 u16 new_tx_pending = ring->tx_pending;
4648
4649 if (ring->rx_pending == 0 || ring->tx_pending == 0)
4650 return -EINVAL;
4651
4652 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4653 new_rx_pending = MVPP2_MAX_RXD_MAX;
4654 else if (ring->rx_pending < MSS_THRESHOLD_START)
4655 new_rx_pending = MSS_THRESHOLD_START;
4656 else if (!IS_ALIGNED(ring->rx_pending, 16))
4657 new_rx_pending = ALIGN(ring->rx_pending, 16);
4658
4659 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4660 new_tx_pending = MVPP2_MAX_TXD_MAX;
4661 else if (!IS_ALIGNED(ring->tx_pending, 32))
4662 new_tx_pending = ALIGN(ring->tx_pending, 32);
4663
4664 /* The Tx ring size cannot be smaller than the minimum number of
4665 * descriptors needed for TSO.
4666 */
4667 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4668 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4669
4670 if (ring->rx_pending != new_rx_pending) {
4671 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4672 ring->rx_pending, new_rx_pending);
4673 ring->rx_pending = new_rx_pending;
4674 }
4675
4676 if (ring->tx_pending != new_tx_pending) {
4677 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4678 ring->tx_pending, new_tx_pending);
4679 ring->tx_pending = new_tx_pending;
4680 }
4681
4682 return 0;
4683 }
4684
mvpp21_get_mac_address(struct mvpp2_port * port,unsigned char * addr)4685 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4686 {
4687 u32 mac_addr_l, mac_addr_m, mac_addr_h;
4688
4689 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4690 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4691 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4692 addr[0] = (mac_addr_h >> 24) & 0xFF;
4693 addr[1] = (mac_addr_h >> 16) & 0xFF;
4694 addr[2] = (mac_addr_h >> 8) & 0xFF;
4695 addr[3] = mac_addr_h & 0xFF;
4696 addr[4] = mac_addr_m & 0xFF;
4697 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4698 }
4699
mvpp2_irqs_init(struct mvpp2_port * port)4700 static int mvpp2_irqs_init(struct mvpp2_port *port)
4701 {
4702 int err, i;
4703
4704 for (i = 0; i < port->nqvecs; i++) {
4705 struct mvpp2_queue_vector *qv = port->qvecs + i;
4706
4707 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4708 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4709 if (!qv->mask) {
4710 err = -ENOMEM;
4711 goto err;
4712 }
4713
4714 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4715 }
4716
4717 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4718 if (err)
4719 goto err;
4720
4721 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4722 unsigned int cpu;
4723
4724 for_each_present_cpu(cpu) {
4725 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4726 qv->sw_thread_id)
4727 cpumask_set_cpu(cpu, qv->mask);
4728 }
4729
4730 irq_set_affinity_hint(qv->irq, qv->mask);
4731 }
4732 }
4733
4734 return 0;
4735 err:
4736 for (i = 0; i < port->nqvecs; i++) {
4737 struct mvpp2_queue_vector *qv = port->qvecs + i;
4738
4739 irq_set_affinity_hint(qv->irq, NULL);
4740 kfree(qv->mask);
4741 qv->mask = NULL;
4742 free_irq(qv->irq, qv);
4743 }
4744
4745 return err;
4746 }
4747
mvpp2_irqs_deinit(struct mvpp2_port * port)4748 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4749 {
4750 int i;
4751
4752 for (i = 0; i < port->nqvecs; i++) {
4753 struct mvpp2_queue_vector *qv = port->qvecs + i;
4754
4755 irq_set_affinity_hint(qv->irq, NULL);
4756 kfree(qv->mask);
4757 qv->mask = NULL;
4758 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4759 free_irq(qv->irq, qv);
4760 }
4761 }
4762
mvpp22_rss_is_supported(struct mvpp2_port * port)4763 static bool mvpp22_rss_is_supported(struct mvpp2_port *port)
4764 {
4765 return (queue_mode == MVPP2_QDIST_MULTI_MODE) &&
4766 !(port->flags & MVPP2_F_LOOPBACK);
4767 }
4768
mvpp2_open(struct net_device * dev)4769 static int mvpp2_open(struct net_device *dev)
4770 {
4771 struct mvpp2_port *port = netdev_priv(dev);
4772 struct mvpp2 *priv = port->priv;
4773 unsigned char mac_bcast[ETH_ALEN] = {
4774 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4775 bool valid = false;
4776 int err;
4777
4778 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4779 if (err) {
4780 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4781 return err;
4782 }
4783 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4784 if (err) {
4785 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4786 return err;
4787 }
4788 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4789 if (err) {
4790 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4791 return err;
4792 }
4793 err = mvpp2_prs_def_flow(port);
4794 if (err) {
4795 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4796 return err;
4797 }
4798
4799 /* Allocate the Rx/Tx queues */
4800 err = mvpp2_setup_rxqs(port);
4801 if (err) {
4802 netdev_err(port->dev, "cannot allocate Rx queues\n");
4803 return err;
4804 }
4805
4806 err = mvpp2_setup_txqs(port);
4807 if (err) {
4808 netdev_err(port->dev, "cannot allocate Tx queues\n");
4809 goto err_cleanup_rxqs;
4810 }
4811
4812 err = mvpp2_irqs_init(port);
4813 if (err) {
4814 netdev_err(port->dev, "cannot init IRQs\n");
4815 goto err_cleanup_txqs;
4816 }
4817
4818 if (port->phylink) {
4819 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0);
4820 if (err) {
4821 netdev_err(port->dev, "could not attach PHY (%d)\n",
4822 err);
4823 goto err_free_irq;
4824 }
4825
4826 valid = true;
4827 }
4828
4829 if (priv->hw_version >= MVPP22 && port->port_irq) {
4830 err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4831 dev->name, port);
4832 if (err) {
4833 netdev_err(port->dev,
4834 "cannot request port link/ptp IRQ %d\n",
4835 port->port_irq);
4836 goto err_free_irq;
4837 }
4838
4839 mvpp22_gop_setup_irq(port);
4840
4841 /* In default link is down */
4842 netif_carrier_off(port->dev);
4843
4844 valid = true;
4845 } else {
4846 port->port_irq = 0;
4847 }
4848
4849 if (!valid) {
4850 netdev_err(port->dev,
4851 "invalid configuration: no dt or link IRQ");
4852 err = -ENOENT;
4853 goto err_free_irq;
4854 }
4855
4856 /* Unmask interrupts on all CPUs */
4857 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4858 mvpp2_shared_interrupt_mask_unmask(port, false);
4859
4860 mvpp2_start_dev(port);
4861
4862 /* Start hardware statistics gathering */
4863 queue_delayed_work(priv->stats_queue, &port->stats_work,
4864 MVPP2_MIB_COUNTERS_STATS_DELAY);
4865
4866 return 0;
4867
4868 err_free_irq:
4869 mvpp2_irqs_deinit(port);
4870 err_cleanup_txqs:
4871 mvpp2_cleanup_txqs(port);
4872 err_cleanup_rxqs:
4873 mvpp2_cleanup_rxqs(port);
4874 return err;
4875 }
4876
mvpp2_stop(struct net_device * dev)4877 static int mvpp2_stop(struct net_device *dev)
4878 {
4879 struct mvpp2_port *port = netdev_priv(dev);
4880 struct mvpp2_port_pcpu *port_pcpu;
4881 unsigned int thread;
4882
4883 mvpp2_stop_dev(port);
4884
4885 /* Mask interrupts on all threads */
4886 on_each_cpu(mvpp2_interrupts_mask, port, 1);
4887 mvpp2_shared_interrupt_mask_unmask(port, true);
4888
4889 if (port->phylink)
4890 phylink_disconnect_phy(port->phylink);
4891 if (port->port_irq)
4892 free_irq(port->port_irq, port);
4893
4894 mvpp2_irqs_deinit(port);
4895 if (!port->has_tx_irqs) {
4896 for (thread = 0; thread < port->priv->nthreads; thread++) {
4897 port_pcpu = per_cpu_ptr(port->pcpu, thread);
4898
4899 hrtimer_cancel(&port_pcpu->tx_done_timer);
4900 port_pcpu->timer_scheduled = false;
4901 }
4902 }
4903 mvpp2_cleanup_rxqs(port);
4904 mvpp2_cleanup_txqs(port);
4905
4906 cancel_delayed_work_sync(&port->stats_work);
4907
4908 mvpp2_mac_reset_assert(port);
4909 mvpp22_pcs_reset_assert(port);
4910
4911 return 0;
4912 }
4913
mvpp2_prs_mac_da_accept_list(struct mvpp2_port * port,struct netdev_hw_addr_list * list)4914 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4915 struct netdev_hw_addr_list *list)
4916 {
4917 struct netdev_hw_addr *ha;
4918 int ret;
4919
4920 netdev_hw_addr_list_for_each(ha, list) {
4921 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4922 if (ret)
4923 return ret;
4924 }
4925
4926 return 0;
4927 }
4928
mvpp2_set_rx_promisc(struct mvpp2_port * port,bool enable)4929 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4930 {
4931 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4932 mvpp2_prs_vid_enable_filtering(port);
4933 else
4934 mvpp2_prs_vid_disable_filtering(port);
4935
4936 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4937 MVPP2_PRS_L2_UNI_CAST, enable);
4938
4939 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4940 MVPP2_PRS_L2_MULTI_CAST, enable);
4941 }
4942
mvpp2_set_rx_mode(struct net_device * dev)4943 static void mvpp2_set_rx_mode(struct net_device *dev)
4944 {
4945 struct mvpp2_port *port = netdev_priv(dev);
4946
4947 /* Clear the whole UC and MC list */
4948 mvpp2_prs_mac_del_all(port);
4949
4950 if (dev->flags & IFF_PROMISC) {
4951 mvpp2_set_rx_promisc(port, true);
4952 return;
4953 }
4954
4955 mvpp2_set_rx_promisc(port, false);
4956
4957 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4958 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4959 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4960 MVPP2_PRS_L2_UNI_CAST, true);
4961
4962 if (dev->flags & IFF_ALLMULTI) {
4963 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4964 MVPP2_PRS_L2_MULTI_CAST, true);
4965 return;
4966 }
4967
4968 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4969 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4970 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4971 MVPP2_PRS_L2_MULTI_CAST, true);
4972 }
4973
mvpp2_set_mac_address(struct net_device * dev,void * p)4974 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4975 {
4976 const struct sockaddr *addr = p;
4977 int err;
4978
4979 if (!is_valid_ether_addr(addr->sa_data))
4980 return -EADDRNOTAVAIL;
4981
4982 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4983 if (err) {
4984 /* Reconfigure parser accept the original MAC address */
4985 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4986 netdev_err(dev, "failed to change MAC address\n");
4987 }
4988 return err;
4989 }
4990
4991 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4992 * then bring up again all ports.
4993 */
mvpp2_bm_switch_buffers(struct mvpp2 * priv,bool percpu)4994 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4995 {
4996 bool change_percpu = (percpu != priv->percpu_pools);
4997 int numbufs = MVPP2_BM_POOLS_NUM, i;
4998 struct mvpp2_port *port = NULL;
4999 bool status[MVPP2_MAX_PORTS];
5000
5001 for (i = 0; i < priv->port_count; i++) {
5002 port = priv->port_list[i];
5003 status[i] = netif_running(port->dev);
5004 if (status[i])
5005 mvpp2_stop(port->dev);
5006 }
5007
5008 /* nrxqs is the same for all ports */
5009 if (priv->percpu_pools)
5010 numbufs = port->nrxqs * 2;
5011
5012 if (change_percpu)
5013 mvpp2_bm_pool_update_priv_fc(priv, false);
5014
5015 for (i = 0; i < numbufs; i++)
5016 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
5017
5018 devm_kfree(port->dev->dev.parent, priv->bm_pools);
5019 priv->percpu_pools = percpu;
5020 mvpp2_bm_init(port->dev->dev.parent, priv);
5021
5022 for (i = 0; i < priv->port_count; i++) {
5023 port = priv->port_list[i];
5024 mvpp2_swf_bm_pool_init(port);
5025 if (status[i])
5026 mvpp2_open(port->dev);
5027 }
5028
5029 if (change_percpu)
5030 mvpp2_bm_pool_update_priv_fc(priv, true);
5031
5032 return 0;
5033 }
5034
mvpp2_change_mtu(struct net_device * dev,int mtu)5035 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5036 {
5037 struct mvpp2_port *port = netdev_priv(dev);
5038 bool running = netif_running(dev);
5039 struct mvpp2 *priv = port->priv;
5040 int err;
5041
5042 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5043 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5044 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5045 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5046 }
5047
5048 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) {
5049 netdev_err(dev, "Illegal MTU value %d (> %d) for XDP mode\n",
5050 mtu, (int)MVPP2_MAX_RX_BUF_SIZE);
5051 return -EINVAL;
5052 }
5053
5054 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
5055 if (priv->percpu_pools) {
5056 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
5057 mvpp2_bm_switch_buffers(priv, false);
5058 }
5059 } else {
5060 bool jumbo = false;
5061 int i;
5062
5063 for (i = 0; i < priv->port_count; i++)
5064 if (priv->port_list[i] != port &&
5065 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
5066 MVPP2_BM_LONG_PKT_SIZE) {
5067 jumbo = true;
5068 break;
5069 }
5070
5071 /* No port is using jumbo frames */
5072 if (!jumbo) {
5073 dev_info(port->dev->dev.parent,
5074 "all ports have a low MTU, switching to per-cpu buffers");
5075 mvpp2_bm_switch_buffers(priv, true);
5076 }
5077 }
5078
5079 if (running)
5080 mvpp2_stop_dev(port);
5081
5082 err = mvpp2_bm_update_mtu(dev, mtu);
5083 if (err) {
5084 netdev_err(dev, "failed to change MTU\n");
5085 /* Reconfigure BM to the original MTU */
5086 mvpp2_bm_update_mtu(dev, dev->mtu);
5087 } else {
5088 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5089 }
5090
5091 if (running) {
5092 mvpp2_start_dev(port);
5093 mvpp2_egress_enable(port);
5094 mvpp2_ingress_enable(port);
5095 }
5096
5097 return err;
5098 }
5099
mvpp2_check_pagepool_dma(struct mvpp2_port * port)5100 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
5101 {
5102 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
5103 struct mvpp2 *priv = port->priv;
5104 int err = -1, i;
5105
5106 if (!priv->percpu_pools)
5107 return err;
5108
5109 if (!priv->page_pool[0])
5110 return -ENOMEM;
5111
5112 for (i = 0; i < priv->port_count; i++) {
5113 port = priv->port_list[i];
5114 if (port->xdp_prog) {
5115 dma_dir = DMA_BIDIRECTIONAL;
5116 break;
5117 }
5118 }
5119
5120 /* All pools are equal in terms of DMA direction */
5121 if (priv->page_pool[0]->p.dma_dir != dma_dir)
5122 err = mvpp2_bm_switch_buffers(priv, true);
5123
5124 return err;
5125 }
5126
5127 static void
mvpp2_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)5128 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5129 {
5130 struct mvpp2_port *port = netdev_priv(dev);
5131 unsigned int start;
5132 unsigned int cpu;
5133
5134 for_each_possible_cpu(cpu) {
5135 struct mvpp2_pcpu_stats *cpu_stats;
5136 u64 rx_packets;
5137 u64 rx_bytes;
5138 u64 tx_packets;
5139 u64 tx_bytes;
5140
5141 cpu_stats = per_cpu_ptr(port->stats, cpu);
5142 do {
5143 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5144 rx_packets = cpu_stats->rx_packets;
5145 rx_bytes = cpu_stats->rx_bytes;
5146 tx_packets = cpu_stats->tx_packets;
5147 tx_bytes = cpu_stats->tx_bytes;
5148 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5149
5150 stats->rx_packets += rx_packets;
5151 stats->rx_bytes += rx_bytes;
5152 stats->tx_packets += tx_packets;
5153 stats->tx_bytes += tx_bytes;
5154 }
5155
5156 stats->rx_errors = dev->stats.rx_errors;
5157 stats->rx_dropped = dev->stats.rx_dropped;
5158 stats->tx_dropped = dev->stats.tx_dropped;
5159 }
5160
mvpp2_set_ts_config(struct mvpp2_port * port,struct ifreq * ifr)5161 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5162 {
5163 struct hwtstamp_config config;
5164 void __iomem *ptp;
5165 u32 gcr, int_mask;
5166
5167 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5168 return -EFAULT;
5169
5170 if (config.tx_type != HWTSTAMP_TX_OFF &&
5171 config.tx_type != HWTSTAMP_TX_ON)
5172 return -ERANGE;
5173
5174 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
5175
5176 int_mask = gcr = 0;
5177 if (config.tx_type != HWTSTAMP_TX_OFF) {
5178 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
5179 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
5180 MVPP22_PTP_INT_MASK_QUEUE0;
5181 }
5182
5183 /* It seems we must also release the TX reset when enabling the TSU */
5184 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
5185 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
5186 MVPP22_PTP_GCR_TX_RESET;
5187
5188 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
5189 mvpp22_tai_start(port->priv->tai);
5190
5191 if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
5192 config.rx_filter = HWTSTAMP_FILTER_ALL;
5193 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5194 MVPP22_PTP_GCR_RX_RESET |
5195 MVPP22_PTP_GCR_TX_RESET |
5196 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5197 port->rx_hwtstamp = true;
5198 } else {
5199 port->rx_hwtstamp = false;
5200 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5201 MVPP22_PTP_GCR_RX_RESET |
5202 MVPP22_PTP_GCR_TX_RESET |
5203 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5204 }
5205
5206 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
5207 MVPP22_PTP_INT_MASK_QUEUE1 |
5208 MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
5209
5210 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
5211 mvpp22_tai_stop(port->priv->tai);
5212
5213 port->tx_hwtstamp_type = config.tx_type;
5214
5215 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5216 return -EFAULT;
5217
5218 return 0;
5219 }
5220
mvpp2_get_ts_config(struct mvpp2_port * port,struct ifreq * ifr)5221 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5222 {
5223 struct hwtstamp_config config;
5224
5225 memset(&config, 0, sizeof(config));
5226
5227 config.tx_type = port->tx_hwtstamp_type;
5228 config.rx_filter = port->rx_hwtstamp ?
5229 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
5230
5231 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5232 return -EFAULT;
5233
5234 return 0;
5235 }
5236
mvpp2_ethtool_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)5237 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
5238 struct ethtool_ts_info *info)
5239 {
5240 struct mvpp2_port *port = netdev_priv(dev);
5241
5242 if (!port->hwtstamp)
5243 return -EOPNOTSUPP;
5244
5245 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
5246 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5247 SOF_TIMESTAMPING_RX_SOFTWARE |
5248 SOF_TIMESTAMPING_SOFTWARE |
5249 SOF_TIMESTAMPING_TX_HARDWARE |
5250 SOF_TIMESTAMPING_RX_HARDWARE |
5251 SOF_TIMESTAMPING_RAW_HARDWARE;
5252 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
5253 BIT(HWTSTAMP_TX_ON);
5254 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
5255 BIT(HWTSTAMP_FILTER_ALL);
5256
5257 return 0;
5258 }
5259
mvpp2_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)5260 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5261 {
5262 struct mvpp2_port *port = netdev_priv(dev);
5263
5264 switch (cmd) {
5265 case SIOCSHWTSTAMP:
5266 if (port->hwtstamp)
5267 return mvpp2_set_ts_config(port, ifr);
5268 break;
5269
5270 case SIOCGHWTSTAMP:
5271 if (port->hwtstamp)
5272 return mvpp2_get_ts_config(port, ifr);
5273 break;
5274 }
5275
5276 if (!port->phylink)
5277 return -ENOTSUPP;
5278
5279 return phylink_mii_ioctl(port->phylink, ifr, cmd);
5280 }
5281
mvpp2_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)5282 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
5283 {
5284 struct mvpp2_port *port = netdev_priv(dev);
5285 int ret;
5286
5287 ret = mvpp2_prs_vid_entry_add(port, vid);
5288 if (ret)
5289 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
5290 MVPP2_PRS_VLAN_FILT_MAX - 1);
5291 return ret;
5292 }
5293
mvpp2_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)5294 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
5295 {
5296 struct mvpp2_port *port = netdev_priv(dev);
5297
5298 mvpp2_prs_vid_entry_remove(port, vid);
5299 return 0;
5300 }
5301
mvpp2_set_features(struct net_device * dev,netdev_features_t features)5302 static int mvpp2_set_features(struct net_device *dev,
5303 netdev_features_t features)
5304 {
5305 netdev_features_t changed = dev->features ^ features;
5306 struct mvpp2_port *port = netdev_priv(dev);
5307
5308 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
5309 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
5310 mvpp2_prs_vid_enable_filtering(port);
5311 } else {
5312 /* Invalidate all registered VID filters for this
5313 * port
5314 */
5315 mvpp2_prs_vid_remove_all(port);
5316
5317 mvpp2_prs_vid_disable_filtering(port);
5318 }
5319 }
5320
5321 if (changed & NETIF_F_RXHASH) {
5322 if (features & NETIF_F_RXHASH)
5323 mvpp22_port_rss_enable(port);
5324 else
5325 mvpp22_port_rss_disable(port);
5326 }
5327
5328 return 0;
5329 }
5330
mvpp2_xdp_setup(struct mvpp2_port * port,struct netdev_bpf * bpf)5331 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
5332 {
5333 struct bpf_prog *prog = bpf->prog, *old_prog;
5334 bool running = netif_running(port->dev);
5335 bool reset = !prog != !port->xdp_prog;
5336
5337 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) {
5338 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP");
5339 return -EOPNOTSUPP;
5340 }
5341
5342 if (!port->priv->percpu_pools) {
5343 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
5344 return -EOPNOTSUPP;
5345 }
5346
5347 if (port->ntxqs < num_possible_cpus() * 2) {
5348 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
5349 return -EOPNOTSUPP;
5350 }
5351
5352 /* device is up and bpf is added/removed, must setup the RX queues */
5353 if (running && reset)
5354 mvpp2_stop(port->dev);
5355
5356 old_prog = xchg(&port->xdp_prog, prog);
5357 if (old_prog)
5358 bpf_prog_put(old_prog);
5359
5360 /* bpf is just replaced, RXQ and MTU are already setup */
5361 if (!reset)
5362 return 0;
5363
5364 /* device was up, restore the link */
5365 if (running)
5366 mvpp2_open(port->dev);
5367
5368 /* Check Page Pool DMA Direction */
5369 mvpp2_check_pagepool_dma(port);
5370
5371 return 0;
5372 }
5373
mvpp2_xdp(struct net_device * dev,struct netdev_bpf * xdp)5374 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5375 {
5376 struct mvpp2_port *port = netdev_priv(dev);
5377
5378 switch (xdp->command) {
5379 case XDP_SETUP_PROG:
5380 return mvpp2_xdp_setup(port, xdp);
5381 default:
5382 return -EINVAL;
5383 }
5384 }
5385
5386 /* Ethtool methods */
5387
mvpp2_ethtool_nway_reset(struct net_device * dev)5388 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
5389 {
5390 struct mvpp2_port *port = netdev_priv(dev);
5391
5392 if (!port->phylink)
5393 return -ENOTSUPP;
5394
5395 return phylink_ethtool_nway_reset(port->phylink);
5396 }
5397
5398 /* Set interrupt coalescing for ethtools */
5399 static int
mvpp2_ethtool_set_coalesce(struct net_device * dev,struct ethtool_coalesce * c,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)5400 mvpp2_ethtool_set_coalesce(struct net_device *dev,
5401 struct ethtool_coalesce *c,
5402 struct kernel_ethtool_coalesce *kernel_coal,
5403 struct netlink_ext_ack *extack)
5404 {
5405 struct mvpp2_port *port = netdev_priv(dev);
5406 int queue;
5407
5408 for (queue = 0; queue < port->nrxqs; queue++) {
5409 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5410
5411 rxq->time_coal = c->rx_coalesce_usecs;
5412 rxq->pkts_coal = c->rx_max_coalesced_frames;
5413 mvpp2_rx_pkts_coal_set(port, rxq);
5414 mvpp2_rx_time_coal_set(port, rxq);
5415 }
5416
5417 if (port->has_tx_irqs) {
5418 port->tx_time_coal = c->tx_coalesce_usecs;
5419 mvpp2_tx_time_coal_set(port);
5420 }
5421
5422 for (queue = 0; queue < port->ntxqs; queue++) {
5423 struct mvpp2_tx_queue *txq = port->txqs[queue];
5424
5425 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5426
5427 if (port->has_tx_irqs)
5428 mvpp2_tx_pkts_coal_set(port, txq);
5429 }
5430
5431 return 0;
5432 }
5433
5434 /* get coalescing for ethtools */
5435 static int
mvpp2_ethtool_get_coalesce(struct net_device * dev,struct ethtool_coalesce * c,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)5436 mvpp2_ethtool_get_coalesce(struct net_device *dev,
5437 struct ethtool_coalesce *c,
5438 struct kernel_ethtool_coalesce *kernel_coal,
5439 struct netlink_ext_ack *extack)
5440 {
5441 struct mvpp2_port *port = netdev_priv(dev);
5442
5443 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
5444 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5445 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5446 c->tx_coalesce_usecs = port->tx_time_coal;
5447 return 0;
5448 }
5449
mvpp2_ethtool_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)5450 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5451 struct ethtool_drvinfo *drvinfo)
5452 {
5453 strscpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5454 sizeof(drvinfo->driver));
5455 strscpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5456 sizeof(drvinfo->version));
5457 strscpy(drvinfo->bus_info, dev_name(&dev->dev),
5458 sizeof(drvinfo->bus_info));
5459 }
5460
5461 static void
mvpp2_ethtool_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)5462 mvpp2_ethtool_get_ringparam(struct net_device *dev,
5463 struct ethtool_ringparam *ring,
5464 struct kernel_ethtool_ringparam *kernel_ring,
5465 struct netlink_ext_ack *extack)
5466 {
5467 struct mvpp2_port *port = netdev_priv(dev);
5468
5469 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5470 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5471 ring->rx_pending = port->rx_ring_size;
5472 ring->tx_pending = port->tx_ring_size;
5473 }
5474
5475 static int
mvpp2_ethtool_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)5476 mvpp2_ethtool_set_ringparam(struct net_device *dev,
5477 struct ethtool_ringparam *ring,
5478 struct kernel_ethtool_ringparam *kernel_ring,
5479 struct netlink_ext_ack *extack)
5480 {
5481 struct mvpp2_port *port = netdev_priv(dev);
5482 u16 prev_rx_ring_size = port->rx_ring_size;
5483 u16 prev_tx_ring_size = port->tx_ring_size;
5484 int err;
5485
5486 err = mvpp2_check_ringparam_valid(dev, ring);
5487 if (err)
5488 return err;
5489
5490 if (!netif_running(dev)) {
5491 port->rx_ring_size = ring->rx_pending;
5492 port->tx_ring_size = ring->tx_pending;
5493 return 0;
5494 }
5495
5496 /* The interface is running, so we have to force a
5497 * reallocation of the queues
5498 */
5499 mvpp2_stop_dev(port);
5500 mvpp2_cleanup_rxqs(port);
5501 mvpp2_cleanup_txqs(port);
5502
5503 port->rx_ring_size = ring->rx_pending;
5504 port->tx_ring_size = ring->tx_pending;
5505
5506 err = mvpp2_setup_rxqs(port);
5507 if (err) {
5508 /* Reallocate Rx queues with the original ring size */
5509 port->rx_ring_size = prev_rx_ring_size;
5510 ring->rx_pending = prev_rx_ring_size;
5511 err = mvpp2_setup_rxqs(port);
5512 if (err)
5513 goto err_out;
5514 }
5515 err = mvpp2_setup_txqs(port);
5516 if (err) {
5517 /* Reallocate Tx queues with the original ring size */
5518 port->tx_ring_size = prev_tx_ring_size;
5519 ring->tx_pending = prev_tx_ring_size;
5520 err = mvpp2_setup_txqs(port);
5521 if (err)
5522 goto err_clean_rxqs;
5523 }
5524
5525 mvpp2_start_dev(port);
5526 mvpp2_egress_enable(port);
5527 mvpp2_ingress_enable(port);
5528
5529 return 0;
5530
5531 err_clean_rxqs:
5532 mvpp2_cleanup_rxqs(port);
5533 err_out:
5534 netdev_err(dev, "failed to change ring parameters");
5535 return err;
5536 }
5537
mvpp2_ethtool_get_pause_param(struct net_device * dev,struct ethtool_pauseparam * pause)5538 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5539 struct ethtool_pauseparam *pause)
5540 {
5541 struct mvpp2_port *port = netdev_priv(dev);
5542
5543 if (!port->phylink)
5544 return;
5545
5546 phylink_ethtool_get_pauseparam(port->phylink, pause);
5547 }
5548
mvpp2_ethtool_set_pause_param(struct net_device * dev,struct ethtool_pauseparam * pause)5549 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5550 struct ethtool_pauseparam *pause)
5551 {
5552 struct mvpp2_port *port = netdev_priv(dev);
5553
5554 if (!port->phylink)
5555 return -ENOTSUPP;
5556
5557 return phylink_ethtool_set_pauseparam(port->phylink, pause);
5558 }
5559
mvpp2_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)5560 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5561 struct ethtool_link_ksettings *cmd)
5562 {
5563 struct mvpp2_port *port = netdev_priv(dev);
5564
5565 if (!port->phylink)
5566 return -ENOTSUPP;
5567
5568 return phylink_ethtool_ksettings_get(port->phylink, cmd);
5569 }
5570
mvpp2_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)5571 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5572 const struct ethtool_link_ksettings *cmd)
5573 {
5574 struct mvpp2_port *port = netdev_priv(dev);
5575
5576 if (!port->phylink)
5577 return -ENOTSUPP;
5578
5579 return phylink_ethtool_ksettings_set(port->phylink, cmd);
5580 }
5581
mvpp2_ethtool_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rules)5582 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5583 struct ethtool_rxnfc *info, u32 *rules)
5584 {
5585 struct mvpp2_port *port = netdev_priv(dev);
5586 int ret = 0, i, loc = 0;
5587
5588 if (!mvpp22_rss_is_supported(port))
5589 return -EOPNOTSUPP;
5590
5591 switch (info->cmd) {
5592 case ETHTOOL_GRXFH:
5593 ret = mvpp2_ethtool_rxfh_get(port, info);
5594 break;
5595 case ETHTOOL_GRXRINGS:
5596 info->data = port->nrxqs;
5597 break;
5598 case ETHTOOL_GRXCLSRLCNT:
5599 info->rule_cnt = port->n_rfs_rules;
5600 break;
5601 case ETHTOOL_GRXCLSRULE:
5602 ret = mvpp2_ethtool_cls_rule_get(port, info);
5603 break;
5604 case ETHTOOL_GRXCLSRLALL:
5605 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5606 if (loc == info->rule_cnt) {
5607 ret = -EMSGSIZE;
5608 break;
5609 }
5610
5611 if (port->rfs_rules[i])
5612 rules[loc++] = i;
5613 }
5614 break;
5615 default:
5616 return -ENOTSUPP;
5617 }
5618
5619 return ret;
5620 }
5621
mvpp2_ethtool_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info)5622 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5623 struct ethtool_rxnfc *info)
5624 {
5625 struct mvpp2_port *port = netdev_priv(dev);
5626 int ret = 0;
5627
5628 if (!mvpp22_rss_is_supported(port))
5629 return -EOPNOTSUPP;
5630
5631 switch (info->cmd) {
5632 case ETHTOOL_SRXFH:
5633 ret = mvpp2_ethtool_rxfh_set(port, info);
5634 break;
5635 case ETHTOOL_SRXCLSRLINS:
5636 ret = mvpp2_ethtool_cls_rule_ins(port, info);
5637 break;
5638 case ETHTOOL_SRXCLSRLDEL:
5639 ret = mvpp2_ethtool_cls_rule_del(port, info);
5640 break;
5641 default:
5642 return -EOPNOTSUPP;
5643 }
5644 return ret;
5645 }
5646
mvpp2_ethtool_get_rxfh_indir_size(struct net_device * dev)5647 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5648 {
5649 struct mvpp2_port *port = netdev_priv(dev);
5650
5651 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;
5652 }
5653
mvpp2_ethtool_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)5654 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5655 u8 *hfunc)
5656 {
5657 struct mvpp2_port *port = netdev_priv(dev);
5658 int ret = 0;
5659
5660 if (!mvpp22_rss_is_supported(port))
5661 return -EOPNOTSUPP;
5662
5663 if (indir)
5664 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5665
5666 if (hfunc)
5667 *hfunc = ETH_RSS_HASH_CRC32;
5668
5669 return ret;
5670 }
5671
mvpp2_ethtool_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)5672 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5673 const u8 *key, const u8 hfunc)
5674 {
5675 struct mvpp2_port *port = netdev_priv(dev);
5676 int ret = 0;
5677
5678 if (!mvpp22_rss_is_supported(port))
5679 return -EOPNOTSUPP;
5680
5681 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5682 return -EOPNOTSUPP;
5683
5684 if (key)
5685 return -EOPNOTSUPP;
5686
5687 if (indir)
5688 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5689
5690 return ret;
5691 }
5692
mvpp2_ethtool_get_rxfh_context(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc,u32 rss_context)5693 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5694 u8 *key, u8 *hfunc, u32 rss_context)
5695 {
5696 struct mvpp2_port *port = netdev_priv(dev);
5697 int ret = 0;
5698
5699 if (!mvpp22_rss_is_supported(port))
5700 return -EOPNOTSUPP;
5701 if (rss_context >= MVPP22_N_RSS_TABLES)
5702 return -EINVAL;
5703
5704 if (hfunc)
5705 *hfunc = ETH_RSS_HASH_CRC32;
5706
5707 if (indir)
5708 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5709
5710 return ret;
5711 }
5712
mvpp2_ethtool_set_rxfh_context(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc,u32 * rss_context,bool delete)5713 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5714 const u32 *indir, const u8 *key,
5715 const u8 hfunc, u32 *rss_context,
5716 bool delete)
5717 {
5718 struct mvpp2_port *port = netdev_priv(dev);
5719 int ret;
5720
5721 if (!mvpp22_rss_is_supported(port))
5722 return -EOPNOTSUPP;
5723
5724 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5725 return -EOPNOTSUPP;
5726
5727 if (key)
5728 return -EOPNOTSUPP;
5729
5730 if (delete)
5731 return mvpp22_port_rss_ctx_delete(port, *rss_context);
5732
5733 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5734 ret = mvpp22_port_rss_ctx_create(port, rss_context);
5735 if (ret)
5736 return ret;
5737 }
5738
5739 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5740 }
5741 /* Device ops */
5742
5743 static const struct net_device_ops mvpp2_netdev_ops = {
5744 .ndo_open = mvpp2_open,
5745 .ndo_stop = mvpp2_stop,
5746 .ndo_start_xmit = mvpp2_tx,
5747 .ndo_set_rx_mode = mvpp2_set_rx_mode,
5748 .ndo_set_mac_address = mvpp2_set_mac_address,
5749 .ndo_change_mtu = mvpp2_change_mtu,
5750 .ndo_get_stats64 = mvpp2_get_stats64,
5751 .ndo_eth_ioctl = mvpp2_ioctl,
5752 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
5753 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
5754 .ndo_set_features = mvpp2_set_features,
5755 .ndo_bpf = mvpp2_xdp,
5756 .ndo_xdp_xmit = mvpp2_xdp_xmit,
5757 };
5758
5759 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5760 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5761 ETHTOOL_COALESCE_MAX_FRAMES,
5762 .nway_reset = mvpp2_ethtool_nway_reset,
5763 .get_link = ethtool_op_get_link,
5764 .get_ts_info = mvpp2_ethtool_get_ts_info,
5765 .set_coalesce = mvpp2_ethtool_set_coalesce,
5766 .get_coalesce = mvpp2_ethtool_get_coalesce,
5767 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
5768 .get_ringparam = mvpp2_ethtool_get_ringparam,
5769 .set_ringparam = mvpp2_ethtool_set_ringparam,
5770 .get_strings = mvpp2_ethtool_get_strings,
5771 .get_ethtool_stats = mvpp2_ethtool_get_stats,
5772 .get_sset_count = mvpp2_ethtool_get_sset_count,
5773 .get_pauseparam = mvpp2_ethtool_get_pause_param,
5774 .set_pauseparam = mvpp2_ethtool_set_pause_param,
5775 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
5776 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
5777 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
5778 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
5779 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
5780 .get_rxfh = mvpp2_ethtool_get_rxfh,
5781 .set_rxfh = mvpp2_ethtool_set_rxfh,
5782 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context,
5783 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context,
5784 };
5785
5786 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5787 * had a single IRQ defined per-port.
5788 */
mvpp2_simple_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5789 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5790 struct device_node *port_node)
5791 {
5792 struct mvpp2_queue_vector *v = &port->qvecs[0];
5793
5794 v->first_rxq = 0;
5795 v->nrxqs = port->nrxqs;
5796 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5797 v->sw_thread_id = 0;
5798 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5799 v->port = port;
5800 v->irq = irq_of_parse_and_map(port_node, 0);
5801 if (v->irq <= 0)
5802 return -EINVAL;
5803 netif_napi_add(port->dev, &v->napi, mvpp2_poll);
5804
5805 port->nqvecs = 1;
5806
5807 return 0;
5808 }
5809
mvpp2_multi_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5810 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5811 struct device_node *port_node)
5812 {
5813 struct mvpp2 *priv = port->priv;
5814 struct mvpp2_queue_vector *v;
5815 int i, ret;
5816
5817 switch (queue_mode) {
5818 case MVPP2_QDIST_SINGLE_MODE:
5819 port->nqvecs = priv->nthreads + 1;
5820 break;
5821 case MVPP2_QDIST_MULTI_MODE:
5822 port->nqvecs = priv->nthreads;
5823 break;
5824 }
5825
5826 for (i = 0; i < port->nqvecs; i++) {
5827 char irqname[16];
5828
5829 v = port->qvecs + i;
5830
5831 v->port = port;
5832 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5833 v->sw_thread_id = i;
5834 v->sw_thread_mask = BIT(i);
5835
5836 if (port->flags & MVPP2_F_DT_COMPAT)
5837 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5838 else
5839 snprintf(irqname, sizeof(irqname), "hif%d", i);
5840
5841 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5842 v->first_rxq = i;
5843 v->nrxqs = 1;
5844 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5845 i == (port->nqvecs - 1)) {
5846 v->first_rxq = 0;
5847 v->nrxqs = port->nrxqs;
5848 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5849
5850 if (port->flags & MVPP2_F_DT_COMPAT)
5851 strncpy(irqname, "rx-shared", sizeof(irqname));
5852 }
5853
5854 if (port_node)
5855 v->irq = of_irq_get_byname(port_node, irqname);
5856 else
5857 v->irq = fwnode_irq_get(port->fwnode, i);
5858 if (v->irq <= 0) {
5859 ret = -EINVAL;
5860 goto err;
5861 }
5862
5863 netif_napi_add(port->dev, &v->napi, mvpp2_poll);
5864 }
5865
5866 return 0;
5867
5868 err:
5869 for (i = 0; i < port->nqvecs; i++)
5870 irq_dispose_mapping(port->qvecs[i].irq);
5871 return ret;
5872 }
5873
mvpp2_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5874 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5875 struct device_node *port_node)
5876 {
5877 if (port->has_tx_irqs)
5878 return mvpp2_multi_queue_vectors_init(port, port_node);
5879 else
5880 return mvpp2_simple_queue_vectors_init(port, port_node);
5881 }
5882
mvpp2_queue_vectors_deinit(struct mvpp2_port * port)5883 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5884 {
5885 int i;
5886
5887 for (i = 0; i < port->nqvecs; i++)
5888 irq_dispose_mapping(port->qvecs[i].irq);
5889 }
5890
5891 /* Configure Rx queue group interrupt for this port */
mvpp2_rx_irqs_setup(struct mvpp2_port * port)5892 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5893 {
5894 struct mvpp2 *priv = port->priv;
5895 u32 val;
5896 int i;
5897
5898 if (priv->hw_version == MVPP21) {
5899 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5900 port->nrxqs);
5901 return;
5902 }
5903
5904 /* Handle the more complicated PPv2.2 and PPv2.3 case */
5905 for (i = 0; i < port->nqvecs; i++) {
5906 struct mvpp2_queue_vector *qv = port->qvecs + i;
5907
5908 if (!qv->nrxqs)
5909 continue;
5910
5911 val = qv->sw_thread_id;
5912 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5913 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5914
5915 val = qv->first_rxq;
5916 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5917 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5918 }
5919 }
5920
5921 /* Initialize port HW */
mvpp2_port_init(struct mvpp2_port * port)5922 static int mvpp2_port_init(struct mvpp2_port *port)
5923 {
5924 struct device *dev = port->dev->dev.parent;
5925 struct mvpp2 *priv = port->priv;
5926 struct mvpp2_txq_pcpu *txq_pcpu;
5927 unsigned int thread;
5928 int queue, err, val;
5929
5930 /* Checks for hardware constraints */
5931 if (port->first_rxq + port->nrxqs >
5932 MVPP2_MAX_PORTS * priv->max_port_rxqs)
5933 return -EINVAL;
5934
5935 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5936 return -EINVAL;
5937
5938 /* Disable port */
5939 mvpp2_egress_disable(port);
5940 mvpp2_port_disable(port);
5941
5942 if (mvpp2_is_xlg(port->phy_interface)) {
5943 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5944 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5945 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5946 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5947 } else {
5948 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5949 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5950 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5951 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5952 }
5953
5954 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5955
5956 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5957 GFP_KERNEL);
5958 if (!port->txqs)
5959 return -ENOMEM;
5960
5961 /* Associate physical Tx queues to this port and initialize.
5962 * The mapping is predefined.
5963 */
5964 for (queue = 0; queue < port->ntxqs; queue++) {
5965 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5966 struct mvpp2_tx_queue *txq;
5967
5968 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5969 if (!txq) {
5970 err = -ENOMEM;
5971 goto err_free_percpu;
5972 }
5973
5974 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5975 if (!txq->pcpu) {
5976 err = -ENOMEM;
5977 goto err_free_percpu;
5978 }
5979
5980 txq->id = queue_phy_id;
5981 txq->log_id = queue;
5982 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5983 for (thread = 0; thread < priv->nthreads; thread++) {
5984 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5985 txq_pcpu->thread = thread;
5986 }
5987
5988 port->txqs[queue] = txq;
5989 }
5990
5991 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5992 GFP_KERNEL);
5993 if (!port->rxqs) {
5994 err = -ENOMEM;
5995 goto err_free_percpu;
5996 }
5997
5998 /* Allocate and initialize Rx queue for this port */
5999 for (queue = 0; queue < port->nrxqs; queue++) {
6000 struct mvpp2_rx_queue *rxq;
6001
6002 /* Map physical Rx queue to port's logical Rx queue */
6003 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
6004 if (!rxq) {
6005 err = -ENOMEM;
6006 goto err_free_percpu;
6007 }
6008 /* Map this Rx queue to a physical queue */
6009 rxq->id = port->first_rxq + queue;
6010 rxq->port = port->id;
6011 rxq->logic_rxq = queue;
6012
6013 port->rxqs[queue] = rxq;
6014 }
6015
6016 mvpp2_rx_irqs_setup(port);
6017
6018 /* Create Rx descriptor rings */
6019 for (queue = 0; queue < port->nrxqs; queue++) {
6020 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
6021
6022 rxq->size = port->rx_ring_size;
6023 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
6024 rxq->time_coal = MVPP2_RX_COAL_USEC;
6025 }
6026
6027 mvpp2_ingress_disable(port);
6028
6029 /* Port default configuration */
6030 mvpp2_defaults_set(port);
6031
6032 /* Port's classifier configuration */
6033 mvpp2_cls_oversize_rxq_set(port);
6034 mvpp2_cls_port_config(port);
6035
6036 if (mvpp22_rss_is_supported(port))
6037 mvpp22_port_rss_init(port);
6038
6039 /* Provide an initial Rx packet size */
6040 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6041
6042 /* Initialize pools for swf */
6043 err = mvpp2_swf_bm_pool_init(port);
6044 if (err)
6045 goto err_free_percpu;
6046
6047 /* Clear all port stats */
6048 mvpp2_read_stats(port);
6049 memset(port->ethtool_stats, 0,
6050 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6051
6052 return 0;
6053
6054 err_free_percpu:
6055 for (queue = 0; queue < port->ntxqs; queue++) {
6056 if (!port->txqs[queue])
6057 continue;
6058 free_percpu(port->txqs[queue]->pcpu);
6059 }
6060 return err;
6061 }
6062
mvpp22_port_has_legacy_tx_irqs(struct device_node * port_node,unsigned long * flags)6063 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
6064 unsigned long *flags)
6065 {
6066 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
6067 "tx-cpu3" };
6068 int i;
6069
6070 for (i = 0; i < 5; i++)
6071 if (of_property_match_string(port_node, "interrupt-names",
6072 irqs[i]) < 0)
6073 return false;
6074
6075 *flags |= MVPP2_F_DT_COMPAT;
6076 return true;
6077 }
6078
6079 /* Checks if the port dt description has the required Tx interrupts:
6080 * - PPv2.1: there are no such interrupts.
6081 * - PPv2.2 and PPv2.3:
6082 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6083 * - The new ones have: "hifX" with X in [0..8]
6084 *
6085 * All those variants are supported to keep the backward compatibility.
6086 */
mvpp2_port_has_irqs(struct mvpp2 * priv,struct device_node * port_node,unsigned long * flags)6087 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
6088 struct device_node *port_node,
6089 unsigned long *flags)
6090 {
6091 char name[5];
6092 int i;
6093
6094 /* ACPI */
6095 if (!port_node)
6096 return true;
6097
6098 if (priv->hw_version == MVPP21)
6099 return false;
6100
6101 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
6102 return true;
6103
6104 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6105 snprintf(name, 5, "hif%d", i);
6106 if (of_property_match_string(port_node, "interrupt-names",
6107 name) < 0)
6108 return false;
6109 }
6110
6111 return true;
6112 }
6113
mvpp2_port_copy_mac_addr(struct net_device * dev,struct mvpp2 * priv,struct fwnode_handle * fwnode,char ** mac_from)6114 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
6115 struct fwnode_handle *fwnode,
6116 char **mac_from)
6117 {
6118 struct mvpp2_port *port = netdev_priv(dev);
6119 char hw_mac_addr[ETH_ALEN] = {0};
6120 char fw_mac_addr[ETH_ALEN];
6121
6122 if (!fwnode_get_mac_address(fwnode, fw_mac_addr)) {
6123 *mac_from = "firmware node";
6124 eth_hw_addr_set(dev, fw_mac_addr);
6125 return;
6126 }
6127
6128 if (priv->hw_version == MVPP21) {
6129 mvpp21_get_mac_address(port, hw_mac_addr);
6130 if (is_valid_ether_addr(hw_mac_addr)) {
6131 *mac_from = "hardware";
6132 eth_hw_addr_set(dev, hw_mac_addr);
6133 return;
6134 }
6135 }
6136
6137 *mac_from = "random";
6138 eth_hw_addr_random(dev);
6139 }
6140
mvpp2_phylink_to_port(struct phylink_config * config)6141 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
6142 {
6143 return container_of(config, struct mvpp2_port, phylink_config);
6144 }
6145
mvpp2_pcs_xlg_to_port(struct phylink_pcs * pcs)6146 static struct mvpp2_port *mvpp2_pcs_xlg_to_port(struct phylink_pcs *pcs)
6147 {
6148 return container_of(pcs, struct mvpp2_port, pcs_xlg);
6149 }
6150
mvpp2_pcs_gmac_to_port(struct phylink_pcs * pcs)6151 static struct mvpp2_port *mvpp2_pcs_gmac_to_port(struct phylink_pcs *pcs)
6152 {
6153 return container_of(pcs, struct mvpp2_port, pcs_gmac);
6154 }
6155
mvpp2_xlg_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)6156 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
6157 struct phylink_link_state *state)
6158 {
6159 struct mvpp2_port *port = mvpp2_pcs_xlg_to_port(pcs);
6160 u32 val;
6161
6162 if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER)
6163 state->speed = SPEED_5000;
6164 else
6165 state->speed = SPEED_10000;
6166 state->duplex = 1;
6167 state->an_complete = 1;
6168
6169 val = readl(port->base + MVPP22_XLG_STATUS);
6170 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
6171
6172 state->pause = 0;
6173 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6174 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
6175 state->pause |= MLO_PAUSE_TX;
6176 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
6177 state->pause |= MLO_PAUSE_RX;
6178 }
6179
mvpp2_xlg_pcs_config(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)6180 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
6181 unsigned int mode,
6182 phy_interface_t interface,
6183 const unsigned long *advertising,
6184 bool permit_pause_to_mac)
6185 {
6186 return 0;
6187 }
6188
6189 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
6190 .pcs_get_state = mvpp2_xlg_pcs_get_state,
6191 .pcs_config = mvpp2_xlg_pcs_config,
6192 };
6193
mvpp2_gmac_pcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)6194 static int mvpp2_gmac_pcs_validate(struct phylink_pcs *pcs,
6195 unsigned long *supported,
6196 const struct phylink_link_state *state)
6197 {
6198 /* When in 802.3z mode, we must have AN enabled:
6199 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
6200 * When <PortType> = 1 (1000BASE-X) this field must be set to 1.
6201 */
6202 if (phy_interface_mode_is_8023z(state->interface) &&
6203 !phylink_test(state->advertising, Autoneg))
6204 return -EINVAL;
6205
6206 return 0;
6207 }
6208
mvpp2_gmac_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)6209 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
6210 struct phylink_link_state *state)
6211 {
6212 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6213 u32 val;
6214
6215 val = readl(port->base + MVPP2_GMAC_STATUS0);
6216
6217 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
6218 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
6219 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
6220
6221 switch (port->phy_interface) {
6222 case PHY_INTERFACE_MODE_1000BASEX:
6223 state->speed = SPEED_1000;
6224 break;
6225 case PHY_INTERFACE_MODE_2500BASEX:
6226 state->speed = SPEED_2500;
6227 break;
6228 default:
6229 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
6230 state->speed = SPEED_1000;
6231 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
6232 state->speed = SPEED_100;
6233 else
6234 state->speed = SPEED_10;
6235 }
6236
6237 state->pause = 0;
6238 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
6239 state->pause |= MLO_PAUSE_RX;
6240 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
6241 state->pause |= MLO_PAUSE_TX;
6242 }
6243
mvpp2_gmac_pcs_config(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)6244 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
6245 phy_interface_t interface,
6246 const unsigned long *advertising,
6247 bool permit_pause_to_mac)
6248 {
6249 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6250 u32 mask, val, an, old_an, changed;
6251
6252 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
6253 MVPP2_GMAC_IN_BAND_AUTONEG |
6254 MVPP2_GMAC_AN_SPEED_EN |
6255 MVPP2_GMAC_FLOW_CTRL_AUTONEG |
6256 MVPP2_GMAC_AN_DUPLEX_EN;
6257
6258 if (phylink_autoneg_inband(mode)) {
6259 mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
6260 MVPP2_GMAC_CONFIG_GMII_SPEED |
6261 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6262 val = MVPP2_GMAC_IN_BAND_AUTONEG;
6263
6264 if (interface == PHY_INTERFACE_MODE_SGMII) {
6265 /* SGMII mode receives the speed and duplex from PHY */
6266 val |= MVPP2_GMAC_AN_SPEED_EN |
6267 MVPP2_GMAC_AN_DUPLEX_EN;
6268 } else {
6269 /* 802.3z mode has fixed speed and duplex */
6270 val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
6271 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6272
6273 /* The FLOW_CTRL_AUTONEG bit selects either the hardware
6274 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
6275 * manually controls the GMAC pause modes.
6276 */
6277 if (permit_pause_to_mac)
6278 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
6279
6280 /* Configure advertisement bits */
6281 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
6282 if (phylink_test(advertising, Pause))
6283 val |= MVPP2_GMAC_FC_ADV_EN;
6284 if (phylink_test(advertising, Asym_Pause))
6285 val |= MVPP2_GMAC_FC_ADV_ASM_EN;
6286 }
6287 } else {
6288 val = 0;
6289 }
6290
6291 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6292 an = (an & ~mask) | val;
6293 changed = an ^ old_an;
6294 if (changed)
6295 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6296
6297 /* We are only interested in the advertisement bits changing */
6298 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
6299 }
6300
mvpp2_gmac_pcs_an_restart(struct phylink_pcs * pcs)6301 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
6302 {
6303 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6304 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6305
6306 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
6307 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6308 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
6309 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6310 }
6311
6312 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
6313 .pcs_validate = mvpp2_gmac_pcs_validate,
6314 .pcs_get_state = mvpp2_gmac_pcs_get_state,
6315 .pcs_config = mvpp2_gmac_pcs_config,
6316 .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
6317 };
6318
mvpp2_xlg_config(struct mvpp2_port * port,unsigned int mode,const struct phylink_link_state * state)6319 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
6320 const struct phylink_link_state *state)
6321 {
6322 u32 val;
6323
6324 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6325 MVPP22_XLG_CTRL0_MAC_RESET_DIS,
6326 MVPP22_XLG_CTRL0_MAC_RESET_DIS);
6327 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
6328 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
6329 MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
6330 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
6331 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
6332
6333 /* Wait for reset to deassert */
6334 do {
6335 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6336 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
6337 }
6338
mvpp2_gmac_config(struct mvpp2_port * port,unsigned int mode,const struct phylink_link_state * state)6339 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
6340 const struct phylink_link_state *state)
6341 {
6342 u32 old_ctrl0, ctrl0;
6343 u32 old_ctrl2, ctrl2;
6344 u32 old_ctrl4, ctrl4;
6345
6346 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
6347 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
6348 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
6349
6350 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
6351 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
6352
6353 /* Configure port type */
6354 if (phy_interface_mode_is_8023z(state->interface)) {
6355 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
6356 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6357 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6358 MVPP22_CTRL4_DP_CLK_SEL |
6359 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6360 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6361 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
6362 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6363 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6364 MVPP22_CTRL4_DP_CLK_SEL |
6365 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6366 } else if (phy_interface_mode_is_rgmii(state->interface)) {
6367 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
6368 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
6369 MVPP22_CTRL4_SYNC_BYPASS_DIS |
6370 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6371 }
6372
6373 /* Configure negotiation style */
6374 if (!phylink_autoneg_inband(mode)) {
6375 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
6376 * configured speed, duplex and flow control as-is.
6377 */
6378 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6379 /* SGMII in-band mode receives the speed and duplex from
6380 * the PHY. Flow control information is not received. */
6381 } else if (phy_interface_mode_is_8023z(state->interface)) {
6382 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6383 * they negotiate duplex: they are always operating with a fixed
6384 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6385 * speed and full duplex here.
6386 */
6387 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6388 }
6389
6390 if (old_ctrl0 != ctrl0)
6391 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6392 if (old_ctrl2 != ctrl2)
6393 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6394 if (old_ctrl4 != ctrl4)
6395 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6396 }
6397
mvpp2_select_pcs(struct phylink_config * config,phy_interface_t interface)6398 static struct phylink_pcs *mvpp2_select_pcs(struct phylink_config *config,
6399 phy_interface_t interface)
6400 {
6401 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6402
6403 /* Select the appropriate PCS operations depending on the
6404 * configured interface mode. We will only switch to a mode
6405 * that the validate() checks have already passed.
6406 */
6407 if (mvpp2_is_xlg(interface))
6408 return &port->pcs_xlg;
6409 else
6410 return &port->pcs_gmac;
6411 }
6412
mvpp2_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6413 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6414 phy_interface_t interface)
6415 {
6416 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6417
6418 /* Check for invalid configuration */
6419 if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6420 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6421 return -EINVAL;
6422 }
6423
6424 if (port->phy_interface != interface ||
6425 phylink_autoneg_inband(mode)) {
6426 /* Force the link down when changing the interface or if in
6427 * in-band mode to ensure we do not change the configuration
6428 * while the hardware is indicating link is up. We force both
6429 * XLG and GMAC down to ensure that they're both in a known
6430 * state.
6431 */
6432 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6433 MVPP2_GMAC_FORCE_LINK_PASS |
6434 MVPP2_GMAC_FORCE_LINK_DOWN,
6435 MVPP2_GMAC_FORCE_LINK_DOWN);
6436
6437 if (mvpp2_port_supports_xlg(port))
6438 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6439 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6440 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6441 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6442 }
6443
6444 /* Make sure the port is disabled when reconfiguring the mode */
6445 mvpp2_port_disable(port);
6446
6447 if (port->phy_interface != interface) {
6448 /* Place GMAC into reset */
6449 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6450 MVPP2_GMAC_PORT_RESET_MASK,
6451 MVPP2_GMAC_PORT_RESET_MASK);
6452
6453 if (port->priv->hw_version >= MVPP22) {
6454 mvpp22_gop_mask_irq(port);
6455
6456 phy_power_off(port->comphy);
6457
6458 /* Reconfigure the serdes lanes */
6459 mvpp22_mode_reconfigure(port, interface);
6460 }
6461 }
6462
6463 return 0;
6464 }
6465
mvpp2_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)6466 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6467 const struct phylink_link_state *state)
6468 {
6469 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6470
6471 /* mac (re)configuration */
6472 if (mvpp2_is_xlg(state->interface))
6473 mvpp2_xlg_config(port, mode, state);
6474 else if (phy_interface_mode_is_rgmii(state->interface) ||
6475 phy_interface_mode_is_8023z(state->interface) ||
6476 state->interface == PHY_INTERFACE_MODE_SGMII)
6477 mvpp2_gmac_config(port, mode, state);
6478
6479 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6480 mvpp2_port_loopback_set(port, state);
6481 }
6482
mvpp2_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6483 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6484 phy_interface_t interface)
6485 {
6486 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6487
6488 if (port->priv->hw_version >= MVPP22 &&
6489 port->phy_interface != interface) {
6490 port->phy_interface = interface;
6491
6492 /* Unmask interrupts */
6493 mvpp22_gop_unmask_irq(port);
6494 }
6495
6496 if (!mvpp2_is_xlg(interface)) {
6497 /* Release GMAC reset and wait */
6498 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6499 MVPP2_GMAC_PORT_RESET_MASK, 0);
6500
6501 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6502 MVPP2_GMAC_PORT_RESET_MASK)
6503 continue;
6504 }
6505
6506 mvpp2_port_enable(port);
6507
6508 /* Allow the link to come up if in in-band mode, otherwise the
6509 * link is forced via mac_link_down()/mac_link_up()
6510 */
6511 if (phylink_autoneg_inband(mode)) {
6512 if (mvpp2_is_xlg(interface))
6513 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6514 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6515 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6516 else
6517 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6518 MVPP2_GMAC_FORCE_LINK_PASS |
6519 MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6520 }
6521
6522 return 0;
6523 }
6524
mvpp2_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)6525 static void mvpp2_mac_link_up(struct phylink_config *config,
6526 struct phy_device *phy,
6527 unsigned int mode, phy_interface_t interface,
6528 int speed, int duplex,
6529 bool tx_pause, bool rx_pause)
6530 {
6531 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6532 u32 val;
6533 int i;
6534
6535 if (mvpp2_is_xlg(interface)) {
6536 if (!phylink_autoneg_inband(mode)) {
6537 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6538 if (tx_pause)
6539 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6540 if (rx_pause)
6541 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6542
6543 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6544 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6545 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6546 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6547 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6548 }
6549 } else {
6550 if (!phylink_autoneg_inband(mode)) {
6551 val = MVPP2_GMAC_FORCE_LINK_PASS;
6552
6553 if (speed == SPEED_1000 || speed == SPEED_2500)
6554 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6555 else if (speed == SPEED_100)
6556 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6557
6558 if (duplex == DUPLEX_FULL)
6559 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6560
6561 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6562 MVPP2_GMAC_FORCE_LINK_DOWN |
6563 MVPP2_GMAC_FORCE_LINK_PASS |
6564 MVPP2_GMAC_CONFIG_MII_SPEED |
6565 MVPP2_GMAC_CONFIG_GMII_SPEED |
6566 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6567 }
6568
6569 /* We can always update the flow control enable bits;
6570 * these will only be effective if flow control AN
6571 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6572 */
6573 val = 0;
6574 if (tx_pause)
6575 val |= MVPP22_CTRL4_TX_FC_EN;
6576 if (rx_pause)
6577 val |= MVPP22_CTRL4_RX_FC_EN;
6578
6579 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6580 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6581 val);
6582 }
6583
6584 if (port->priv->global_tx_fc) {
6585 port->tx_fc = tx_pause;
6586 if (tx_pause)
6587 mvpp2_rxq_enable_fc(port);
6588 else
6589 mvpp2_rxq_disable_fc(port);
6590 if (port->priv->percpu_pools) {
6591 for (i = 0; i < port->nrxqs; i++)
6592 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
6593 } else {
6594 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
6595 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
6596 }
6597 if (port->priv->hw_version == MVPP23)
6598 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
6599 }
6600
6601 mvpp2_port_enable(port);
6602
6603 mvpp2_egress_enable(port);
6604 mvpp2_ingress_enable(port);
6605 netif_tx_wake_all_queues(port->dev);
6606 }
6607
mvpp2_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6608 static void mvpp2_mac_link_down(struct phylink_config *config,
6609 unsigned int mode, phy_interface_t interface)
6610 {
6611 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6612 u32 val;
6613
6614 if (!phylink_autoneg_inband(mode)) {
6615 if (mvpp2_is_xlg(interface)) {
6616 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6617 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6618 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6619 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6620 } else {
6621 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6622 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6623 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6624 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6625 }
6626 }
6627
6628 netif_tx_stop_all_queues(port->dev);
6629 mvpp2_egress_disable(port);
6630 mvpp2_ingress_disable(port);
6631
6632 mvpp2_port_disable(port);
6633 }
6634
6635 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6636 .validate = phylink_generic_validate,
6637 .mac_select_pcs = mvpp2_select_pcs,
6638 .mac_prepare = mvpp2_mac_prepare,
6639 .mac_config = mvpp2_mac_config,
6640 .mac_finish = mvpp2_mac_finish,
6641 .mac_link_up = mvpp2_mac_link_up,
6642 .mac_link_down = mvpp2_mac_link_down,
6643 };
6644
6645 /* Work-around for ACPI */
mvpp2_acpi_start(struct mvpp2_port * port)6646 static void mvpp2_acpi_start(struct mvpp2_port *port)
6647 {
6648 /* Phylink isn't used as of now for ACPI, so the MAC has to be
6649 * configured manually when the interface is started. This will
6650 * be removed as soon as the phylink ACPI support lands in.
6651 */
6652 struct phylink_link_state state = {
6653 .interface = port->phy_interface,
6654 };
6655 struct phylink_pcs *pcs;
6656
6657 pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface);
6658
6659 mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6660 port->phy_interface);
6661 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6662 pcs->ops->pcs_config(pcs, MLO_AN_INBAND, port->phy_interface,
6663 state.advertising, false);
6664 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6665 port->phy_interface);
6666 mvpp2_mac_link_up(&port->phylink_config, NULL,
6667 MLO_AN_INBAND, port->phy_interface,
6668 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6669 }
6670
6671 /* In order to ensure backward compatibility for ACPI, check if the port
6672 * firmware node comprises the necessary description allowing to use phylink.
6673 */
mvpp2_use_acpi_compat_mode(struct fwnode_handle * port_fwnode)6674 static bool mvpp2_use_acpi_compat_mode(struct fwnode_handle *port_fwnode)
6675 {
6676 if (!is_acpi_node(port_fwnode))
6677 return false;
6678
6679 return (!fwnode_property_present(port_fwnode, "phy-handle") &&
6680 !fwnode_property_present(port_fwnode, "managed") &&
6681 !fwnode_get_named_child_node(port_fwnode, "fixed-link"));
6682 }
6683
6684 /* Ports initialization */
mvpp2_port_probe(struct platform_device * pdev,struct fwnode_handle * port_fwnode,struct mvpp2 * priv)6685 static int mvpp2_port_probe(struct platform_device *pdev,
6686 struct fwnode_handle *port_fwnode,
6687 struct mvpp2 *priv)
6688 {
6689 struct phy *comphy = NULL;
6690 struct mvpp2_port *port;
6691 struct mvpp2_port_pcpu *port_pcpu;
6692 struct device_node *port_node = to_of_node(port_fwnode);
6693 netdev_features_t features;
6694 struct net_device *dev;
6695 struct phylink *phylink;
6696 char *mac_from = "";
6697 unsigned int ntxqs, nrxqs, thread;
6698 unsigned long flags = 0;
6699 bool has_tx_irqs;
6700 u32 id;
6701 int phy_mode;
6702 int err, i;
6703
6704 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6705 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6706 dev_err(&pdev->dev,
6707 "not enough IRQs to support multi queue mode\n");
6708 return -EINVAL;
6709 }
6710
6711 ntxqs = MVPP2_MAX_TXQ;
6712 nrxqs = mvpp2_get_nrxqs(priv);
6713
6714 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6715 if (!dev)
6716 return -ENOMEM;
6717
6718 phy_mode = fwnode_get_phy_mode(port_fwnode);
6719 if (phy_mode < 0) {
6720 dev_err(&pdev->dev, "incorrect phy mode\n");
6721 err = phy_mode;
6722 goto err_free_netdev;
6723 }
6724
6725 /*
6726 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6727 * Existing usage of 10GBASE-KR is not correct; no backplane
6728 * negotiation is done, and this driver does not actually support
6729 * 10GBASE-KR.
6730 */
6731 if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6732 phy_mode = PHY_INTERFACE_MODE_10GBASER;
6733
6734 if (port_node) {
6735 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6736 if (IS_ERR(comphy)) {
6737 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6738 err = -EPROBE_DEFER;
6739 goto err_free_netdev;
6740 }
6741 comphy = NULL;
6742 }
6743 }
6744
6745 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6746 err = -EINVAL;
6747 dev_err(&pdev->dev, "missing port-id value\n");
6748 goto err_free_netdev;
6749 }
6750
6751 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6752 dev->watchdog_timeo = 5 * HZ;
6753 dev->netdev_ops = &mvpp2_netdev_ops;
6754 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6755
6756 port = netdev_priv(dev);
6757 port->dev = dev;
6758 port->fwnode = port_fwnode;
6759 port->ntxqs = ntxqs;
6760 port->nrxqs = nrxqs;
6761 port->priv = priv;
6762 port->has_tx_irqs = has_tx_irqs;
6763 port->flags = flags;
6764
6765 err = mvpp2_queue_vectors_init(port, port_node);
6766 if (err)
6767 goto err_free_netdev;
6768
6769 if (port_node)
6770 port->port_irq = of_irq_get_byname(port_node, "link");
6771 else
6772 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6773 if (port->port_irq == -EPROBE_DEFER) {
6774 err = -EPROBE_DEFER;
6775 goto err_deinit_qvecs;
6776 }
6777 if (port->port_irq <= 0)
6778 /* the link irq is optional */
6779 port->port_irq = 0;
6780
6781 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6782 port->flags |= MVPP2_F_LOOPBACK;
6783
6784 port->id = id;
6785 if (priv->hw_version == MVPP21)
6786 port->first_rxq = port->id * port->nrxqs;
6787 else
6788 port->first_rxq = port->id * priv->max_port_rxqs;
6789
6790 port->of_node = port_node;
6791 port->phy_interface = phy_mode;
6792 port->comphy = comphy;
6793
6794 if (priv->hw_version == MVPP21) {
6795 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6796 if (IS_ERR(port->base)) {
6797 err = PTR_ERR(port->base);
6798 goto err_free_irq;
6799 }
6800
6801 port->stats_base = port->priv->lms_base +
6802 MVPP21_MIB_COUNTERS_OFFSET +
6803 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6804 } else {
6805 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6806 &port->gop_id)) {
6807 err = -EINVAL;
6808 dev_err(&pdev->dev, "missing gop-port-id value\n");
6809 goto err_deinit_qvecs;
6810 }
6811
6812 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6813 port->stats_base = port->priv->iface_base +
6814 MVPP22_MIB_COUNTERS_OFFSET +
6815 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6816
6817 /* We may want a property to describe whether we should use
6818 * MAC hardware timestamping.
6819 */
6820 if (priv->tai)
6821 port->hwtstamp = true;
6822 }
6823
6824 /* Alloc per-cpu and ethtool stats */
6825 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6826 if (!port->stats) {
6827 err = -ENOMEM;
6828 goto err_free_irq;
6829 }
6830
6831 port->ethtool_stats = devm_kcalloc(&pdev->dev,
6832 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6833 sizeof(u64), GFP_KERNEL);
6834 if (!port->ethtool_stats) {
6835 err = -ENOMEM;
6836 goto err_free_stats;
6837 }
6838
6839 mutex_init(&port->gather_stats_lock);
6840 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6841
6842 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6843
6844 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6845 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6846 SET_NETDEV_DEV(dev, &pdev->dev);
6847
6848 err = mvpp2_port_init(port);
6849 if (err < 0) {
6850 dev_err(&pdev->dev, "failed to init port %d\n", id);
6851 goto err_free_stats;
6852 }
6853
6854 mvpp2_port_periodic_xon_disable(port);
6855
6856 mvpp2_mac_reset_assert(port);
6857 mvpp22_pcs_reset_assert(port);
6858
6859 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6860 if (!port->pcpu) {
6861 err = -ENOMEM;
6862 goto err_free_txq_pcpu;
6863 }
6864
6865 if (!port->has_tx_irqs) {
6866 for (thread = 0; thread < priv->nthreads; thread++) {
6867 port_pcpu = per_cpu_ptr(port->pcpu, thread);
6868
6869 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6870 HRTIMER_MODE_REL_PINNED_SOFT);
6871 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6872 port_pcpu->timer_scheduled = false;
6873 port_pcpu->dev = dev;
6874 }
6875 }
6876
6877 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6878 NETIF_F_TSO;
6879 dev->features = features | NETIF_F_RXCSUM;
6880 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6881 NETIF_F_HW_VLAN_CTAG_FILTER;
6882
6883 if (mvpp22_rss_is_supported(port)) {
6884 dev->hw_features |= NETIF_F_RXHASH;
6885 dev->features |= NETIF_F_NTUPLE;
6886 }
6887
6888 if (!port->priv->percpu_pools)
6889 mvpp2_set_hw_csum(port, port->pool_long->id);
6890
6891 dev->vlan_features |= features;
6892 netif_set_tso_max_segs(dev, MVPP2_MAX_TSO_SEGS);
6893 dev->priv_flags |= IFF_UNICAST_FLT;
6894
6895 /* MTU range: 68 - 9704 */
6896 dev->min_mtu = ETH_MIN_MTU;
6897 /* 9704 == 9728 - 20 and rounding to 8 */
6898 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6899 dev->dev.of_node = port_node;
6900
6901 port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops;
6902 port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops;
6903
6904 if (!mvpp2_use_acpi_compat_mode(port_fwnode)) {
6905 port->phylink_config.dev = &dev->dev;
6906 port->phylink_config.type = PHYLINK_NETDEV;
6907 port->phylink_config.mac_capabilities =
6908 MAC_2500FD | MAC_1000FD | MAC_100 | MAC_10;
6909
6910 if (port->priv->global_tx_fc)
6911 port->phylink_config.mac_capabilities |=
6912 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
6913
6914 if (mvpp2_port_supports_xlg(port)) {
6915 /* If a COMPHY is present, we can support any of
6916 * the serdes modes and switch between them.
6917 */
6918 if (comphy) {
6919 __set_bit(PHY_INTERFACE_MODE_5GBASER,
6920 port->phylink_config.supported_interfaces);
6921 __set_bit(PHY_INTERFACE_MODE_10GBASER,
6922 port->phylink_config.supported_interfaces);
6923 __set_bit(PHY_INTERFACE_MODE_XAUI,
6924 port->phylink_config.supported_interfaces);
6925 } else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) {
6926 __set_bit(PHY_INTERFACE_MODE_5GBASER,
6927 port->phylink_config.supported_interfaces);
6928 } else if (phy_mode == PHY_INTERFACE_MODE_10GBASER) {
6929 __set_bit(PHY_INTERFACE_MODE_10GBASER,
6930 port->phylink_config.supported_interfaces);
6931 } else if (phy_mode == PHY_INTERFACE_MODE_XAUI) {
6932 __set_bit(PHY_INTERFACE_MODE_XAUI,
6933 port->phylink_config.supported_interfaces);
6934 }
6935
6936 if (comphy)
6937 port->phylink_config.mac_capabilities |=
6938 MAC_10000FD | MAC_5000FD;
6939 else if (phy_mode == PHY_INTERFACE_MODE_5GBASER)
6940 port->phylink_config.mac_capabilities |=
6941 MAC_5000FD;
6942 else
6943 port->phylink_config.mac_capabilities |=
6944 MAC_10000FD;
6945 }
6946
6947 if (mvpp2_port_supports_rgmii(port))
6948 phy_interface_set_rgmii(port->phylink_config.supported_interfaces);
6949
6950 if (comphy) {
6951 /* If a COMPHY is present, we can support any of the
6952 * serdes modes and switch between them.
6953 */
6954 __set_bit(PHY_INTERFACE_MODE_SGMII,
6955 port->phylink_config.supported_interfaces);
6956 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
6957 port->phylink_config.supported_interfaces);
6958 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
6959 port->phylink_config.supported_interfaces);
6960 } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
6961 /* No COMPHY, with only 2500BASE-X mode supported */
6962 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
6963 port->phylink_config.supported_interfaces);
6964 } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
6965 phy_mode == PHY_INTERFACE_MODE_SGMII) {
6966 /* No COMPHY, we can switch between 1000BASE-X and SGMII
6967 */
6968 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
6969 port->phylink_config.supported_interfaces);
6970 __set_bit(PHY_INTERFACE_MODE_SGMII,
6971 port->phylink_config.supported_interfaces);
6972 }
6973
6974 phylink = phylink_create(&port->phylink_config, port_fwnode,
6975 phy_mode, &mvpp2_phylink_ops);
6976 if (IS_ERR(phylink)) {
6977 err = PTR_ERR(phylink);
6978 goto err_free_port_pcpu;
6979 }
6980 port->phylink = phylink;
6981 } else {
6982 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id);
6983 port->phylink = NULL;
6984 }
6985
6986 /* Cycle the comphy to power it down, saving 270mW per port -
6987 * don't worry about an error powering it up. When the comphy
6988 * driver does this, we can remove this code.
6989 */
6990 if (port->comphy) {
6991 err = mvpp22_comphy_init(port, port->phy_interface);
6992 if (err == 0)
6993 phy_power_off(port->comphy);
6994 }
6995
6996 err = register_netdev(dev);
6997 if (err < 0) {
6998 dev_err(&pdev->dev, "failed to register netdev\n");
6999 goto err_phylink;
7000 }
7001 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
7002
7003 priv->port_list[priv->port_count++] = port;
7004
7005 return 0;
7006
7007 err_phylink:
7008 if (port->phylink)
7009 phylink_destroy(port->phylink);
7010 err_free_port_pcpu:
7011 free_percpu(port->pcpu);
7012 err_free_txq_pcpu:
7013 for (i = 0; i < port->ntxqs; i++)
7014 free_percpu(port->txqs[i]->pcpu);
7015 err_free_stats:
7016 free_percpu(port->stats);
7017 err_free_irq:
7018 if (port->port_irq)
7019 irq_dispose_mapping(port->port_irq);
7020 err_deinit_qvecs:
7021 mvpp2_queue_vectors_deinit(port);
7022 err_free_netdev:
7023 free_netdev(dev);
7024 return err;
7025 }
7026
7027 /* Ports removal routine */
mvpp2_port_remove(struct mvpp2_port * port)7028 static void mvpp2_port_remove(struct mvpp2_port *port)
7029 {
7030 int i;
7031
7032 unregister_netdev(port->dev);
7033 if (port->phylink)
7034 phylink_destroy(port->phylink);
7035 free_percpu(port->pcpu);
7036 free_percpu(port->stats);
7037 for (i = 0; i < port->ntxqs; i++)
7038 free_percpu(port->txqs[i]->pcpu);
7039 mvpp2_queue_vectors_deinit(port);
7040 if (port->port_irq)
7041 irq_dispose_mapping(port->port_irq);
7042 free_netdev(port->dev);
7043 }
7044
7045 /* Initialize decoding windows */
mvpp2_conf_mbus_windows(const struct mbus_dram_target_info * dram,struct mvpp2 * priv)7046 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
7047 struct mvpp2 *priv)
7048 {
7049 u32 win_enable;
7050 int i;
7051
7052 for (i = 0; i < 6; i++) {
7053 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
7054 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
7055
7056 if (i < 4)
7057 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
7058 }
7059
7060 win_enable = 0;
7061
7062 for (i = 0; i < dram->num_cs; i++) {
7063 const struct mbus_dram_window *cs = dram->cs + i;
7064
7065 mvpp2_write(priv, MVPP2_WIN_BASE(i),
7066 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
7067 dram->mbus_dram_target_id);
7068
7069 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
7070 (cs->size - 1) & 0xffff0000);
7071
7072 win_enable |= (1 << i);
7073 }
7074
7075 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
7076 }
7077
7078 /* Initialize Rx FIFO's */
mvpp2_rx_fifo_init(struct mvpp2 * priv)7079 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
7080 {
7081 int port;
7082
7083 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
7084 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
7085 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7086 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
7087 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
7088 }
7089
7090 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7091 MVPP2_RX_FIFO_PORT_MIN_PKT);
7092 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7093 }
7094
mvpp22_rx_fifo_set_hw(struct mvpp2 * priv,int port,int data_size)7095 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
7096 {
7097 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
7098
7099 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
7100 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
7101 }
7102
7103 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
7104 * 4kB fixed space must be assigned for the loopback port.
7105 * Redistribute remaining avialable 44kB space among all active ports.
7106 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7107 * SGMII link.
7108 */
mvpp22_rx_fifo_init(struct mvpp2 * priv)7109 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
7110 {
7111 int remaining_ports_count;
7112 unsigned long port_map;
7113 int size_remainder;
7114 int port, size;
7115
7116 /* The loopback requires fixed 4kB of the FIFO space assignment. */
7117 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7118 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7119 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7120
7121 /* Set RX FIFO size to 0 for inactive ports. */
7122 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7123 mvpp22_rx_fifo_set_hw(priv, port, 0);
7124
7125 /* Assign remaining RX FIFO space among all active ports. */
7126 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
7127 remaining_ports_count = hweight_long(port_map);
7128
7129 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7130 if (remaining_ports_count == 1)
7131 size = size_remainder;
7132 else if (port == 0)
7133 size = max(size_remainder / remaining_ports_count,
7134 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
7135 else if (port == 1)
7136 size = max(size_remainder / remaining_ports_count,
7137 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
7138 else
7139 size = size_remainder / remaining_ports_count;
7140
7141 size_remainder -= size;
7142 remaining_ports_count--;
7143
7144 mvpp22_rx_fifo_set_hw(priv, port, size);
7145 }
7146
7147 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7148 MVPP2_RX_FIFO_PORT_MIN_PKT);
7149 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7150 }
7151
7152 /* Configure Rx FIFO Flow control thresholds */
mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 * priv)7153 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
7154 {
7155 int port, val;
7156
7157 /* Port 0: maximum speed -10Gb/s port
7158 * required by spec RX FIFO threshold 9KB
7159 * Port 1: maximum speed -5Gb/s port
7160 * required by spec RX FIFO threshold 4KB
7161 * Port 2: maximum speed -1Gb/s port
7162 * required by spec RX FIFO threshold 2KB
7163 */
7164
7165 /* Without loopback port */
7166 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
7167 if (port == 0) {
7168 val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7169 << MVPP2_RX_FC_TRSH_OFFS;
7170 val &= MVPP2_RX_FC_TRSH_MASK;
7171 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7172 } else if (port == 1) {
7173 val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7174 << MVPP2_RX_FC_TRSH_OFFS;
7175 val &= MVPP2_RX_FC_TRSH_MASK;
7176 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7177 } else {
7178 val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7179 << MVPP2_RX_FC_TRSH_OFFS;
7180 val &= MVPP2_RX_FC_TRSH_MASK;
7181 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7182 }
7183 }
7184 }
7185
7186 /* Configure Rx FIFO Flow control thresholds */
mvpp23_rx_fifo_fc_en(struct mvpp2 * priv,int port,bool en)7187 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
7188 {
7189 int val;
7190
7191 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
7192
7193 if (en)
7194 val |= MVPP2_RX_FC_EN;
7195 else
7196 val &= ~MVPP2_RX_FC_EN;
7197
7198 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7199 }
7200
mvpp22_tx_fifo_set_hw(struct mvpp2 * priv,int port,int size)7201 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
7202 {
7203 int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
7204
7205 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
7206 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
7207 }
7208
7209 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
7210 * 1kB fixed space must be assigned for the loopback port.
7211 * Redistribute remaining avialable 18kB space among all active ports.
7212 * The 10G interface should use 10kB (which is maximum possible size
7213 * per single port).
7214 */
mvpp22_tx_fifo_init(struct mvpp2 * priv)7215 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
7216 {
7217 int remaining_ports_count;
7218 unsigned long port_map;
7219 int size_remainder;
7220 int port, size;
7221
7222 /* The loopback requires fixed 1kB of the FIFO space assignment. */
7223 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7224 MVPP22_TX_FIFO_DATA_SIZE_1KB);
7225 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7226
7227 /* Set TX FIFO size to 0 for inactive ports. */
7228 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7229 mvpp22_tx_fifo_set_hw(priv, port, 0);
7230
7231 /* Assign remaining TX FIFO space among all active ports. */
7232 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB;
7233 remaining_ports_count = hweight_long(port_map);
7234
7235 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7236 if (remaining_ports_count == 1)
7237 size = min(size_remainder,
7238 MVPP22_TX_FIFO_DATA_SIZE_10KB);
7239 else if (port == 0)
7240 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
7241 else
7242 size = size_remainder / remaining_ports_count;
7243
7244 size_remainder -= size;
7245 remaining_ports_count--;
7246
7247 mvpp22_tx_fifo_set_hw(priv, port, size);
7248 }
7249 }
7250
mvpp2_axi_init(struct mvpp2 * priv)7251 static void mvpp2_axi_init(struct mvpp2 *priv)
7252 {
7253 u32 val, rdval, wrval;
7254
7255 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
7256
7257 /* AXI Bridge Configuration */
7258
7259 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
7260 << MVPP22_AXI_ATTR_CACHE_OFFS;
7261 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7262 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7263
7264 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
7265 << MVPP22_AXI_ATTR_CACHE_OFFS;
7266 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7267 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7268
7269 /* BM */
7270 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
7271 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
7272
7273 /* Descriptors */
7274 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
7275 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
7276 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
7277 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
7278
7279 /* Buffer Data */
7280 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
7281 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
7282
7283 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
7284 << MVPP22_AXI_CODE_CACHE_OFFS;
7285 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
7286 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7287 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
7288 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
7289
7290 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
7291 << MVPP22_AXI_CODE_CACHE_OFFS;
7292 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7293 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7294
7295 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
7296
7297 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
7298 << MVPP22_AXI_CODE_CACHE_OFFS;
7299 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7300 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7301
7302 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
7303 }
7304
7305 /* Initialize network controller common part HW */
mvpp2_init(struct platform_device * pdev,struct mvpp2 * priv)7306 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
7307 {
7308 const struct mbus_dram_target_info *dram_target_info;
7309 int err, i;
7310 u32 val;
7311
7312 /* MBUS windows configuration */
7313 dram_target_info = mv_mbus_dram_info();
7314 if (dram_target_info)
7315 mvpp2_conf_mbus_windows(dram_target_info, priv);
7316
7317 if (priv->hw_version >= MVPP22)
7318 mvpp2_axi_init(priv);
7319
7320 /* Disable HW PHY polling */
7321 if (priv->hw_version == MVPP21) {
7322 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7323 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
7324 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7325 } else {
7326 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7327 val &= ~MVPP22_SMI_POLLING_EN;
7328 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7329 }
7330
7331 /* Allocate and initialize aggregated TXQs */
7332 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
7333 sizeof(*priv->aggr_txqs),
7334 GFP_KERNEL);
7335 if (!priv->aggr_txqs)
7336 return -ENOMEM;
7337
7338 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7339 priv->aggr_txqs[i].id = i;
7340 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
7341 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
7342 if (err < 0)
7343 return err;
7344 }
7345
7346 /* Fifo Init */
7347 if (priv->hw_version == MVPP21) {
7348 mvpp2_rx_fifo_init(priv);
7349 } else {
7350 mvpp22_rx_fifo_init(priv);
7351 mvpp22_tx_fifo_init(priv);
7352 if (priv->hw_version == MVPP23)
7353 mvpp23_rx_fifo_fc_set_tresh(priv);
7354 }
7355
7356 if (priv->hw_version == MVPP21)
7357 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
7358 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
7359
7360 /* Allow cache snoop when transmiting packets */
7361 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
7362
7363 /* Buffer Manager initialization */
7364 err = mvpp2_bm_init(&pdev->dev, priv);
7365 if (err < 0)
7366 return err;
7367
7368 /* Parser default initialization */
7369 err = mvpp2_prs_default_init(pdev, priv);
7370 if (err < 0)
7371 return err;
7372
7373 /* Classifier default initialization */
7374 mvpp2_cls_init(priv);
7375
7376 return 0;
7377 }
7378
mvpp2_get_sram(struct platform_device * pdev,struct mvpp2 * priv)7379 static int mvpp2_get_sram(struct platform_device *pdev,
7380 struct mvpp2 *priv)
7381 {
7382 struct resource *res;
7383 void __iomem *base;
7384
7385 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7386 if (!res) {
7387 if (has_acpi_companion(&pdev->dev))
7388 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
7389 else
7390 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
7391 return 0;
7392 }
7393
7394 base = devm_ioremap_resource(&pdev->dev, res);
7395 if (IS_ERR(base))
7396 return PTR_ERR(base);
7397
7398 priv->cm3_base = base;
7399 return 0;
7400 }
7401
mvpp2_probe(struct platform_device * pdev)7402 static int mvpp2_probe(struct platform_device *pdev)
7403 {
7404 struct fwnode_handle *fwnode = pdev->dev.fwnode;
7405 struct fwnode_handle *port_fwnode;
7406 struct mvpp2 *priv;
7407 struct resource *res;
7408 void __iomem *base;
7409 int i, shared;
7410 int err;
7411
7412 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
7413 if (!priv)
7414 return -ENOMEM;
7415
7416 priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
7417
7418 /* multi queue mode isn't supported on PPV2.1, fallback to single
7419 * mode
7420 */
7421 if (priv->hw_version == MVPP21)
7422 queue_mode = MVPP2_QDIST_SINGLE_MODE;
7423
7424 base = devm_platform_ioremap_resource(pdev, 0);
7425 if (IS_ERR(base))
7426 return PTR_ERR(base);
7427
7428 if (priv->hw_version == MVPP21) {
7429 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
7430 if (IS_ERR(priv->lms_base))
7431 return PTR_ERR(priv->lms_base);
7432 } else {
7433 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7434 if (!res) {
7435 dev_err(&pdev->dev, "Invalid resource\n");
7436 return -EINVAL;
7437 }
7438 if (has_acpi_companion(&pdev->dev)) {
7439 /* In case the MDIO memory region is declared in
7440 * the ACPI, it can already appear as 'in-use'
7441 * in the OS. Because it is overlapped by second
7442 * region of the network controller, make
7443 * sure it is released, before requesting it again.
7444 * The care is taken by mvpp2 driver to avoid
7445 * concurrent access to this memory region.
7446 */
7447 release_resource(res);
7448 }
7449 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
7450 if (IS_ERR(priv->iface_base))
7451 return PTR_ERR(priv->iface_base);
7452
7453 /* Map CM3 SRAM */
7454 err = mvpp2_get_sram(pdev, priv);
7455 if (err)
7456 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
7457
7458 /* Enable global Flow Control only if handler to SRAM not NULL */
7459 if (priv->cm3_base)
7460 priv->global_tx_fc = true;
7461 }
7462
7463 if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
7464 priv->sysctrl_base =
7465 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
7466 "marvell,system-controller");
7467 if (IS_ERR(priv->sysctrl_base))
7468 /* The system controller regmap is optional for dt
7469 * compatibility reasons. When not provided, the
7470 * configuration of the GoP relies on the
7471 * firmware/bootloader.
7472 */
7473 priv->sysctrl_base = NULL;
7474 }
7475
7476 if (priv->hw_version >= MVPP22 &&
7477 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
7478 priv->percpu_pools = 1;
7479
7480 mvpp2_setup_bm_pool();
7481
7482
7483 priv->nthreads = min_t(unsigned int, num_present_cpus(),
7484 MVPP2_MAX_THREADS);
7485
7486 shared = num_present_cpus() - priv->nthreads;
7487 if (shared > 0)
7488 bitmap_set(&priv->lock_map, 0,
7489 min_t(int, shared, MVPP2_MAX_THREADS));
7490
7491 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7492 u32 addr_space_sz;
7493
7494 addr_space_sz = (priv->hw_version == MVPP21 ?
7495 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
7496 priv->swth_base[i] = base + i * addr_space_sz;
7497 }
7498
7499 if (priv->hw_version == MVPP21)
7500 priv->max_port_rxqs = 8;
7501 else
7502 priv->max_port_rxqs = 32;
7503
7504 if (dev_of_node(&pdev->dev)) {
7505 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
7506 if (IS_ERR(priv->pp_clk))
7507 return PTR_ERR(priv->pp_clk);
7508 err = clk_prepare_enable(priv->pp_clk);
7509 if (err < 0)
7510 return err;
7511
7512 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
7513 if (IS_ERR(priv->gop_clk)) {
7514 err = PTR_ERR(priv->gop_clk);
7515 goto err_pp_clk;
7516 }
7517 err = clk_prepare_enable(priv->gop_clk);
7518 if (err < 0)
7519 goto err_pp_clk;
7520
7521 if (priv->hw_version >= MVPP22) {
7522 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
7523 if (IS_ERR(priv->mg_clk)) {
7524 err = PTR_ERR(priv->mg_clk);
7525 goto err_gop_clk;
7526 }
7527
7528 err = clk_prepare_enable(priv->mg_clk);
7529 if (err < 0)
7530 goto err_gop_clk;
7531
7532 priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk");
7533 if (IS_ERR(priv->mg_core_clk)) {
7534 err = PTR_ERR(priv->mg_core_clk);
7535 goto err_mg_clk;
7536 }
7537
7538 err = clk_prepare_enable(priv->mg_core_clk);
7539 if (err < 0)
7540 goto err_mg_clk;
7541 }
7542
7543 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk");
7544 if (IS_ERR(priv->axi_clk)) {
7545 err = PTR_ERR(priv->axi_clk);
7546 goto err_mg_core_clk;
7547 }
7548
7549 err = clk_prepare_enable(priv->axi_clk);
7550 if (err < 0)
7551 goto err_mg_core_clk;
7552
7553 /* Get system's tclk rate */
7554 priv->tclk = clk_get_rate(priv->pp_clk);
7555 } else {
7556 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk);
7557 if (err) {
7558 dev_err(&pdev->dev, "missing clock-frequency value\n");
7559 return err;
7560 }
7561 }
7562
7563 if (priv->hw_version >= MVPP22) {
7564 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7565 if (err)
7566 goto err_axi_clk;
7567 /* Sadly, the BM pools all share the same register to
7568 * store the high 32 bits of their address. So they
7569 * must all have the same high 32 bits, which forces
7570 * us to restrict coherent memory to DMA_BIT_MASK(32).
7571 */
7572 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7573 if (err)
7574 goto err_axi_clk;
7575 }
7576
7577 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7578 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7579 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7580 priv->port_map |= BIT(i);
7581 }
7582
7583 if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
7584 priv->hw_version = MVPP23;
7585
7586 /* Init mss lock */
7587 spin_lock_init(&priv->mss_spinlock);
7588
7589 /* Initialize network controller */
7590 err = mvpp2_init(pdev, priv);
7591 if (err < 0) {
7592 dev_err(&pdev->dev, "failed to initialize controller\n");
7593 goto err_axi_clk;
7594 }
7595
7596 err = mvpp22_tai_probe(&pdev->dev, priv);
7597 if (err < 0)
7598 goto err_axi_clk;
7599
7600 /* Initialize ports */
7601 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7602 err = mvpp2_port_probe(pdev, port_fwnode, priv);
7603 if (err < 0)
7604 goto err_port_probe;
7605 }
7606
7607 if (priv->port_count == 0) {
7608 dev_err(&pdev->dev, "no ports enabled\n");
7609 err = -ENODEV;
7610 goto err_axi_clk;
7611 }
7612
7613 /* Statistics must be gathered regularly because some of them (like
7614 * packets counters) are 32-bit registers and could overflow quite
7615 * quickly. For instance, a 10Gb link used at full bandwidth with the
7616 * smallest packets (64B) will overflow a 32-bit counter in less than
7617 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7618 */
7619 snprintf(priv->queue_name, sizeof(priv->queue_name),
7620 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7621 priv->port_count > 1 ? "+" : "");
7622 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7623 if (!priv->stats_queue) {
7624 err = -ENOMEM;
7625 goto err_port_probe;
7626 }
7627
7628 if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
7629 err = mvpp2_enable_global_fc(priv);
7630 if (err)
7631 dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
7632 }
7633
7634 mvpp2_dbgfs_init(priv, pdev->name);
7635
7636 platform_set_drvdata(pdev, priv);
7637 return 0;
7638
7639 err_port_probe:
7640 fwnode_handle_put(port_fwnode);
7641
7642 i = 0;
7643 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7644 if (priv->port_list[i])
7645 mvpp2_port_remove(priv->port_list[i]);
7646 i++;
7647 }
7648 err_axi_clk:
7649 clk_disable_unprepare(priv->axi_clk);
7650 err_mg_core_clk:
7651 clk_disable_unprepare(priv->mg_core_clk);
7652 err_mg_clk:
7653 clk_disable_unprepare(priv->mg_clk);
7654 err_gop_clk:
7655 clk_disable_unprepare(priv->gop_clk);
7656 err_pp_clk:
7657 clk_disable_unprepare(priv->pp_clk);
7658 return err;
7659 }
7660
mvpp2_remove(struct platform_device * pdev)7661 static int mvpp2_remove(struct platform_device *pdev)
7662 {
7663 struct mvpp2 *priv = platform_get_drvdata(pdev);
7664 struct fwnode_handle *fwnode = pdev->dev.fwnode;
7665 int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7666 struct fwnode_handle *port_fwnode;
7667
7668 mvpp2_dbgfs_cleanup(priv);
7669
7670 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7671 if (priv->port_list[i]) {
7672 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7673 mvpp2_port_remove(priv->port_list[i]);
7674 }
7675 i++;
7676 }
7677
7678 destroy_workqueue(priv->stats_queue);
7679
7680 if (priv->percpu_pools)
7681 poolnum = mvpp2_get_nrxqs(priv) * 2;
7682
7683 for (i = 0; i < poolnum; i++) {
7684 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7685
7686 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7687 }
7688
7689 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7690 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7691
7692 dma_free_coherent(&pdev->dev,
7693 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7694 aggr_txq->descs,
7695 aggr_txq->descs_dma);
7696 }
7697
7698 if (is_acpi_node(port_fwnode))
7699 return 0;
7700
7701 clk_disable_unprepare(priv->axi_clk);
7702 clk_disable_unprepare(priv->mg_core_clk);
7703 clk_disable_unprepare(priv->mg_clk);
7704 clk_disable_unprepare(priv->pp_clk);
7705 clk_disable_unprepare(priv->gop_clk);
7706
7707 return 0;
7708 }
7709
7710 static const struct of_device_id mvpp2_match[] = {
7711 {
7712 .compatible = "marvell,armada-375-pp2",
7713 .data = (void *)MVPP21,
7714 },
7715 {
7716 .compatible = "marvell,armada-7k-pp22",
7717 .data = (void *)MVPP22,
7718 },
7719 { }
7720 };
7721 MODULE_DEVICE_TABLE(of, mvpp2_match);
7722
7723 #ifdef CONFIG_ACPI
7724 static const struct acpi_device_id mvpp2_acpi_match[] = {
7725 { "MRVL0110", MVPP22 },
7726 { },
7727 };
7728 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7729 #endif
7730
7731 static struct platform_driver mvpp2_driver = {
7732 .probe = mvpp2_probe,
7733 .remove = mvpp2_remove,
7734 .driver = {
7735 .name = MVPP2_DRIVER_NAME,
7736 .of_match_table = mvpp2_match,
7737 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7738 },
7739 };
7740
mvpp2_driver_init(void)7741 static int __init mvpp2_driver_init(void)
7742 {
7743 return platform_driver_register(&mvpp2_driver);
7744 }
7745 module_init(mvpp2_driver_init);
7746
mvpp2_driver_exit(void)7747 static void __exit mvpp2_driver_exit(void)
7748 {
7749 platform_driver_unregister(&mvpp2_driver);
7750 mvpp2_dbgfs_exit();
7751 }
7752 module_exit(mvpp2_driver_exit);
7753
7754 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7755 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7756 MODULE_LICENSE("GPL v2");
7757