1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/iommu.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/property.h>
22 #include <linux/string_helpers.h>
23
24 #include "nhi.h"
25 #include "nhi_regs.h"
26 #include "tb.h"
27
28 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
29
30 #define RING_FIRST_USABLE_HOPID 1
31 /*
32 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are
33 * transferred.
34 */
35 #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID
36 /*
37 * Minimal number of vectors when we use MSI-X. Two for control channel
38 * Rx/Tx and the rest four are for cross domain DMA paths.
39 */
40 #define MSIX_MIN_VECS 6
41 #define MSIX_MAX_VECS 16
42
43 #define NHI_MAILBOX_TIMEOUT 500 /* ms */
44
45 /* Host interface quirks */
46 #define QUIRK_AUTO_CLEAR_INT BIT(0)
47 #define QUIRK_E2E BIT(1)
48
ring_interrupt_index(const struct tb_ring * ring)49 static int ring_interrupt_index(const struct tb_ring *ring)
50 {
51 int bit = ring->hop;
52 if (!ring->is_tx)
53 bit += ring->nhi->hop_count;
54 return bit;
55 }
56
nhi_mask_interrupt(struct tb_nhi * nhi,int mask,int ring)57 static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring)
58 {
59 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
60 u32 val;
61
62 val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
63 iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
64 } else {
65 iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring);
66 }
67 }
68
nhi_clear_interrupt(struct tb_nhi * nhi,int ring)69 static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)
70 {
71 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
72 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring);
73 else
74 iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring);
75 }
76
77 /*
78 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
79 *
80 * ring->nhi->lock must be held.
81 */
ring_interrupt_active(struct tb_ring * ring,bool active)82 static void ring_interrupt_active(struct tb_ring *ring, bool active)
83 {
84 int index = ring_interrupt_index(ring) / 32 * 4;
85 int reg = REG_RING_INTERRUPT_BASE + index;
86 int interrupt_bit = ring_interrupt_index(ring) & 31;
87 int mask = 1 << interrupt_bit;
88 u32 old, new;
89
90 if (ring->irq > 0) {
91 u32 step, shift, ivr, misc;
92 void __iomem *ivr_base;
93 int auto_clear_bit;
94 int index;
95
96 if (ring->is_tx)
97 index = ring->hop;
98 else
99 index = ring->hop + ring->nhi->hop_count;
100
101 /*
102 * Intel routers support a bit that isn't part of
103 * the USB4 spec to ask the hardware to clear
104 * interrupt status bits automatically since
105 * we already know which interrupt was triggered.
106 *
107 * Other routers explicitly disable auto-clear
108 * to prevent conditions that may occur where two
109 * MSIX interrupts are simultaneously active and
110 * reading the register clears both of them.
111 */
112 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
113 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
114 auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR;
115 else
116 auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR;
117 if (!(misc & auto_clear_bit))
118 iowrite32(misc | auto_clear_bit,
119 ring->nhi->iobase + REG_DMA_MISC);
120
121 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
122 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
123 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
124 ivr = ioread32(ivr_base + step);
125 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
126 if (active)
127 ivr |= ring->vector << shift;
128 iowrite32(ivr, ivr_base + step);
129 }
130
131 old = ioread32(ring->nhi->iobase + reg);
132 if (active)
133 new = old | mask;
134 else
135 new = old & ~mask;
136
137 dev_dbg(&ring->nhi->pdev->dev,
138 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
139 active ? "enabling" : "disabling", reg, interrupt_bit, old, new);
140
141 if (new == old)
142 dev_WARN(&ring->nhi->pdev->dev,
143 "interrupt for %s %d is already %s\n",
144 RING_TYPE(ring), ring->hop,
145 active ? "enabled" : "disabled");
146
147 if (active)
148 iowrite32(new, ring->nhi->iobase + reg);
149 else
150 nhi_mask_interrupt(ring->nhi, mask, index);
151 }
152
153 /*
154 * nhi_disable_interrupts() - disable interrupts for all rings
155 *
156 * Use only during init and shutdown.
157 */
nhi_disable_interrupts(struct tb_nhi * nhi)158 static void nhi_disable_interrupts(struct tb_nhi *nhi)
159 {
160 int i = 0;
161 /* disable interrupts */
162 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
163 nhi_mask_interrupt(nhi, ~0, 4 * i);
164
165 /* clear interrupt status bits */
166 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
167 nhi_clear_interrupt(nhi, 4 * i);
168 }
169
170 /* ring helper methods */
171
ring_desc_base(struct tb_ring * ring)172 static void __iomem *ring_desc_base(struct tb_ring *ring)
173 {
174 void __iomem *io = ring->nhi->iobase;
175 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
176 io += ring->hop * 16;
177 return io;
178 }
179
ring_options_base(struct tb_ring * ring)180 static void __iomem *ring_options_base(struct tb_ring *ring)
181 {
182 void __iomem *io = ring->nhi->iobase;
183 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
184 io += ring->hop * 32;
185 return io;
186 }
187
ring_iowrite_cons(struct tb_ring * ring,u16 cons)188 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
189 {
190 /*
191 * The other 16-bits in the register is read-only and writes to it
192 * are ignored by the hardware so we can save one ioread32() by
193 * filling the read-only bits with zeroes.
194 */
195 iowrite32(cons, ring_desc_base(ring) + 8);
196 }
197
ring_iowrite_prod(struct tb_ring * ring,u16 prod)198 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
199 {
200 /* See ring_iowrite_cons() above for explanation */
201 iowrite32(prod << 16, ring_desc_base(ring) + 8);
202 }
203
ring_iowrite32desc(struct tb_ring * ring,u32 value,u32 offset)204 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
205 {
206 iowrite32(value, ring_desc_base(ring) + offset);
207 }
208
ring_iowrite64desc(struct tb_ring * ring,u64 value,u32 offset)209 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
210 {
211 iowrite32(value, ring_desc_base(ring) + offset);
212 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
213 }
214
ring_iowrite32options(struct tb_ring * ring,u32 value,u32 offset)215 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
216 {
217 iowrite32(value, ring_options_base(ring) + offset);
218 }
219
ring_full(struct tb_ring * ring)220 static bool ring_full(struct tb_ring *ring)
221 {
222 return ((ring->head + 1) % ring->size) == ring->tail;
223 }
224
ring_empty(struct tb_ring * ring)225 static bool ring_empty(struct tb_ring *ring)
226 {
227 return ring->head == ring->tail;
228 }
229
230 /*
231 * ring_write_descriptors() - post frames from ring->queue to the controller
232 *
233 * ring->lock is held.
234 */
ring_write_descriptors(struct tb_ring * ring)235 static void ring_write_descriptors(struct tb_ring *ring)
236 {
237 struct ring_frame *frame, *n;
238 struct ring_desc *descriptor;
239 list_for_each_entry_safe(frame, n, &ring->queue, list) {
240 if (ring_full(ring))
241 break;
242 list_move_tail(&frame->list, &ring->in_flight);
243 descriptor = &ring->descriptors[ring->head];
244 descriptor->phys = frame->buffer_phy;
245 descriptor->time = 0;
246 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
247 if (ring->is_tx) {
248 descriptor->length = frame->size;
249 descriptor->eof = frame->eof;
250 descriptor->sof = frame->sof;
251 }
252 ring->head = (ring->head + 1) % ring->size;
253 if (ring->is_tx)
254 ring_iowrite_prod(ring, ring->head);
255 else
256 ring_iowrite_cons(ring, ring->head);
257 }
258 }
259
260 /*
261 * ring_work() - progress completed frames
262 *
263 * If the ring is shutting down then all frames are marked as canceled and
264 * their callbacks are invoked.
265 *
266 * Otherwise we collect all completed frame from the ring buffer, write new
267 * frame to the ring buffer and invoke the callbacks for the completed frames.
268 */
ring_work(struct work_struct * work)269 static void ring_work(struct work_struct *work)
270 {
271 struct tb_ring *ring = container_of(work, typeof(*ring), work);
272 struct ring_frame *frame;
273 bool canceled = false;
274 unsigned long flags;
275 LIST_HEAD(done);
276
277 spin_lock_irqsave(&ring->lock, flags);
278
279 if (!ring->running) {
280 /* Move all frames to done and mark them as canceled. */
281 list_splice_tail_init(&ring->in_flight, &done);
282 list_splice_tail_init(&ring->queue, &done);
283 canceled = true;
284 goto invoke_callback;
285 }
286
287 while (!ring_empty(ring)) {
288 if (!(ring->descriptors[ring->tail].flags
289 & RING_DESC_COMPLETED))
290 break;
291 frame = list_first_entry(&ring->in_flight, typeof(*frame),
292 list);
293 list_move_tail(&frame->list, &done);
294 if (!ring->is_tx) {
295 frame->size = ring->descriptors[ring->tail].length;
296 frame->eof = ring->descriptors[ring->tail].eof;
297 frame->sof = ring->descriptors[ring->tail].sof;
298 frame->flags = ring->descriptors[ring->tail].flags;
299 }
300 ring->tail = (ring->tail + 1) % ring->size;
301 }
302 ring_write_descriptors(ring);
303
304 invoke_callback:
305 /* allow callbacks to schedule new work */
306 spin_unlock_irqrestore(&ring->lock, flags);
307 while (!list_empty(&done)) {
308 frame = list_first_entry(&done, typeof(*frame), list);
309 /*
310 * The callback may reenqueue or delete frame.
311 * Do not hold on to it.
312 */
313 list_del_init(&frame->list);
314 if (frame->callback)
315 frame->callback(ring, frame, canceled);
316 }
317 }
318
__tb_ring_enqueue(struct tb_ring * ring,struct ring_frame * frame)319 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
320 {
321 unsigned long flags;
322 int ret = 0;
323
324 spin_lock_irqsave(&ring->lock, flags);
325 if (ring->running) {
326 list_add_tail(&frame->list, &ring->queue);
327 ring_write_descriptors(ring);
328 } else {
329 ret = -ESHUTDOWN;
330 }
331 spin_unlock_irqrestore(&ring->lock, flags);
332 return ret;
333 }
334 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
335
336 /**
337 * tb_ring_poll() - Poll one completed frame from the ring
338 * @ring: Ring to poll
339 *
340 * This function can be called when @start_poll callback of the @ring
341 * has been called. It will read one completed frame from the ring and
342 * return it to the caller. Returns %NULL if there is no more completed
343 * frames.
344 */
tb_ring_poll(struct tb_ring * ring)345 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
346 {
347 struct ring_frame *frame = NULL;
348 unsigned long flags;
349
350 spin_lock_irqsave(&ring->lock, flags);
351 if (!ring->running)
352 goto unlock;
353 if (ring_empty(ring))
354 goto unlock;
355
356 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
357 frame = list_first_entry(&ring->in_flight, typeof(*frame),
358 list);
359 list_del_init(&frame->list);
360
361 if (!ring->is_tx) {
362 frame->size = ring->descriptors[ring->tail].length;
363 frame->eof = ring->descriptors[ring->tail].eof;
364 frame->sof = ring->descriptors[ring->tail].sof;
365 frame->flags = ring->descriptors[ring->tail].flags;
366 }
367
368 ring->tail = (ring->tail + 1) % ring->size;
369 }
370
371 unlock:
372 spin_unlock_irqrestore(&ring->lock, flags);
373 return frame;
374 }
375 EXPORT_SYMBOL_GPL(tb_ring_poll);
376
__ring_interrupt_mask(struct tb_ring * ring,bool mask)377 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
378 {
379 int idx = ring_interrupt_index(ring);
380 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
381 int bit = idx % 32;
382 u32 val;
383
384 val = ioread32(ring->nhi->iobase + reg);
385 if (mask)
386 val &= ~BIT(bit);
387 else
388 val |= BIT(bit);
389 iowrite32(val, ring->nhi->iobase + reg);
390 }
391
392 /* Both @nhi->lock and @ring->lock should be held */
__ring_interrupt(struct tb_ring * ring)393 static void __ring_interrupt(struct tb_ring *ring)
394 {
395 if (!ring->running)
396 return;
397
398 if (ring->start_poll) {
399 __ring_interrupt_mask(ring, true);
400 ring->start_poll(ring->poll_data);
401 } else {
402 schedule_work(&ring->work);
403 }
404 }
405
406 /**
407 * tb_ring_poll_complete() - Re-start interrupt for the ring
408 * @ring: Ring to re-start the interrupt
409 *
410 * This will re-start (unmask) the ring interrupt once the user is done
411 * with polling.
412 */
tb_ring_poll_complete(struct tb_ring * ring)413 void tb_ring_poll_complete(struct tb_ring *ring)
414 {
415 unsigned long flags;
416
417 spin_lock_irqsave(&ring->nhi->lock, flags);
418 spin_lock(&ring->lock);
419 if (ring->start_poll)
420 __ring_interrupt_mask(ring, false);
421 spin_unlock(&ring->lock);
422 spin_unlock_irqrestore(&ring->nhi->lock, flags);
423 }
424 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
425
ring_clear_msix(const struct tb_ring * ring)426 static void ring_clear_msix(const struct tb_ring *ring)
427 {
428 int bit;
429
430 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
431 return;
432
433 bit = ring_interrupt_index(ring) & 31;
434 if (ring->is_tx)
435 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR);
436 else
437 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR +
438 4 * (ring->nhi->hop_count / 32));
439 }
440
ring_msix(int irq,void * data)441 static irqreturn_t ring_msix(int irq, void *data)
442 {
443 struct tb_ring *ring = data;
444
445 spin_lock(&ring->nhi->lock);
446 ring_clear_msix(ring);
447 spin_lock(&ring->lock);
448 __ring_interrupt(ring);
449 spin_unlock(&ring->lock);
450 spin_unlock(&ring->nhi->lock);
451
452 return IRQ_HANDLED;
453 }
454
ring_request_msix(struct tb_ring * ring,bool no_suspend)455 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
456 {
457 struct tb_nhi *nhi = ring->nhi;
458 unsigned long irqflags;
459 int ret;
460
461 if (!nhi->pdev->msix_enabled)
462 return 0;
463
464 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
465 if (ret < 0)
466 return ret;
467
468 ring->vector = ret;
469
470 ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
471 if (ret < 0)
472 goto err_ida_remove;
473
474 ring->irq = ret;
475
476 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
477 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
478 if (ret)
479 goto err_ida_remove;
480
481 return 0;
482
483 err_ida_remove:
484 ida_simple_remove(&nhi->msix_ida, ring->vector);
485
486 return ret;
487 }
488
ring_release_msix(struct tb_ring * ring)489 static void ring_release_msix(struct tb_ring *ring)
490 {
491 if (ring->irq <= 0)
492 return;
493
494 free_irq(ring->irq, ring);
495 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
496 ring->vector = 0;
497 ring->irq = 0;
498 }
499
nhi_alloc_hop(struct tb_nhi * nhi,struct tb_ring * ring)500 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
501 {
502 unsigned int start_hop = RING_FIRST_USABLE_HOPID;
503 int ret = 0;
504
505 if (nhi->quirks & QUIRK_E2E) {
506 start_hop = RING_FIRST_USABLE_HOPID + 1;
507 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
508 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n",
509 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID);
510 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID;
511 }
512 }
513
514 spin_lock_irq(&nhi->lock);
515
516 if (ring->hop < 0) {
517 unsigned int i;
518
519 /*
520 * Automatically allocate HopID from the non-reserved
521 * range 1 .. hop_count - 1.
522 */
523 for (i = start_hop; i < nhi->hop_count; i++) {
524 if (ring->is_tx) {
525 if (!nhi->tx_rings[i]) {
526 ring->hop = i;
527 break;
528 }
529 } else {
530 if (!nhi->rx_rings[i]) {
531 ring->hop = i;
532 break;
533 }
534 }
535 }
536 }
537
538 if (ring->hop > 0 && ring->hop < start_hop) {
539 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
540 ret = -EINVAL;
541 goto err_unlock;
542 }
543 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
544 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
545 ret = -EINVAL;
546 goto err_unlock;
547 }
548 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
549 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
550 ring->hop);
551 ret = -EBUSY;
552 goto err_unlock;
553 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
554 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
555 ring->hop);
556 ret = -EBUSY;
557 goto err_unlock;
558 }
559
560 if (ring->is_tx)
561 nhi->tx_rings[ring->hop] = ring;
562 else
563 nhi->rx_rings[ring->hop] = ring;
564
565 err_unlock:
566 spin_unlock_irq(&nhi->lock);
567
568 return ret;
569 }
570
tb_ring_alloc(struct tb_nhi * nhi,u32 hop,int size,bool transmit,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)571 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
572 bool transmit, unsigned int flags,
573 int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
574 void (*start_poll)(void *),
575 void *poll_data)
576 {
577 struct tb_ring *ring = NULL;
578
579 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
580 transmit ? "TX" : "RX", hop, size);
581
582 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
583 if (!ring)
584 return NULL;
585
586 spin_lock_init(&ring->lock);
587 INIT_LIST_HEAD(&ring->queue);
588 INIT_LIST_HEAD(&ring->in_flight);
589 INIT_WORK(&ring->work, ring_work);
590
591 ring->nhi = nhi;
592 ring->hop = hop;
593 ring->is_tx = transmit;
594 ring->size = size;
595 ring->flags = flags;
596 ring->e2e_tx_hop = e2e_tx_hop;
597 ring->sof_mask = sof_mask;
598 ring->eof_mask = eof_mask;
599 ring->head = 0;
600 ring->tail = 0;
601 ring->running = false;
602 ring->start_poll = start_poll;
603 ring->poll_data = poll_data;
604
605 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
606 size * sizeof(*ring->descriptors),
607 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
608 if (!ring->descriptors)
609 goto err_free_ring;
610
611 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
612 goto err_free_descs;
613
614 if (nhi_alloc_hop(nhi, ring))
615 goto err_release_msix;
616
617 return ring;
618
619 err_release_msix:
620 ring_release_msix(ring);
621 err_free_descs:
622 dma_free_coherent(&ring->nhi->pdev->dev,
623 ring->size * sizeof(*ring->descriptors),
624 ring->descriptors, ring->descriptors_dma);
625 err_free_ring:
626 kfree(ring);
627
628 return NULL;
629 }
630
631 /**
632 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
633 * @nhi: Pointer to the NHI the ring is to be allocated
634 * @hop: HopID (ring) to allocate
635 * @size: Number of entries in the ring
636 * @flags: Flags for the ring
637 */
tb_ring_alloc_tx(struct tb_nhi * nhi,int hop,int size,unsigned int flags)638 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
639 unsigned int flags)
640 {
641 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
642 }
643 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
644
645 /**
646 * tb_ring_alloc_rx() - Allocate DMA ring for receive
647 * @nhi: Pointer to the NHI the ring is to be allocated
648 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
649 * @size: Number of entries in the ring
650 * @flags: Flags for the ring
651 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
652 * @sof_mask: Mask of PDF values that start a frame
653 * @eof_mask: Mask of PDF values that end a frame
654 * @start_poll: If not %NULL the ring will call this function when an
655 * interrupt is triggered and masked, instead of callback
656 * in each Rx frame.
657 * @poll_data: Optional data passed to @start_poll
658 */
tb_ring_alloc_rx(struct tb_nhi * nhi,int hop,int size,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)659 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
660 unsigned int flags, int e2e_tx_hop,
661 u16 sof_mask, u16 eof_mask,
662 void (*start_poll)(void *), void *poll_data)
663 {
664 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
665 start_poll, poll_data);
666 }
667 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
668
669 /**
670 * tb_ring_start() - enable a ring
671 * @ring: Ring to start
672 *
673 * Must not be invoked in parallel with tb_ring_stop().
674 */
tb_ring_start(struct tb_ring * ring)675 void tb_ring_start(struct tb_ring *ring)
676 {
677 u16 frame_size;
678 u32 flags;
679
680 spin_lock_irq(&ring->nhi->lock);
681 spin_lock(&ring->lock);
682 if (ring->nhi->going_away)
683 goto err;
684 if (ring->running) {
685 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
686 goto err;
687 }
688 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
689 RING_TYPE(ring), ring->hop);
690
691 if (ring->flags & RING_FLAG_FRAME) {
692 /* Means 4096 */
693 frame_size = 0;
694 flags = RING_FLAG_ENABLE;
695 } else {
696 frame_size = TB_FRAME_SIZE;
697 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
698 }
699
700 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
701 if (ring->is_tx) {
702 ring_iowrite32desc(ring, ring->size, 12);
703 ring_iowrite32options(ring, 0, 4); /* time releated ? */
704 ring_iowrite32options(ring, flags, 0);
705 } else {
706 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
707
708 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
709 ring_iowrite32options(ring, sof_eof_mask, 4);
710 ring_iowrite32options(ring, flags, 0);
711 }
712
713 /*
714 * Now that the ring valid bit is set we can configure E2E if
715 * enabled for the ring.
716 */
717 if (ring->flags & RING_FLAG_E2E) {
718 if (!ring->is_tx) {
719 u32 hop;
720
721 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
722 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
723 flags |= hop;
724
725 dev_dbg(&ring->nhi->pdev->dev,
726 "enabling E2E for %s %d with TX HopID %d\n",
727 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
728 } else {
729 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
730 RING_TYPE(ring), ring->hop);
731 }
732
733 flags |= RING_FLAG_E2E_FLOW_CONTROL;
734 ring_iowrite32options(ring, flags, 0);
735 }
736
737 ring_interrupt_active(ring, true);
738 ring->running = true;
739 err:
740 spin_unlock(&ring->lock);
741 spin_unlock_irq(&ring->nhi->lock);
742 }
743 EXPORT_SYMBOL_GPL(tb_ring_start);
744
745 /**
746 * tb_ring_stop() - shutdown a ring
747 * @ring: Ring to stop
748 *
749 * Must not be invoked from a callback.
750 *
751 * This method will disable the ring. Further calls to
752 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
753 * called.
754 *
755 * All enqueued frames will be canceled and their callbacks will be executed
756 * with frame->canceled set to true (on the callback thread). This method
757 * returns only after all callback invocations have finished.
758 */
tb_ring_stop(struct tb_ring * ring)759 void tb_ring_stop(struct tb_ring *ring)
760 {
761 spin_lock_irq(&ring->nhi->lock);
762 spin_lock(&ring->lock);
763 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
764 RING_TYPE(ring), ring->hop);
765 if (ring->nhi->going_away)
766 goto err;
767 if (!ring->running) {
768 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
769 RING_TYPE(ring), ring->hop);
770 goto err;
771 }
772 ring_interrupt_active(ring, false);
773
774 ring_iowrite32options(ring, 0, 0);
775 ring_iowrite64desc(ring, 0, 0);
776 ring_iowrite32desc(ring, 0, 8);
777 ring_iowrite32desc(ring, 0, 12);
778 ring->head = 0;
779 ring->tail = 0;
780 ring->running = false;
781
782 err:
783 spin_unlock(&ring->lock);
784 spin_unlock_irq(&ring->nhi->lock);
785
786 /*
787 * schedule ring->work to invoke callbacks on all remaining frames.
788 */
789 schedule_work(&ring->work);
790 flush_work(&ring->work);
791 }
792 EXPORT_SYMBOL_GPL(tb_ring_stop);
793
794 /*
795 * tb_ring_free() - free ring
796 *
797 * When this method returns all invocations of ring->callback will have
798 * finished.
799 *
800 * Ring must be stopped.
801 *
802 * Must NOT be called from ring_frame->callback!
803 */
tb_ring_free(struct tb_ring * ring)804 void tb_ring_free(struct tb_ring *ring)
805 {
806 spin_lock_irq(&ring->nhi->lock);
807 /*
808 * Dissociate the ring from the NHI. This also ensures that
809 * nhi_interrupt_work cannot reschedule ring->work.
810 */
811 if (ring->is_tx)
812 ring->nhi->tx_rings[ring->hop] = NULL;
813 else
814 ring->nhi->rx_rings[ring->hop] = NULL;
815
816 if (ring->running) {
817 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
818 RING_TYPE(ring), ring->hop);
819 }
820 spin_unlock_irq(&ring->nhi->lock);
821
822 ring_release_msix(ring);
823
824 dma_free_coherent(&ring->nhi->pdev->dev,
825 ring->size * sizeof(*ring->descriptors),
826 ring->descriptors, ring->descriptors_dma);
827
828 ring->descriptors = NULL;
829 ring->descriptors_dma = 0;
830
831
832 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
833 ring->hop);
834
835 /*
836 * ring->work can no longer be scheduled (it is scheduled only
837 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
838 * to finish before freeing the ring.
839 */
840 flush_work(&ring->work);
841 kfree(ring);
842 }
843 EXPORT_SYMBOL_GPL(tb_ring_free);
844
845 /**
846 * nhi_mailbox_cmd() - Send a command through NHI mailbox
847 * @nhi: Pointer to the NHI structure
848 * @cmd: Command to send
849 * @data: Data to be send with the command
850 *
851 * Sends mailbox command to the firmware running on NHI. Returns %0 in
852 * case of success and negative errno in case of failure.
853 */
nhi_mailbox_cmd(struct tb_nhi * nhi,enum nhi_mailbox_cmd cmd,u32 data)854 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
855 {
856 ktime_t timeout;
857 u32 val;
858
859 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
860
861 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
862 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
863 val |= REG_INMAIL_OP_REQUEST | cmd;
864 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
865
866 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
867 do {
868 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
869 if (!(val & REG_INMAIL_OP_REQUEST))
870 break;
871 usleep_range(10, 20);
872 } while (ktime_before(ktime_get(), timeout));
873
874 if (val & REG_INMAIL_OP_REQUEST)
875 return -ETIMEDOUT;
876 if (val & REG_INMAIL_ERROR)
877 return -EIO;
878
879 return 0;
880 }
881
882 /**
883 * nhi_mailbox_mode() - Return current firmware operation mode
884 * @nhi: Pointer to the NHI structure
885 *
886 * The function reads current firmware operation mode using NHI mailbox
887 * registers and returns it to the caller.
888 */
nhi_mailbox_mode(struct tb_nhi * nhi)889 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
890 {
891 u32 val;
892
893 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
894 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
895 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
896
897 return (enum nhi_fw_mode)val;
898 }
899
nhi_interrupt_work(struct work_struct * work)900 static void nhi_interrupt_work(struct work_struct *work)
901 {
902 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
903 int value = 0; /* Suppress uninitialized usage warning. */
904 int bit;
905 int hop = -1;
906 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
907 struct tb_ring *ring;
908
909 spin_lock_irq(&nhi->lock);
910
911 /*
912 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
913 * (TX, RX, RX overflow). We iterate over the bits and read a new
914 * dwords as required. The registers are cleared on read.
915 */
916 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
917 if (bit % 32 == 0)
918 value = ioread32(nhi->iobase
919 + REG_RING_NOTIFY_BASE
920 + 4 * (bit / 32));
921 if (++hop == nhi->hop_count) {
922 hop = 0;
923 type++;
924 }
925 if ((value & (1 << (bit % 32))) == 0)
926 continue;
927 if (type == 2) {
928 dev_warn(&nhi->pdev->dev,
929 "RX overflow for ring %d\n",
930 hop);
931 continue;
932 }
933 if (type == 0)
934 ring = nhi->tx_rings[hop];
935 else
936 ring = nhi->rx_rings[hop];
937 if (ring == NULL) {
938 dev_warn(&nhi->pdev->dev,
939 "got interrupt for inactive %s ring %d\n",
940 type ? "RX" : "TX",
941 hop);
942 continue;
943 }
944
945 spin_lock(&ring->lock);
946 __ring_interrupt(ring);
947 spin_unlock(&ring->lock);
948 }
949 spin_unlock_irq(&nhi->lock);
950 }
951
nhi_msi(int irq,void * data)952 static irqreturn_t nhi_msi(int irq, void *data)
953 {
954 struct tb_nhi *nhi = data;
955 schedule_work(&nhi->interrupt_work);
956 return IRQ_HANDLED;
957 }
958
__nhi_suspend_noirq(struct device * dev,bool wakeup)959 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
960 {
961 struct pci_dev *pdev = to_pci_dev(dev);
962 struct tb *tb = pci_get_drvdata(pdev);
963 struct tb_nhi *nhi = tb->nhi;
964 int ret;
965
966 ret = tb_domain_suspend_noirq(tb);
967 if (ret)
968 return ret;
969
970 if (nhi->ops && nhi->ops->suspend_noirq) {
971 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
972 if (ret)
973 return ret;
974 }
975
976 return 0;
977 }
978
nhi_suspend_noirq(struct device * dev)979 static int nhi_suspend_noirq(struct device *dev)
980 {
981 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
982 }
983
nhi_freeze_noirq(struct device * dev)984 static int nhi_freeze_noirq(struct device *dev)
985 {
986 struct pci_dev *pdev = to_pci_dev(dev);
987 struct tb *tb = pci_get_drvdata(pdev);
988
989 return tb_domain_freeze_noirq(tb);
990 }
991
nhi_thaw_noirq(struct device * dev)992 static int nhi_thaw_noirq(struct device *dev)
993 {
994 struct pci_dev *pdev = to_pci_dev(dev);
995 struct tb *tb = pci_get_drvdata(pdev);
996
997 return tb_domain_thaw_noirq(tb);
998 }
999
nhi_wake_supported(struct pci_dev * pdev)1000 static bool nhi_wake_supported(struct pci_dev *pdev)
1001 {
1002 u8 val;
1003
1004 /*
1005 * If power rails are sustainable for wakeup from S4 this
1006 * property is set by the BIOS.
1007 */
1008 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
1009 return !!val;
1010
1011 return true;
1012 }
1013
nhi_poweroff_noirq(struct device * dev)1014 static int nhi_poweroff_noirq(struct device *dev)
1015 {
1016 struct pci_dev *pdev = to_pci_dev(dev);
1017 bool wakeup;
1018
1019 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
1020 return __nhi_suspend_noirq(dev, wakeup);
1021 }
1022
nhi_enable_int_throttling(struct tb_nhi * nhi)1023 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
1024 {
1025 /* Throttling is specified in 256ns increments */
1026 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
1027 unsigned int i;
1028
1029 /*
1030 * Configure interrupt throttling for all vectors even if we
1031 * only use few.
1032 */
1033 for (i = 0; i < MSIX_MAX_VECS; i++) {
1034 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
1035 iowrite32(throttle, nhi->iobase + reg);
1036 }
1037 }
1038
nhi_resume_noirq(struct device * dev)1039 static int nhi_resume_noirq(struct device *dev)
1040 {
1041 struct pci_dev *pdev = to_pci_dev(dev);
1042 struct tb *tb = pci_get_drvdata(pdev);
1043 struct tb_nhi *nhi = tb->nhi;
1044 int ret;
1045
1046 /*
1047 * Check that the device is still there. It may be that the user
1048 * unplugged last device which causes the host controller to go
1049 * away on PCs.
1050 */
1051 if (!pci_device_is_present(pdev)) {
1052 nhi->going_away = true;
1053 } else {
1054 if (nhi->ops && nhi->ops->resume_noirq) {
1055 ret = nhi->ops->resume_noirq(nhi);
1056 if (ret)
1057 return ret;
1058 }
1059 nhi_enable_int_throttling(tb->nhi);
1060 }
1061
1062 return tb_domain_resume_noirq(tb);
1063 }
1064
nhi_suspend(struct device * dev)1065 static int nhi_suspend(struct device *dev)
1066 {
1067 struct pci_dev *pdev = to_pci_dev(dev);
1068 struct tb *tb = pci_get_drvdata(pdev);
1069
1070 return tb_domain_suspend(tb);
1071 }
1072
nhi_complete(struct device * dev)1073 static void nhi_complete(struct device *dev)
1074 {
1075 struct pci_dev *pdev = to_pci_dev(dev);
1076 struct tb *tb = pci_get_drvdata(pdev);
1077
1078 /*
1079 * If we were runtime suspended when system suspend started,
1080 * schedule runtime resume now. It should bring the domain back
1081 * to functional state.
1082 */
1083 if (pm_runtime_suspended(&pdev->dev))
1084 pm_runtime_resume(&pdev->dev);
1085 else
1086 tb_domain_complete(tb);
1087 }
1088
nhi_runtime_suspend(struct device * dev)1089 static int nhi_runtime_suspend(struct device *dev)
1090 {
1091 struct pci_dev *pdev = to_pci_dev(dev);
1092 struct tb *tb = pci_get_drvdata(pdev);
1093 struct tb_nhi *nhi = tb->nhi;
1094 int ret;
1095
1096 ret = tb_domain_runtime_suspend(tb);
1097 if (ret)
1098 return ret;
1099
1100 if (nhi->ops && nhi->ops->runtime_suspend) {
1101 ret = nhi->ops->runtime_suspend(tb->nhi);
1102 if (ret)
1103 return ret;
1104 }
1105 return 0;
1106 }
1107
nhi_runtime_resume(struct device * dev)1108 static int nhi_runtime_resume(struct device *dev)
1109 {
1110 struct pci_dev *pdev = to_pci_dev(dev);
1111 struct tb *tb = pci_get_drvdata(pdev);
1112 struct tb_nhi *nhi = tb->nhi;
1113 int ret;
1114
1115 if (nhi->ops && nhi->ops->runtime_resume) {
1116 ret = nhi->ops->runtime_resume(nhi);
1117 if (ret)
1118 return ret;
1119 }
1120
1121 nhi_enable_int_throttling(nhi);
1122 return tb_domain_runtime_resume(tb);
1123 }
1124
nhi_shutdown(struct tb_nhi * nhi)1125 static void nhi_shutdown(struct tb_nhi *nhi)
1126 {
1127 int i;
1128
1129 dev_dbg(&nhi->pdev->dev, "shutdown\n");
1130
1131 for (i = 0; i < nhi->hop_count; i++) {
1132 if (nhi->tx_rings[i])
1133 dev_WARN(&nhi->pdev->dev,
1134 "TX ring %d is still active\n", i);
1135 if (nhi->rx_rings[i])
1136 dev_WARN(&nhi->pdev->dev,
1137 "RX ring %d is still active\n", i);
1138 }
1139 nhi_disable_interrupts(nhi);
1140 /*
1141 * We have to release the irq before calling flush_work. Otherwise an
1142 * already executing IRQ handler could call schedule_work again.
1143 */
1144 if (!nhi->pdev->msix_enabled) {
1145 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1146 flush_work(&nhi->interrupt_work);
1147 }
1148 ida_destroy(&nhi->msix_ida);
1149
1150 if (nhi->ops && nhi->ops->shutdown)
1151 nhi->ops->shutdown(nhi);
1152 }
1153
nhi_check_quirks(struct tb_nhi * nhi)1154 static void nhi_check_quirks(struct tb_nhi *nhi)
1155 {
1156 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) {
1157 /*
1158 * Intel hardware supports auto clear of the interrupt
1159 * status register right after interrupt is being
1160 * issued.
1161 */
1162 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
1163
1164 switch (nhi->pdev->device) {
1165 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
1166 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
1167 /*
1168 * Falcon Ridge controller needs the end-to-end
1169 * flow control workaround to avoid losing Rx
1170 * packets when RING_FLAG_E2E is set.
1171 */
1172 nhi->quirks |= QUIRK_E2E;
1173 break;
1174 }
1175 }
1176 }
1177
nhi_check_iommu_pdev(struct pci_dev * pdev,void * data)1178 static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data)
1179 {
1180 if (!pdev->external_facing ||
1181 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION))
1182 return 0;
1183 *(bool *)data = true;
1184 return 1; /* Stop walking */
1185 }
1186
nhi_check_iommu(struct tb_nhi * nhi)1187 static void nhi_check_iommu(struct tb_nhi *nhi)
1188 {
1189 struct pci_bus *bus = nhi->pdev->bus;
1190 bool port_ok = false;
1191
1192 /*
1193 * Ideally what we'd do here is grab every PCI device that
1194 * represents a tunnelling adapter for this NHI and check their
1195 * status directly, but unfortunately USB4 seems to make it
1196 * obnoxiously difficult to reliably make any correlation.
1197 *
1198 * So for now we'll have to bodge it... Hoping that the system
1199 * is at least sane enough that an adapter is in the same PCI
1200 * segment as its NHI, if we can find *something* on that segment
1201 * which meets the requirements for Kernel DMA Protection, we'll
1202 * take that to imply that firmware is aware and has (hopefully)
1203 * done the right thing in general. We need to know that the PCI
1204 * layer has seen the ExternalFacingPort property which will then
1205 * inform the IOMMU layer to enforce the complete "untrusted DMA"
1206 * flow, but also that the IOMMU driver itself can be trusted not
1207 * to have been subverted by a pre-boot DMA attack.
1208 */
1209 while (bus->parent)
1210 bus = bus->parent;
1211
1212 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok);
1213
1214 nhi->iommu_dma_protection = port_ok;
1215 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n",
1216 str_enabled_disabled(port_ok));
1217 }
1218
nhi_init_msi(struct tb_nhi * nhi)1219 static int nhi_init_msi(struct tb_nhi *nhi)
1220 {
1221 struct pci_dev *pdev = nhi->pdev;
1222 struct device *dev = &pdev->dev;
1223 int res, irq, nvec;
1224
1225 /* In case someone left them on. */
1226 nhi_disable_interrupts(nhi);
1227
1228 nhi_enable_int_throttling(nhi);
1229
1230 ida_init(&nhi->msix_ida);
1231
1232 /*
1233 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1234 * get all MSI-X vectors and if we succeed, each ring will have
1235 * one MSI-X. If for some reason that does not work out, we
1236 * fallback to a single MSI.
1237 */
1238 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1239 PCI_IRQ_MSIX);
1240 if (nvec < 0) {
1241 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1242 if (nvec < 0)
1243 return nvec;
1244
1245 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1246
1247 irq = pci_irq_vector(nhi->pdev, 0);
1248 if (irq < 0)
1249 return irq;
1250
1251 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1252 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1253 if (res)
1254 return dev_err_probe(dev, res, "request_irq failed, aborting\n");
1255 }
1256
1257 return 0;
1258 }
1259
nhi_imr_valid(struct pci_dev * pdev)1260 static bool nhi_imr_valid(struct pci_dev *pdev)
1261 {
1262 u8 val;
1263
1264 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1265 return !!val;
1266
1267 return true;
1268 }
1269
nhi_select_cm(struct tb_nhi * nhi)1270 static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1271 {
1272 struct tb *tb;
1273
1274 /*
1275 * USB4 case is simple. If we got control of any of the
1276 * capabilities, we use software CM.
1277 */
1278 if (tb_acpi_is_native())
1279 return tb_probe(nhi);
1280
1281 /*
1282 * Either firmware based CM is running (we did not get control
1283 * from the firmware) or this is pre-USB4 PC so try first
1284 * firmware CM and then fallback to software CM.
1285 */
1286 tb = icm_probe(nhi);
1287 if (!tb)
1288 tb = tb_probe(nhi);
1289
1290 return tb;
1291 }
1292
nhi_probe(struct pci_dev * pdev,const struct pci_device_id * id)1293 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1294 {
1295 struct device *dev = &pdev->dev;
1296 struct tb_nhi *nhi;
1297 struct tb *tb;
1298 int res;
1299
1300 if (!nhi_imr_valid(pdev))
1301 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n");
1302
1303 res = pcim_enable_device(pdev);
1304 if (res)
1305 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n");
1306
1307 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1308 if (res)
1309 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n");
1310
1311 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1312 if (!nhi)
1313 return -ENOMEM;
1314
1315 nhi->pdev = pdev;
1316 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1317 /* cannot fail - table is allocated in pcim_iomap_regions */
1318 nhi->iobase = pcim_iomap_table(pdev)[0];
1319 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1320 dev_dbg(dev, "total paths: %d\n", nhi->hop_count);
1321
1322 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1323 sizeof(*nhi->tx_rings), GFP_KERNEL);
1324 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1325 sizeof(*nhi->rx_rings), GFP_KERNEL);
1326 if (!nhi->tx_rings || !nhi->rx_rings)
1327 return -ENOMEM;
1328
1329 nhi_check_quirks(nhi);
1330 nhi_check_iommu(nhi);
1331
1332 res = nhi_init_msi(nhi);
1333 if (res)
1334 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n");
1335
1336 spin_lock_init(&nhi->lock);
1337
1338 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1339 if (res)
1340 return dev_err_probe(dev, res, "failed to set DMA mask\n");
1341
1342 pci_set_master(pdev);
1343
1344 if (nhi->ops && nhi->ops->init) {
1345 res = nhi->ops->init(nhi);
1346 if (res)
1347 return res;
1348 }
1349
1350 tb = nhi_select_cm(nhi);
1351 if (!tb)
1352 return dev_err_probe(dev, -ENODEV,
1353 "failed to determine connection manager, aborting\n");
1354
1355 dev_dbg(dev, "NHI initialized, starting thunderbolt\n");
1356
1357 res = tb_domain_add(tb);
1358 if (res) {
1359 /*
1360 * At this point the RX/TX rings might already have been
1361 * activated. Do a proper shutdown.
1362 */
1363 tb_domain_put(tb);
1364 nhi_shutdown(nhi);
1365 return res;
1366 }
1367 pci_set_drvdata(pdev, tb);
1368
1369 device_wakeup_enable(&pdev->dev);
1370
1371 pm_runtime_allow(&pdev->dev);
1372 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1373 pm_runtime_use_autosuspend(&pdev->dev);
1374 pm_runtime_put_autosuspend(&pdev->dev);
1375
1376 return 0;
1377 }
1378
nhi_remove(struct pci_dev * pdev)1379 static void nhi_remove(struct pci_dev *pdev)
1380 {
1381 struct tb *tb = pci_get_drvdata(pdev);
1382 struct tb_nhi *nhi = tb->nhi;
1383
1384 pm_runtime_get_sync(&pdev->dev);
1385 pm_runtime_dont_use_autosuspend(&pdev->dev);
1386 pm_runtime_forbid(&pdev->dev);
1387
1388 tb_domain_remove(tb);
1389 nhi_shutdown(nhi);
1390 }
1391
1392 /*
1393 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1394 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1395 * resume_noirq until we are done.
1396 */
1397 static const struct dev_pm_ops nhi_pm_ops = {
1398 .suspend_noirq = nhi_suspend_noirq,
1399 .resume_noirq = nhi_resume_noirq,
1400 .freeze_noirq = nhi_freeze_noirq, /*
1401 * we just disable hotplug, the
1402 * pci-tunnels stay alive.
1403 */
1404 .thaw_noirq = nhi_thaw_noirq,
1405 .restore_noirq = nhi_resume_noirq,
1406 .suspend = nhi_suspend,
1407 .poweroff_noirq = nhi_poweroff_noirq,
1408 .poweroff = nhi_suspend,
1409 .complete = nhi_complete,
1410 .runtime_suspend = nhi_runtime_suspend,
1411 .runtime_resume = nhi_runtime_resume,
1412 };
1413
1414 static struct pci_device_id nhi_ids[] = {
1415 /*
1416 * We have to specify class, the TB bridges use the same device and
1417 * vendor (sub)id on gen 1 and gen 2 controllers.
1418 */
1419 {
1420 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1421 .vendor = PCI_VENDOR_ID_INTEL,
1422 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1423 .subvendor = 0x2222, .subdevice = 0x1111,
1424 },
1425 {
1426 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1427 .vendor = PCI_VENDOR_ID_INTEL,
1428 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1429 .subvendor = 0x2222, .subdevice = 0x1111,
1430 },
1431 {
1432 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1433 .vendor = PCI_VENDOR_ID_INTEL,
1434 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1435 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1436 },
1437 {
1438 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1439 .vendor = PCI_VENDOR_ID_INTEL,
1440 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1441 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1442 },
1443
1444 /* Thunderbolt 3 */
1445 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1447 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1448 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1450 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1451 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1452 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1453 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1454 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1455 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1456 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1457 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1458 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1459 /* Thunderbolt 4 */
1460 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1461 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1462 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1463 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1464 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1465 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1466 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1467 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1468 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1469 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1470 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1471 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1472 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0),
1473 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1474 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1),
1475 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1476 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0),
1477 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1478 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0),
1479 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1480 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1),
1481 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1482 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) },
1483 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) },
1484
1485 /* Any USB4 compliant host */
1486 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1487
1488 { 0,}
1489 };
1490
1491 MODULE_DEVICE_TABLE(pci, nhi_ids);
1492 MODULE_LICENSE("GPL");
1493
1494 static struct pci_driver nhi_driver = {
1495 .name = "thunderbolt",
1496 .id_table = nhi_ids,
1497 .probe = nhi_probe,
1498 .remove = nhi_remove,
1499 .shutdown = nhi_remove,
1500 .driver.pm = &nhi_pm_ops,
1501 };
1502
nhi_init(void)1503 static int __init nhi_init(void)
1504 {
1505 int ret;
1506
1507 ret = tb_domain_init();
1508 if (ret)
1509 return ret;
1510 ret = pci_register_driver(&nhi_driver);
1511 if (ret)
1512 tb_domain_exit();
1513 return ret;
1514 }
1515
nhi_unload(void)1516 static void __exit nhi_unload(void)
1517 {
1518 pci_unregister_driver(&nhi_driver);
1519 tb_domain_exit();
1520 }
1521
1522 rootfs_initcall(nhi_init);
1523 module_exit(nhi_unload);
1524