1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/dsa/ocelot.h>
8 #include <linux/interrupt.h>
9 #include <linux/iopoll.h>
10 #include <linux/module.h>
11 #include <linux/of_net.h>
12 #include <linux/netdevice.h>
13 #include <linux/phylink.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_platform.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/skbuff.h>
18 #include <net/switchdev.h>
19
20 #include <soc/mscc/ocelot_vcap.h>
21 #include <soc/mscc/ocelot_hsio.h>
22 #include <soc/mscc/vsc7514_regs.h>
23 #include "ocelot_fdma.h"
24 #include "ocelot.h"
25
26 #define VSC7514_VCAP_POLICER_BASE 128
27 #define VSC7514_VCAP_POLICER_MAX 191
28
29 #define MEM_INIT_SLEEP_US 1000
30 #define MEM_INIT_TIMEOUT_US 100000
31
32 static const u32 *ocelot_regmap[TARGET_MAX] = {
33 [ANA] = vsc7514_ana_regmap,
34 [QS] = vsc7514_qs_regmap,
35 [QSYS] = vsc7514_qsys_regmap,
36 [REW] = vsc7514_rew_regmap,
37 [SYS] = vsc7514_sys_regmap,
38 [S0] = vsc7514_vcap_regmap,
39 [S1] = vsc7514_vcap_regmap,
40 [S2] = vsc7514_vcap_regmap,
41 [PTP] = vsc7514_ptp_regmap,
42 [DEV_GMII] = vsc7514_dev_gmii_regmap,
43 };
44
45 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = {
46 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
47 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
48 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
49 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
50 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
51 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
52 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
53 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
54 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
55 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
56 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
57 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
58 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
59 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
60 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
61 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
62 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
63 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
64 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
65 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
66 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
67 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
68 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
69 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
70 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
71 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
72 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
73 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
74 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
75 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
76 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
77 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
78 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
79 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
80 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
81 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
82 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
83 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
84 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
85 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
86 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
87 /* Replicated per number of ports (12), register size 4 per port */
88 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4),
89 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4),
90 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4),
91 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4),
92 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4),
93 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4),
94 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4),
95 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4),
96 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4),
97 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4),
98 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4),
99 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4),
100 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4),
101 };
102
103 static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = {
104 OCELOT_COMMON_STATS,
105 };
106
ocelot_pll5_init(struct ocelot * ocelot)107 static void ocelot_pll5_init(struct ocelot *ocelot)
108 {
109 /* Configure PLL5. This will need a proper CCF driver
110 * The values are coming from the VTSS API for Ocelot
111 */
112 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
113 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
114 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
115 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
116 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
117 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
118 HSIO_PLL5G_CFG0_ENA_BIAS |
119 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
120 HSIO_PLL5G_CFG0_ENA_CP1 |
121 HSIO_PLL5G_CFG0_SELCPI(2) |
122 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
123 HSIO_PLL5G_CFG0_SELBGV820(4) |
124 HSIO_PLL5G_CFG0_DIV4 |
125 HSIO_PLL5G_CFG0_ENA_CLKTREE |
126 HSIO_PLL5G_CFG0_ENA_LANE);
127 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
128 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
129 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
130 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
131 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
132 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
133 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
134 }
135
ocelot_chip_init(struct ocelot * ocelot,const struct ocelot_ops * ops)136 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
137 {
138 int ret;
139
140 ocelot->map = ocelot_regmap;
141 ocelot->stats_layout = ocelot_stats_layout;
142 ocelot->num_mact_rows = 1024;
143 ocelot->ops = ops;
144
145 ret = ocelot_regfields_init(ocelot, ocelot_regfields);
146 if (ret)
147 return ret;
148
149 ocelot_pll5_init(ocelot);
150
151 eth_random_addr(ocelot->base_mac);
152 ocelot->base_mac[5] &= 0xf0;
153
154 return 0;
155 }
156
ocelot_xtr_irq_handler(int irq,void * arg)157 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
158 {
159 struct ocelot *ocelot = arg;
160 int grp = 0, err;
161
162 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) {
163 struct sk_buff *skb;
164
165 err = ocelot_xtr_poll_frame(ocelot, grp, &skb);
166 if (err)
167 goto out;
168
169 skb->dev->stats.rx_bytes += skb->len;
170 skb->dev->stats.rx_packets++;
171
172 if (!skb_defer_rx_timestamp(skb))
173 netif_rx(skb);
174 }
175
176 out:
177 if (err < 0)
178 ocelot_drain_cpu_queue(ocelot, 0);
179
180 return IRQ_HANDLED;
181 }
182
ocelot_ptp_rdy_irq_handler(int irq,void * arg)183 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg)
184 {
185 struct ocelot *ocelot = arg;
186
187 ocelot_get_txtstamp(ocelot);
188
189 return IRQ_HANDLED;
190 }
191
192 static const struct of_device_id mscc_ocelot_match[] = {
193 { .compatible = "mscc,vsc7514-switch" },
194 { }
195 };
196 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
197
ocelot_mem_init_status(struct ocelot * ocelot)198 static int ocelot_mem_init_status(struct ocelot *ocelot)
199 {
200 unsigned int val;
201 int err;
202
203 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
204 &val);
205
206 return err ?: val;
207 }
208
ocelot_reset(struct ocelot * ocelot)209 static int ocelot_reset(struct ocelot *ocelot)
210 {
211 int err;
212 u32 val;
213
214 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
215 if (err)
216 return err;
217
218 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
219 if (err)
220 return err;
221
222 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
223 * 100us) before enabling the switch core.
224 */
225 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
226 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
227 if (err)
228 return err;
229
230 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
231 if (err)
232 return err;
233
234 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
235 }
236
237 /* Watermark encode
238 * Bit 8: Unit; 0:1, 1:16
239 * Bit 7-0: Value to be multiplied with unit
240 */
ocelot_wm_enc(u16 value)241 static u16 ocelot_wm_enc(u16 value)
242 {
243 WARN_ON(value >= 16 * BIT(8));
244
245 if (value >= BIT(8))
246 return BIT(8) | (value / 16);
247
248 return value;
249 }
250
ocelot_wm_dec(u16 wm)251 static u16 ocelot_wm_dec(u16 wm)
252 {
253 if (wm & BIT(8))
254 return (wm & GENMASK(7, 0)) * 16;
255
256 return wm;
257 }
258
ocelot_wm_stat(u32 val,u32 * inuse,u32 * maxuse)259 static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
260 {
261 *inuse = (val & GENMASK(23, 12)) >> 12;
262 *maxuse = val & GENMASK(11, 0);
263 }
264
265 static const struct ocelot_ops ocelot_ops = {
266 .reset = ocelot_reset,
267 .wm_enc = ocelot_wm_enc,
268 .wm_dec = ocelot_wm_dec,
269 .wm_stat = ocelot_wm_stat,
270 .port_to_netdev = ocelot_port_to_netdev,
271 .netdev_to_port = ocelot_netdev_to_port,
272 };
273
274 static struct vcap_props vsc7514_vcap_props[] = {
275 [VCAP_ES0] = {
276 .action_type_width = 0,
277 .action_table = {
278 [ES0_ACTION_TYPE_NORMAL] = {
279 .width = 73, /* HIT_STICKY not included */
280 .count = 1,
281 },
282 },
283 .target = S0,
284 .keys = vsc7514_vcap_es0_keys,
285 .actions = vsc7514_vcap_es0_actions,
286 },
287 [VCAP_IS1] = {
288 .action_type_width = 0,
289 .action_table = {
290 [IS1_ACTION_TYPE_NORMAL] = {
291 .width = 78, /* HIT_STICKY not included */
292 .count = 4,
293 },
294 },
295 .target = S1,
296 .keys = vsc7514_vcap_is1_keys,
297 .actions = vsc7514_vcap_is1_actions,
298 },
299 [VCAP_IS2] = {
300 .action_type_width = 1,
301 .action_table = {
302 [IS2_ACTION_TYPE_NORMAL] = {
303 .width = 49,
304 .count = 2
305 },
306 [IS2_ACTION_TYPE_SMAC_SIP] = {
307 .width = 6,
308 .count = 4
309 },
310 },
311 .target = S2,
312 .keys = vsc7514_vcap_is2_keys,
313 .actions = vsc7514_vcap_is2_actions,
314 },
315 };
316
317 static struct ptp_clock_info ocelot_ptp_clock_info = {
318 .owner = THIS_MODULE,
319 .name = "ocelot ptp",
320 .max_adj = 0x7fffffff,
321 .n_alarm = 0,
322 .n_ext_ts = 0,
323 .n_per_out = OCELOT_PTP_PINS_NUM,
324 .n_pins = OCELOT_PTP_PINS_NUM,
325 .pps = 0,
326 .gettime64 = ocelot_ptp_gettime64,
327 .settime64 = ocelot_ptp_settime64,
328 .adjtime = ocelot_ptp_adjtime,
329 .adjfine = ocelot_ptp_adjfine,
330 .verify = ocelot_ptp_verify,
331 .enable = ocelot_ptp_enable,
332 };
333
mscc_ocelot_teardown_devlink_ports(struct ocelot * ocelot)334 static void mscc_ocelot_teardown_devlink_ports(struct ocelot *ocelot)
335 {
336 int port;
337
338 for (port = 0; port < ocelot->num_phys_ports; port++)
339 ocelot_port_devlink_teardown(ocelot, port);
340 }
341
mscc_ocelot_release_ports(struct ocelot * ocelot)342 static void mscc_ocelot_release_ports(struct ocelot *ocelot)
343 {
344 int port;
345
346 for (port = 0; port < ocelot->num_phys_ports; port++) {
347 struct ocelot_port *ocelot_port;
348
349 ocelot_port = ocelot->ports[port];
350 if (!ocelot_port)
351 continue;
352
353 ocelot_deinit_port(ocelot, port);
354 ocelot_release_port(ocelot_port);
355 }
356 }
357
mscc_ocelot_init_ports(struct platform_device * pdev,struct device_node * ports)358 static int mscc_ocelot_init_ports(struct platform_device *pdev,
359 struct device_node *ports)
360 {
361 struct ocelot *ocelot = platform_get_drvdata(pdev);
362 u32 devlink_ports_registered = 0;
363 struct device_node *portnp;
364 int port, err;
365 u32 reg;
366
367 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
368 sizeof(struct ocelot_port *), GFP_KERNEL);
369 if (!ocelot->ports)
370 return -ENOMEM;
371
372 ocelot->devlink_ports = devm_kcalloc(ocelot->dev,
373 ocelot->num_phys_ports,
374 sizeof(*ocelot->devlink_ports),
375 GFP_KERNEL);
376 if (!ocelot->devlink_ports)
377 return -ENOMEM;
378
379 for_each_available_child_of_node(ports, portnp) {
380 struct ocelot_port_private *priv;
381 struct ocelot_port *ocelot_port;
382 struct devlink_port *dlp;
383 struct regmap *target;
384 struct resource *res;
385 char res_name[8];
386
387 if (of_property_read_u32(portnp, "reg", ®))
388 continue;
389
390 port = reg;
391 if (port < 0 || port >= ocelot->num_phys_ports) {
392 dev_err(ocelot->dev,
393 "invalid port number: %d >= %d\n", port,
394 ocelot->num_phys_ports);
395 continue;
396 }
397
398 snprintf(res_name, sizeof(res_name), "port%d", port);
399
400 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
401 res_name);
402 target = ocelot_regmap_init(ocelot, res);
403 if (IS_ERR(target)) {
404 err = PTR_ERR(target);
405 of_node_put(portnp);
406 goto out_teardown;
407 }
408
409 err = ocelot_port_devlink_init(ocelot, port,
410 DEVLINK_PORT_FLAVOUR_PHYSICAL);
411 if (err) {
412 of_node_put(portnp);
413 goto out_teardown;
414 }
415
416 err = ocelot_probe_port(ocelot, port, target, portnp);
417 if (err) {
418 ocelot_port_devlink_teardown(ocelot, port);
419 continue;
420 }
421
422 devlink_ports_registered |= BIT(port);
423
424 ocelot_port = ocelot->ports[port];
425 priv = container_of(ocelot_port, struct ocelot_port_private,
426 port);
427 dlp = &ocelot->devlink_ports[port];
428 devlink_port_type_eth_set(dlp, priv->dev);
429 }
430
431 /* Initialize unused devlink ports at the end */
432 for (port = 0; port < ocelot->num_phys_ports; port++) {
433 if (devlink_ports_registered & BIT(port))
434 continue;
435
436 err = ocelot_port_devlink_init(ocelot, port,
437 DEVLINK_PORT_FLAVOUR_UNUSED);
438 if (err)
439 goto out_teardown;
440
441 devlink_ports_registered |= BIT(port);
442 }
443
444 return 0;
445
446 out_teardown:
447 /* Unregister the network interfaces */
448 mscc_ocelot_release_ports(ocelot);
449 /* Tear down devlink ports for the registered network interfaces */
450 for (port = 0; port < ocelot->num_phys_ports; port++) {
451 if (devlink_ports_registered & BIT(port))
452 ocelot_port_devlink_teardown(ocelot, port);
453 }
454 return err;
455 }
456
mscc_ocelot_probe(struct platform_device * pdev)457 static int mscc_ocelot_probe(struct platform_device *pdev)
458 {
459 struct device_node *np = pdev->dev.of_node;
460 int err, irq_xtr, irq_ptp_rdy;
461 struct device_node *ports;
462 struct devlink *devlink;
463 struct ocelot *ocelot;
464 struct regmap *hsio;
465 unsigned int i;
466
467 struct {
468 enum ocelot_target id;
469 char *name;
470 u8 optional:1;
471 } io_target[] = {
472 { SYS, "sys" },
473 { REW, "rew" },
474 { QSYS, "qsys" },
475 { ANA, "ana" },
476 { QS, "qs" },
477 { S0, "s0" },
478 { S1, "s1" },
479 { S2, "s2" },
480 { PTP, "ptp", 1 },
481 { FDMA, "fdma", 1 },
482 };
483
484 if (!np && !pdev->dev.platform_data)
485 return -ENODEV;
486
487 devlink =
488 devlink_alloc(&ocelot_devlink_ops, sizeof(*ocelot), &pdev->dev);
489 if (!devlink)
490 return -ENOMEM;
491
492 ocelot = devlink_priv(devlink);
493 ocelot->devlink = priv_to_devlink(ocelot);
494 platform_set_drvdata(pdev, ocelot);
495 ocelot->dev = &pdev->dev;
496
497 for (i = 0; i < ARRAY_SIZE(io_target); i++) {
498 struct regmap *target;
499 struct resource *res;
500
501 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
502 io_target[i].name);
503
504 target = ocelot_regmap_init(ocelot, res);
505 if (IS_ERR(target)) {
506 if (io_target[i].optional) {
507 ocelot->targets[io_target[i].id] = NULL;
508 continue;
509 }
510 err = PTR_ERR(target);
511 goto out_free_devlink;
512 }
513
514 ocelot->targets[io_target[i].id] = target;
515 }
516
517 if (ocelot->targets[FDMA])
518 ocelot_fdma_init(pdev, ocelot);
519
520 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
521 if (IS_ERR(hsio)) {
522 dev_err(&pdev->dev, "missing hsio syscon\n");
523 err = PTR_ERR(hsio);
524 goto out_free_devlink;
525 }
526
527 ocelot->targets[HSIO] = hsio;
528
529 err = ocelot_chip_init(ocelot, &ocelot_ops);
530 if (err)
531 goto out_free_devlink;
532
533 irq_xtr = platform_get_irq_byname(pdev, "xtr");
534 if (irq_xtr < 0) {
535 err = irq_xtr;
536 goto out_free_devlink;
537 }
538
539 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL,
540 ocelot_xtr_irq_handler, IRQF_ONESHOT,
541 "frame extraction", ocelot);
542 if (err)
543 goto out_free_devlink;
544
545 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy");
546 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) {
547 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL,
548 ocelot_ptp_rdy_irq_handler,
549 IRQF_ONESHOT, "ptp ready",
550 ocelot);
551 if (err)
552 goto out_free_devlink;
553
554 /* Both the PTP interrupt and the PTP bank are available */
555 ocelot->ptp = 1;
556 }
557
558 ports = of_get_child_by_name(np, "ethernet-ports");
559 if (!ports) {
560 dev_err(ocelot->dev, "no ethernet-ports child node found\n");
561 err = -ENODEV;
562 goto out_free_devlink;
563 }
564
565 ocelot->num_phys_ports = of_get_child_count(ports);
566 ocelot->num_flooding_pgids = 1;
567
568 ocelot->vcap = vsc7514_vcap_props;
569
570 ocelot->vcap_pol.base = VSC7514_VCAP_POLICER_BASE;
571 ocelot->vcap_pol.max = VSC7514_VCAP_POLICER_MAX;
572
573 ocelot->npi = -1;
574
575 err = ocelot_init(ocelot);
576 if (err)
577 goto out_put_ports;
578
579 err = mscc_ocelot_init_ports(pdev, ports);
580 if (err)
581 goto out_ocelot_devlink_unregister;
582
583 if (ocelot->fdma)
584 ocelot_fdma_start(ocelot);
585
586 err = ocelot_devlink_sb_register(ocelot);
587 if (err)
588 goto out_ocelot_release_ports;
589
590 if (ocelot->ptp) {
591 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info);
592 if (err) {
593 dev_err(ocelot->dev,
594 "Timestamp initialization failed\n");
595 ocelot->ptp = 0;
596 }
597 }
598
599 register_netdevice_notifier(&ocelot_netdevice_nb);
600 register_switchdev_notifier(&ocelot_switchdev_nb);
601 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
602
603 of_node_put(ports);
604 devlink_register(devlink);
605
606 dev_info(&pdev->dev, "Ocelot switch probed\n");
607
608 return 0;
609
610 out_ocelot_release_ports:
611 mscc_ocelot_release_ports(ocelot);
612 mscc_ocelot_teardown_devlink_ports(ocelot);
613 out_ocelot_devlink_unregister:
614 ocelot_deinit(ocelot);
615 out_put_ports:
616 of_node_put(ports);
617 out_free_devlink:
618 devlink_free(devlink);
619 return err;
620 }
621
mscc_ocelot_remove(struct platform_device * pdev)622 static int mscc_ocelot_remove(struct platform_device *pdev)
623 {
624 struct ocelot *ocelot = platform_get_drvdata(pdev);
625
626 if (ocelot->fdma)
627 ocelot_fdma_deinit(ocelot);
628 devlink_unregister(ocelot->devlink);
629 ocelot_deinit_timestamp(ocelot);
630 ocelot_devlink_sb_unregister(ocelot);
631 mscc_ocelot_release_ports(ocelot);
632 mscc_ocelot_teardown_devlink_ports(ocelot);
633 ocelot_deinit(ocelot);
634 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
635 unregister_switchdev_notifier(&ocelot_switchdev_nb);
636 unregister_netdevice_notifier(&ocelot_netdevice_nb);
637 devlink_free(ocelot->devlink);
638
639 return 0;
640 }
641
642 static struct platform_driver mscc_ocelot_driver = {
643 .probe = mscc_ocelot_probe,
644 .remove = mscc_ocelot_remove,
645 .driver = {
646 .name = "ocelot-switch",
647 .of_match_table = mscc_ocelot_match,
648 },
649 };
650
651 module_platform_driver(mscc_ocelot_driver);
652
653 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
654 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
655 MODULE_LICENSE("Dual MIT/GPL");
656