1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/regmap.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/if_vlan.h>
18 #include <linux/reset.h>
19 #include <linux/tcp.h>
20 #include <linux/interrupt.h>
21 #include <linux/pinctrl/devinfo.h>
22 #include <linux/phylink.h>
23 #include <linux/jhash.h>
24 #include <linux/bitfield.h>
25 #include <net/dsa.h>
26
27 #include "mtk_eth_soc.h"
28 #include "mtk_wed.h"
29
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36
37 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
38 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
39 sizeof(u64) }
40
41 static const struct mtk_reg_map mtk_reg_map = {
42 .tx_irq_mask = 0x1a1c,
43 .tx_irq_status = 0x1a18,
44 .pdma = {
45 .rx_ptr = 0x0900,
46 .rx_cnt_cfg = 0x0904,
47 .pcrx_ptr = 0x0908,
48 .glo_cfg = 0x0a04,
49 .rst_idx = 0x0a08,
50 .delay_irq = 0x0a0c,
51 .irq_status = 0x0a20,
52 .irq_mask = 0x0a28,
53 .int_grp = 0x0a50,
54 },
55 .qdma = {
56 .qtx_cfg = 0x1800,
57 .rx_ptr = 0x1900,
58 .rx_cnt_cfg = 0x1904,
59 .qcrx_ptr = 0x1908,
60 .glo_cfg = 0x1a04,
61 .rst_idx = 0x1a08,
62 .delay_irq = 0x1a0c,
63 .fc_th = 0x1a10,
64 .int_grp = 0x1a20,
65 .hred = 0x1a44,
66 .ctx_ptr = 0x1b00,
67 .dtx_ptr = 0x1b04,
68 .crx_ptr = 0x1b10,
69 .drx_ptr = 0x1b14,
70 .fq_head = 0x1b20,
71 .fq_tail = 0x1b24,
72 .fq_count = 0x1b28,
73 .fq_blen = 0x1b2c,
74 },
75 .gdm1_cnt = 0x2400,
76 .gdma_to_ppe = 0x4444,
77 .ppe_base = 0x0c00,
78 .wdma_base = {
79 [0] = 0x2800,
80 [1] = 0x2c00,
81 },
82 };
83
84 static const struct mtk_reg_map mt7628_reg_map = {
85 .tx_irq_mask = 0x0a28,
86 .tx_irq_status = 0x0a20,
87 .pdma = {
88 .rx_ptr = 0x0900,
89 .rx_cnt_cfg = 0x0904,
90 .pcrx_ptr = 0x0908,
91 .glo_cfg = 0x0a04,
92 .rst_idx = 0x0a08,
93 .delay_irq = 0x0a0c,
94 .irq_status = 0x0a20,
95 .irq_mask = 0x0a28,
96 .int_grp = 0x0a50,
97 },
98 };
99
100 static const struct mtk_reg_map mt7986_reg_map = {
101 .tx_irq_mask = 0x461c,
102 .tx_irq_status = 0x4618,
103 .pdma = {
104 .rx_ptr = 0x6100,
105 .rx_cnt_cfg = 0x6104,
106 .pcrx_ptr = 0x6108,
107 .glo_cfg = 0x6204,
108 .rst_idx = 0x6208,
109 .delay_irq = 0x620c,
110 .irq_status = 0x6220,
111 .irq_mask = 0x6228,
112 .int_grp = 0x6250,
113 },
114 .qdma = {
115 .qtx_cfg = 0x4400,
116 .rx_ptr = 0x4500,
117 .rx_cnt_cfg = 0x4504,
118 .qcrx_ptr = 0x4508,
119 .glo_cfg = 0x4604,
120 .rst_idx = 0x4608,
121 .delay_irq = 0x460c,
122 .fc_th = 0x4610,
123 .int_grp = 0x4620,
124 .hred = 0x4644,
125 .ctx_ptr = 0x4700,
126 .dtx_ptr = 0x4704,
127 .crx_ptr = 0x4710,
128 .drx_ptr = 0x4714,
129 .fq_head = 0x4720,
130 .fq_tail = 0x4724,
131 .fq_count = 0x4728,
132 .fq_blen = 0x472c,
133 },
134 .gdm1_cnt = 0x1c00,
135 .gdma_to_ppe = 0x3333,
136 .ppe_base = 0x2000,
137 .wdma_base = {
138 [0] = 0x4800,
139 [1] = 0x4c00,
140 },
141 };
142
143 /* strings used by ethtool */
144 static const struct mtk_ethtool_stats {
145 char str[ETH_GSTRING_LEN];
146 u32 offset;
147 } mtk_ethtool_stats[] = {
148 MTK_ETHTOOL_STAT(tx_bytes),
149 MTK_ETHTOOL_STAT(tx_packets),
150 MTK_ETHTOOL_STAT(tx_skip),
151 MTK_ETHTOOL_STAT(tx_collisions),
152 MTK_ETHTOOL_STAT(rx_bytes),
153 MTK_ETHTOOL_STAT(rx_packets),
154 MTK_ETHTOOL_STAT(rx_overflow),
155 MTK_ETHTOOL_STAT(rx_fcs_errors),
156 MTK_ETHTOOL_STAT(rx_short_errors),
157 MTK_ETHTOOL_STAT(rx_long_errors),
158 MTK_ETHTOOL_STAT(rx_checksum_errors),
159 MTK_ETHTOOL_STAT(rx_flow_control_packets),
160 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
161 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
162 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
163 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
164 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
165 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
166 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
167 };
168
169 static const char * const mtk_clks_source_name[] = {
170 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
171 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
172 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
173 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
174 };
175
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)176 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
177 {
178 __raw_writel(val, eth->base + reg);
179 }
180
mtk_r32(struct mtk_eth * eth,unsigned reg)181 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
182 {
183 return __raw_readl(eth->base + reg);
184 }
185
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned reg)186 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
187 {
188 u32 val;
189
190 val = mtk_r32(eth, reg);
191 val &= ~mask;
192 val |= set;
193 mtk_w32(eth, val, reg);
194 return reg;
195 }
196
mtk_mdio_busy_wait(struct mtk_eth * eth)197 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
198 {
199 unsigned long t_start = jiffies;
200
201 while (1) {
202 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
203 return 0;
204 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
205 break;
206 cond_resched();
207 }
208
209 dev_err(eth->dev, "mdio: MDIO timeout\n");
210 return -ETIMEDOUT;
211 }
212
_mtk_mdio_write(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg,u32 write_data)213 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
214 u32 write_data)
215 {
216 int ret;
217
218 ret = mtk_mdio_busy_wait(eth);
219 if (ret < 0)
220 return ret;
221
222 if (phy_reg & MII_ADDR_C45) {
223 mtk_w32(eth, PHY_IAC_ACCESS |
224 PHY_IAC_START_C45 |
225 PHY_IAC_CMD_C45_ADDR |
226 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
227 PHY_IAC_ADDR(phy_addr) |
228 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
229 MTK_PHY_IAC);
230
231 ret = mtk_mdio_busy_wait(eth);
232 if (ret < 0)
233 return ret;
234
235 mtk_w32(eth, PHY_IAC_ACCESS |
236 PHY_IAC_START_C45 |
237 PHY_IAC_CMD_WRITE |
238 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
239 PHY_IAC_ADDR(phy_addr) |
240 PHY_IAC_DATA(write_data),
241 MTK_PHY_IAC);
242 } else {
243 mtk_w32(eth, PHY_IAC_ACCESS |
244 PHY_IAC_START_C22 |
245 PHY_IAC_CMD_WRITE |
246 PHY_IAC_REG(phy_reg) |
247 PHY_IAC_ADDR(phy_addr) |
248 PHY_IAC_DATA(write_data),
249 MTK_PHY_IAC);
250 }
251
252 ret = mtk_mdio_busy_wait(eth);
253 if (ret < 0)
254 return ret;
255
256 return 0;
257 }
258
_mtk_mdio_read(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg)259 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
260 {
261 int ret;
262
263 ret = mtk_mdio_busy_wait(eth);
264 if (ret < 0)
265 return ret;
266
267 if (phy_reg & MII_ADDR_C45) {
268 mtk_w32(eth, PHY_IAC_ACCESS |
269 PHY_IAC_START_C45 |
270 PHY_IAC_CMD_C45_ADDR |
271 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
272 PHY_IAC_ADDR(phy_addr) |
273 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
274 MTK_PHY_IAC);
275
276 ret = mtk_mdio_busy_wait(eth);
277 if (ret < 0)
278 return ret;
279
280 mtk_w32(eth, PHY_IAC_ACCESS |
281 PHY_IAC_START_C45 |
282 PHY_IAC_CMD_C45_READ |
283 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
284 PHY_IAC_ADDR(phy_addr),
285 MTK_PHY_IAC);
286 } else {
287 mtk_w32(eth, PHY_IAC_ACCESS |
288 PHY_IAC_START_C22 |
289 PHY_IAC_CMD_C22_READ |
290 PHY_IAC_REG(phy_reg) |
291 PHY_IAC_ADDR(phy_addr),
292 MTK_PHY_IAC);
293 }
294
295 ret = mtk_mdio_busy_wait(eth);
296 if (ret < 0)
297 return ret;
298
299 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
300 }
301
mtk_mdio_write(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)302 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
303 int phy_reg, u16 val)
304 {
305 struct mtk_eth *eth = bus->priv;
306
307 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
308 }
309
mtk_mdio_read(struct mii_bus * bus,int phy_addr,int phy_reg)310 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
311 {
312 struct mtk_eth *eth = bus->priv;
313
314 return _mtk_mdio_read(eth, phy_addr, phy_reg);
315 }
316
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)317 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
318 phy_interface_t interface)
319 {
320 u32 val;
321
322 /* Check DDR memory type.
323 * Currently TRGMII mode with DDR2 memory is not supported.
324 */
325 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
326 if (interface == PHY_INTERFACE_MODE_TRGMII &&
327 val & SYSCFG_DRAM_TYPE_DDR2) {
328 dev_err(eth->dev,
329 "TRGMII mode with DDR2 memory is not supported!\n");
330 return -EOPNOTSUPP;
331 }
332
333 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
334 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
335
336 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
337 ETHSYS_TRGMII_MT7621_MASK, val);
338
339 return 0;
340 }
341
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface,int speed)342 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
343 phy_interface_t interface, int speed)
344 {
345 u32 val;
346 int ret;
347
348 if (interface == PHY_INTERFACE_MODE_TRGMII) {
349 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
350 val = 500000000;
351 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
352 if (ret)
353 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
354 return;
355 }
356
357 val = (speed == SPEED_1000) ?
358 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
359 mtk_w32(eth, val, INTF_MODE);
360
361 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
362 ETHSYS_TRGMII_CLK_SEL362_5,
363 ETHSYS_TRGMII_CLK_SEL362_5);
364
365 val = (speed == SPEED_1000) ? 250000000 : 500000000;
366 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
367 if (ret)
368 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
369
370 val = (speed == SPEED_1000) ?
371 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
372 mtk_w32(eth, val, TRGMII_RCK_CTRL);
373
374 val = (speed == SPEED_1000) ?
375 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
376 mtk_w32(eth, val, TRGMII_TCK_CTRL);
377 }
378
mtk_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)379 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
380 phy_interface_t interface)
381 {
382 struct mtk_mac *mac = container_of(config, struct mtk_mac,
383 phylink_config);
384 struct mtk_eth *eth = mac->hw;
385 unsigned int sid;
386
387 if (interface == PHY_INTERFACE_MODE_SGMII ||
388 phy_interface_mode_is_8023z(interface)) {
389 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
390 0 : mac->id;
391
392 return mtk_sgmii_select_pcs(eth->sgmii, sid);
393 }
394
395 return NULL;
396 }
397
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)398 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
399 const struct phylink_link_state *state)
400 {
401 struct mtk_mac *mac = container_of(config, struct mtk_mac,
402 phylink_config);
403 struct mtk_eth *eth = mac->hw;
404 int val, ge_mode, err = 0;
405 u32 i;
406
407 /* MT76x8 has no hardware settings between for the MAC */
408 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
409 mac->interface != state->interface) {
410 /* Setup soc pin functions */
411 switch (state->interface) {
412 case PHY_INTERFACE_MODE_TRGMII:
413 if (mac->id)
414 goto err_phy;
415 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
416 MTK_GMAC1_TRGMII))
417 goto err_phy;
418 fallthrough;
419 case PHY_INTERFACE_MODE_RGMII_TXID:
420 case PHY_INTERFACE_MODE_RGMII_RXID:
421 case PHY_INTERFACE_MODE_RGMII_ID:
422 case PHY_INTERFACE_MODE_RGMII:
423 case PHY_INTERFACE_MODE_MII:
424 case PHY_INTERFACE_MODE_REVMII:
425 case PHY_INTERFACE_MODE_RMII:
426 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
427 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
428 if (err)
429 goto init_err;
430 }
431 break;
432 case PHY_INTERFACE_MODE_1000BASEX:
433 case PHY_INTERFACE_MODE_2500BASEX:
434 case PHY_INTERFACE_MODE_SGMII:
435 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
436 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
437 if (err)
438 goto init_err;
439 }
440 break;
441 case PHY_INTERFACE_MODE_GMII:
442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
443 err = mtk_gmac_gephy_path_setup(eth, mac->id);
444 if (err)
445 goto init_err;
446 }
447 break;
448 default:
449 goto err_phy;
450 }
451
452 /* Setup clock for 1st gmac */
453 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
454 !phy_interface_mode_is_8023z(state->interface) &&
455 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
456 if (MTK_HAS_CAPS(mac->hw->soc->caps,
457 MTK_TRGMII_MT7621_CLK)) {
458 if (mt7621_gmac0_rgmii_adjust(mac->hw,
459 state->interface))
460 goto err_phy;
461 } else {
462 /* FIXME: this is incorrect. Not only does it
463 * use state->speed (which is not guaranteed
464 * to be correct) but it also makes use of it
465 * in a code path that will only be reachable
466 * when the PHY interface mode changes, not
467 * when the speed changes. Consequently, RGMII
468 * is probably broken.
469 */
470 mtk_gmac0_rgmii_adjust(mac->hw,
471 state->interface,
472 state->speed);
473
474 /* mt7623_pad_clk_setup */
475 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
476 mtk_w32(mac->hw,
477 TD_DM_DRVP(8) | TD_DM_DRVN(8),
478 TRGMII_TD_ODT(i));
479
480 /* Assert/release MT7623 RXC reset */
481 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
482 TRGMII_RCK_CTRL);
483 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
484 }
485 }
486
487 ge_mode = 0;
488 switch (state->interface) {
489 case PHY_INTERFACE_MODE_MII:
490 case PHY_INTERFACE_MODE_GMII:
491 ge_mode = 1;
492 break;
493 case PHY_INTERFACE_MODE_REVMII:
494 ge_mode = 2;
495 break;
496 case PHY_INTERFACE_MODE_RMII:
497 if (mac->id)
498 goto err_phy;
499 ge_mode = 3;
500 break;
501 default:
502 break;
503 }
504
505 /* put the gmac into the right mode */
506 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
507 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
508 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
509 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
510
511 mac->interface = state->interface;
512 }
513
514 /* SGMII */
515 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
516 phy_interface_mode_is_8023z(state->interface)) {
517 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
518 * being setup done.
519 */
520 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
521
522 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
523 SYSCFG0_SGMII_MASK,
524 ~(u32)SYSCFG0_SGMII_MASK);
525
526 /* Save the syscfg0 value for mac_finish */
527 mac->syscfg0 = val;
528 } else if (phylink_autoneg_inband(mode)) {
529 dev_err(eth->dev,
530 "In-band mode not supported in non SGMII mode!\n");
531 return;
532 }
533
534 return;
535
536 err_phy:
537 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
538 mac->id, phy_modes(state->interface));
539 return;
540
541 init_err:
542 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
543 mac->id, phy_modes(state->interface), err);
544 }
545
mtk_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)546 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
547 phy_interface_t interface)
548 {
549 struct mtk_mac *mac = container_of(config, struct mtk_mac,
550 phylink_config);
551 struct mtk_eth *eth = mac->hw;
552 u32 mcr_cur, mcr_new;
553
554 /* Enable SGMII */
555 if (interface == PHY_INTERFACE_MODE_SGMII ||
556 phy_interface_mode_is_8023z(interface))
557 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
558 SYSCFG0_SGMII_MASK, mac->syscfg0);
559
560 /* Setup gmac */
561 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
562 mcr_new = mcr_cur;
563 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
564 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK |
565 MAC_MCR_RX_FIFO_CLR_DIS;
566
567 /* Only update control register when needed! */
568 if (mcr_new != mcr_cur)
569 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
570
571 return 0;
572 }
573
mtk_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)574 static void mtk_mac_pcs_get_state(struct phylink_config *config,
575 struct phylink_link_state *state)
576 {
577 struct mtk_mac *mac = container_of(config, struct mtk_mac,
578 phylink_config);
579 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
580
581 state->link = (pmsr & MAC_MSR_LINK);
582 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
583
584 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
585 case 0:
586 state->speed = SPEED_10;
587 break;
588 case MAC_MSR_SPEED_100:
589 state->speed = SPEED_100;
590 break;
591 case MAC_MSR_SPEED_1000:
592 state->speed = SPEED_1000;
593 break;
594 default:
595 state->speed = SPEED_UNKNOWN;
596 break;
597 }
598
599 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
600 if (pmsr & MAC_MSR_RX_FC)
601 state->pause |= MLO_PAUSE_RX;
602 if (pmsr & MAC_MSR_TX_FC)
603 state->pause |= MLO_PAUSE_TX;
604 }
605
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)606 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
607 phy_interface_t interface)
608 {
609 struct mtk_mac *mac = container_of(config, struct mtk_mac,
610 phylink_config);
611 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
612
613 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
614 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
615 }
616
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)617 static void mtk_mac_link_up(struct phylink_config *config,
618 struct phy_device *phy,
619 unsigned int mode, phy_interface_t interface,
620 int speed, int duplex, bool tx_pause, bool rx_pause)
621 {
622 struct mtk_mac *mac = container_of(config, struct mtk_mac,
623 phylink_config);
624 u32 mcr;
625
626 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
627 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
628 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
629 MAC_MCR_FORCE_RX_FC);
630
631 /* Configure speed */
632 switch (speed) {
633 case SPEED_2500:
634 case SPEED_1000:
635 mcr |= MAC_MCR_SPEED_1000;
636 break;
637 case SPEED_100:
638 mcr |= MAC_MCR_SPEED_100;
639 break;
640 }
641
642 /* Configure duplex */
643 if (duplex == DUPLEX_FULL)
644 mcr |= MAC_MCR_FORCE_DPX;
645
646 /* Configure pause modes - phylink will avoid these for half duplex */
647 if (tx_pause)
648 mcr |= MAC_MCR_FORCE_TX_FC;
649 if (rx_pause)
650 mcr |= MAC_MCR_FORCE_RX_FC;
651
652 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
653 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
654 }
655
656 static const struct phylink_mac_ops mtk_phylink_ops = {
657 .validate = phylink_generic_validate,
658 .mac_select_pcs = mtk_mac_select_pcs,
659 .mac_pcs_get_state = mtk_mac_pcs_get_state,
660 .mac_config = mtk_mac_config,
661 .mac_finish = mtk_mac_finish,
662 .mac_link_down = mtk_mac_link_down,
663 .mac_link_up = mtk_mac_link_up,
664 };
665
mtk_mdio_init(struct mtk_eth * eth)666 static int mtk_mdio_init(struct mtk_eth *eth)
667 {
668 struct device_node *mii_np;
669 int ret;
670
671 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
672 if (!mii_np) {
673 dev_err(eth->dev, "no %s child node found", "mdio-bus");
674 return -ENODEV;
675 }
676
677 if (!of_device_is_available(mii_np)) {
678 ret = -ENODEV;
679 goto err_put_node;
680 }
681
682 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
683 if (!eth->mii_bus) {
684 ret = -ENOMEM;
685 goto err_put_node;
686 }
687
688 eth->mii_bus->name = "mdio";
689 eth->mii_bus->read = mtk_mdio_read;
690 eth->mii_bus->write = mtk_mdio_write;
691 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
692 eth->mii_bus->priv = eth;
693 eth->mii_bus->parent = eth->dev;
694
695 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
696 ret = of_mdiobus_register(eth->mii_bus, mii_np);
697
698 err_put_node:
699 of_node_put(mii_np);
700 return ret;
701 }
702
mtk_mdio_cleanup(struct mtk_eth * eth)703 static void mtk_mdio_cleanup(struct mtk_eth *eth)
704 {
705 if (!eth->mii_bus)
706 return;
707
708 mdiobus_unregister(eth->mii_bus);
709 }
710
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)711 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
712 {
713 unsigned long flags;
714 u32 val;
715
716 spin_lock_irqsave(ð->tx_irq_lock, flags);
717 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
718 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
719 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
720 }
721
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)722 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
723 {
724 unsigned long flags;
725 u32 val;
726
727 spin_lock_irqsave(ð->tx_irq_lock, flags);
728 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
729 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
730 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
731 }
732
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)733 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
734 {
735 unsigned long flags;
736 u32 val;
737
738 spin_lock_irqsave(ð->rx_irq_lock, flags);
739 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
740 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
741 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
742 }
743
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)744 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
745 {
746 unsigned long flags;
747 u32 val;
748
749 spin_lock_irqsave(ð->rx_irq_lock, flags);
750 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
751 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
752 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
753 }
754
mtk_set_mac_address(struct net_device * dev,void * p)755 static int mtk_set_mac_address(struct net_device *dev, void *p)
756 {
757 int ret = eth_mac_addr(dev, p);
758 struct mtk_mac *mac = netdev_priv(dev);
759 struct mtk_eth *eth = mac->hw;
760 const char *macaddr = dev->dev_addr;
761
762 if (ret)
763 return ret;
764
765 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
766 return -EBUSY;
767
768 spin_lock_bh(&mac->hw->page_lock);
769 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
770 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
771 MT7628_SDM_MAC_ADRH);
772 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
773 (macaddr[4] << 8) | macaddr[5],
774 MT7628_SDM_MAC_ADRL);
775 } else {
776 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
777 MTK_GDMA_MAC_ADRH(mac->id));
778 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
779 (macaddr[4] << 8) | macaddr[5],
780 MTK_GDMA_MAC_ADRL(mac->id));
781 }
782 spin_unlock_bh(&mac->hw->page_lock);
783
784 return 0;
785 }
786
mtk_stats_update_mac(struct mtk_mac * mac)787 void mtk_stats_update_mac(struct mtk_mac *mac)
788 {
789 struct mtk_hw_stats *hw_stats = mac->hw_stats;
790 struct mtk_eth *eth = mac->hw;
791
792 u64_stats_update_begin(&hw_stats->syncp);
793
794 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
795 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
796 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
797 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
798 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
799 hw_stats->rx_checksum_errors +=
800 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
801 } else {
802 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
803 unsigned int offs = hw_stats->reg_offset;
804 u64 stats;
805
806 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
807 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
808 if (stats)
809 hw_stats->rx_bytes += (stats << 32);
810 hw_stats->rx_packets +=
811 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
812 hw_stats->rx_overflow +=
813 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
814 hw_stats->rx_fcs_errors +=
815 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
816 hw_stats->rx_short_errors +=
817 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
818 hw_stats->rx_long_errors +=
819 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
820 hw_stats->rx_checksum_errors +=
821 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
822 hw_stats->rx_flow_control_packets +=
823 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
824 hw_stats->tx_skip +=
825 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
826 hw_stats->tx_collisions +=
827 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
828 hw_stats->tx_bytes +=
829 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
830 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
831 if (stats)
832 hw_stats->tx_bytes += (stats << 32);
833 hw_stats->tx_packets +=
834 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
835 }
836
837 u64_stats_update_end(&hw_stats->syncp);
838 }
839
mtk_stats_update(struct mtk_eth * eth)840 static void mtk_stats_update(struct mtk_eth *eth)
841 {
842 int i;
843
844 for (i = 0; i < MTK_MAC_COUNT; i++) {
845 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
846 continue;
847 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
848 mtk_stats_update_mac(eth->mac[i]);
849 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
850 }
851 }
852 }
853
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)854 static void mtk_get_stats64(struct net_device *dev,
855 struct rtnl_link_stats64 *storage)
856 {
857 struct mtk_mac *mac = netdev_priv(dev);
858 struct mtk_hw_stats *hw_stats = mac->hw_stats;
859 unsigned int start;
860
861 if (netif_running(dev) && netif_device_present(dev)) {
862 if (spin_trylock_bh(&hw_stats->stats_lock)) {
863 mtk_stats_update_mac(mac);
864 spin_unlock_bh(&hw_stats->stats_lock);
865 }
866 }
867
868 do {
869 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
870 storage->rx_packets = hw_stats->rx_packets;
871 storage->tx_packets = hw_stats->tx_packets;
872 storage->rx_bytes = hw_stats->rx_bytes;
873 storage->tx_bytes = hw_stats->tx_bytes;
874 storage->collisions = hw_stats->tx_collisions;
875 storage->rx_length_errors = hw_stats->rx_short_errors +
876 hw_stats->rx_long_errors;
877 storage->rx_over_errors = hw_stats->rx_overflow;
878 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
879 storage->rx_errors = hw_stats->rx_checksum_errors;
880 storage->tx_aborted_errors = hw_stats->tx_skip;
881 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
882
883 storage->tx_errors = dev->stats.tx_errors;
884 storage->rx_dropped = dev->stats.rx_dropped;
885 storage->tx_dropped = dev->stats.tx_dropped;
886 }
887
mtk_max_frag_size(int mtu)888 static inline int mtk_max_frag_size(int mtu)
889 {
890 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
891 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
892 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
893
894 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
895 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
896 }
897
mtk_max_buf_size(int frag_size)898 static inline int mtk_max_buf_size(int frag_size)
899 {
900 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
901 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
902
903 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
904
905 return buf_size;
906 }
907
mtk_rx_get_desc(struct mtk_eth * eth,struct mtk_rx_dma_v2 * rxd,struct mtk_rx_dma_v2 * dma_rxd)908 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
909 struct mtk_rx_dma_v2 *dma_rxd)
910 {
911 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
912 if (!(rxd->rxd2 & RX_DMA_DONE))
913 return false;
914
915 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
916 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
917 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
918 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
919 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
920 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
921 }
922
923 return true;
924 }
925
mtk_max_lro_buf_alloc(gfp_t gfp_mask)926 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
927 {
928 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
929 unsigned long data;
930
931 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
932 get_order(size));
933
934 return (void *)data;
935 }
936
937 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)938 static int mtk_init_fq_dma(struct mtk_eth *eth)
939 {
940 const struct mtk_soc_data *soc = eth->soc;
941 dma_addr_t phy_ring_tail;
942 int cnt = MTK_DMA_SIZE;
943 dma_addr_t dma_addr;
944 int i;
945
946 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
947 cnt * soc->txrx.txd_size,
948 ð->phy_scratch_ring,
949 GFP_KERNEL);
950 if (unlikely(!eth->scratch_ring))
951 return -ENOMEM;
952
953 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
954 if (unlikely(!eth->scratch_head))
955 return -ENOMEM;
956
957 dma_addr = dma_map_single(eth->dma_dev,
958 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
959 DMA_FROM_DEVICE);
960 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
961 return -ENOMEM;
962
963 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
964
965 for (i = 0; i < cnt; i++) {
966 struct mtk_tx_dma_v2 *txd;
967
968 txd = eth->scratch_ring + i * soc->txrx.txd_size;
969 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
970 if (i < cnt - 1)
971 txd->txd2 = eth->phy_scratch_ring +
972 (i + 1) * soc->txrx.txd_size;
973
974 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
975 txd->txd4 = 0;
976 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
977 txd->txd5 = 0;
978 txd->txd6 = 0;
979 txd->txd7 = 0;
980 txd->txd8 = 0;
981 }
982 }
983
984 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
985 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
986 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
987 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
988
989 return 0;
990 }
991
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)992 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
993 {
994 return ring->dma + (desc - ring->phys);
995 }
996
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,void * txd,u32 txd_size)997 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
998 void *txd, u32 txd_size)
999 {
1000 int idx = (txd - ring->dma) / txd_size;
1001
1002 return &ring->buf[idx];
1003 }
1004
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)1005 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1006 struct mtk_tx_dma *dma)
1007 {
1008 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1009 }
1010
txd_to_idx(struct mtk_tx_ring * ring,void * dma,u32 txd_size)1011 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1012 {
1013 return (dma - ring->dma) / txd_size;
1014 }
1015
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct xdp_frame_bulk * bq,bool napi)1016 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1017 struct xdp_frame_bulk *bq, bool napi)
1018 {
1019 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1020 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1021 dma_unmap_single(eth->dma_dev,
1022 dma_unmap_addr(tx_buf, dma_addr0),
1023 dma_unmap_len(tx_buf, dma_len0),
1024 DMA_TO_DEVICE);
1025 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1026 dma_unmap_page(eth->dma_dev,
1027 dma_unmap_addr(tx_buf, dma_addr0),
1028 dma_unmap_len(tx_buf, dma_len0),
1029 DMA_TO_DEVICE);
1030 }
1031 } else {
1032 if (dma_unmap_len(tx_buf, dma_len0)) {
1033 dma_unmap_page(eth->dma_dev,
1034 dma_unmap_addr(tx_buf, dma_addr0),
1035 dma_unmap_len(tx_buf, dma_len0),
1036 DMA_TO_DEVICE);
1037 }
1038
1039 if (dma_unmap_len(tx_buf, dma_len1)) {
1040 dma_unmap_page(eth->dma_dev,
1041 dma_unmap_addr(tx_buf, dma_addr1),
1042 dma_unmap_len(tx_buf, dma_len1),
1043 DMA_TO_DEVICE);
1044 }
1045 }
1046
1047 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1048 if (tx_buf->type == MTK_TYPE_SKB) {
1049 struct sk_buff *skb = tx_buf->data;
1050
1051 if (napi)
1052 napi_consume_skb(skb, napi);
1053 else
1054 dev_kfree_skb_any(skb);
1055 } else {
1056 struct xdp_frame *xdpf = tx_buf->data;
1057
1058 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1059 xdp_return_frame_rx_napi(xdpf);
1060 else if (bq)
1061 xdp_return_frame_bulk(xdpf, bq);
1062 else
1063 xdp_return_frame(xdpf);
1064 }
1065 }
1066 tx_buf->flags = 0;
1067 tx_buf->data = NULL;
1068 }
1069
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)1070 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1071 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1072 size_t size, int idx)
1073 {
1074 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1075 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1076 dma_unmap_len_set(tx_buf, dma_len0, size);
1077 } else {
1078 if (idx & 1) {
1079 txd->txd3 = mapped_addr;
1080 txd->txd2 |= TX_DMA_PLEN1(size);
1081 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1082 dma_unmap_len_set(tx_buf, dma_len1, size);
1083 } else {
1084 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1085 txd->txd1 = mapped_addr;
1086 txd->txd2 = TX_DMA_PLEN0(size);
1087 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1088 dma_unmap_len_set(tx_buf, dma_len0, size);
1089 }
1090 }
1091 }
1092
mtk_tx_set_dma_desc_v1(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1093 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1094 struct mtk_tx_dma_desc_info *info)
1095 {
1096 struct mtk_mac *mac = netdev_priv(dev);
1097 struct mtk_eth *eth = mac->hw;
1098 struct mtk_tx_dma *desc = txd;
1099 u32 data;
1100
1101 WRITE_ONCE(desc->txd1, info->addr);
1102
1103 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size);
1104 if (info->last)
1105 data |= TX_DMA_LS0;
1106 WRITE_ONCE(desc->txd3, data);
1107
1108 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1109 if (info->first) {
1110 if (info->gso)
1111 data |= TX_DMA_TSO;
1112 /* tx checksum offload */
1113 if (info->csum)
1114 data |= TX_DMA_CHKSUM;
1115 /* vlan header offload */
1116 if (info->vlan)
1117 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1118 }
1119 WRITE_ONCE(desc->txd4, data);
1120 }
1121
mtk_tx_set_dma_desc_v2(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1122 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1123 struct mtk_tx_dma_desc_info *info)
1124 {
1125 struct mtk_mac *mac = netdev_priv(dev);
1126 struct mtk_tx_dma_v2 *desc = txd;
1127 struct mtk_eth *eth = mac->hw;
1128 u32 data;
1129
1130 WRITE_ONCE(desc->txd1, info->addr);
1131
1132 data = TX_DMA_PLEN0(info->size);
1133 if (info->last)
1134 data |= TX_DMA_LS0;
1135 WRITE_ONCE(desc->txd3, data);
1136
1137 if (!info->qid && mac->id)
1138 info->qid = MTK_QDMA_GMAC2_QID;
1139
1140 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
1141 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1142 WRITE_ONCE(desc->txd4, data);
1143
1144 data = 0;
1145 if (info->first) {
1146 if (info->gso)
1147 data |= TX_DMA_TSO_V2;
1148 /* tx checksum offload */
1149 if (info->csum)
1150 data |= TX_DMA_CHKSUM_V2;
1151 }
1152 WRITE_ONCE(desc->txd5, data);
1153
1154 data = 0;
1155 if (info->first && info->vlan)
1156 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1157 WRITE_ONCE(desc->txd6, data);
1158
1159 WRITE_ONCE(desc->txd7, 0);
1160 WRITE_ONCE(desc->txd8, 0);
1161 }
1162
mtk_tx_set_dma_desc(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1163 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1164 struct mtk_tx_dma_desc_info *info)
1165 {
1166 struct mtk_mac *mac = netdev_priv(dev);
1167 struct mtk_eth *eth = mac->hw;
1168
1169 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1170 mtk_tx_set_dma_desc_v2(dev, txd, info);
1171 else
1172 mtk_tx_set_dma_desc_v1(dev, txd, info);
1173 }
1174
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)1175 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1176 int tx_num, struct mtk_tx_ring *ring, bool gso)
1177 {
1178 struct mtk_tx_dma_desc_info txd_info = {
1179 .size = skb_headlen(skb),
1180 .gso = gso,
1181 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1182 .vlan = skb_vlan_tag_present(skb),
1183 .qid = skb->mark & MTK_QDMA_TX_MASK,
1184 .vlan_tci = skb_vlan_tag_get(skb),
1185 .first = true,
1186 .last = !skb_is_nonlinear(skb),
1187 };
1188 struct mtk_mac *mac = netdev_priv(dev);
1189 struct mtk_eth *eth = mac->hw;
1190 const struct mtk_soc_data *soc = eth->soc;
1191 struct mtk_tx_dma *itxd, *txd;
1192 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1193 struct mtk_tx_buf *itx_buf, *tx_buf;
1194 int i, n_desc = 1;
1195 int k = 0;
1196
1197 itxd = ring->next_free;
1198 itxd_pdma = qdma_to_pdma(ring, itxd);
1199 if (itxd == ring->last_free)
1200 return -ENOMEM;
1201
1202 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1203 memset(itx_buf, 0, sizeof(*itx_buf));
1204
1205 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1206 DMA_TO_DEVICE);
1207 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1208 return -ENOMEM;
1209
1210 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1211
1212 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1213 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1214 MTK_TX_FLAGS_FPORT1;
1215 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1216 k++);
1217
1218 /* TX SG offload */
1219 txd = itxd;
1220 txd_pdma = qdma_to_pdma(ring, txd);
1221
1222 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1223 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1224 unsigned int offset = 0;
1225 int frag_size = skb_frag_size(frag);
1226
1227 while (frag_size) {
1228 bool new_desc = true;
1229
1230 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1231 (i & 0x1)) {
1232 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1233 txd_pdma = qdma_to_pdma(ring, txd);
1234 if (txd == ring->last_free)
1235 goto err_dma;
1236
1237 n_desc++;
1238 } else {
1239 new_desc = false;
1240 }
1241
1242 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1243 txd_info.size = min_t(unsigned int, frag_size,
1244 soc->txrx.dma_max_len);
1245 txd_info.qid = skb->mark & MTK_QDMA_TX_MASK;
1246 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1247 !(frag_size - txd_info.size);
1248 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1249 offset, txd_info.size,
1250 DMA_TO_DEVICE);
1251 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1252 goto err_dma;
1253
1254 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1255
1256 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1257 soc->txrx.txd_size);
1258 if (new_desc)
1259 memset(tx_buf, 0, sizeof(*tx_buf));
1260 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1261 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1262 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1263 MTK_TX_FLAGS_FPORT1;
1264
1265 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1266 txd_info.size, k++);
1267
1268 frag_size -= txd_info.size;
1269 offset += txd_info.size;
1270 }
1271 }
1272
1273 /* store skb to cleanup */
1274 itx_buf->type = MTK_TYPE_SKB;
1275 itx_buf->data = skb;
1276
1277 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1278 if (k & 0x1)
1279 txd_pdma->txd2 |= TX_DMA_LS0;
1280 else
1281 txd_pdma->txd2 |= TX_DMA_LS1;
1282 }
1283
1284 netdev_sent_queue(dev, skb->len);
1285 skb_tx_timestamp(skb);
1286
1287 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1288 atomic_sub(n_desc, &ring->free_count);
1289
1290 /* make sure that all changes to the dma ring are flushed before we
1291 * continue
1292 */
1293 wmb();
1294
1295 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1296 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1297 !netdev_xmit_more())
1298 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1299 } else {
1300 int next_idx;
1301
1302 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
1303 ring->dma_size);
1304 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1305 }
1306
1307 return 0;
1308
1309 err_dma:
1310 do {
1311 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1312
1313 /* unmap dma */
1314 mtk_tx_unmap(eth, tx_buf, NULL, false);
1315
1316 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1317 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1318 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1319
1320 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1321 itxd_pdma = qdma_to_pdma(ring, itxd);
1322 } while (itxd != txd);
1323
1324 return -ENOMEM;
1325 }
1326
mtk_cal_txd_req(struct mtk_eth * eth,struct sk_buff * skb)1327 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1328 {
1329 int i, nfrags = 1;
1330 skb_frag_t *frag;
1331
1332 if (skb_is_gso(skb)) {
1333 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1334 frag = &skb_shinfo(skb)->frags[i];
1335 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1336 eth->soc->txrx.dma_max_len);
1337 }
1338 } else {
1339 nfrags += skb_shinfo(skb)->nr_frags;
1340 }
1341
1342 return nfrags;
1343 }
1344
mtk_queue_stopped(struct mtk_eth * eth)1345 static int mtk_queue_stopped(struct mtk_eth *eth)
1346 {
1347 int i;
1348
1349 for (i = 0; i < MTK_MAC_COUNT; i++) {
1350 if (!eth->netdev[i])
1351 continue;
1352 if (netif_queue_stopped(eth->netdev[i]))
1353 return 1;
1354 }
1355
1356 return 0;
1357 }
1358
mtk_wake_queue(struct mtk_eth * eth)1359 static void mtk_wake_queue(struct mtk_eth *eth)
1360 {
1361 int i;
1362
1363 for (i = 0; i < MTK_MAC_COUNT; i++) {
1364 if (!eth->netdev[i])
1365 continue;
1366 netif_wake_queue(eth->netdev[i]);
1367 }
1368 }
1369
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1370 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1371 {
1372 struct mtk_mac *mac = netdev_priv(dev);
1373 struct mtk_eth *eth = mac->hw;
1374 struct mtk_tx_ring *ring = ð->tx_ring;
1375 struct net_device_stats *stats = &dev->stats;
1376 bool gso = false;
1377 int tx_num;
1378
1379 /* normally we can rely on the stack not calling this more than once,
1380 * however we have 2 queues running on the same ring so we need to lock
1381 * the ring access
1382 */
1383 spin_lock(ð->page_lock);
1384
1385 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1386 goto drop;
1387
1388 tx_num = mtk_cal_txd_req(eth, skb);
1389 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1390 netif_stop_queue(dev);
1391 netif_err(eth, tx_queued, dev,
1392 "Tx Ring full when queue awake!\n");
1393 spin_unlock(ð->page_lock);
1394 return NETDEV_TX_BUSY;
1395 }
1396
1397 /* TSO: fill MSS info in tcp checksum field */
1398 if (skb_is_gso(skb)) {
1399 if (skb_cow_head(skb, 0)) {
1400 netif_warn(eth, tx_err, dev,
1401 "GSO expand head fail.\n");
1402 goto drop;
1403 }
1404
1405 if (skb_shinfo(skb)->gso_type &
1406 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1407 gso = true;
1408 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1409 }
1410 }
1411
1412 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1413 goto drop;
1414
1415 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1416 netif_stop_queue(dev);
1417
1418 spin_unlock(ð->page_lock);
1419
1420 return NETDEV_TX_OK;
1421
1422 drop:
1423 spin_unlock(ð->page_lock);
1424 stats->tx_dropped++;
1425 dev_kfree_skb_any(skb);
1426 return NETDEV_TX_OK;
1427 }
1428
mtk_get_rx_ring(struct mtk_eth * eth)1429 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1430 {
1431 int i;
1432 struct mtk_rx_ring *ring;
1433 int idx;
1434
1435 if (!eth->hwlro)
1436 return ð->rx_ring[0];
1437
1438 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1439 struct mtk_rx_dma *rxd;
1440
1441 ring = ð->rx_ring[i];
1442 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1443 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1444 if (rxd->rxd2 & RX_DMA_DONE) {
1445 ring->calc_idx_update = true;
1446 return ring;
1447 }
1448 }
1449
1450 return NULL;
1451 }
1452
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1453 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1454 {
1455 struct mtk_rx_ring *ring;
1456 int i;
1457
1458 if (!eth->hwlro) {
1459 ring = ð->rx_ring[0];
1460 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1461 } else {
1462 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1463 ring = ð->rx_ring[i];
1464 if (ring->calc_idx_update) {
1465 ring->calc_idx_update = false;
1466 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1467 }
1468 }
1469 }
1470 }
1471
mtk_page_pool_enabled(struct mtk_eth * eth)1472 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1473 {
1474 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
1475 }
1476
mtk_create_page_pool(struct mtk_eth * eth,struct xdp_rxq_info * xdp_q,int id,int size)1477 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1478 struct xdp_rxq_info *xdp_q,
1479 int id, int size)
1480 {
1481 struct page_pool_params pp_params = {
1482 .order = 0,
1483 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1484 .pool_size = size,
1485 .nid = NUMA_NO_NODE,
1486 .dev = eth->dma_dev,
1487 .offset = MTK_PP_HEADROOM,
1488 .max_len = MTK_PP_MAX_BUF_SIZE,
1489 };
1490 struct page_pool *pp;
1491 int err;
1492
1493 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1494 : DMA_FROM_DEVICE;
1495 pp = page_pool_create(&pp_params);
1496 if (IS_ERR(pp))
1497 return pp;
1498
1499 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id,
1500 eth->rx_napi.napi_id, PAGE_SIZE);
1501 if (err < 0)
1502 goto err_free_pp;
1503
1504 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1505 if (err)
1506 goto err_unregister_rxq;
1507
1508 return pp;
1509
1510 err_unregister_rxq:
1511 xdp_rxq_info_unreg(xdp_q);
1512 err_free_pp:
1513 page_pool_destroy(pp);
1514
1515 return ERR_PTR(err);
1516 }
1517
mtk_page_pool_get_buff(struct page_pool * pp,dma_addr_t * dma_addr,gfp_t gfp_mask)1518 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1519 gfp_t gfp_mask)
1520 {
1521 struct page *page;
1522
1523 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1524 if (!page)
1525 return NULL;
1526
1527 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1528 return page_address(page);
1529 }
1530
mtk_rx_put_buff(struct mtk_rx_ring * ring,void * data,bool napi)1531 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1532 {
1533 if (ring->page_pool)
1534 page_pool_put_full_page(ring->page_pool,
1535 virt_to_head_page(data), napi);
1536 else
1537 skb_free_frag(data);
1538 }
1539
mtk_xdp_frame_map(struct mtk_eth * eth,struct net_device * dev,struct mtk_tx_dma_desc_info * txd_info,struct mtk_tx_dma * txd,struct mtk_tx_buf * tx_buf,void * data,u16 headroom,int index,bool dma_map)1540 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1541 struct mtk_tx_dma_desc_info *txd_info,
1542 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1543 void *data, u16 headroom, int index, bool dma_map)
1544 {
1545 struct mtk_tx_ring *ring = ð->tx_ring;
1546 struct mtk_mac *mac = netdev_priv(dev);
1547 struct mtk_tx_dma *txd_pdma;
1548
1549 if (dma_map) { /* ndo_xdp_xmit */
1550 txd_info->addr = dma_map_single(eth->dma_dev, data,
1551 txd_info->size, DMA_TO_DEVICE);
1552 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1553 return -ENOMEM;
1554
1555 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1556 } else {
1557 struct page *page = virt_to_head_page(data);
1558
1559 txd_info->addr = page_pool_get_dma_addr(page) +
1560 sizeof(struct xdp_frame) + headroom;
1561 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1562 txd_info->size, DMA_BIDIRECTIONAL);
1563 }
1564 mtk_tx_set_dma_desc(dev, txd, txd_info);
1565
1566 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1;
1567 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1568 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1569
1570 txd_pdma = qdma_to_pdma(ring, txd);
1571 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1572 index);
1573
1574 return 0;
1575 }
1576
mtk_xdp_submit_frame(struct mtk_eth * eth,struct xdp_frame * xdpf,struct net_device * dev,bool dma_map)1577 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1578 struct net_device *dev, bool dma_map)
1579 {
1580 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1581 const struct mtk_soc_data *soc = eth->soc;
1582 struct mtk_tx_ring *ring = ð->tx_ring;
1583 struct mtk_tx_dma_desc_info txd_info = {
1584 .size = xdpf->len,
1585 .first = true,
1586 .last = !xdp_frame_has_frags(xdpf),
1587 };
1588 int err, index = 0, n_desc = 1, nr_frags;
1589 struct mtk_tx_buf *htx_buf, *tx_buf;
1590 struct mtk_tx_dma *htxd, *txd;
1591 void *data = xdpf->data;
1592
1593 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1594 return -EBUSY;
1595
1596 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1597 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1598 return -EBUSY;
1599
1600 spin_lock(ð->page_lock);
1601
1602 txd = ring->next_free;
1603 if (txd == ring->last_free) {
1604 spin_unlock(ð->page_lock);
1605 return -ENOMEM;
1606 }
1607 htxd = txd;
1608
1609 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
1610 memset(tx_buf, 0, sizeof(*tx_buf));
1611 htx_buf = tx_buf;
1612
1613 for (;;) {
1614 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1615 data, xdpf->headroom, index, dma_map);
1616 if (err < 0)
1617 goto unmap;
1618
1619 if (txd_info.last)
1620 break;
1621
1622 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1623 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1624 if (txd == ring->last_free)
1625 goto unmap;
1626
1627 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1628 soc->txrx.txd_size);
1629 memset(tx_buf, 0, sizeof(*tx_buf));
1630 n_desc++;
1631 }
1632
1633 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1634 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1635 txd_info.last = index + 1 == nr_frags;
1636 data = skb_frag_address(&sinfo->frags[index]);
1637
1638 index++;
1639 }
1640 /* store xdpf for cleanup */
1641 htx_buf->data = xdpf;
1642
1643 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1644 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1645
1646 if (index & 1)
1647 txd_pdma->txd2 |= TX_DMA_LS0;
1648 else
1649 txd_pdma->txd2 |= TX_DMA_LS1;
1650 }
1651
1652 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1653 atomic_sub(n_desc, &ring->free_count);
1654
1655 /* make sure that all changes to the dma ring are flushed before we
1656 * continue
1657 */
1658 wmb();
1659
1660 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1661 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1662 } else {
1663 int idx;
1664
1665 idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
1666 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1667 MT7628_TX_CTX_IDX0);
1668 }
1669
1670 spin_unlock(ð->page_lock);
1671
1672 return 0;
1673
1674 unmap:
1675 while (htxd != txd) {
1676 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
1677 mtk_tx_unmap(eth, tx_buf, NULL, false);
1678
1679 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1680 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1681 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1682
1683 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1684 }
1685
1686 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1687 }
1688
1689 spin_unlock(ð->page_lock);
1690
1691 return err;
1692 }
1693
mtk_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)1694 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1695 struct xdp_frame **frames, u32 flags)
1696 {
1697 struct mtk_mac *mac = netdev_priv(dev);
1698 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1699 struct mtk_eth *eth = mac->hw;
1700 int i, nxmit = 0;
1701
1702 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1703 return -EINVAL;
1704
1705 for (i = 0; i < num_frame; i++) {
1706 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1707 break;
1708 nxmit++;
1709 }
1710
1711 u64_stats_update_begin(&hw_stats->syncp);
1712 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1713 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1714 u64_stats_update_end(&hw_stats->syncp);
1715
1716 return nxmit;
1717 }
1718
mtk_xdp_run(struct mtk_eth * eth,struct mtk_rx_ring * ring,struct xdp_buff * xdp,struct net_device * dev)1719 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1720 struct xdp_buff *xdp, struct net_device *dev)
1721 {
1722 struct mtk_mac *mac = netdev_priv(dev);
1723 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1724 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
1725 struct bpf_prog *prog;
1726 u32 act = XDP_PASS;
1727
1728 rcu_read_lock();
1729
1730 prog = rcu_dereference(eth->prog);
1731 if (!prog)
1732 goto out;
1733
1734 act = bpf_prog_run_xdp(prog, xdp);
1735 switch (act) {
1736 case XDP_PASS:
1737 count = &hw_stats->xdp_stats.rx_xdp_pass;
1738 goto update_stats;
1739 case XDP_REDIRECT:
1740 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1741 act = XDP_DROP;
1742 break;
1743 }
1744
1745 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1746 goto update_stats;
1747 case XDP_TX: {
1748 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1749
1750 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
1751 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1752 act = XDP_DROP;
1753 break;
1754 }
1755
1756 count = &hw_stats->xdp_stats.rx_xdp_tx;
1757 goto update_stats;
1758 }
1759 default:
1760 bpf_warn_invalid_xdp_action(dev, prog, act);
1761 fallthrough;
1762 case XDP_ABORTED:
1763 trace_xdp_exception(dev, prog, act);
1764 fallthrough;
1765 case XDP_DROP:
1766 break;
1767 }
1768
1769 page_pool_put_full_page(ring->page_pool,
1770 virt_to_head_page(xdp->data), true);
1771
1772 update_stats:
1773 u64_stats_update_begin(&hw_stats->syncp);
1774 *count = *count + 1;
1775 u64_stats_update_end(&hw_stats->syncp);
1776 out:
1777 rcu_read_unlock();
1778
1779 return act;
1780 }
1781
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)1782 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1783 struct mtk_eth *eth)
1784 {
1785 struct dim_sample dim_sample = {};
1786 struct mtk_rx_ring *ring;
1787 bool xdp_flush = false;
1788 int idx;
1789 struct sk_buff *skb;
1790 u8 *data, *new_data;
1791 struct mtk_rx_dma_v2 *rxd, trxd;
1792 int done = 0, bytes = 0;
1793
1794 while (done < budget) {
1795 unsigned int pktlen, *rxdcsum;
1796 struct net_device *netdev;
1797 dma_addr_t dma_addr;
1798 u32 hash, reason;
1799 int mac = 0;
1800
1801 ring = mtk_get_rx_ring(eth);
1802 if (unlikely(!ring))
1803 goto rx_done;
1804
1805 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1806 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1807 data = ring->data[idx];
1808
1809 if (!mtk_rx_get_desc(eth, &trxd, rxd))
1810 break;
1811
1812 /* find out which mac the packet come from. values start at 1 */
1813 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1814 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
1815 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
1816 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
1817 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
1818
1819 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1820 !eth->netdev[mac]))
1821 goto release_desc;
1822
1823 netdev = eth->netdev[mac];
1824
1825 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1826 goto release_desc;
1827
1828 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1829
1830 /* alloc new buffer */
1831 if (ring->page_pool) {
1832 struct page *page = virt_to_head_page(data);
1833 struct xdp_buff xdp;
1834 u32 ret;
1835
1836 new_data = mtk_page_pool_get_buff(ring->page_pool,
1837 &dma_addr,
1838 GFP_ATOMIC);
1839 if (unlikely(!new_data)) {
1840 netdev->stats.rx_dropped++;
1841 goto release_desc;
1842 }
1843
1844 dma_sync_single_for_cpu(eth->dma_dev,
1845 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
1846 pktlen, page_pool_get_dma_dir(ring->page_pool));
1847
1848 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
1849 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
1850 false);
1851 xdp_buff_clear_frags_flag(&xdp);
1852
1853 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
1854 if (ret == XDP_REDIRECT)
1855 xdp_flush = true;
1856
1857 if (ret != XDP_PASS)
1858 goto skip_rx;
1859
1860 skb = build_skb(data, PAGE_SIZE);
1861 if (unlikely(!skb)) {
1862 page_pool_put_full_page(ring->page_pool,
1863 page, true);
1864 netdev->stats.rx_dropped++;
1865 goto skip_rx;
1866 }
1867
1868 skb_reserve(skb, xdp.data - xdp.data_hard_start);
1869 skb_put(skb, xdp.data_end - xdp.data);
1870 skb_mark_for_recycle(skb);
1871 } else {
1872 if (ring->frag_size <= PAGE_SIZE)
1873 new_data = napi_alloc_frag(ring->frag_size);
1874 else
1875 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
1876
1877 if (unlikely(!new_data)) {
1878 netdev->stats.rx_dropped++;
1879 goto release_desc;
1880 }
1881
1882 dma_addr = dma_map_single(eth->dma_dev,
1883 new_data + NET_SKB_PAD + eth->ip_align,
1884 ring->buf_size, DMA_FROM_DEVICE);
1885 if (unlikely(dma_mapping_error(eth->dma_dev,
1886 dma_addr))) {
1887 skb_free_frag(new_data);
1888 netdev->stats.rx_dropped++;
1889 goto release_desc;
1890 }
1891
1892 dma_unmap_single(eth->dma_dev, trxd.rxd1,
1893 ring->buf_size, DMA_FROM_DEVICE);
1894
1895 skb = build_skb(data, ring->frag_size);
1896 if (unlikely(!skb)) {
1897 netdev->stats.rx_dropped++;
1898 skb_free_frag(data);
1899 goto skip_rx;
1900 }
1901
1902 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1903 skb_put(skb, pktlen);
1904 }
1905
1906 skb->dev = netdev;
1907 bytes += skb->len;
1908
1909 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
1910 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
1911 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
1912 if (hash != MTK_RXD5_FOE_ENTRY)
1913 skb_set_hash(skb, jhash_1word(hash, 0),
1914 PKT_HASH_TYPE_L4);
1915 rxdcsum = &trxd.rxd3;
1916 } else {
1917 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
1918 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
1919 if (hash != MTK_RXD4_FOE_ENTRY)
1920 skb_set_hash(skb, jhash_1word(hash, 0),
1921 PKT_HASH_TYPE_L4);
1922 rxdcsum = &trxd.rxd4;
1923 }
1924
1925 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
1926 skb->ip_summed = CHECKSUM_UNNECESSARY;
1927 else
1928 skb_checksum_none_assert(skb);
1929 skb->protocol = eth_type_trans(skb, netdev);
1930
1931 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
1932 mtk_ppe_check_skb(eth->ppe[0], skb, hash);
1933
1934 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
1935 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
1936 if (trxd.rxd3 & RX_DMA_VTAG_V2)
1937 __vlan_hwaccel_put_tag(skb,
1938 htons(RX_DMA_VPID(trxd.rxd4)),
1939 RX_DMA_VID(trxd.rxd4));
1940 } else if (trxd.rxd2 & RX_DMA_VTAG) {
1941 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1942 RX_DMA_VID(trxd.rxd3));
1943 }
1944
1945 /* If the device is attached to a dsa switch, the special
1946 * tag inserted in VLAN field by hw switch can * be offloaded
1947 * by RX HW VLAN offload. Clear vlan info.
1948 */
1949 if (netdev_uses_dsa(netdev))
1950 __vlan_hwaccel_clear_tag(skb);
1951 }
1952
1953 skb_record_rx_queue(skb, 0);
1954 napi_gro_receive(napi, skb);
1955
1956 skip_rx:
1957 ring->data[idx] = new_data;
1958 rxd->rxd1 = (unsigned int)dma_addr;
1959 release_desc:
1960 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1961 rxd->rxd2 = RX_DMA_LSO;
1962 else
1963 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
1964
1965 ring->calc_idx = idx;
1966 done++;
1967 }
1968
1969 rx_done:
1970 if (done) {
1971 /* make sure that all changes to the dma ring are flushed before
1972 * we continue
1973 */
1974 wmb();
1975 mtk_update_rx_cpu_idx(eth);
1976 }
1977
1978 eth->rx_packets += done;
1979 eth->rx_bytes += bytes;
1980 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
1981 &dim_sample);
1982 net_dim(ð->rx_dim, dim_sample);
1983
1984 if (xdp_flush)
1985 xdp_do_flush_map();
1986
1987 return done;
1988 }
1989
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1990 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1991 unsigned int *done, unsigned int *bytes)
1992 {
1993 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
1994 struct mtk_tx_ring *ring = ð->tx_ring;
1995 struct mtk_tx_buf *tx_buf;
1996 struct xdp_frame_bulk bq;
1997 struct mtk_tx_dma *desc;
1998 u32 cpu, dma;
1999
2000 cpu = ring->last_free_ptr;
2001 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2002
2003 desc = mtk_qdma_phys_to_virt(ring, cpu);
2004 xdp_frame_bulk_init(&bq);
2005
2006 while ((cpu != dma) && budget) {
2007 u32 next_cpu = desc->txd2;
2008 int mac = 0;
2009
2010 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2011 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2012 break;
2013
2014 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2015 eth->soc->txrx.txd_size);
2016 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
2017 mac = 1;
2018
2019 if (!tx_buf->data)
2020 break;
2021
2022 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2023 if (tx_buf->type == MTK_TYPE_SKB) {
2024 struct sk_buff *skb = tx_buf->data;
2025
2026 bytes[mac] += skb->len;
2027 done[mac]++;
2028 }
2029 budget--;
2030 }
2031 mtk_tx_unmap(eth, tx_buf, &bq, true);
2032
2033 ring->last_free = desc;
2034 atomic_inc(&ring->free_count);
2035
2036 cpu = next_cpu;
2037 }
2038 xdp_flush_frame_bulk(&bq);
2039
2040 ring->last_free_ptr = cpu;
2041 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2042
2043 return budget;
2044 }
2045
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)2046 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2047 unsigned int *done, unsigned int *bytes)
2048 {
2049 struct mtk_tx_ring *ring = ð->tx_ring;
2050 struct mtk_tx_buf *tx_buf;
2051 struct xdp_frame_bulk bq;
2052 struct mtk_tx_dma *desc;
2053 u32 cpu, dma;
2054
2055 cpu = ring->cpu_idx;
2056 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2057 xdp_frame_bulk_init(&bq);
2058
2059 while ((cpu != dma) && budget) {
2060 tx_buf = &ring->buf[cpu];
2061 if (!tx_buf->data)
2062 break;
2063
2064 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2065 if (tx_buf->type == MTK_TYPE_SKB) {
2066 struct sk_buff *skb = tx_buf->data;
2067
2068 bytes[0] += skb->len;
2069 done[0]++;
2070 }
2071 budget--;
2072 }
2073 mtk_tx_unmap(eth, tx_buf, &bq, true);
2074
2075 desc = ring->dma + cpu * eth->soc->txrx.txd_size;
2076 ring->last_free = desc;
2077 atomic_inc(&ring->free_count);
2078
2079 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2080 }
2081 xdp_flush_frame_bulk(&bq);
2082
2083 ring->cpu_idx = cpu;
2084
2085 return budget;
2086 }
2087
mtk_poll_tx(struct mtk_eth * eth,int budget)2088 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2089 {
2090 struct mtk_tx_ring *ring = ð->tx_ring;
2091 struct dim_sample dim_sample = {};
2092 unsigned int done[MTK_MAX_DEVS];
2093 unsigned int bytes[MTK_MAX_DEVS];
2094 int total = 0, i;
2095
2096 memset(done, 0, sizeof(done));
2097 memset(bytes, 0, sizeof(bytes));
2098
2099 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2100 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
2101 else
2102 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
2103
2104 for (i = 0; i < MTK_MAC_COUNT; i++) {
2105 if (!eth->netdev[i] || !done[i])
2106 continue;
2107 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
2108 total += done[i];
2109 eth->tx_packets += done[i];
2110 eth->tx_bytes += bytes[i];
2111 }
2112
2113 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2114 &dim_sample);
2115 net_dim(ð->tx_dim, dim_sample);
2116
2117 if (mtk_queue_stopped(eth) &&
2118 (atomic_read(&ring->free_count) > ring->thresh))
2119 mtk_wake_queue(eth);
2120
2121 return total;
2122 }
2123
mtk_handle_status_irq(struct mtk_eth * eth)2124 static void mtk_handle_status_irq(struct mtk_eth *eth)
2125 {
2126 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2127
2128 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2129 mtk_stats_update(eth);
2130 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2131 MTK_INT_STATUS2);
2132 }
2133 }
2134
mtk_napi_tx(struct napi_struct * napi,int budget)2135 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2136 {
2137 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2138 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2139 int tx_done = 0;
2140
2141 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2142 mtk_handle_status_irq(eth);
2143 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2144 tx_done = mtk_poll_tx(eth, budget);
2145
2146 if (unlikely(netif_msg_intr(eth))) {
2147 dev_info(eth->dev,
2148 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2149 mtk_r32(eth, reg_map->tx_irq_status),
2150 mtk_r32(eth, reg_map->tx_irq_mask));
2151 }
2152
2153 if (tx_done == budget)
2154 return budget;
2155
2156 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2157 return budget;
2158
2159 if (napi_complete_done(napi, tx_done))
2160 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2161
2162 return tx_done;
2163 }
2164
mtk_napi_rx(struct napi_struct * napi,int budget)2165 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2166 {
2167 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2168 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2169 int rx_done_total = 0;
2170
2171 mtk_handle_status_irq(eth);
2172
2173 do {
2174 int rx_done;
2175
2176 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
2177 reg_map->pdma.irq_status);
2178 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2179 rx_done_total += rx_done;
2180
2181 if (unlikely(netif_msg_intr(eth))) {
2182 dev_info(eth->dev,
2183 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2184 mtk_r32(eth, reg_map->pdma.irq_status),
2185 mtk_r32(eth, reg_map->pdma.irq_mask));
2186 }
2187
2188 if (rx_done_total == budget)
2189 return budget;
2190
2191 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2192 eth->soc->txrx.rx_irq_done_mask);
2193
2194 if (napi_complete_done(napi, rx_done_total))
2195 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2196
2197 return rx_done_total;
2198 }
2199
mtk_tx_alloc(struct mtk_eth * eth)2200 static int mtk_tx_alloc(struct mtk_eth *eth)
2201 {
2202 const struct mtk_soc_data *soc = eth->soc;
2203 struct mtk_tx_ring *ring = ð->tx_ring;
2204 int i, sz = soc->txrx.txd_size;
2205 struct mtk_tx_dma_v2 *txd;
2206
2207 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
2208 GFP_KERNEL);
2209 if (!ring->buf)
2210 goto no_tx_mem;
2211
2212 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
2213 &ring->phys, GFP_KERNEL);
2214 if (!ring->dma)
2215 goto no_tx_mem;
2216
2217 for (i = 0; i < MTK_DMA_SIZE; i++) {
2218 int next = (i + 1) % MTK_DMA_SIZE;
2219 u32 next_ptr = ring->phys + next * sz;
2220
2221 txd = ring->dma + i * sz;
2222 txd->txd2 = next_ptr;
2223 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2224 txd->txd4 = 0;
2225 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
2226 txd->txd5 = 0;
2227 txd->txd6 = 0;
2228 txd->txd7 = 0;
2229 txd->txd8 = 0;
2230 }
2231 }
2232
2233 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2234 * only as the framework. The real HW descriptors are the PDMA
2235 * descriptors in ring->dma_pdma.
2236 */
2237 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2238 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
2239 &ring->phys_pdma, GFP_KERNEL);
2240 if (!ring->dma_pdma)
2241 goto no_tx_mem;
2242
2243 for (i = 0; i < MTK_DMA_SIZE; i++) {
2244 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2245 ring->dma_pdma[i].txd4 = 0;
2246 }
2247 }
2248
2249 ring->dma_size = MTK_DMA_SIZE;
2250 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
2251 ring->next_free = ring->dma;
2252 ring->last_free = (void *)txd;
2253 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz));
2254 ring->thresh = MAX_SKB_FRAGS;
2255
2256 /* make sure that all changes to the dma ring are flushed before we
2257 * continue
2258 */
2259 wmb();
2260
2261 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2262 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2263 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2264 mtk_w32(eth,
2265 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
2266 soc->reg_map->qdma.crx_ptr);
2267 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2268 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
2269 soc->reg_map->qdma.qtx_cfg);
2270 } else {
2271 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2272 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
2273 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2274 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2275 }
2276
2277 return 0;
2278
2279 no_tx_mem:
2280 return -ENOMEM;
2281 }
2282
mtk_tx_clean(struct mtk_eth * eth)2283 static void mtk_tx_clean(struct mtk_eth *eth)
2284 {
2285 const struct mtk_soc_data *soc = eth->soc;
2286 struct mtk_tx_ring *ring = ð->tx_ring;
2287 int i;
2288
2289 if (ring->buf) {
2290 for (i = 0; i < MTK_DMA_SIZE; i++)
2291 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2292 kfree(ring->buf);
2293 ring->buf = NULL;
2294 }
2295
2296 if (ring->dma) {
2297 dma_free_coherent(eth->dma_dev,
2298 MTK_DMA_SIZE * soc->txrx.txd_size,
2299 ring->dma, ring->phys);
2300 ring->dma = NULL;
2301 }
2302
2303 if (ring->dma_pdma) {
2304 dma_free_coherent(eth->dma_dev,
2305 MTK_DMA_SIZE * soc->txrx.txd_size,
2306 ring->dma_pdma, ring->phys_pdma);
2307 ring->dma_pdma = NULL;
2308 }
2309 }
2310
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)2311 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2312 {
2313 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2314 struct mtk_rx_ring *ring;
2315 int rx_data_len, rx_dma_size;
2316 int i;
2317
2318 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2319 if (ring_no)
2320 return -EINVAL;
2321 ring = ð->rx_ring_qdma;
2322 } else {
2323 ring = ð->rx_ring[ring_no];
2324 }
2325
2326 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2327 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2328 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2329 } else {
2330 rx_data_len = ETH_DATA_LEN;
2331 rx_dma_size = MTK_DMA_SIZE;
2332 }
2333
2334 ring->frag_size = mtk_max_frag_size(rx_data_len);
2335 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2336 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2337 GFP_KERNEL);
2338 if (!ring->data)
2339 return -ENOMEM;
2340
2341 if (mtk_page_pool_enabled(eth)) {
2342 struct page_pool *pp;
2343
2344 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2345 rx_dma_size);
2346 if (IS_ERR(pp))
2347 return PTR_ERR(pp);
2348
2349 ring->page_pool = pp;
2350 }
2351
2352 ring->dma = dma_alloc_coherent(eth->dma_dev,
2353 rx_dma_size * eth->soc->txrx.rxd_size,
2354 &ring->phys, GFP_KERNEL);
2355 if (!ring->dma)
2356 return -ENOMEM;
2357
2358 for (i = 0; i < rx_dma_size; i++) {
2359 struct mtk_rx_dma_v2 *rxd;
2360 dma_addr_t dma_addr;
2361 void *data;
2362
2363 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2364 if (ring->page_pool) {
2365 data = mtk_page_pool_get_buff(ring->page_pool,
2366 &dma_addr, GFP_KERNEL);
2367 if (!data)
2368 return -ENOMEM;
2369 } else {
2370 if (ring->frag_size <= PAGE_SIZE)
2371 data = netdev_alloc_frag(ring->frag_size);
2372 else
2373 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2374
2375 if (!data)
2376 return -ENOMEM;
2377
2378 dma_addr = dma_map_single(eth->dma_dev,
2379 data + NET_SKB_PAD + eth->ip_align,
2380 ring->buf_size, DMA_FROM_DEVICE);
2381 if (unlikely(dma_mapping_error(eth->dma_dev,
2382 dma_addr))) {
2383 skb_free_frag(data);
2384 return -ENOMEM;
2385 }
2386 }
2387 rxd->rxd1 = (unsigned int)dma_addr;
2388 ring->data[i] = data;
2389
2390 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2391 rxd->rxd2 = RX_DMA_LSO;
2392 else
2393 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2394
2395 rxd->rxd3 = 0;
2396 rxd->rxd4 = 0;
2397 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2398 rxd->rxd5 = 0;
2399 rxd->rxd6 = 0;
2400 rxd->rxd7 = 0;
2401 rxd->rxd8 = 0;
2402 }
2403 }
2404
2405 ring->dma_size = rx_dma_size;
2406 ring->calc_idx_update = false;
2407 ring->calc_idx = rx_dma_size - 1;
2408 if (rx_flag == MTK_RX_FLAGS_QDMA)
2409 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2410 ring_no * MTK_QRX_OFFSET;
2411 else
2412 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2413 ring_no * MTK_QRX_OFFSET;
2414 /* make sure that all changes to the dma ring are flushed before we
2415 * continue
2416 */
2417 wmb();
2418
2419 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2420 mtk_w32(eth, ring->phys,
2421 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2422 mtk_w32(eth, rx_dma_size,
2423 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2424 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2425 reg_map->qdma.rst_idx);
2426 } else {
2427 mtk_w32(eth, ring->phys,
2428 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2429 mtk_w32(eth, rx_dma_size,
2430 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2431 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2432 reg_map->pdma.rst_idx);
2433 }
2434 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2435
2436 return 0;
2437 }
2438
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring)2439 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
2440 {
2441 int i;
2442
2443 if (ring->data && ring->dma) {
2444 for (i = 0; i < ring->dma_size; i++) {
2445 struct mtk_rx_dma *rxd;
2446
2447 if (!ring->data[i])
2448 continue;
2449
2450 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2451 if (!rxd->rxd1)
2452 continue;
2453
2454 dma_unmap_single(eth->dma_dev, rxd->rxd1,
2455 ring->buf_size, DMA_FROM_DEVICE);
2456 mtk_rx_put_buff(ring, ring->data[i], false);
2457 }
2458 kfree(ring->data);
2459 ring->data = NULL;
2460 }
2461
2462 if (ring->dma) {
2463 dma_free_coherent(eth->dma_dev,
2464 ring->dma_size * eth->soc->txrx.rxd_size,
2465 ring->dma, ring->phys);
2466 ring->dma = NULL;
2467 }
2468
2469 if (ring->page_pool) {
2470 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2471 xdp_rxq_info_unreg(&ring->xdp_q);
2472 page_pool_destroy(ring->page_pool);
2473 ring->page_pool = NULL;
2474 }
2475 }
2476
mtk_hwlro_rx_init(struct mtk_eth * eth)2477 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2478 {
2479 int i;
2480 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2481 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2482
2483 /* set LRO rings to auto-learn modes */
2484 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2485
2486 /* validate LRO ring */
2487 ring_ctrl_dw2 |= MTK_RING_VLD;
2488
2489 /* set AGE timer (unit: 20us) */
2490 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2491 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2492
2493 /* set max AGG timer (unit: 20us) */
2494 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2495
2496 /* set max LRO AGG count */
2497 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2498 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2499
2500 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2501 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2502 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2503 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2504 }
2505
2506 /* IPv4 checksum update enable */
2507 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2508
2509 /* switch priority comparison to packet count mode */
2510 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2511
2512 /* bandwidth threshold setting */
2513 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2514
2515 /* auto-learn score delta setting */
2516 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2517
2518 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2519 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2520 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2521
2522 /* set HW LRO mode & the max aggregation count for rx packets */
2523 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2524
2525 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2526 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2527
2528 /* enable HW LRO */
2529 lro_ctrl_dw0 |= MTK_LRO_EN;
2530
2531 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2532 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2533
2534 return 0;
2535 }
2536
mtk_hwlro_rx_uninit(struct mtk_eth * eth)2537 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2538 {
2539 int i;
2540 u32 val;
2541
2542 /* relinquish lro rings, flush aggregated packets */
2543 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2544
2545 /* wait for relinquishments done */
2546 for (i = 0; i < 10; i++) {
2547 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2548 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2549 msleep(20);
2550 continue;
2551 }
2552 break;
2553 }
2554
2555 /* invalidate lro rings */
2556 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2557 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2558
2559 /* disable HW LRO */
2560 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2561 }
2562
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)2563 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2564 {
2565 u32 reg_val;
2566
2567 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2568
2569 /* invalidate the IP setting */
2570 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2571
2572 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2573
2574 /* validate the IP setting */
2575 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2576 }
2577
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)2578 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2579 {
2580 u32 reg_val;
2581
2582 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2583
2584 /* invalidate the IP setting */
2585 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2586
2587 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2588 }
2589
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)2590 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2591 {
2592 int cnt = 0;
2593 int i;
2594
2595 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2596 if (mac->hwlro_ip[i])
2597 cnt++;
2598 }
2599
2600 return cnt;
2601 }
2602
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2603 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2604 struct ethtool_rxnfc *cmd)
2605 {
2606 struct ethtool_rx_flow_spec *fsp =
2607 (struct ethtool_rx_flow_spec *)&cmd->fs;
2608 struct mtk_mac *mac = netdev_priv(dev);
2609 struct mtk_eth *eth = mac->hw;
2610 int hwlro_idx;
2611
2612 if ((fsp->flow_type != TCP_V4_FLOW) ||
2613 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2614 (fsp->location > 1))
2615 return -EINVAL;
2616
2617 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2618 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2619
2620 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2621
2622 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2623
2624 return 0;
2625 }
2626
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2627 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2628 struct ethtool_rxnfc *cmd)
2629 {
2630 struct ethtool_rx_flow_spec *fsp =
2631 (struct ethtool_rx_flow_spec *)&cmd->fs;
2632 struct mtk_mac *mac = netdev_priv(dev);
2633 struct mtk_eth *eth = mac->hw;
2634 int hwlro_idx;
2635
2636 if (fsp->location > 1)
2637 return -EINVAL;
2638
2639 mac->hwlro_ip[fsp->location] = 0;
2640 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2641
2642 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2643
2644 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2645
2646 return 0;
2647 }
2648
mtk_hwlro_netdev_disable(struct net_device * dev)2649 static void mtk_hwlro_netdev_disable(struct net_device *dev)
2650 {
2651 struct mtk_mac *mac = netdev_priv(dev);
2652 struct mtk_eth *eth = mac->hw;
2653 int i, hwlro_idx;
2654
2655 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2656 mac->hwlro_ip[i] = 0;
2657 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2658
2659 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2660 }
2661
2662 mac->hwlro_ip_cnt = 0;
2663 }
2664
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)2665 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2666 struct ethtool_rxnfc *cmd)
2667 {
2668 struct mtk_mac *mac = netdev_priv(dev);
2669 struct ethtool_rx_flow_spec *fsp =
2670 (struct ethtool_rx_flow_spec *)&cmd->fs;
2671
2672 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
2673 return -EINVAL;
2674
2675 /* only tcp dst ipv4 is meaningful, others are meaningless */
2676 fsp->flow_type = TCP_V4_FLOW;
2677 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
2678 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
2679
2680 fsp->h_u.tcp_ip4_spec.ip4src = 0;
2681 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
2682 fsp->h_u.tcp_ip4_spec.psrc = 0;
2683 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
2684 fsp->h_u.tcp_ip4_spec.pdst = 0;
2685 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2686 fsp->h_u.tcp_ip4_spec.tos = 0;
2687 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2688
2689 return 0;
2690 }
2691
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2692 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2693 struct ethtool_rxnfc *cmd,
2694 u32 *rule_locs)
2695 {
2696 struct mtk_mac *mac = netdev_priv(dev);
2697 int cnt = 0;
2698 int i;
2699
2700 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2701 if (cnt == cmd->rule_cnt)
2702 return -EMSGSIZE;
2703
2704 if (mac->hwlro_ip[i]) {
2705 rule_locs[cnt] = i;
2706 cnt++;
2707 }
2708 }
2709
2710 cmd->rule_cnt = cnt;
2711
2712 return 0;
2713 }
2714
mtk_fix_features(struct net_device * dev,netdev_features_t features)2715 static netdev_features_t mtk_fix_features(struct net_device *dev,
2716 netdev_features_t features)
2717 {
2718 if (!(features & NETIF_F_LRO)) {
2719 struct mtk_mac *mac = netdev_priv(dev);
2720 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2721
2722 if (ip_cnt) {
2723 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2724
2725 features |= NETIF_F_LRO;
2726 }
2727 }
2728
2729 return features;
2730 }
2731
mtk_set_features(struct net_device * dev,netdev_features_t features)2732 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2733 {
2734 int err = 0;
2735
2736 if (!((dev->features ^ features) & NETIF_F_LRO))
2737 return 0;
2738
2739 if (!(features & NETIF_F_LRO))
2740 mtk_hwlro_netdev_disable(dev);
2741
2742 return err;
2743 }
2744
2745 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)2746 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2747 {
2748 unsigned int reg;
2749 int ret;
2750 u32 val;
2751
2752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2753 reg = eth->soc->reg_map->qdma.glo_cfg;
2754 else
2755 reg = eth->soc->reg_map->pdma.glo_cfg;
2756
2757 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
2758 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
2759 5, MTK_DMA_BUSY_TIMEOUT_US);
2760 if (ret)
2761 dev_err(eth->dev, "DMA init timeout\n");
2762
2763 return ret;
2764 }
2765
mtk_dma_init(struct mtk_eth * eth)2766 static int mtk_dma_init(struct mtk_eth *eth)
2767 {
2768 int err;
2769 u32 i;
2770
2771 if (mtk_dma_busy_wait(eth))
2772 return -EBUSY;
2773
2774 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2775 /* QDMA needs scratch memory for internal reordering of the
2776 * descriptors
2777 */
2778 err = mtk_init_fq_dma(eth);
2779 if (err)
2780 return err;
2781 }
2782
2783 err = mtk_tx_alloc(eth);
2784 if (err)
2785 return err;
2786
2787 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2788 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2789 if (err)
2790 return err;
2791 }
2792
2793 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2794 if (err)
2795 return err;
2796
2797 if (eth->hwlro) {
2798 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2799 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2800 if (err)
2801 return err;
2802 }
2803 err = mtk_hwlro_rx_init(eth);
2804 if (err)
2805 return err;
2806 }
2807
2808 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2809 /* Enable random early drop and set drop threshold
2810 * automatically
2811 */
2812 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2813 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
2814 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
2815 }
2816
2817 return 0;
2818 }
2819
mtk_dma_free(struct mtk_eth * eth)2820 static void mtk_dma_free(struct mtk_eth *eth)
2821 {
2822 const struct mtk_soc_data *soc = eth->soc;
2823 int i;
2824
2825 for (i = 0; i < MTK_MAC_COUNT; i++)
2826 if (eth->netdev[i])
2827 netdev_reset_queue(eth->netdev[i]);
2828 if (eth->scratch_ring) {
2829 dma_free_coherent(eth->dma_dev,
2830 MTK_DMA_SIZE * soc->txrx.txd_size,
2831 eth->scratch_ring, eth->phy_scratch_ring);
2832 eth->scratch_ring = NULL;
2833 eth->phy_scratch_ring = 0;
2834 }
2835 mtk_tx_clean(eth);
2836 mtk_rx_clean(eth, ð->rx_ring[0]);
2837 mtk_rx_clean(eth, ð->rx_ring_qdma);
2838
2839 if (eth->hwlro) {
2840 mtk_hwlro_rx_uninit(eth);
2841 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2842 mtk_rx_clean(eth, ð->rx_ring[i]);
2843 }
2844
2845 kfree(eth->scratch_head);
2846 }
2847
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)2848 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
2849 {
2850 struct mtk_mac *mac = netdev_priv(dev);
2851 struct mtk_eth *eth = mac->hw;
2852
2853 eth->netdev[mac->id]->stats.tx_errors++;
2854 netif_err(eth, tx_err, dev,
2855 "transmit timed out\n");
2856 schedule_work(ð->pending_work);
2857 }
2858
mtk_handle_irq_rx(int irq,void * _eth)2859 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2860 {
2861 struct mtk_eth *eth = _eth;
2862
2863 eth->rx_events++;
2864 if (likely(napi_schedule_prep(ð->rx_napi))) {
2865 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
2866 __napi_schedule(ð->rx_napi);
2867 }
2868
2869 return IRQ_HANDLED;
2870 }
2871
mtk_handle_irq_tx(int irq,void * _eth)2872 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2873 {
2874 struct mtk_eth *eth = _eth;
2875
2876 eth->tx_events++;
2877 if (likely(napi_schedule_prep(ð->tx_napi))) {
2878 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2879 __napi_schedule(ð->tx_napi);
2880 }
2881
2882 return IRQ_HANDLED;
2883 }
2884
mtk_handle_irq(int irq,void * _eth)2885 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2886 {
2887 struct mtk_eth *eth = _eth;
2888 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2889
2890 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
2891 eth->soc->txrx.rx_irq_done_mask) {
2892 if (mtk_r32(eth, reg_map->pdma.irq_status) &
2893 eth->soc->txrx.rx_irq_done_mask)
2894 mtk_handle_irq_rx(irq, _eth);
2895 }
2896 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
2897 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2898 mtk_handle_irq_tx(irq, _eth);
2899 }
2900
2901 return IRQ_HANDLED;
2902 }
2903
2904 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)2905 static void mtk_poll_controller(struct net_device *dev)
2906 {
2907 struct mtk_mac *mac = netdev_priv(dev);
2908 struct mtk_eth *eth = mac->hw;
2909
2910 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2911 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
2912 mtk_handle_irq_rx(eth->irq[2], dev);
2913 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2914 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2915 }
2916 #endif
2917
mtk_start_dma(struct mtk_eth * eth)2918 static int mtk_start_dma(struct mtk_eth *eth)
2919 {
2920 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2921 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2922 int err;
2923
2924 err = mtk_dma_init(eth);
2925 if (err) {
2926 mtk_dma_free(eth);
2927 return err;
2928 }
2929
2930 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2931 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
2932 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2933 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
2934 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
2935
2936 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
2937 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
2938 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
2939 MTK_CHK_DDONE_EN;
2940 else
2941 val |= MTK_RX_BT_32DWORDS;
2942 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
2943
2944 mtk_w32(eth,
2945 MTK_RX_DMA_EN | rx_2b_offset |
2946 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2947 reg_map->pdma.glo_cfg);
2948 } else {
2949 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2950 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2951 reg_map->pdma.glo_cfg);
2952 }
2953
2954 return 0;
2955 }
2956
mtk_gdm_config(struct mtk_eth * eth,u32 config)2957 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2958 {
2959 int i;
2960
2961 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2962 return;
2963
2964 for (i = 0; i < MTK_MAC_COUNT; i++) {
2965 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2966
2967 /* default setup the forward port to send frame to PDMA */
2968 val &= ~0xffff;
2969
2970 /* Enable RX checksum */
2971 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2972
2973 val |= config;
2974
2975 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
2976 val |= MTK_GDMA_SPECIAL_TAG;
2977
2978 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2979 }
2980 /* Reset and enable PSE */
2981 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2982 mtk_w32(eth, 0, MTK_RST_GL);
2983 }
2984
mtk_open(struct net_device * dev)2985 static int mtk_open(struct net_device *dev)
2986 {
2987 struct mtk_mac *mac = netdev_priv(dev);
2988 struct mtk_eth *eth = mac->hw;
2989 int err;
2990
2991 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2992 if (err) {
2993 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2994 err);
2995 return err;
2996 }
2997
2998 /* we run 2 netdevs on the same dma ring so we only bring it up once */
2999 if (!refcount_read(ð->dma_refcnt)) {
3000 const struct mtk_soc_data *soc = eth->soc;
3001 u32 gdm_config;
3002 int i;
3003
3004 err = mtk_start_dma(eth);
3005 if (err) {
3006 phylink_disconnect_phy(mac->phylink);
3007 return err;
3008 }
3009
3010 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3011 mtk_ppe_start(eth->ppe[i]);
3012
3013 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe
3014 : MTK_GDMA_TO_PDMA;
3015 mtk_gdm_config(eth, gdm_config);
3016
3017 napi_enable(ð->tx_napi);
3018 napi_enable(ð->rx_napi);
3019 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3020 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
3021 refcount_set(ð->dma_refcnt, 1);
3022 }
3023 else
3024 refcount_inc(ð->dma_refcnt);
3025
3026 phylink_start(mac->phylink);
3027 netif_start_queue(dev);
3028 return 0;
3029 }
3030
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)3031 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3032 {
3033 u32 val;
3034 int i;
3035
3036 /* stop the dma engine */
3037 spin_lock_bh(ð->page_lock);
3038 val = mtk_r32(eth, glo_cfg);
3039 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3040 glo_cfg);
3041 spin_unlock_bh(ð->page_lock);
3042
3043 /* wait for dma stop */
3044 for (i = 0; i < 10; i++) {
3045 val = mtk_r32(eth, glo_cfg);
3046 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3047 msleep(20);
3048 continue;
3049 }
3050 break;
3051 }
3052 }
3053
mtk_stop(struct net_device * dev)3054 static int mtk_stop(struct net_device *dev)
3055 {
3056 struct mtk_mac *mac = netdev_priv(dev);
3057 struct mtk_eth *eth = mac->hw;
3058 int i;
3059
3060 phylink_stop(mac->phylink);
3061
3062 netif_tx_disable(dev);
3063
3064 phylink_disconnect_phy(mac->phylink);
3065
3066 /* only shutdown DMA if this is the last user */
3067 if (!refcount_dec_and_test(ð->dma_refcnt))
3068 return 0;
3069
3070 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
3071
3072 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3073 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3074 napi_disable(ð->tx_napi);
3075 napi_disable(ð->rx_napi);
3076
3077 cancel_work_sync(ð->rx_dim.work);
3078 cancel_work_sync(ð->tx_dim.work);
3079
3080 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3081 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3082 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3083
3084 mtk_dma_free(eth);
3085
3086 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3087 mtk_ppe_stop(eth->ppe[i]);
3088
3089 return 0;
3090 }
3091
mtk_xdp_setup(struct net_device * dev,struct bpf_prog * prog,struct netlink_ext_ack * extack)3092 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3093 struct netlink_ext_ack *extack)
3094 {
3095 struct mtk_mac *mac = netdev_priv(dev);
3096 struct mtk_eth *eth = mac->hw;
3097 struct bpf_prog *old_prog;
3098 bool need_update;
3099
3100 if (eth->hwlro) {
3101 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3102 return -EOPNOTSUPP;
3103 }
3104
3105 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3106 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3107 return -EOPNOTSUPP;
3108 }
3109
3110 need_update = !!eth->prog != !!prog;
3111 if (netif_running(dev) && need_update)
3112 mtk_stop(dev);
3113
3114 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3115 if (old_prog)
3116 bpf_prog_put(old_prog);
3117
3118 if (netif_running(dev) && need_update)
3119 return mtk_open(dev);
3120
3121 return 0;
3122 }
3123
mtk_xdp(struct net_device * dev,struct netdev_bpf * xdp)3124 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3125 {
3126 switch (xdp->command) {
3127 case XDP_SETUP_PROG:
3128 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3129 default:
3130 return -EINVAL;
3131 }
3132 }
3133
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)3134 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3135 {
3136 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3137 reset_bits,
3138 reset_bits);
3139
3140 usleep_range(1000, 1100);
3141 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3142 reset_bits,
3143 ~reset_bits);
3144 mdelay(10);
3145 }
3146
mtk_clk_disable(struct mtk_eth * eth)3147 static void mtk_clk_disable(struct mtk_eth *eth)
3148 {
3149 int clk;
3150
3151 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3152 clk_disable_unprepare(eth->clks[clk]);
3153 }
3154
mtk_clk_enable(struct mtk_eth * eth)3155 static int mtk_clk_enable(struct mtk_eth *eth)
3156 {
3157 int clk, ret;
3158
3159 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3160 ret = clk_prepare_enable(eth->clks[clk]);
3161 if (ret)
3162 goto err_disable_clks;
3163 }
3164
3165 return 0;
3166
3167 err_disable_clks:
3168 while (--clk >= 0)
3169 clk_disable_unprepare(eth->clks[clk]);
3170
3171 return ret;
3172 }
3173
mtk_dim_rx(struct work_struct * work)3174 static void mtk_dim_rx(struct work_struct *work)
3175 {
3176 struct dim *dim = container_of(work, struct dim, work);
3177 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3178 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3179 struct dim_cq_moder cur_profile;
3180 u32 val, cur;
3181
3182 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3183 dim->profile_ix);
3184 spin_lock_bh(ð->dim_lock);
3185
3186 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3187 val &= MTK_PDMA_DELAY_TX_MASK;
3188 val |= MTK_PDMA_DELAY_RX_EN;
3189
3190 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3191 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3192
3193 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3194 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3195
3196 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3197 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3198 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3199
3200 spin_unlock_bh(ð->dim_lock);
3201
3202 dim->state = DIM_START_MEASURE;
3203 }
3204
mtk_dim_tx(struct work_struct * work)3205 static void mtk_dim_tx(struct work_struct *work)
3206 {
3207 struct dim *dim = container_of(work, struct dim, work);
3208 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3209 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3210 struct dim_cq_moder cur_profile;
3211 u32 val, cur;
3212
3213 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3214 dim->profile_ix);
3215 spin_lock_bh(ð->dim_lock);
3216
3217 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3218 val &= MTK_PDMA_DELAY_RX_MASK;
3219 val |= MTK_PDMA_DELAY_TX_EN;
3220
3221 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3222 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3223
3224 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3225 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3226
3227 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3228 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3229 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3230
3231 spin_unlock_bh(ð->dim_lock);
3232
3233 dim->state = DIM_START_MEASURE;
3234 }
3235
mtk_set_mcr_max_rx(struct mtk_mac * mac,u32 val)3236 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3237 {
3238 struct mtk_eth *eth = mac->hw;
3239 u32 mcr_cur, mcr_new;
3240
3241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3242 return;
3243
3244 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3245 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3246
3247 if (val <= 1518)
3248 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3249 else if (val <= 1536)
3250 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3251 else if (val <= 1552)
3252 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3253 else
3254 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3255
3256 if (mcr_new != mcr_cur)
3257 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3258 }
3259
mtk_hw_init(struct mtk_eth * eth)3260 static int mtk_hw_init(struct mtk_eth *eth)
3261 {
3262 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3263 ETHSYS_DMA_AG_MAP_PPE;
3264 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3265 int i, val, ret;
3266
3267 if (test_and_set_bit(MTK_HW_INIT, ð->state))
3268 return 0;
3269
3270 pm_runtime_enable(eth->dev);
3271 pm_runtime_get_sync(eth->dev);
3272
3273 ret = mtk_clk_enable(eth);
3274 if (ret)
3275 goto err_disable_pm;
3276
3277 if (eth->ethsys)
3278 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3279 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3280
3281 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3282 ret = device_reset(eth->dev);
3283 if (ret) {
3284 dev_err(eth->dev, "MAC reset failed!\n");
3285 goto err_disable_pm;
3286 }
3287
3288 /* set interrupt delays based on current Net DIM sample */
3289 mtk_dim_rx(ð->rx_dim.work);
3290 mtk_dim_tx(ð->tx_dim.work);
3291
3292 /* disable delay and normal interrupt */
3293 mtk_tx_irq_disable(eth, ~0);
3294 mtk_rx_irq_disable(eth, ~0);
3295
3296 return 0;
3297 }
3298
3299 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3300 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3301 val = RSTCTRL_PPE0_V2;
3302 } else {
3303 val = RSTCTRL_PPE0;
3304 }
3305
3306 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3307 val |= RSTCTRL_PPE1;
3308
3309 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3310
3311 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3312 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3313 0x3ffffff);
3314
3315 /* Set FE to PDMAv2 if necessary */
3316 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3317 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3318 }
3319
3320 if (eth->pctl) {
3321 /* Set GE2 driving and slew rate */
3322 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
3323
3324 /* set GE2 TDSEL */
3325 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
3326
3327 /* set GE2 TUNE */
3328 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3329 }
3330
3331 /* Set linkdown as the default for each GMAC. Its own MCR would be set
3332 * up with the more appropriate value when mtk_mac_config call is being
3333 * invoked.
3334 */
3335 for (i = 0; i < MTK_MAC_COUNT; i++) {
3336 struct net_device *dev = eth->netdev[i];
3337
3338 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3339 if (dev) {
3340 struct mtk_mac *mac = netdev_priv(dev);
3341
3342 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN);
3343 }
3344 }
3345
3346 /* Indicates CDM to parse the MTK special tag from CPU
3347 * which also is working out for untag packets.
3348 */
3349 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3350 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3351
3352 /* Enable RX VLan Offloading */
3353 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3354
3355 /* set interrupt delays based on current Net DIM sample */
3356 mtk_dim_rx(ð->rx_dim.work);
3357 mtk_dim_tx(ð->tx_dim.work);
3358
3359 /* disable delay and normal interrupt */
3360 mtk_tx_irq_disable(eth, ~0);
3361 mtk_rx_irq_disable(eth, ~0);
3362
3363 /* FE int grouping */
3364 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
3365 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
3366 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
3367 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
3368 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
3369
3370 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3371 /* PSE should not drop port8 and port9 packets from WDMA Tx */
3372 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
3373
3374 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
3375 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
3376
3377 /* PSE Free Queue Flow Control */
3378 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
3379
3380 /* PSE config input queue threshold */
3381 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
3382 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
3383 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
3384 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
3385 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
3386 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
3387 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
3388 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
3389
3390 /* PSE config output queue threshold */
3391 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
3392 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
3393 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
3394 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
3395 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
3396 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
3397 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
3398 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
3399
3400 /* GDM and CDM Threshold */
3401 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
3402 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
3403 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
3404 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
3405 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
3406 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
3407 }
3408
3409 return 0;
3410
3411 err_disable_pm:
3412 pm_runtime_put_sync(eth->dev);
3413 pm_runtime_disable(eth->dev);
3414
3415 return ret;
3416 }
3417
mtk_hw_deinit(struct mtk_eth * eth)3418 static int mtk_hw_deinit(struct mtk_eth *eth)
3419 {
3420 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
3421 return 0;
3422
3423 mtk_clk_disable(eth);
3424
3425 pm_runtime_put_sync(eth->dev);
3426 pm_runtime_disable(eth->dev);
3427
3428 return 0;
3429 }
3430
mtk_uninit(struct net_device * dev)3431 static void mtk_uninit(struct net_device *dev)
3432 {
3433 struct mtk_mac *mac = netdev_priv(dev);
3434 struct mtk_eth *eth = mac->hw;
3435
3436 phylink_disconnect_phy(mac->phylink);
3437 mtk_tx_irq_disable(eth, ~0);
3438 mtk_rx_irq_disable(eth, ~0);
3439 }
3440
mtk_change_mtu(struct net_device * dev,int new_mtu)3441 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
3442 {
3443 int length = new_mtu + MTK_RX_ETH_HLEN;
3444 struct mtk_mac *mac = netdev_priv(dev);
3445 struct mtk_eth *eth = mac->hw;
3446
3447 if (rcu_access_pointer(eth->prog) &&
3448 length > MTK_PP_MAX_BUF_SIZE) {
3449 netdev_err(dev, "Invalid MTU for XDP mode\n");
3450 return -EINVAL;
3451 }
3452
3453 mtk_set_mcr_max_rx(mac, length);
3454 dev->mtu = new_mtu;
3455
3456 return 0;
3457 }
3458
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)3459 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3460 {
3461 struct mtk_mac *mac = netdev_priv(dev);
3462
3463 switch (cmd) {
3464 case SIOCGMIIPHY:
3465 case SIOCGMIIREG:
3466 case SIOCSMIIREG:
3467 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
3468 default:
3469 break;
3470 }
3471
3472 return -EOPNOTSUPP;
3473 }
3474
mtk_pending_work(struct work_struct * work)3475 static void mtk_pending_work(struct work_struct *work)
3476 {
3477 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
3478 int err, i;
3479 unsigned long restart = 0;
3480
3481 rtnl_lock();
3482
3483 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
3484
3485 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
3486 cpu_relax();
3487
3488 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
3489 /* stop all devices to make sure that dma is properly shut down */
3490 for (i = 0; i < MTK_MAC_COUNT; i++) {
3491 if (!eth->netdev[i])
3492 continue;
3493 mtk_stop(eth->netdev[i]);
3494 __set_bit(i, &restart);
3495 }
3496 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
3497
3498 /* restart underlying hardware such as power, clock, pin mux
3499 * and the connected phy
3500 */
3501 mtk_hw_deinit(eth);
3502
3503 if (eth->dev->pins)
3504 pinctrl_select_state(eth->dev->pins->p,
3505 eth->dev->pins->default_state);
3506 mtk_hw_init(eth);
3507
3508 /* restart DMA and enable IRQs */
3509 for (i = 0; i < MTK_MAC_COUNT; i++) {
3510 if (!test_bit(i, &restart))
3511 continue;
3512 err = mtk_open(eth->netdev[i]);
3513 if (err) {
3514 netif_alert(eth, ifup, eth->netdev[i],
3515 "Driver up/down cycle failed, closing device.\n");
3516 dev_close(eth->netdev[i]);
3517 }
3518 }
3519
3520 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
3521
3522 clear_bit_unlock(MTK_RESETTING, ð->state);
3523
3524 rtnl_unlock();
3525 }
3526
mtk_free_dev(struct mtk_eth * eth)3527 static int mtk_free_dev(struct mtk_eth *eth)
3528 {
3529 int i;
3530
3531 for (i = 0; i < MTK_MAC_COUNT; i++) {
3532 if (!eth->netdev[i])
3533 continue;
3534 free_netdev(eth->netdev[i]);
3535 }
3536
3537 return 0;
3538 }
3539
mtk_unreg_dev(struct mtk_eth * eth)3540 static int mtk_unreg_dev(struct mtk_eth *eth)
3541 {
3542 int i;
3543
3544 for (i = 0; i < MTK_MAC_COUNT; i++) {
3545 if (!eth->netdev[i])
3546 continue;
3547 unregister_netdev(eth->netdev[i]);
3548 }
3549
3550 return 0;
3551 }
3552
mtk_cleanup(struct mtk_eth * eth)3553 static int mtk_cleanup(struct mtk_eth *eth)
3554 {
3555 mtk_unreg_dev(eth);
3556 mtk_free_dev(eth);
3557 cancel_work_sync(ð->pending_work);
3558
3559 return 0;
3560 }
3561
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)3562 static int mtk_get_link_ksettings(struct net_device *ndev,
3563 struct ethtool_link_ksettings *cmd)
3564 {
3565 struct mtk_mac *mac = netdev_priv(ndev);
3566
3567 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3568 return -EBUSY;
3569
3570 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
3571 }
3572
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)3573 static int mtk_set_link_ksettings(struct net_device *ndev,
3574 const struct ethtool_link_ksettings *cmd)
3575 {
3576 struct mtk_mac *mac = netdev_priv(ndev);
3577
3578 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3579 return -EBUSY;
3580
3581 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
3582 }
3583
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)3584 static void mtk_get_drvinfo(struct net_device *dev,
3585 struct ethtool_drvinfo *info)
3586 {
3587 struct mtk_mac *mac = netdev_priv(dev);
3588
3589 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
3590 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
3591 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
3592 }
3593
mtk_get_msglevel(struct net_device * dev)3594 static u32 mtk_get_msglevel(struct net_device *dev)
3595 {
3596 struct mtk_mac *mac = netdev_priv(dev);
3597
3598 return mac->hw->msg_enable;
3599 }
3600
mtk_set_msglevel(struct net_device * dev,u32 value)3601 static void mtk_set_msglevel(struct net_device *dev, u32 value)
3602 {
3603 struct mtk_mac *mac = netdev_priv(dev);
3604
3605 mac->hw->msg_enable = value;
3606 }
3607
mtk_nway_reset(struct net_device * dev)3608 static int mtk_nway_reset(struct net_device *dev)
3609 {
3610 struct mtk_mac *mac = netdev_priv(dev);
3611
3612 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3613 return -EBUSY;
3614
3615 if (!mac->phylink)
3616 return -ENOTSUPP;
3617
3618 return phylink_ethtool_nway_reset(mac->phylink);
3619 }
3620
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)3621 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3622 {
3623 int i;
3624
3625 switch (stringset) {
3626 case ETH_SS_STATS: {
3627 struct mtk_mac *mac = netdev_priv(dev);
3628
3629 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
3630 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
3631 data += ETH_GSTRING_LEN;
3632 }
3633 if (mtk_page_pool_enabled(mac->hw))
3634 page_pool_ethtool_stats_get_strings(data);
3635 break;
3636 }
3637 default:
3638 break;
3639 }
3640 }
3641
mtk_get_sset_count(struct net_device * dev,int sset)3642 static int mtk_get_sset_count(struct net_device *dev, int sset)
3643 {
3644 switch (sset) {
3645 case ETH_SS_STATS: {
3646 int count = ARRAY_SIZE(mtk_ethtool_stats);
3647 struct mtk_mac *mac = netdev_priv(dev);
3648
3649 if (mtk_page_pool_enabled(mac->hw))
3650 count += page_pool_ethtool_stats_get_count();
3651 return count;
3652 }
3653 default:
3654 return -EOPNOTSUPP;
3655 }
3656 }
3657
mtk_ethtool_pp_stats(struct mtk_eth * eth,u64 * data)3658 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
3659 {
3660 struct page_pool_stats stats = {};
3661 int i;
3662
3663 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
3664 struct mtk_rx_ring *ring = ð->rx_ring[i];
3665
3666 if (!ring->page_pool)
3667 continue;
3668
3669 page_pool_get_stats(ring->page_pool, &stats);
3670 }
3671 page_pool_ethtool_stats_get(data, &stats);
3672 }
3673
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3674 static void mtk_get_ethtool_stats(struct net_device *dev,
3675 struct ethtool_stats *stats, u64 *data)
3676 {
3677 struct mtk_mac *mac = netdev_priv(dev);
3678 struct mtk_hw_stats *hwstats = mac->hw_stats;
3679 u64 *data_src, *data_dst;
3680 unsigned int start;
3681 int i;
3682
3683 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3684 return;
3685
3686 if (netif_running(dev) && netif_device_present(dev)) {
3687 if (spin_trylock_bh(&hwstats->stats_lock)) {
3688 mtk_stats_update_mac(mac);
3689 spin_unlock_bh(&hwstats->stats_lock);
3690 }
3691 }
3692
3693 data_src = (u64 *)hwstats;
3694
3695 do {
3696 data_dst = data;
3697 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
3698
3699 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
3700 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
3701 if (mtk_page_pool_enabled(mac->hw))
3702 mtk_ethtool_pp_stats(mac->hw, data_dst);
3703 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
3704 }
3705
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3706 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
3707 u32 *rule_locs)
3708 {
3709 int ret = -EOPNOTSUPP;
3710
3711 switch (cmd->cmd) {
3712 case ETHTOOL_GRXRINGS:
3713 if (dev->hw_features & NETIF_F_LRO) {
3714 cmd->data = MTK_MAX_RX_RING_NUM;
3715 ret = 0;
3716 }
3717 break;
3718 case ETHTOOL_GRXCLSRLCNT:
3719 if (dev->hw_features & NETIF_F_LRO) {
3720 struct mtk_mac *mac = netdev_priv(dev);
3721
3722 cmd->rule_cnt = mac->hwlro_ip_cnt;
3723 ret = 0;
3724 }
3725 break;
3726 case ETHTOOL_GRXCLSRULE:
3727 if (dev->hw_features & NETIF_F_LRO)
3728 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
3729 break;
3730 case ETHTOOL_GRXCLSRLALL:
3731 if (dev->hw_features & NETIF_F_LRO)
3732 ret = mtk_hwlro_get_fdir_all(dev, cmd,
3733 rule_locs);
3734 break;
3735 default:
3736 break;
3737 }
3738
3739 return ret;
3740 }
3741
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)3742 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3743 {
3744 int ret = -EOPNOTSUPP;
3745
3746 switch (cmd->cmd) {
3747 case ETHTOOL_SRXCLSRLINS:
3748 if (dev->hw_features & NETIF_F_LRO)
3749 ret = mtk_hwlro_add_ipaddr(dev, cmd);
3750 break;
3751 case ETHTOOL_SRXCLSRLDEL:
3752 if (dev->hw_features & NETIF_F_LRO)
3753 ret = mtk_hwlro_del_ipaddr(dev, cmd);
3754 break;
3755 default:
3756 break;
3757 }
3758
3759 return ret;
3760 }
3761
3762 static const struct ethtool_ops mtk_ethtool_ops = {
3763 .get_link_ksettings = mtk_get_link_ksettings,
3764 .set_link_ksettings = mtk_set_link_ksettings,
3765 .get_drvinfo = mtk_get_drvinfo,
3766 .get_msglevel = mtk_get_msglevel,
3767 .set_msglevel = mtk_set_msglevel,
3768 .nway_reset = mtk_nway_reset,
3769 .get_link = ethtool_op_get_link,
3770 .get_strings = mtk_get_strings,
3771 .get_sset_count = mtk_get_sset_count,
3772 .get_ethtool_stats = mtk_get_ethtool_stats,
3773 .get_rxnfc = mtk_get_rxnfc,
3774 .set_rxnfc = mtk_set_rxnfc,
3775 };
3776
3777 static const struct net_device_ops mtk_netdev_ops = {
3778 .ndo_uninit = mtk_uninit,
3779 .ndo_open = mtk_open,
3780 .ndo_stop = mtk_stop,
3781 .ndo_start_xmit = mtk_start_xmit,
3782 .ndo_set_mac_address = mtk_set_mac_address,
3783 .ndo_validate_addr = eth_validate_addr,
3784 .ndo_eth_ioctl = mtk_do_ioctl,
3785 .ndo_change_mtu = mtk_change_mtu,
3786 .ndo_tx_timeout = mtk_tx_timeout,
3787 .ndo_get_stats64 = mtk_get_stats64,
3788 .ndo_fix_features = mtk_fix_features,
3789 .ndo_set_features = mtk_set_features,
3790 #ifdef CONFIG_NET_POLL_CONTROLLER
3791 .ndo_poll_controller = mtk_poll_controller,
3792 #endif
3793 .ndo_setup_tc = mtk_eth_setup_tc,
3794 .ndo_bpf = mtk_xdp,
3795 .ndo_xdp_xmit = mtk_xdp_xmit,
3796 };
3797
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)3798 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
3799 {
3800 const __be32 *_id = of_get_property(np, "reg", NULL);
3801 phy_interface_t phy_mode;
3802 struct phylink *phylink;
3803 struct mtk_mac *mac;
3804 int id, err;
3805
3806 if (!_id) {
3807 dev_err(eth->dev, "missing mac id\n");
3808 return -EINVAL;
3809 }
3810
3811 id = be32_to_cpup(_id);
3812 if (id >= MTK_MAC_COUNT) {
3813 dev_err(eth->dev, "%d is not a valid mac id\n", id);
3814 return -EINVAL;
3815 }
3816
3817 if (eth->netdev[id]) {
3818 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
3819 return -EINVAL;
3820 }
3821
3822 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
3823 if (!eth->netdev[id]) {
3824 dev_err(eth->dev, "alloc_etherdev failed\n");
3825 return -ENOMEM;
3826 }
3827 mac = netdev_priv(eth->netdev[id]);
3828 eth->mac[id] = mac;
3829 mac->id = id;
3830 mac->hw = eth;
3831 mac->of_node = np;
3832
3833 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
3834 if (err == -EPROBE_DEFER)
3835 return err;
3836
3837 if (err) {
3838 /* If the mac address is invalid, use random mac address */
3839 eth_hw_addr_random(eth->netdev[id]);
3840 dev_err(eth->dev, "generated random MAC address %pM\n",
3841 eth->netdev[id]->dev_addr);
3842 }
3843
3844 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
3845 mac->hwlro_ip_cnt = 0;
3846
3847 mac->hw_stats = devm_kzalloc(eth->dev,
3848 sizeof(*mac->hw_stats),
3849 GFP_KERNEL);
3850 if (!mac->hw_stats) {
3851 dev_err(eth->dev, "failed to allocate counter memory\n");
3852 err = -ENOMEM;
3853 goto free_netdev;
3854 }
3855 spin_lock_init(&mac->hw_stats->stats_lock);
3856 u64_stats_init(&mac->hw_stats->syncp);
3857 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
3858
3859 /* phylink create */
3860 err = of_get_phy_mode(np, &phy_mode);
3861 if (err) {
3862 dev_err(eth->dev, "incorrect phy-mode\n");
3863 goto free_netdev;
3864 }
3865
3866 /* mac config is not set */
3867 mac->interface = PHY_INTERFACE_MODE_NA;
3868 mac->speed = SPEED_UNKNOWN;
3869
3870 mac->phylink_config.dev = ð->netdev[id]->dev;
3871 mac->phylink_config.type = PHYLINK_NETDEV;
3872 /* This driver makes use of state->speed in mac_config */
3873 mac->phylink_config.legacy_pre_march2020 = true;
3874 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
3875 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
3876
3877 __set_bit(PHY_INTERFACE_MODE_MII,
3878 mac->phylink_config.supported_interfaces);
3879 __set_bit(PHY_INTERFACE_MODE_GMII,
3880 mac->phylink_config.supported_interfaces);
3881
3882 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
3883 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
3884
3885 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
3886 __set_bit(PHY_INTERFACE_MODE_TRGMII,
3887 mac->phylink_config.supported_interfaces);
3888
3889 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
3890 __set_bit(PHY_INTERFACE_MODE_SGMII,
3891 mac->phylink_config.supported_interfaces);
3892 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
3893 mac->phylink_config.supported_interfaces);
3894 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
3895 mac->phylink_config.supported_interfaces);
3896 }
3897
3898 phylink = phylink_create(&mac->phylink_config,
3899 of_fwnode_handle(mac->of_node),
3900 phy_mode, &mtk_phylink_ops);
3901 if (IS_ERR(phylink)) {
3902 err = PTR_ERR(phylink);
3903 goto free_netdev;
3904 }
3905
3906 mac->phylink = phylink;
3907
3908 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
3909 eth->netdev[id]->watchdog_timeo = 5 * HZ;
3910 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
3911 eth->netdev[id]->base_addr = (unsigned long)eth->base;
3912
3913 eth->netdev[id]->hw_features = eth->soc->hw_features;
3914 if (eth->hwlro)
3915 eth->netdev[id]->hw_features |= NETIF_F_LRO;
3916
3917 eth->netdev[id]->vlan_features = eth->soc->hw_features &
3918 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
3919 eth->netdev[id]->features |= eth->soc->hw_features;
3920 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
3921
3922 eth->netdev[id]->irq = eth->irq[0];
3923 eth->netdev[id]->dev.of_node = np;
3924
3925 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3926 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
3927 else
3928 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
3929
3930 return 0;
3931
3932 free_netdev:
3933 free_netdev(eth->netdev[id]);
3934 return err;
3935 }
3936
mtk_eth_set_dma_device(struct mtk_eth * eth,struct device * dma_dev)3937 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
3938 {
3939 struct net_device *dev, *tmp;
3940 LIST_HEAD(dev_list);
3941 int i;
3942
3943 rtnl_lock();
3944
3945 for (i = 0; i < MTK_MAC_COUNT; i++) {
3946 dev = eth->netdev[i];
3947
3948 if (!dev || !(dev->flags & IFF_UP))
3949 continue;
3950
3951 list_add_tail(&dev->close_list, &dev_list);
3952 }
3953
3954 dev_close_many(&dev_list, false);
3955
3956 eth->dma_dev = dma_dev;
3957
3958 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
3959 list_del_init(&dev->close_list);
3960 dev_open(dev, NULL);
3961 }
3962
3963 rtnl_unlock();
3964 }
3965
mtk_probe(struct platform_device * pdev)3966 static int mtk_probe(struct platform_device *pdev)
3967 {
3968 struct resource *res = NULL;
3969 struct device_node *mac_np;
3970 struct mtk_eth *eth;
3971 int err, i;
3972
3973 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
3974 if (!eth)
3975 return -ENOMEM;
3976
3977 eth->soc = of_device_get_match_data(&pdev->dev);
3978
3979 eth->dev = &pdev->dev;
3980 eth->dma_dev = &pdev->dev;
3981 eth->base = devm_platform_ioremap_resource(pdev, 0);
3982 if (IS_ERR(eth->base))
3983 return PTR_ERR(eth->base);
3984
3985 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3986 eth->ip_align = NET_IP_ALIGN;
3987
3988 spin_lock_init(ð->page_lock);
3989 spin_lock_init(ð->tx_irq_lock);
3990 spin_lock_init(ð->rx_irq_lock);
3991 spin_lock_init(ð->dim_lock);
3992
3993 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
3994 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
3995
3996 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
3997 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
3998
3999 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4000 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4001 "mediatek,ethsys");
4002 if (IS_ERR(eth->ethsys)) {
4003 dev_err(&pdev->dev, "no ethsys regmap found\n");
4004 return PTR_ERR(eth->ethsys);
4005 }
4006 }
4007
4008 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4009 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4010 "mediatek,infracfg");
4011 if (IS_ERR(eth->infra)) {
4012 dev_err(&pdev->dev, "no infracfg regmap found\n");
4013 return PTR_ERR(eth->infra);
4014 }
4015 }
4016
4017 if (of_dma_is_coherent(pdev->dev.of_node)) {
4018 struct regmap *cci;
4019
4020 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4021 "cci-control-port");
4022 /* enable CPU/bus coherency */
4023 if (!IS_ERR(cci))
4024 regmap_write(cci, 0, 3);
4025 }
4026
4027 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4028 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
4029 GFP_KERNEL);
4030 if (!eth->sgmii)
4031 return -ENOMEM;
4032
4033 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
4034 eth->soc->ana_rgc3);
4035
4036 if (err)
4037 return err;
4038 }
4039
4040 if (eth->soc->required_pctl) {
4041 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4042 "mediatek,pctl");
4043 if (IS_ERR(eth->pctl)) {
4044 dev_err(&pdev->dev, "no pctl regmap found\n");
4045 return PTR_ERR(eth->pctl);
4046 }
4047 }
4048
4049 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
4050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4051 if (!res)
4052 return -EINVAL;
4053 }
4054
4055 if (eth->soc->offload_version) {
4056 for (i = 0;; i++) {
4057 struct device_node *np;
4058 phys_addr_t wdma_phy;
4059 u32 wdma_base;
4060
4061 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4062 break;
4063
4064 np = of_parse_phandle(pdev->dev.of_node,
4065 "mediatek,wed", i);
4066 if (!np)
4067 break;
4068
4069 wdma_base = eth->soc->reg_map->wdma_base[i];
4070 wdma_phy = res ? res->start + wdma_base : 0;
4071 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4072 wdma_phy, i);
4073 }
4074 }
4075
4076 for (i = 0; i < 3; i++) {
4077 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4078 eth->irq[i] = eth->irq[0];
4079 else
4080 eth->irq[i] = platform_get_irq(pdev, i);
4081 if (eth->irq[i] < 0) {
4082 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
4083 err = -ENXIO;
4084 goto err_wed_exit;
4085 }
4086 }
4087 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4088 eth->clks[i] = devm_clk_get(eth->dev,
4089 mtk_clks_source_name[i]);
4090 if (IS_ERR(eth->clks[i])) {
4091 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4092 err = -EPROBE_DEFER;
4093 goto err_wed_exit;
4094 }
4095 if (eth->soc->required_clks & BIT(i)) {
4096 dev_err(&pdev->dev, "clock %s not found\n",
4097 mtk_clks_source_name[i]);
4098 err = -EINVAL;
4099 goto err_wed_exit;
4100 }
4101 eth->clks[i] = NULL;
4102 }
4103 }
4104
4105 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
4106 INIT_WORK(ð->pending_work, mtk_pending_work);
4107
4108 err = mtk_hw_init(eth);
4109 if (err)
4110 goto err_wed_exit;
4111
4112 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
4113
4114 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4115 if (!of_device_is_compatible(mac_np,
4116 "mediatek,eth-mac"))
4117 continue;
4118
4119 if (!of_device_is_available(mac_np))
4120 continue;
4121
4122 err = mtk_add_mac(eth, mac_np);
4123 if (err) {
4124 of_node_put(mac_np);
4125 goto err_deinit_hw;
4126 }
4127 }
4128
4129 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
4130 err = devm_request_irq(eth->dev, eth->irq[0],
4131 mtk_handle_irq, 0,
4132 dev_name(eth->dev), eth);
4133 } else {
4134 err = devm_request_irq(eth->dev, eth->irq[1],
4135 mtk_handle_irq_tx, 0,
4136 dev_name(eth->dev), eth);
4137 if (err)
4138 goto err_free_dev;
4139
4140 err = devm_request_irq(eth->dev, eth->irq[2],
4141 mtk_handle_irq_rx, 0,
4142 dev_name(eth->dev), eth);
4143 }
4144 if (err)
4145 goto err_free_dev;
4146
4147 /* No MT7628/88 support yet */
4148 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4149 err = mtk_mdio_init(eth);
4150 if (err)
4151 goto err_free_dev;
4152 }
4153
4154 if (eth->soc->offload_version) {
4155 u32 num_ppe;
4156
4157 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
4158 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
4159 for (i = 0; i < num_ppe; i++) {
4160 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
4161
4162 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr,
4163 eth->soc->offload_version, i);
4164 if (!eth->ppe[i]) {
4165 err = -ENOMEM;
4166 goto err_deinit_ppe;
4167 }
4168 }
4169
4170 err = mtk_eth_offload_init(eth);
4171 if (err)
4172 goto err_deinit_ppe;
4173 }
4174
4175 for (i = 0; i < MTK_MAX_DEVS; i++) {
4176 if (!eth->netdev[i])
4177 continue;
4178
4179 err = register_netdev(eth->netdev[i]);
4180 if (err) {
4181 dev_err(eth->dev, "error bringing up device\n");
4182 goto err_deinit_ppe;
4183 } else
4184 netif_info(eth, probe, eth->netdev[i],
4185 "mediatek frame engine at 0x%08lx, irq %d\n",
4186 eth->netdev[i]->base_addr, eth->irq[0]);
4187 }
4188
4189 /* we run 2 devices on the same DMA ring so we need a dummy device
4190 * for NAPI to work
4191 */
4192 init_dummy_netdev(ð->dummy_dev);
4193 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx);
4194 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx);
4195
4196 platform_set_drvdata(pdev, eth);
4197
4198 return 0;
4199
4200 err_deinit_ppe:
4201 mtk_ppe_deinit(eth);
4202 mtk_mdio_cleanup(eth);
4203 err_free_dev:
4204 mtk_free_dev(eth);
4205 err_deinit_hw:
4206 mtk_hw_deinit(eth);
4207 err_wed_exit:
4208 mtk_wed_exit();
4209
4210 return err;
4211 }
4212
mtk_remove(struct platform_device * pdev)4213 static int mtk_remove(struct platform_device *pdev)
4214 {
4215 struct mtk_eth *eth = platform_get_drvdata(pdev);
4216 struct mtk_mac *mac;
4217 int i;
4218
4219 /* stop all devices to make sure that dma is properly shut down */
4220 for (i = 0; i < MTK_MAC_COUNT; i++) {
4221 if (!eth->netdev[i])
4222 continue;
4223 mtk_stop(eth->netdev[i]);
4224 mac = netdev_priv(eth->netdev[i]);
4225 phylink_disconnect_phy(mac->phylink);
4226 }
4227
4228 mtk_wed_exit();
4229 mtk_hw_deinit(eth);
4230
4231 netif_napi_del(ð->tx_napi);
4232 netif_napi_del(ð->rx_napi);
4233 mtk_cleanup(eth);
4234 mtk_mdio_cleanup(eth);
4235
4236 return 0;
4237 }
4238
4239 static const struct mtk_soc_data mt2701_data = {
4240 .reg_map = &mtk_reg_map,
4241 .caps = MT7623_CAPS | MTK_HWLRO,
4242 .hw_features = MTK_HW_FEATURES,
4243 .required_clks = MT7623_CLKS_BITMAP,
4244 .required_pctl = true,
4245 .txrx = {
4246 .txd_size = sizeof(struct mtk_tx_dma),
4247 .rxd_size = sizeof(struct mtk_rx_dma),
4248 .rx_irq_done_mask = MTK_RX_DONE_INT,
4249 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4250 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4251 .dma_len_offset = 16,
4252 },
4253 };
4254
4255 static const struct mtk_soc_data mt7621_data = {
4256 .reg_map = &mtk_reg_map,
4257 .caps = MT7621_CAPS,
4258 .hw_features = MTK_HW_FEATURES,
4259 .required_clks = MT7621_CLKS_BITMAP,
4260 .required_pctl = false,
4261 .offload_version = 2,
4262 .hash_offset = 2,
4263 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4264 .txrx = {
4265 .txd_size = sizeof(struct mtk_tx_dma),
4266 .rxd_size = sizeof(struct mtk_rx_dma),
4267 .rx_irq_done_mask = MTK_RX_DONE_INT,
4268 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4269 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4270 .dma_len_offset = 16,
4271 },
4272 };
4273
4274 static const struct mtk_soc_data mt7622_data = {
4275 .reg_map = &mtk_reg_map,
4276 .ana_rgc3 = 0x2028,
4277 .caps = MT7622_CAPS | MTK_HWLRO,
4278 .hw_features = MTK_HW_FEATURES,
4279 .required_clks = MT7622_CLKS_BITMAP,
4280 .required_pctl = false,
4281 .offload_version = 2,
4282 .hash_offset = 2,
4283 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4284 .txrx = {
4285 .txd_size = sizeof(struct mtk_tx_dma),
4286 .rxd_size = sizeof(struct mtk_rx_dma),
4287 .rx_irq_done_mask = MTK_RX_DONE_INT,
4288 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4289 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4290 .dma_len_offset = 16,
4291 },
4292 };
4293
4294 static const struct mtk_soc_data mt7623_data = {
4295 .reg_map = &mtk_reg_map,
4296 .caps = MT7623_CAPS | MTK_HWLRO,
4297 .hw_features = MTK_HW_FEATURES,
4298 .required_clks = MT7623_CLKS_BITMAP,
4299 .required_pctl = true,
4300 .offload_version = 2,
4301 .hash_offset = 2,
4302 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4303 .txrx = {
4304 .txd_size = sizeof(struct mtk_tx_dma),
4305 .rxd_size = sizeof(struct mtk_rx_dma),
4306 .rx_irq_done_mask = MTK_RX_DONE_INT,
4307 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4308 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4309 .dma_len_offset = 16,
4310 },
4311 };
4312
4313 static const struct mtk_soc_data mt7629_data = {
4314 .reg_map = &mtk_reg_map,
4315 .ana_rgc3 = 0x128,
4316 .caps = MT7629_CAPS | MTK_HWLRO,
4317 .hw_features = MTK_HW_FEATURES,
4318 .required_clks = MT7629_CLKS_BITMAP,
4319 .required_pctl = false,
4320 .txrx = {
4321 .txd_size = sizeof(struct mtk_tx_dma),
4322 .rxd_size = sizeof(struct mtk_rx_dma),
4323 .rx_irq_done_mask = MTK_RX_DONE_INT,
4324 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4325 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4326 .dma_len_offset = 16,
4327 },
4328 };
4329
4330 static const struct mtk_soc_data mt7986_data = {
4331 .reg_map = &mt7986_reg_map,
4332 .ana_rgc3 = 0x128,
4333 .caps = MT7986_CAPS,
4334 .hw_features = MTK_HW_FEATURES,
4335 .required_clks = MT7986_CLKS_BITMAP,
4336 .required_pctl = false,
4337 .hash_offset = 4,
4338 .foe_entry_size = sizeof(struct mtk_foe_entry),
4339 .txrx = {
4340 .txd_size = sizeof(struct mtk_tx_dma_v2),
4341 .rxd_size = sizeof(struct mtk_rx_dma_v2),
4342 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
4343 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
4344 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
4345 .dma_len_offset = 8,
4346 },
4347 };
4348
4349 static const struct mtk_soc_data rt5350_data = {
4350 .reg_map = &mt7628_reg_map,
4351 .caps = MT7628_CAPS,
4352 .hw_features = MTK_HW_FEATURES_MT7628,
4353 .required_clks = MT7628_CLKS_BITMAP,
4354 .required_pctl = false,
4355 .txrx = {
4356 .txd_size = sizeof(struct mtk_tx_dma),
4357 .rxd_size = sizeof(struct mtk_rx_dma),
4358 .rx_irq_done_mask = MTK_RX_DONE_INT,
4359 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
4360 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4361 .dma_len_offset = 16,
4362 },
4363 };
4364
4365 const struct of_device_id of_mtk_match[] = {
4366 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
4367 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
4368 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
4369 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
4370 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
4371 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
4372 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
4373 {},
4374 };
4375 MODULE_DEVICE_TABLE(of, of_mtk_match);
4376
4377 static struct platform_driver mtk_driver = {
4378 .probe = mtk_probe,
4379 .remove = mtk_remove,
4380 .driver = {
4381 .name = "mtk_soc_eth",
4382 .of_match_table = of_mtk_match,
4383 },
4384 };
4385
4386 module_platform_driver(mtk_driver);
4387
4388 MODULE_LICENSE("GPL");
4389 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4390 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
4391