1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * Open Host Controller Interface (OHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 *
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the https://www.usb.org website.
20 *
21 * This file is licenced under the GPL.
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/usb.h>
37 #include <linux/usb/otg.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmapool.h>
41 #include <linux/workqueue.h>
42 #include <linux/debugfs.h>
43 #include <linux/genalloc.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47 #include <asm/unaligned.h>
48 #include <asm/byteorder.h>
49
50
51 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
53
54 /*-------------------------------------------------------------------------*/
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62 #ifdef __hppa__
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64 #define IR_DISABLE
65 #endif
66
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
69 #define IR_DISABLE
70 #endif
71
72 /*-------------------------------------------------------------------------*/
73
74 static const char hcd_name [] = "ohci_hcd";
75
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78 #define IO_WATCHDOG_OFF 0xffffff00
79
80 #include "ohci.h"
81 #include "pci-quirks.h"
82
83 static void ohci_dump(struct ohci_hcd *ohci);
84 static void ohci_stop(struct usb_hcd *hcd);
85 static void io_watchdog_func(struct timer_list *t);
86
87 #include "ohci-hub.c"
88 #include "ohci-dbg.c"
89 #include "ohci-mem.c"
90 #include "ohci-q.c"
91
92
93 /*
94 * On architectures with edge-triggered interrupts we must never return
95 * IRQ_NONE.
96 */
97 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
98 #define IRQ_NOTMINE IRQ_HANDLED
99 #else
100 #define IRQ_NOTMINE IRQ_NONE
101 #endif
102
103
104 /* Some boards misreport power switching/overcurrent */
105 static bool distrust_firmware;
106 module_param (distrust_firmware, bool, 0);
107 MODULE_PARM_DESC (distrust_firmware,
108 "true to distrust firmware power/overcurrent setup");
109
110 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
111 static bool no_handshake;
112 module_param (no_handshake, bool, 0);
113 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
114
115 /*-------------------------------------------------------------------------*/
116
number_of_tds(struct urb * urb)117 static int number_of_tds(struct urb *urb)
118 {
119 int len, i, num, this_sg_len;
120 struct scatterlist *sg;
121
122 len = urb->transfer_buffer_length;
123 i = urb->num_mapped_sgs;
124
125 if (len > 0 && i > 0) { /* Scatter-gather transfer */
126 num = 0;
127 sg = urb->sg;
128 for (;;) {
129 this_sg_len = min_t(int, sg_dma_len(sg), len);
130 num += DIV_ROUND_UP(this_sg_len, 4096);
131 len -= this_sg_len;
132 if (--i <= 0 || len <= 0)
133 break;
134 sg = sg_next(sg);
135 }
136
137 } else { /* Non-SG transfer */
138 /* one TD for every 4096 Bytes (could be up to 8K) */
139 num = DIV_ROUND_UP(len, 4096);
140 }
141 return num;
142 }
143
144 /*
145 * queue up an urb for anything except the root hub
146 */
ohci_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)147 static int ohci_urb_enqueue (
148 struct usb_hcd *hcd,
149 struct urb *urb,
150 gfp_t mem_flags
151 ) {
152 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
153 struct ed *ed;
154 urb_priv_t *urb_priv;
155 unsigned int pipe = urb->pipe;
156 int i, size = 0;
157 unsigned long flags;
158 int retval = 0;
159
160 /* every endpoint has a ed, locate and maybe (re)initialize it */
161 ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
162 if (! ed)
163 return -ENOMEM;
164
165 /* for the private part of the URB we need the number of TDs (size) */
166 switch (ed->type) {
167 case PIPE_CONTROL:
168 /* td_submit_urb() doesn't yet handle these */
169 if (urb->transfer_buffer_length > 4096)
170 return -EMSGSIZE;
171
172 /* 1 TD for setup, 1 for ACK, plus ... */
173 size = 2;
174 fallthrough;
175 // case PIPE_INTERRUPT:
176 // case PIPE_BULK:
177 default:
178 size += number_of_tds(urb);
179 /* maybe a zero-length packet to wrap it up */
180 if (size == 0)
181 size++;
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket(urb->dev, pipe)) == 0)
185 size++;
186 break;
187 case PIPE_ISOCHRONOUS: /* number of packets from URB */
188 size = urb->number_of_packets;
189 break;
190 }
191
192 /* allocate the private part of the URB */
193 urb_priv = kzalloc(struct_size(urb_priv, td, size), mem_flags);
194 if (!urb_priv)
195 return -ENOMEM;
196 INIT_LIST_HEAD (&urb_priv->pending);
197 urb_priv->length = size;
198 urb_priv->ed = ed;
199
200 /* allocate the TDs (deferring hash chain updates) */
201 for (i = 0; i < size; i++) {
202 urb_priv->td [i] = td_alloc (ohci, mem_flags);
203 if (!urb_priv->td [i]) {
204 urb_priv->length = i;
205 urb_free_priv (ohci, urb_priv);
206 return -ENOMEM;
207 }
208 }
209
210 spin_lock_irqsave (&ohci->lock, flags);
211
212 /* don't submit to a dead HC */
213 if (!HCD_HW_ACCESSIBLE(hcd)) {
214 retval = -ENODEV;
215 goto fail;
216 }
217 if (ohci->rh_state != OHCI_RH_RUNNING) {
218 retval = -ENODEV;
219 goto fail;
220 }
221 retval = usb_hcd_link_urb_to_ep(hcd, urb);
222 if (retval)
223 goto fail;
224
225 /* schedule the ed if needed */
226 if (ed->state == ED_IDLE) {
227 retval = ed_schedule (ohci, ed);
228 if (retval < 0) {
229 usb_hcd_unlink_urb_from_ep(hcd, urb);
230 goto fail;
231 }
232
233 /* Start up the I/O watchdog timer, if it's not running */
234 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
235 list_empty(&ohci->eds_in_use) &&
236 !(ohci->flags & OHCI_QUIRK_QEMU)) {
237 ohci->prev_frame_no = ohci_frame_no(ohci);
238 mod_timer(&ohci->io_watchdog,
239 jiffies + IO_WATCHDOG_DELAY);
240 }
241 list_add(&ed->in_use_list, &ohci->eds_in_use);
242
243 if (ed->type == PIPE_ISOCHRONOUS) {
244 u16 frame = ohci_frame_no(ohci);
245
246 /* delay a few frames before the first TD */
247 frame += max_t (u16, 8, ed->interval);
248 frame &= ~(ed->interval - 1);
249 frame |= ed->branch;
250 urb->start_frame = frame;
251 ed->last_iso = frame + ed->interval * (size - 1);
252 }
253 } else if (ed->type == PIPE_ISOCHRONOUS) {
254 u16 next = ohci_frame_no(ohci) + 1;
255 u16 frame = ed->last_iso + ed->interval;
256 u16 length = ed->interval * (size - 1);
257
258 /* Behind the scheduling threshold? */
259 if (unlikely(tick_before(frame, next))) {
260
261 /* URB_ISO_ASAP: Round up to the first available slot */
262 if (urb->transfer_flags & URB_ISO_ASAP) {
263 frame += (next - frame + ed->interval - 1) &
264 -ed->interval;
265
266 /*
267 * Not ASAP: Use the next slot in the stream,
268 * no matter what.
269 */
270 } else {
271 /*
272 * Some OHCI hardware doesn't handle late TDs
273 * correctly. After retiring them it proceeds
274 * to the next ED instead of the next TD.
275 * Therefore we have to omit the late TDs
276 * entirely.
277 */
278 urb_priv->td_cnt = DIV_ROUND_UP(
279 (u16) (next - frame),
280 ed->interval);
281 if (urb_priv->td_cnt >= urb_priv->length) {
282 ++urb_priv->td_cnt; /* Mark it */
283 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
284 urb, frame, length,
285 next);
286 }
287 }
288 }
289 urb->start_frame = frame;
290 ed->last_iso = frame + length;
291 }
292
293 /* fill the TDs and link them to the ed; and
294 * enable that part of the schedule, if needed
295 * and update count of queued periodic urbs
296 */
297 urb->hcpriv = urb_priv;
298 td_submit_urb (ohci, urb);
299
300 fail:
301 if (retval)
302 urb_free_priv (ohci, urb_priv);
303 spin_unlock_irqrestore (&ohci->lock, flags);
304 return retval;
305 }
306
307 /*
308 * decouple the URB from the HC queues (TDs, urb_priv).
309 * reporting is always done
310 * asynchronously, and we might be dealing with an urb that's
311 * partially transferred, or an ED with other urbs being unlinked.
312 */
ohci_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)313 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
314 {
315 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
316 unsigned long flags;
317 int rc;
318 urb_priv_t *urb_priv;
319
320 spin_lock_irqsave (&ohci->lock, flags);
321 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
322 if (rc == 0) {
323
324 /* Unless an IRQ completed the unlink while it was being
325 * handed to us, flag it for unlink and giveback, and force
326 * some upcoming INTR_SF to call finish_unlinks()
327 */
328 urb_priv = urb->hcpriv;
329 if (urb_priv->ed->state == ED_OPER)
330 start_ed_unlink(ohci, urb_priv->ed);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333 /* With HC dead, we can clean up right away */
334 ohci_work(ohci);
335 }
336 }
337 spin_unlock_irqrestore (&ohci->lock, flags);
338 return rc;
339 }
340
341 /*-------------------------------------------------------------------------*/
342
343 /* frees config/altsetting state for endpoints,
344 * including ED memory, dummy TD, and bulk/intr data toggle
345 */
346
347 static void
ohci_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * ep)348 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
349 {
350 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
351 unsigned long flags;
352 struct ed *ed = ep->hcpriv;
353 unsigned limit = 1000;
354
355 /* ASSERT: any requests/urbs are being unlinked */
356 /* ASSERT: nobody can be submitting urbs for this any more */
357
358 if (!ed)
359 return;
360
361 rescan:
362 spin_lock_irqsave (&ohci->lock, flags);
363
364 if (ohci->rh_state != OHCI_RH_RUNNING) {
365 sanitize:
366 ed->state = ED_IDLE;
367 ohci_work(ohci);
368 }
369
370 switch (ed->state) {
371 case ED_UNLINK: /* wait for hw to finish? */
372 /* major IRQ delivery trouble loses INTR_SF too... */
373 if (limit-- == 0) {
374 ohci_warn(ohci, "ED unlink timeout\n");
375 goto sanitize;
376 }
377 spin_unlock_irqrestore (&ohci->lock, flags);
378 schedule_timeout_uninterruptible(1);
379 goto rescan;
380 case ED_IDLE: /* fully unlinked */
381 if (list_empty (&ed->td_list)) {
382 td_free (ohci, ed->dummy);
383 ed_free (ohci, ed);
384 break;
385 }
386 fallthrough;
387 default:
388 /* caller was supposed to have unlinked any requests;
389 * that's not our job. can't recover; must leak ed.
390 */
391 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
392 ed, ep->desc.bEndpointAddress, ed->state,
393 list_empty (&ed->td_list) ? "" : " (has tds)");
394 td_free (ohci, ed->dummy);
395 break;
396 }
397 ep->hcpriv = NULL;
398 spin_unlock_irqrestore (&ohci->lock, flags);
399 }
400
ohci_get_frame(struct usb_hcd * hcd)401 static int ohci_get_frame (struct usb_hcd *hcd)
402 {
403 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
404
405 return ohci_frame_no(ohci);
406 }
407
ohci_usb_reset(struct ohci_hcd * ohci)408 static void ohci_usb_reset (struct ohci_hcd *ohci)
409 {
410 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
411 ohci->hc_control &= OHCI_CTRL_RWC;
412 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
413 ohci->rh_state = OHCI_RH_HALTED;
414 }
415
416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
417 * other cases where the next software may expect clean state from the
418 * "firmware". this is bus-neutral, unlike shutdown() methods.
419 */
_ohci_shutdown(struct usb_hcd * hcd)420 static void _ohci_shutdown(struct usb_hcd *hcd)
421 {
422 struct ohci_hcd *ohci;
423
424 ohci = hcd_to_ohci (hcd);
425 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
426
427 /* Software reset, after which the controller goes into SUSPEND */
428 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
429 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
430 udelay(10);
431
432 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
433 ohci->rh_state = OHCI_RH_HALTED;
434 }
435
ohci_shutdown(struct usb_hcd * hcd)436 static void ohci_shutdown(struct usb_hcd *hcd)
437 {
438 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
439 unsigned long flags;
440
441 spin_lock_irqsave(&ohci->lock, flags);
442 _ohci_shutdown(hcd);
443 spin_unlock_irqrestore(&ohci->lock, flags);
444 }
445
446 /*-------------------------------------------------------------------------*
447 * HC functions
448 *-------------------------------------------------------------------------*/
449
450 /* init memory, and kick BIOS/SMM off */
451
ohci_init(struct ohci_hcd * ohci)452 static int ohci_init (struct ohci_hcd *ohci)
453 {
454 int ret;
455 struct usb_hcd *hcd = ohci_to_hcd(ohci);
456
457 /* Accept arbitrarily long scatter-gather lists */
458 if (!hcd->localmem_pool)
459 hcd->self.sg_tablesize = ~0;
460
461 if (distrust_firmware)
462 ohci->flags |= OHCI_QUIRK_HUB_POWER;
463
464 ohci->rh_state = OHCI_RH_HALTED;
465 ohci->regs = hcd->regs;
466
467 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
468 * was never needed for most non-PCI systems ... remove the code?
469 */
470
471 #ifndef IR_DISABLE
472 /* SMM owns the HC? not for long! */
473 if (!no_handshake && ohci_readl (ohci,
474 &ohci->regs->control) & OHCI_CTRL_IR) {
475 u32 temp;
476
477 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
478
479 /* this timeout is arbitrary. we make it long, so systems
480 * depending on usb keyboards may be usable even if the
481 * BIOS/SMM code seems pretty broken.
482 */
483 temp = 500; /* arbitrary: five seconds */
484
485 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
486 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
487 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
488 msleep (10);
489 if (--temp == 0) {
490 ohci_err (ohci, "USB HC takeover failed!"
491 " (BIOS/SMM bug)\n");
492 return -EBUSY;
493 }
494 }
495 ohci_usb_reset (ohci);
496 }
497 #endif
498
499 /* Disable HC interrupts */
500 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
501
502 /* flush the writes, and save key bits like RWC */
503 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
504 ohci->hc_control |= OHCI_CTRL_RWC;
505
506 /* Read the number of ports unless overridden */
507 if (ohci->num_ports == 0)
508 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
509
510 if (ohci->hcca)
511 return 0;
512
513 timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
514 ohci->prev_frame_no = IO_WATCHDOG_OFF;
515
516 if (hcd->localmem_pool)
517 ohci->hcca = gen_pool_dma_alloc_align(hcd->localmem_pool,
518 sizeof(*ohci->hcca),
519 &ohci->hcca_dma, 256);
520 else
521 ohci->hcca = dma_alloc_coherent(hcd->self.controller,
522 sizeof(*ohci->hcca),
523 &ohci->hcca_dma,
524 GFP_KERNEL);
525 if (!ohci->hcca)
526 return -ENOMEM;
527
528 if ((ret = ohci_mem_init (ohci)) < 0)
529 ohci_stop (hcd);
530 else {
531 create_debug_files (ohci);
532 }
533
534 return ret;
535 }
536
537 /*-------------------------------------------------------------------------*/
538
539 /* Start an OHCI controller, set the BUS operational
540 * resets USB and controller
541 * enable interrupts
542 */
ohci_run(struct ohci_hcd * ohci)543 static int ohci_run (struct ohci_hcd *ohci)
544 {
545 u32 mask, val;
546 int first = ohci->fminterval == 0;
547 struct usb_hcd *hcd = ohci_to_hcd(ohci);
548
549 ohci->rh_state = OHCI_RH_HALTED;
550
551 /* boot firmware should have set this up (5.1.1.3.1) */
552 if (first) {
553
554 val = ohci_readl (ohci, &ohci->regs->fminterval);
555 ohci->fminterval = val & 0x3fff;
556 if (ohci->fminterval != FI)
557 ohci_dbg (ohci, "fminterval delta %d\n",
558 ohci->fminterval - FI);
559 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
560 /* also: power/overcurrent flags in roothub.a */
561 }
562
563 /* Reset USB nearly "by the book". RemoteWakeupConnected has
564 * to be checked in case boot firmware (BIOS/SMM/...) has set up
565 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
566 * If the bus glue detected wakeup capability then it should
567 * already be enabled; if so we'll just enable it again.
568 */
569 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
570 device_set_wakeup_capable(hcd->self.controller, 1);
571
572 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
573 case OHCI_USB_OPER:
574 val = 0;
575 break;
576 case OHCI_USB_SUSPEND:
577 case OHCI_USB_RESUME:
578 ohci->hc_control &= OHCI_CTRL_RWC;
579 ohci->hc_control |= OHCI_USB_RESUME;
580 val = 10 /* msec wait */;
581 break;
582 // case OHCI_USB_RESET:
583 default:
584 ohci->hc_control &= OHCI_CTRL_RWC;
585 ohci->hc_control |= OHCI_USB_RESET;
586 val = 50 /* msec wait */;
587 break;
588 }
589 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
590 // flush the writes
591 (void) ohci_readl (ohci, &ohci->regs->control);
592 msleep(val);
593
594 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
595
596 /* 2msec timelimit here means no irqs/preempt */
597 spin_lock_irq (&ohci->lock);
598
599 retry:
600 /* HC Reset requires max 10 us delay */
601 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
602 val = 30; /* ... allow extra time */
603 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
604 if (--val == 0) {
605 spin_unlock_irq (&ohci->lock);
606 ohci_err (ohci, "USB HC reset timed out!\n");
607 return -1;
608 }
609 udelay (1);
610 }
611
612 /* now we're in the SUSPEND state ... must go OPERATIONAL
613 * within 2msec else HC enters RESUME
614 *
615 * ... but some hardware won't init fmInterval "by the book"
616 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
617 * this if we write fmInterval after we're OPERATIONAL.
618 * Unclear about ALi, ServerWorks, and others ... this could
619 * easily be a longstanding bug in chip init on Linux.
620 */
621 if (ohci->flags & OHCI_QUIRK_INITRESET) {
622 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 // flush those writes
624 (void) ohci_readl (ohci, &ohci->regs->control);
625 }
626
627 /* Tell the controller where the control and bulk lists are
628 * The lists are empty now. */
629 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
630 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
631
632 /* a reset clears this */
633 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
634
635 periodic_reinit (ohci);
636
637 /* some OHCI implementations are finicky about how they init.
638 * bogus values here mean not even enumeration could work.
639 */
640 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
641 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
642 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
643 ohci->flags |= OHCI_QUIRK_INITRESET;
644 ohci_dbg (ohci, "enabling initreset quirk\n");
645 goto retry;
646 }
647 spin_unlock_irq (&ohci->lock);
648 ohci_err (ohci, "init err (%08x %04x)\n",
649 ohci_readl (ohci, &ohci->regs->fminterval),
650 ohci_readl (ohci, &ohci->regs->periodicstart));
651 return -EOVERFLOW;
652 }
653
654 /* use rhsc irqs after hub_wq is allocated */
655 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
656 hcd->uses_new_polling = 1;
657
658 /* start controller operations */
659 ohci->hc_control &= OHCI_CTRL_RWC;
660 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
661 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
662 ohci->rh_state = OHCI_RH_RUNNING;
663
664 /* wake on ConnectStatusChange, matching external hubs */
665 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
666
667 /* Choose the interrupts we care about now, others later on demand */
668 mask = OHCI_INTR_INIT;
669 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
670 ohci_writel (ohci, mask, &ohci->regs->intrenable);
671
672 /* handle root hub init quirks ... */
673 val = roothub_a (ohci);
674 /* Configure for per-port over-current protection by default */
675 val &= ~RH_A_NOCP;
676 val |= RH_A_OCPM;
677 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
678 /* NSC 87560 and maybe others.
679 * Ganged power switching, no over-current protection.
680 */
681 val |= RH_A_NOCP;
682 val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
683 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
684 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
685 /* hub power always on; required for AMD-756 and some
686 * Mac platforms.
687 */
688 val |= RH_A_NPS;
689 }
690 ohci_writel(ohci, val, &ohci->regs->roothub.a);
691
692 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
693 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
694 &ohci->regs->roothub.b);
695 // flush those writes
696 (void) ohci_readl (ohci, &ohci->regs->control);
697
698 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
699 spin_unlock_irq (&ohci->lock);
700
701 // POTPGT delay is bits 24-31, in 2 ms units.
702 mdelay ((val >> 23) & 0x1fe);
703
704 ohci_dump(ohci);
705
706 return 0;
707 }
708
709 /* ohci_setup routine for generic controller initialization */
710
ohci_setup(struct usb_hcd * hcd)711 int ohci_setup(struct usb_hcd *hcd)
712 {
713 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
714
715 ohci_hcd_init(ohci);
716
717 return ohci_init(ohci);
718 }
719 EXPORT_SYMBOL_GPL(ohci_setup);
720
721 /* ohci_start routine for generic controller start of all OHCI bus glue */
ohci_start(struct usb_hcd * hcd)722 static int ohci_start(struct usb_hcd *hcd)
723 {
724 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
725 int ret;
726
727 ret = ohci_run(ohci);
728 if (ret < 0) {
729 ohci_err(ohci, "can't start\n");
730 ohci_stop(hcd);
731 }
732 return ret;
733 }
734
735 /*-------------------------------------------------------------------------*/
736
737 /*
738 * Some OHCI controllers are known to lose track of completed TDs. They
739 * don't add the TDs to the hardware done queue, which means we never see
740 * them as being completed.
741 *
742 * This watchdog routine checks for such problems. Without some way to
743 * tell when those TDs have completed, we would never take their EDs off
744 * the unlink list. As a result, URBs could never be dequeued and
745 * endpoints could never be released.
746 */
io_watchdog_func(struct timer_list * t)747 static void io_watchdog_func(struct timer_list *t)
748 {
749 struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
750 bool takeback_all_pending = false;
751 u32 status;
752 u32 head;
753 struct ed *ed;
754 struct td *td, *td_start, *td_next;
755 unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF;
756 unsigned long flags;
757
758 spin_lock_irqsave(&ohci->lock, flags);
759
760 /*
761 * One way to lose track of completed TDs is if the controller
762 * never writes back the done queue head. If it hasn't been
763 * written back since the last time this function ran and if it
764 * was non-empty at that time, something is badly wrong with the
765 * hardware.
766 */
767 status = ohci_readl(ohci, &ohci->regs->intrstatus);
768 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
769 if (ohci->prev_donehead) {
770 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
771 died:
772 usb_hc_died(ohci_to_hcd(ohci));
773 ohci_dump(ohci);
774 _ohci_shutdown(ohci_to_hcd(ohci));
775 goto done;
776 } else {
777 /* No write back because the done queue was empty */
778 takeback_all_pending = true;
779 }
780 }
781
782 /* Check every ED which might have pending TDs */
783 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
784 if (ed->pending_td) {
785 if (takeback_all_pending ||
786 OKAY_TO_TAKEBACK(ohci, ed)) {
787 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
788
789 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
790 0x007f & tmp,
791 (0x000f & (tmp >> 7)) +
792 ((tmp & ED_IN) >> 5));
793 add_to_done_list(ohci, ed->pending_td);
794 }
795 }
796
797 /* Starting from the latest pending TD, */
798 td = ed->pending_td;
799
800 /* or the last TD on the done list, */
801 if (!td) {
802 list_for_each_entry(td_next, &ed->td_list, td_list) {
803 if (!td_next->next_dl_td)
804 break;
805 td = td_next;
806 }
807 }
808
809 /* find the last TD processed by the controller. */
810 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
811 td_start = td;
812 td_next = list_prepare_entry(td, &ed->td_list, td_list);
813 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
814 if (head == (u32) td_next->td_dma)
815 break;
816 td = td_next; /* head pointer has passed this TD */
817 }
818 if (td != td_start) {
819 /*
820 * In case a WDH cycle is in progress, we will wait
821 * for the next two cycles to complete before assuming
822 * this TD will never get on the done queue.
823 */
824 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
825 ed->pending_td = td;
826 }
827 }
828
829 ohci_work(ohci);
830
831 if (ohci->rh_state == OHCI_RH_RUNNING) {
832
833 /*
834 * Sometimes a controller just stops working. We can tell
835 * by checking that the frame counter has advanced since
836 * the last time we ran.
837 *
838 * But be careful: Some controllers violate the spec by
839 * stopping their frame counter when no ports are active.
840 */
841 frame_no = ohci_frame_no(ohci);
842 if (frame_no == ohci->prev_frame_no) {
843 int active_cnt = 0;
844 int i;
845 unsigned tmp;
846
847 for (i = 0; i < ohci->num_ports; ++i) {
848 tmp = roothub_portstatus(ohci, i);
849 /* Enabled and not suspended? */
850 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
851 ++active_cnt;
852 }
853
854 if (active_cnt > 0) {
855 ohci_err(ohci, "frame counter not updating; disabled\n");
856 goto died;
857 }
858 }
859 if (!list_empty(&ohci->eds_in_use)) {
860 prev_frame_no = frame_no;
861 ohci->prev_wdh_cnt = ohci->wdh_cnt;
862 ohci->prev_donehead = ohci_readl(ohci,
863 &ohci->regs->donehead);
864 mod_timer(&ohci->io_watchdog,
865 jiffies + IO_WATCHDOG_DELAY);
866 }
867 }
868
869 done:
870 ohci->prev_frame_no = prev_frame_no;
871 spin_unlock_irqrestore(&ohci->lock, flags);
872 }
873
874 /* an interrupt happens */
875
ohci_irq(struct usb_hcd * hcd)876 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
877 {
878 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
879 struct ohci_regs __iomem *regs = ohci->regs;
880 int ints;
881
882 /* Read interrupt status (and flush pending writes). We ignore the
883 * optimization of checking the LSB of hcca->done_head; it doesn't
884 * work on all systems (edge triggering for OHCI can be a factor).
885 */
886 ints = ohci_readl(ohci, ®s->intrstatus);
887
888 /* Check for an all 1's result which is a typical consequence
889 * of dead, unclocked, or unplugged (CardBus...) devices
890 */
891 if (ints == ~(u32)0) {
892 ohci->rh_state = OHCI_RH_HALTED;
893 ohci_dbg (ohci, "device removed!\n");
894 usb_hc_died(hcd);
895 return IRQ_HANDLED;
896 }
897
898 /* We only care about interrupts that are enabled */
899 ints &= ohci_readl(ohci, ®s->intrenable);
900
901 /* interrupt for some other device? */
902 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
903 return IRQ_NOTMINE;
904
905 if (ints & OHCI_INTR_UE) {
906 // e.g. due to PCI Master/Target Abort
907 if (quirk_nec(ohci)) {
908 /* Workaround for a silicon bug in some NEC chips used
909 * in Apple's PowerBooks. Adapted from Darwin code.
910 */
911 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
912
913 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
914
915 schedule_work (&ohci->nec_work);
916 } else {
917 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
918 ohci->rh_state = OHCI_RH_HALTED;
919 usb_hc_died(hcd);
920 }
921
922 ohci_dump(ohci);
923 ohci_usb_reset (ohci);
924 }
925
926 if (ints & OHCI_INTR_RHSC) {
927 ohci_dbg(ohci, "rhsc\n");
928 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
929 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
930 ®s->intrstatus);
931
932 /* NOTE: Vendors didn't always make the same implementation
933 * choices for RHSC. Many followed the spec; RHSC triggers
934 * on an edge, like setting and maybe clearing a port status
935 * change bit. With others it's level-triggered, active
936 * until hub_wq clears all the port status change bits. We'll
937 * always disable it here and rely on polling until hub_wq
938 * re-enables it.
939 */
940 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
941 usb_hcd_poll_rh_status(hcd);
942 }
943
944 /* For connect and disconnect events, we expect the controller
945 * to turn on RHSC along with RD. But for remote wakeup events
946 * this might not happen.
947 */
948 else if (ints & OHCI_INTR_RD) {
949 ohci_dbg(ohci, "resume detect\n");
950 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
951 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
952 if (ohci->autostop) {
953 spin_lock (&ohci->lock);
954 ohci_rh_resume (ohci);
955 spin_unlock (&ohci->lock);
956 } else
957 usb_hcd_resume_root_hub(hcd);
958 }
959
960 spin_lock(&ohci->lock);
961 if (ints & OHCI_INTR_WDH)
962 update_done_list(ohci);
963
964 /* could track INTR_SO to reduce available PCI/... bandwidth */
965
966 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
967 * when there's still unlinking to be done (next frame).
968 */
969 ohci_work(ohci);
970 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
971 && ohci->rh_state == OHCI_RH_RUNNING)
972 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
973
974 if (ohci->rh_state == OHCI_RH_RUNNING) {
975 ohci_writel (ohci, ints, ®s->intrstatus);
976 if (ints & OHCI_INTR_WDH)
977 ++ohci->wdh_cnt;
978
979 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
980 // flush those writes
981 (void) ohci_readl (ohci, &ohci->regs->control);
982 }
983 spin_unlock(&ohci->lock);
984
985 return IRQ_HANDLED;
986 }
987
988 /*-------------------------------------------------------------------------*/
989
ohci_stop(struct usb_hcd * hcd)990 static void ohci_stop (struct usb_hcd *hcd)
991 {
992 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
993
994 ohci_dump(ohci);
995
996 if (quirk_nec(ohci))
997 flush_work(&ohci->nec_work);
998 del_timer_sync(&ohci->io_watchdog);
999 ohci->prev_frame_no = IO_WATCHDOG_OFF;
1000
1001 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1002 ohci_usb_reset(ohci);
1003 free_irq(hcd->irq, hcd);
1004 hcd->irq = 0;
1005
1006 if (quirk_amdiso(ohci))
1007 usb_amd_dev_put();
1008
1009 remove_debug_files (ohci);
1010 ohci_mem_cleanup (ohci);
1011 if (ohci->hcca) {
1012 if (hcd->localmem_pool)
1013 gen_pool_free(hcd->localmem_pool,
1014 (unsigned long)ohci->hcca,
1015 sizeof(*ohci->hcca));
1016 else
1017 dma_free_coherent(hcd->self.controller,
1018 sizeof(*ohci->hcca),
1019 ohci->hcca, ohci->hcca_dma);
1020 ohci->hcca = NULL;
1021 ohci->hcca_dma = 0;
1022 }
1023 }
1024
1025 /*-------------------------------------------------------------------------*/
1026
1027 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1028
1029 /* must not be called from interrupt context */
ohci_restart(struct ohci_hcd * ohci)1030 int ohci_restart(struct ohci_hcd *ohci)
1031 {
1032 int temp;
1033 int i;
1034 struct urb_priv *priv;
1035
1036 ohci_init(ohci);
1037 spin_lock_irq(&ohci->lock);
1038 ohci->rh_state = OHCI_RH_HALTED;
1039
1040 /* Recycle any "live" eds/tds (and urbs). */
1041 if (!list_empty (&ohci->pending))
1042 ohci_dbg(ohci, "abort schedule...\n");
1043 list_for_each_entry (priv, &ohci->pending, pending) {
1044 struct urb *urb = priv->td[0]->urb;
1045 struct ed *ed = priv->ed;
1046
1047 switch (ed->state) {
1048 case ED_OPER:
1049 ed->state = ED_UNLINK;
1050 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1051 ed_deschedule (ohci, ed);
1052
1053 ed->ed_next = ohci->ed_rm_list;
1054 ed->ed_prev = NULL;
1055 ohci->ed_rm_list = ed;
1056 fallthrough;
1057 case ED_UNLINK:
1058 break;
1059 default:
1060 ohci_dbg(ohci, "bogus ed %p state %d\n",
1061 ed, ed->state);
1062 }
1063
1064 if (!urb->unlinked)
1065 urb->unlinked = -ESHUTDOWN;
1066 }
1067 ohci_work(ohci);
1068 spin_unlock_irq(&ohci->lock);
1069
1070 /* paranoia, in case that didn't work: */
1071
1072 /* empty the interrupt branches */
1073 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1074 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1075
1076 /* no EDs to remove */
1077 ohci->ed_rm_list = NULL;
1078
1079 /* empty control and bulk lists */
1080 ohci->ed_controltail = NULL;
1081 ohci->ed_bulktail = NULL;
1082
1083 if ((temp = ohci_run (ohci)) < 0) {
1084 ohci_err (ohci, "can't restart, %d\n", temp);
1085 return temp;
1086 }
1087 ohci_dbg(ohci, "restart complete\n");
1088 return 0;
1089 }
1090 EXPORT_SYMBOL_GPL(ohci_restart);
1091
1092 #endif
1093
1094 #ifdef CONFIG_PM
1095
ohci_suspend(struct usb_hcd * hcd,bool do_wakeup)1096 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1097 {
1098 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1099 unsigned long flags;
1100 int rc = 0;
1101
1102 /* Disable irq emission and mark HW unaccessible. Use
1103 * the spinlock to properly synchronize with possible pending
1104 * RH suspend or resume activity.
1105 */
1106 spin_lock_irqsave (&ohci->lock, flags);
1107 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1108 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1109
1110 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1111 spin_unlock_irqrestore (&ohci->lock, flags);
1112
1113 synchronize_irq(hcd->irq);
1114
1115 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1116 ohci_resume(hcd, false);
1117 rc = -EBUSY;
1118 }
1119 return rc;
1120 }
1121 EXPORT_SYMBOL_GPL(ohci_suspend);
1122
1123
ohci_resume(struct usb_hcd * hcd,bool hibernated)1124 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1125 {
1126 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1127 int port;
1128 bool need_reinit = false;
1129
1130 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1131
1132 /* Make sure resume from hibernation re-enumerates everything */
1133 if (hibernated)
1134 ohci_usb_reset(ohci);
1135
1136 /* See if the controller is already running or has been reset */
1137 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1138 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1139 need_reinit = true;
1140 } else {
1141 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1142 case OHCI_USB_OPER:
1143 case OHCI_USB_RESET:
1144 need_reinit = true;
1145 }
1146 }
1147
1148 /* If needed, reinitialize and suspend the root hub */
1149 if (need_reinit) {
1150 spin_lock_irq(&ohci->lock);
1151 ohci_rh_resume(ohci);
1152 ohci_rh_suspend(ohci, 0);
1153 spin_unlock_irq(&ohci->lock);
1154 }
1155
1156 /* Normally just turn on port power and enable interrupts */
1157 else {
1158 ohci_dbg(ohci, "powerup ports\n");
1159 for (port = 0; port < ohci->num_ports; port++)
1160 ohci_writel(ohci, RH_PS_PPS,
1161 &ohci->regs->roothub.portstatus[port]);
1162
1163 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1164 ohci_readl(ohci, &ohci->regs->intrenable);
1165 msleep(20);
1166 }
1167
1168 usb_hcd_resume_root_hub(hcd);
1169
1170 return 0;
1171 }
1172 EXPORT_SYMBOL_GPL(ohci_resume);
1173
1174 #endif
1175
1176 /*-------------------------------------------------------------------------*/
1177
1178 /*
1179 * Generic structure: This gets copied for platform drivers so that
1180 * individual entries can be overridden as needed.
1181 */
1182
1183 static const struct hc_driver ohci_hc_driver = {
1184 .description = hcd_name,
1185 .product_desc = "OHCI Host Controller",
1186 .hcd_priv_size = sizeof(struct ohci_hcd),
1187
1188 /*
1189 * generic hardware linkage
1190 */
1191 .irq = ohci_irq,
1192 .flags = HCD_MEMORY | HCD_DMA | HCD_USB11,
1193
1194 /*
1195 * basic lifecycle operations
1196 */
1197 .reset = ohci_setup,
1198 .start = ohci_start,
1199 .stop = ohci_stop,
1200 .shutdown = ohci_shutdown,
1201
1202 /*
1203 * managing i/o requests and associated device resources
1204 */
1205 .urb_enqueue = ohci_urb_enqueue,
1206 .urb_dequeue = ohci_urb_dequeue,
1207 .endpoint_disable = ohci_endpoint_disable,
1208
1209 /*
1210 * scheduling support
1211 */
1212 .get_frame_number = ohci_get_frame,
1213
1214 /*
1215 * root hub support
1216 */
1217 .hub_status_data = ohci_hub_status_data,
1218 .hub_control = ohci_hub_control,
1219 #ifdef CONFIG_PM
1220 .bus_suspend = ohci_bus_suspend,
1221 .bus_resume = ohci_bus_resume,
1222 #endif
1223 .start_port_reset = ohci_start_port_reset,
1224 };
1225
ohci_init_driver(struct hc_driver * drv,const struct ohci_driver_overrides * over)1226 void ohci_init_driver(struct hc_driver *drv,
1227 const struct ohci_driver_overrides *over)
1228 {
1229 /* Copy the generic table to drv and then apply the overrides */
1230 *drv = ohci_hc_driver;
1231
1232 if (over) {
1233 drv->product_desc = over->product_desc;
1234 drv->hcd_priv_size += over->extra_priv_size;
1235 if (over->reset)
1236 drv->reset = over->reset;
1237 }
1238 }
1239 EXPORT_SYMBOL_GPL(ohci_init_driver);
1240
1241 /*-------------------------------------------------------------------------*/
1242
1243 MODULE_AUTHOR (DRIVER_AUTHOR);
1244 MODULE_DESCRIPTION(DRIVER_DESC);
1245 MODULE_LICENSE ("GPL");
1246
1247 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1248 #include "ohci-sa1111.c"
1249 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1250 #endif
1251
1252 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1253 #include "ohci-ppc-of.c"
1254 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1255 #endif
1256
1257 #ifdef CONFIG_PPC_PS3
1258 #include "ohci-ps3.c"
1259 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1260 #endif
1261
1262 #ifdef CONFIG_MFD_SM501
1263 #include "ohci-sm501.c"
1264 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1265 #endif
1266
1267 #ifdef CONFIG_MFD_TC6393XB
1268 #include "ohci-tmio.c"
1269 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1270 #endif
1271
ohci_hcd_mod_init(void)1272 static int __init ohci_hcd_mod_init(void)
1273 {
1274 int retval = 0;
1275
1276 if (usb_disabled())
1277 return -ENODEV;
1278
1279 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1280 sizeof (struct ed), sizeof (struct td));
1281 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1282
1283 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1284
1285 #ifdef PS3_SYSTEM_BUS_DRIVER
1286 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1287 if (retval < 0)
1288 goto error_ps3;
1289 #endif
1290
1291 #ifdef OF_PLATFORM_DRIVER
1292 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1293 if (retval < 0)
1294 goto error_of_platform;
1295 #endif
1296
1297 #ifdef SA1111_DRIVER
1298 retval = sa1111_driver_register(&SA1111_DRIVER);
1299 if (retval < 0)
1300 goto error_sa1111;
1301 #endif
1302
1303 #ifdef SM501_OHCI_DRIVER
1304 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1305 if (retval < 0)
1306 goto error_sm501;
1307 #endif
1308
1309 #ifdef TMIO_OHCI_DRIVER
1310 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1311 if (retval < 0)
1312 goto error_tmio;
1313 #endif
1314
1315 return retval;
1316
1317 /* Error path */
1318 #ifdef TMIO_OHCI_DRIVER
1319 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1320 error_tmio:
1321 #endif
1322 #ifdef SM501_OHCI_DRIVER
1323 platform_driver_unregister(&SM501_OHCI_DRIVER);
1324 error_sm501:
1325 #endif
1326 #ifdef SA1111_DRIVER
1327 sa1111_driver_unregister(&SA1111_DRIVER);
1328 error_sa1111:
1329 #endif
1330 #ifdef OF_PLATFORM_DRIVER
1331 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1332 error_of_platform:
1333 #endif
1334 #ifdef PS3_SYSTEM_BUS_DRIVER
1335 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1336 error_ps3:
1337 #endif
1338 debugfs_remove(ohci_debug_root);
1339 ohci_debug_root = NULL;
1340
1341 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1342 return retval;
1343 }
1344 module_init(ohci_hcd_mod_init);
1345
ohci_hcd_mod_exit(void)1346 static void __exit ohci_hcd_mod_exit(void)
1347 {
1348 #ifdef TMIO_OHCI_DRIVER
1349 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1350 #endif
1351 #ifdef SM501_OHCI_DRIVER
1352 platform_driver_unregister(&SM501_OHCI_DRIVER);
1353 #endif
1354 #ifdef SA1111_DRIVER
1355 sa1111_driver_unregister(&SA1111_DRIVER);
1356 #endif
1357 #ifdef OF_PLATFORM_DRIVER
1358 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1359 #endif
1360 #ifdef PS3_SYSTEM_BUS_DRIVER
1361 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1362 #endif
1363 debugfs_remove(ohci_debug_root);
1364 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1365 }
1366 module_exit(ohci_hcd_mod_exit);
1367
1368