1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_TXRX_H
9 #define OTX2_TXRX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/iommu.h>
13 #include <linux/if_vlan.h>
14 #include <net/xdp.h>
15
16 #define LBK_CHAN_BASE 0x000
17 #define SDP_CHAN_BASE 0x700
18 #define CGX_CHAN_BASE 0x800
19
20 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
21 #define OTX2_HEAD_ROOM OTX2_ALIGN
22
23 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
24 #define OTX2_MIN_MTU 60
25
26 #define OTX2_MAX_GSO_SEGS 255
27 #define OTX2_MAX_FRAGS_IN_SQE 9
28
29 #define MAX_XDP_MTU (1530 - OTX2_ETH_HLEN)
30
31 /* Rx buffer size should be in multiples of 128bytes */
32 #define RCV_FRAG_LEN1(x) \
33 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
34 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
35
36 /* Prefer 2048 byte buffers for better last level cache
37 * utilization or data distribution across regions.
38 */
39 #define RCV_FRAG_LEN(x) \
40 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
41
42 #define DMA_BUFFER_LEN(x) ((x) - OTX2_HEAD_ROOM)
43
44 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
45 * is equal to this value.
46 */
47 #define CQ_CQE_THRESH_DEFAULT 10
48
49 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
50 * is nonzero and this much time elapses after that.
51 */
52 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
53 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
54
55 /* Min number of CQs (of the ones mapped to this CINT)
56 * with valid CQEs.
57 */
58 #define CQ_QCOUNT_DEFAULT 1
59
60 #define CQ_OP_STAT_OP_ERR 63
61 #define CQ_OP_STAT_CQ_ERR 46
62
63 struct queue_stats {
64 u64 bytes;
65 u64 pkts;
66 };
67
68 struct otx2_rcv_queue {
69 struct queue_stats stats;
70 };
71
72 struct sg_list {
73 u16 num_segs;
74 u64 skb;
75 u64 size[OTX2_MAX_FRAGS_IN_SQE];
76 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
77 };
78
79 struct otx2_snd_queue {
80 u8 aura_id;
81 u16 head;
82 u16 cons_head;
83 u16 sqe_size;
84 u32 sqe_cnt;
85 u16 num_sqbs;
86 u16 sqe_thresh;
87 u8 sqe_per_sqb;
88 u64 io_addr;
89 u64 *aura_fc_addr;
90 u64 *lmt_addr;
91 void *sqe_base;
92 struct qmem *sqe;
93 struct qmem *tso_hdrs;
94 struct sg_list *sg;
95 struct qmem *timestamps;
96 struct queue_stats stats;
97 u16 sqb_count;
98 u64 *sqb_ptrs;
99 } ____cacheline_aligned_in_smp;
100
101 enum cq_type {
102 CQ_RX,
103 CQ_TX,
104 CQ_XDP,
105 CQ_QOS,
106 CQS_PER_CINT = 4, /* RQ + SQ + XDP + QOS_SQ */
107 };
108
109 struct otx2_cq_poll {
110 void *dev;
111 #define CINT_INVALID_CQ 255
112 u8 cint_idx;
113 u8 cq_ids[CQS_PER_CINT];
114 struct dim dim;
115 struct napi_struct napi;
116 };
117
118 struct otx2_pool {
119 struct qmem *stack;
120 struct qmem *fc_addr;
121 u16 rbsize;
122 };
123
124 struct otx2_cq_queue {
125 u8 cq_idx;
126 u8 cq_type;
127 u8 cint_idx; /* CQ interrupt id */
128 u8 refill_task_sched;
129 u16 cqe_size;
130 u16 pool_ptrs;
131 u32 cqe_cnt;
132 u32 cq_head;
133 u32 cq_tail;
134 u32 pend_cqe;
135 void *cqe_base;
136 struct qmem *cqe;
137 struct otx2_pool *rbpool;
138 struct xdp_rxq_info xdp_rxq;
139 } ____cacheline_aligned_in_smp;
140
141 struct otx2_qset {
142 u32 rqe_cnt;
143 u32 sqe_cnt; /* Keep these two at top */
144 #define OTX2_MAX_CQ_CNT 64
145 u16 cq_cnt;
146 u16 xqe_size;
147 struct otx2_pool *pool;
148 struct otx2_cq_poll *napi;
149 struct otx2_cq_queue *cq;
150 struct otx2_snd_queue *sq;
151 struct otx2_rcv_queue *rq;
152 };
153
154 /* Translate IOVA to physical address */
otx2_iova_to_phys(void * iommu_domain,dma_addr_t dma_addr)155 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
156 {
157 /* Translation is installed only when IOMMU is present */
158 if (likely(iommu_domain))
159 return iommu_iova_to_phys(iommu_domain, dma_addr);
160 return dma_addr;
161 }
162
163 int otx2_napi_handler(struct napi_struct *napi, int budget);
164 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
165 struct sk_buff *skb, u16 qidx);
166 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
167 int size, int qidx);
168 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
169 int size, int qidx);
170 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
171 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
172 #endif /* OTX2_TXRX_H */
173