1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/etherdevice.h>
9 #include <net/ip.h>
10 #include <net/tso.h>
11 #include <linux/bpf.h>
12 #include <linux/bpf_trace.h>
13 #include <net/ip6_checksum.h>
14
15 #include "otx2_reg.h"
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
18 #include "otx2_txrx.h"
19 #include "otx2_ptp.h"
20 #include "cn10k.h"
21
22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))
23 #define PTP_PORT 0x13F
24 /* PTPv2 header Original Timestamp starts at byte offset 34 and
25 * contains 6 byte seconds field and 4 byte nano seconds field.
26 */
27 #define PTP_SYNC_SEC_OFFSET 34
28
29 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
30 struct bpf_prog *prog,
31 struct nix_cqe_rx_s *cqe,
32 struct otx2_cq_queue *cq,
33 bool *need_xdp_flush);
34
otx2_nix_cq_op_status(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)35 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf,
36 struct otx2_cq_queue *cq)
37 {
38 u64 incr = (u64)(cq->cq_idx) << 32;
39 u64 status;
40
41 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr);
42
43 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
44 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) {
45 dev_err(pfvf->dev, "CQ stopped due to error");
46 return -EINVAL;
47 }
48
49 cq->cq_tail = status & 0xFFFFF;
50 cq->cq_head = (status >> 20) & 0xFFFFF;
51 if (cq->cq_tail < cq->cq_head)
52 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) +
53 cq->cq_tail;
54 else
55 cq->pend_cqe = cq->cq_tail - cq->cq_head;
56
57 return 0;
58 }
59
otx2_get_next_cqe(struct otx2_cq_queue * cq)60 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq)
61 {
62 struct nix_cqe_hdr_s *cqe_hdr;
63
64 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head);
65 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID)
66 return NULL;
67
68 cq->cq_head++;
69 cq->cq_head &= (cq->cqe_cnt - 1);
70
71 return cqe_hdr;
72 }
73
frag_num(unsigned int i)74 static unsigned int frag_num(unsigned int i)
75 {
76 #ifdef __BIG_ENDIAN
77 return (i & ~3) + 3 - (i & 3);
78 #else
79 return i;
80 #endif
81 }
82
otx2_dma_map_skb_frag(struct otx2_nic * pfvf,struct sk_buff * skb,int seg,int * len)83 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
84 struct sk_buff *skb, int seg, int *len)
85 {
86 const skb_frag_t *frag;
87 struct page *page;
88 int offset;
89
90 /* First segment is always skb->data */
91 if (!seg) {
92 page = virt_to_page(skb->data);
93 offset = offset_in_page(skb->data);
94 *len = skb_headlen(skb);
95 } else {
96 frag = &skb_shinfo(skb)->frags[seg - 1];
97 page = skb_frag_page(frag);
98 offset = skb_frag_off(frag);
99 *len = skb_frag_size(frag);
100 }
101 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE);
102 }
103
otx2_dma_unmap_skb_frags(struct otx2_nic * pfvf,struct sg_list * sg)104 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
105 {
106 int seg;
107
108 for (seg = 0; seg < sg->num_segs; seg++) {
109 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
110 sg->size[seg], DMA_TO_DEVICE);
111 }
112 sg->num_segs = 0;
113 }
114
otx2_xdp_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe)115 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf,
116 struct otx2_snd_queue *sq,
117 struct nix_cqe_tx_s *cqe)
118 {
119 struct nix_send_comp_s *snd_comp = &cqe->comp;
120 struct sg_list *sg;
121 struct page *page;
122 u64 pa;
123
124 sg = &sq->sg[snd_comp->sqe_id];
125
126 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]);
127 otx2_dma_unmap_page(pfvf, sg->dma_addr[0],
128 sg->size[0], DMA_TO_DEVICE);
129 page = virt_to_page(phys_to_virt(pa));
130 put_page(page);
131 }
132
otx2_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe,int budget,int * tx_pkts,int * tx_bytes)133 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf,
134 struct otx2_cq_queue *cq,
135 struct otx2_snd_queue *sq,
136 struct nix_cqe_tx_s *cqe,
137 int budget, int *tx_pkts, int *tx_bytes)
138 {
139 struct nix_send_comp_s *snd_comp = &cqe->comp;
140 struct skb_shared_hwtstamps ts;
141 struct sk_buff *skb = NULL;
142 u64 timestamp, tsns;
143 struct sg_list *sg;
144 int err;
145
146 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf))
147 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n",
148 pfvf->netdev->name, cq->cint_idx,
149 snd_comp->status);
150
151 sg = &sq->sg[snd_comp->sqe_id];
152 skb = (struct sk_buff *)sg->skb;
153 if (unlikely(!skb))
154 return;
155
156 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
157 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id];
158 if (timestamp != 1) {
159 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp);
160 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
161 if (!err) {
162 memset(&ts, 0, sizeof(ts));
163 ts.hwtstamp = ns_to_ktime(tsns);
164 skb_tstamp_tx(skb, &ts);
165 }
166 }
167 }
168
169 *tx_bytes += skb->len;
170 (*tx_pkts)++;
171 otx2_dma_unmap_skb_frags(pfvf, sg);
172 napi_consume_skb(skb, budget);
173 sg->skb = (u64)NULL;
174 }
175
otx2_set_rxtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,void * data)176 static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
177 struct sk_buff *skb, void *data)
178 {
179 u64 timestamp, tsns;
180 int err;
181
182 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
183 return;
184
185 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data);
186 /* The first 8 bytes is the timestamp */
187 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
188 if (err)
189 return;
190
191 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
192 }
193
otx2_skb_add_frag(struct otx2_nic * pfvf,struct sk_buff * skb,u64 iova,int len,struct nix_rx_parse_s * parse,int qidx)194 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
195 u64 iova, int len, struct nix_rx_parse_s *parse,
196 int qidx)
197 {
198 struct page *page;
199 int off = 0;
200 void *va;
201
202 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
203
204 if (likely(!skb_shinfo(skb)->nr_frags)) {
205 /* Check if data starts at some nonzero offset
206 * from the start of the buffer. For now the
207 * only possible offset is 8 bytes in the case
208 * where packet is prepended by a timestamp.
209 */
210 if (parse->laptr) {
211 otx2_set_rxtstamp(pfvf, skb, va);
212 off = OTX2_HW_TIMESTAMP_LEN;
213 }
214 }
215
216 page = virt_to_page(va);
217 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) {
218 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
219 va - page_address(page) + off,
220 len - off, pfvf->rbsize);
221
222 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM,
223 pfvf->rbsize, DMA_FROM_DEVICE);
224 return true;
225 }
226
227 /* If more than MAX_SKB_FRAGS fragments are received then
228 * give back those buffer pointers to hardware for reuse.
229 */
230 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL);
231
232 return false;
233 }
234
otx2_set_rxhash(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,struct sk_buff * skb)235 static void otx2_set_rxhash(struct otx2_nic *pfvf,
236 struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
237 {
238 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
239 struct otx2_rss_info *rss;
240 u32 hash = 0;
241
242 if (!(pfvf->netdev->features & NETIF_F_RXHASH))
243 return;
244
245 rss = &pfvf->hw.rss_info;
246 if (rss->flowkey_cfg) {
247 if (rss->flowkey_cfg &
248 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
249 hash_type = PKT_HASH_TYPE_L4;
250 else
251 hash_type = PKT_HASH_TYPE_L3;
252 hash = cqe->hdr.flow_tag;
253 }
254 skb_set_hash(skb, hash, hash_type);
255 }
256
otx2_free_rcv_seg(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)257 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe,
258 int qidx)
259 {
260 struct nix_rx_sg_s *sg = &cqe->sg;
261 void *end, *start;
262 u64 *seg_addr;
263 int seg;
264
265 start = (void *)sg;
266 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
267 while (start < end) {
268 sg = (struct nix_rx_sg_s *)start;
269 seg_addr = &sg->seg_addr;
270 for (seg = 0; seg < sg->segs; seg++, seg_addr++)
271 pfvf->hw_ops->aura_freeptr(pfvf, qidx,
272 *seg_addr & ~0x07ULL);
273 start += sizeof(*sg);
274 }
275 }
276
otx2_check_rcv_errors(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)277 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf,
278 struct nix_cqe_rx_s *cqe, int qidx)
279 {
280 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats;
281 struct nix_rx_parse_s *parse = &cqe->parse;
282
283 if (netif_msg_rx_err(pfvf))
284 netdev_err(pfvf->netdev,
285 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n",
286 qidx, parse->errlev, parse->errcode);
287
288 if (parse->errlev == NPC_ERRLVL_RE) {
289 switch (parse->errcode) {
290 case ERRCODE_FCS:
291 case ERRCODE_FCS_RCV:
292 atomic_inc(&stats->rx_fcs_errs);
293 break;
294 case ERRCODE_UNDERSIZE:
295 atomic_inc(&stats->rx_undersize_errs);
296 break;
297 case ERRCODE_OVERSIZE:
298 atomic_inc(&stats->rx_oversize_errs);
299 break;
300 case ERRCODE_OL2_LEN_MISMATCH:
301 atomic_inc(&stats->rx_len_errs);
302 break;
303 default:
304 atomic_inc(&stats->rx_other_errs);
305 break;
306 }
307 } else if (parse->errlev == NPC_ERRLVL_NIX) {
308 switch (parse->errcode) {
309 case ERRCODE_OL3_LEN:
310 case ERRCODE_OL4_LEN:
311 case ERRCODE_IL3_LEN:
312 case ERRCODE_IL4_LEN:
313 atomic_inc(&stats->rx_len_errs);
314 break;
315 case ERRCODE_OL4_CSUM:
316 case ERRCODE_IL4_CSUM:
317 atomic_inc(&stats->rx_csum_errs);
318 break;
319 default:
320 atomic_inc(&stats->rx_other_errs);
321 break;
322 }
323 } else {
324 atomic_inc(&stats->rx_other_errs);
325 /* For now ignore all the NPC parser errors and
326 * pass the packets to stack.
327 */
328 return false;
329 }
330
331 /* If RXALL is enabled pass on packets to stack. */
332 if (pfvf->netdev->features & NETIF_F_RXALL)
333 return false;
334
335 /* Free buffer back to pool */
336 if (cqe->sg.segs)
337 otx2_free_rcv_seg(pfvf, cqe, qidx);
338 return true;
339 }
340
otx2_rcv_pkt_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,struct nix_cqe_rx_s * cqe,bool * need_xdp_flush)341 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf,
342 struct napi_struct *napi,
343 struct otx2_cq_queue *cq,
344 struct nix_cqe_rx_s *cqe, bool *need_xdp_flush)
345 {
346 struct nix_rx_parse_s *parse = &cqe->parse;
347 struct nix_rx_sg_s *sg = &cqe->sg;
348 struct sk_buff *skb = NULL;
349 void *end, *start;
350 u64 *seg_addr;
351 u16 *seg_size;
352 int seg;
353
354 if (unlikely(parse->errlev || parse->errcode)) {
355 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx))
356 return;
357 }
358
359 if (pfvf->xdp_prog)
360 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq, need_xdp_flush))
361 return;
362
363 skb = napi_get_frags(napi);
364 if (unlikely(!skb))
365 return;
366
367 start = (void *)sg;
368 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
369 while (start < end) {
370 sg = (struct nix_rx_sg_s *)start;
371 seg_addr = &sg->seg_addr;
372 seg_size = (void *)sg;
373 for (seg = 0; seg < sg->segs; seg++, seg_addr++) {
374 if (otx2_skb_add_frag(pfvf, skb, *seg_addr,
375 seg_size[seg], parse, cq->cq_idx))
376 cq->pool_ptrs++;
377 }
378 start += sizeof(*sg);
379 }
380 otx2_set_rxhash(pfvf, cqe, skb);
381
382 skb_record_rx_queue(skb, cq->cq_idx);
383 if (pfvf->netdev->features & NETIF_F_RXCSUM)
384 skb->ip_summed = CHECKSUM_UNNECESSARY;
385
386 napi_gro_frags(napi);
387 }
388
otx2_rx_napi_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,int budget)389 static int otx2_rx_napi_handler(struct otx2_nic *pfvf,
390 struct napi_struct *napi,
391 struct otx2_cq_queue *cq, int budget)
392 {
393 bool need_xdp_flush = false;
394 struct nix_cqe_rx_s *cqe;
395 int processed_cqe = 0;
396
397 if (cq->pend_cqe >= budget)
398 goto process_cqe;
399
400 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
401 return 0;
402
403 process_cqe:
404 while (likely(processed_cqe < budget) && cq->pend_cqe) {
405 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head);
406 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID ||
407 !cqe->sg.seg_addr) {
408 if (!processed_cqe)
409 return 0;
410 break;
411 }
412 cq->cq_head++;
413 cq->cq_head &= (cq->cqe_cnt - 1);
414
415 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe, &need_xdp_flush);
416
417 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
418 cqe->sg.seg_addr = 0x00;
419 processed_cqe++;
420 cq->pend_cqe--;
421 }
422 if (need_xdp_flush)
423 xdp_do_flush();
424
425 /* Free CQEs to HW */
426 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
427 ((u64)cq->cq_idx << 32) | processed_cqe);
428
429 return processed_cqe;
430 }
431
otx2_refill_pool_ptrs(void * dev,struct otx2_cq_queue * cq)432 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq)
433 {
434 struct otx2_nic *pfvf = dev;
435 dma_addr_t bufptr;
436
437 while (cq->pool_ptrs) {
438 if (otx2_alloc_buffer(pfvf, cq, &bufptr))
439 break;
440 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM);
441 cq->pool_ptrs--;
442 }
443 }
444
otx2_tx_napi_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int budget)445 static int otx2_tx_napi_handler(struct otx2_nic *pfvf,
446 struct otx2_cq_queue *cq, int budget)
447 {
448 int tx_pkts = 0, tx_bytes = 0, qidx;
449 struct otx2_snd_queue *sq;
450 struct nix_cqe_tx_s *cqe;
451 int processed_cqe = 0;
452
453 if (cq->pend_cqe >= budget)
454 goto process_cqe;
455
456 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
457 return 0;
458
459 process_cqe:
460 qidx = cq->cq_idx - pfvf->hw.rx_queues;
461 sq = &pfvf->qset.sq[qidx];
462
463 while (likely(processed_cqe < budget) && cq->pend_cqe) {
464 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
465 if (unlikely(!cqe)) {
466 if (!processed_cqe)
467 return 0;
468 break;
469 }
470
471 qidx = cq->cq_idx - pfvf->hw.rx_queues;
472
473 if (cq->cq_type == CQ_XDP)
474 otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
475 else
476 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[qidx],
477 cqe, budget, &tx_pkts, &tx_bytes);
478
479 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
480 processed_cqe++;
481 cq->pend_cqe--;
482
483 sq->cons_head++;
484 sq->cons_head &= (sq->sqe_cnt - 1);
485 }
486
487 /* Free CQEs to HW */
488 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
489 ((u64)cq->cq_idx << 32) | processed_cqe);
490
491 if (likely(tx_pkts)) {
492 struct netdev_queue *txq;
493
494 qidx = cq->cq_idx - pfvf->hw.rx_queues;
495
496 if (qidx >= pfvf->hw.tx_queues)
497 qidx -= pfvf->hw.xdp_queues;
498 txq = netdev_get_tx_queue(pfvf->netdev, qidx);
499 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
500 /* Check if queue was stopped earlier due to ring full */
501 smp_mb();
502 if (netif_tx_queue_stopped(txq) &&
503 netif_carrier_ok(pfvf->netdev))
504 netif_tx_wake_queue(txq);
505 }
506 return 0;
507 }
508
otx2_adjust_adaptive_coalese(struct otx2_nic * pfvf,struct otx2_cq_poll * cq_poll)509 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll)
510 {
511 struct dim_sample dim_sample;
512 u64 rx_frames, rx_bytes;
513 u64 tx_frames, tx_bytes;
514
515 rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) +
516 OTX2_GET_RX_STATS(RX_UCAST);
517 rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
518 tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
519 tx_frames = OTX2_GET_TX_STATS(TX_UCAST);
520
521 dim_update_sample(pfvf->napi_events,
522 rx_frames + tx_frames,
523 rx_bytes + tx_bytes,
524 &dim_sample);
525 net_dim(&cq_poll->dim, dim_sample);
526 }
527
otx2_napi_handler(struct napi_struct * napi,int budget)528 int otx2_napi_handler(struct napi_struct *napi, int budget)
529 {
530 struct otx2_cq_queue *rx_cq = NULL;
531 struct otx2_cq_poll *cq_poll;
532 int workdone = 0, cq_idx, i;
533 struct otx2_cq_queue *cq;
534 struct otx2_qset *qset;
535 struct otx2_nic *pfvf;
536
537 cq_poll = container_of(napi, struct otx2_cq_poll, napi);
538 pfvf = (struct otx2_nic *)cq_poll->dev;
539 qset = &pfvf->qset;
540
541 for (i = 0; i < CQS_PER_CINT; i++) {
542 cq_idx = cq_poll->cq_ids[i];
543 if (unlikely(cq_idx == CINT_INVALID_CQ))
544 continue;
545 cq = &qset->cq[cq_idx];
546 if (cq->cq_type == CQ_RX) {
547 rx_cq = cq;
548 workdone += otx2_rx_napi_handler(pfvf, napi,
549 cq, budget);
550 } else {
551 workdone += otx2_tx_napi_handler(pfvf, cq, budget);
552 }
553 }
554
555 if (rx_cq && rx_cq->pool_ptrs)
556 pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq);
557 /* Clear the IRQ */
558 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
559
560 if (workdone < budget && napi_complete_done(napi, workdone)) {
561 /* If interface is going down, don't re-enable IRQ */
562 if (pfvf->flags & OTX2_FLAG_INTF_DOWN)
563 return workdone;
564
565 /* Adjust irq coalese using net_dim */
566 if (pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED)
567 otx2_adjust_adaptive_coalese(pfvf, cq_poll);
568
569 /* Re-enable interrupts */
570 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
571 BIT_ULL(0));
572 }
573 return workdone;
574 }
575
otx2_sqe_flush(void * dev,struct otx2_snd_queue * sq,int size,int qidx)576 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
577 int size, int qidx)
578 {
579 u64 status;
580
581 /* Packet data stores should finish before SQE is flushed to HW */
582 dma_wmb();
583
584 do {
585 memcpy(sq->lmt_addr, sq->sqe_base, size);
586 status = otx2_lmt_flush(sq->io_addr);
587 } while (status == 0);
588
589 sq->head++;
590 sq->head &= (sq->sqe_cnt - 1);
591 }
592
593 #define MAX_SEGS_PER_SG 3
594 /* Add SQE scatter/gather subdescriptor structure */
otx2_sqe_add_sg(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int num_segs,int * offset)595 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
596 struct sk_buff *skb, int num_segs, int *offset)
597 {
598 struct nix_sqe_sg_s *sg = NULL;
599 u64 dma_addr, *iova = NULL;
600 u16 *sg_lens = NULL;
601 int seg, len;
602
603 sq->sg[sq->head].num_segs = 0;
604
605 for (seg = 0; seg < num_segs; seg++) {
606 if ((seg % MAX_SEGS_PER_SG) == 0) {
607 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
608 sg->ld_type = NIX_SEND_LDTYPE_LDD;
609 sg->subdc = NIX_SUBDC_SG;
610 sg->segs = 0;
611 sg_lens = (void *)sg;
612 iova = (void *)sg + sizeof(*sg);
613 /* Next subdc always starts at a 16byte boundary.
614 * So if sg->segs is whether 2 or 3, offset += 16bytes.
615 */
616 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
617 *offset += sizeof(*sg) + (3 * sizeof(u64));
618 else
619 *offset += sizeof(*sg) + sizeof(u64);
620 }
621 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
622 if (dma_mapping_error(pfvf->dev, dma_addr))
623 return false;
624
625 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len;
626 sg->segs++;
627 *iova++ = dma_addr;
628
629 /* Save DMA mapping info for later unmapping */
630 sq->sg[sq->head].dma_addr[seg] = dma_addr;
631 sq->sg[sq->head].size[seg] = len;
632 sq->sg[sq->head].num_segs++;
633 }
634
635 sq->sg[sq->head].skb = (u64)skb;
636 return true;
637 }
638
639 /* Add SQE extended header subdescriptor */
otx2_sqe_add_ext(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int * offset)640 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
641 struct sk_buff *skb, int *offset)
642 {
643 struct nix_sqe_ext_s *ext;
644
645 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset);
646 ext->subdc = NIX_SUBDC_EXT;
647 if (skb_shinfo(skb)->gso_size) {
648 ext->lso = 1;
649 ext->lso_sb = skb_tcp_all_headers(skb);
650 ext->lso_mps = skb_shinfo(skb)->gso_size;
651
652 /* Only TSOv4 and TSOv6 GSO offloads are supported */
653 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
654 ext->lso_format = pfvf->hw.lso_tsov4_idx;
655
656 /* HW adds payload size to 'ip_hdr->tot_len' while
657 * sending TSO segment, hence set payload length
658 * in IP header of the packet to just header length.
659 */
660 ip_hdr(skb)->tot_len =
661 htons(ext->lso_sb - skb_network_offset(skb));
662 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
663 ext->lso_format = pfvf->hw.lso_tsov6_idx;
664 ipv6_hdr(skb)->payload_len = htons(tcp_hdrlen(skb));
665 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
666 __be16 l3_proto = vlan_get_protocol(skb);
667 struct udphdr *udph = udp_hdr(skb);
668 u16 iplen;
669
670 ext->lso_sb = skb_transport_offset(skb) +
671 sizeof(struct udphdr);
672
673 /* HW adds payload size to length fields in IP and
674 * UDP headers while segmentation, hence adjust the
675 * lengths to just header sizes.
676 */
677 iplen = htons(ext->lso_sb - skb_network_offset(skb));
678 if (l3_proto == htons(ETH_P_IP)) {
679 ip_hdr(skb)->tot_len = iplen;
680 ext->lso_format = pfvf->hw.lso_udpv4_idx;
681 } else {
682 ipv6_hdr(skb)->payload_len = iplen;
683 ext->lso_format = pfvf->hw.lso_udpv6_idx;
684 }
685
686 udph->len = htons(sizeof(struct udphdr));
687 }
688 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
689 ext->tstmp = 1;
690 }
691
692 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN)
693 if (skb_vlan_tag_present(skb)) {
694 if (skb->vlan_proto == htons(ETH_P_8021Q)) {
695 ext->vlan1_ins_ena = 1;
696 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET;
697 ext->vlan1_ins_tci = skb_vlan_tag_get(skb);
698 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) {
699 ext->vlan0_ins_ena = 1;
700 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET;
701 ext->vlan0_ins_tci = skb_vlan_tag_get(skb);
702 }
703 }
704
705 *offset += sizeof(*ext);
706 }
707
otx2_sqe_add_mem(struct otx2_snd_queue * sq,int * offset,int alg,u64 iova,int ptp_offset,u64 base_ns,bool udp_csum_crt)708 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset,
709 int alg, u64 iova, int ptp_offset,
710 u64 base_ns, bool udp_csum_crt)
711 {
712 struct nix_sqe_mem_s *mem;
713
714 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset);
715 mem->subdc = NIX_SUBDC_MEM;
716 mem->alg = alg;
717 mem->wmem = 1; /* wait for the memory operation */
718 mem->addr = iova;
719
720 if (ptp_offset) {
721 mem->start_offset = ptp_offset;
722 mem->udp_csum_crt = !!udp_csum_crt;
723 mem->base_ns = base_ns;
724 mem->step_type = 1;
725 }
726
727 *offset += sizeof(*mem);
728 }
729
730 /* Add SQE header subdescriptor structure */
otx2_sqe_add_hdr(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_sqe_hdr_s * sqe_hdr,struct sk_buff * skb,u16 qidx)731 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
732 struct nix_sqe_hdr_s *sqe_hdr,
733 struct sk_buff *skb, u16 qidx)
734 {
735 int proto = 0;
736
737 /* Check if SQE was framed before, if yes then no need to
738 * set these constants again and again.
739 */
740 if (!sqe_hdr->total) {
741 /* Don't free Tx buffers to Aura */
742 sqe_hdr->df = 1;
743 sqe_hdr->aura = sq->aura_id;
744 /* Post a CQE Tx after pkt transmission */
745 sqe_hdr->pnc = 1;
746 sqe_hdr->sq = (qidx >= pfvf->hw.tx_queues) ?
747 qidx + pfvf->hw.xdp_queues : qidx;
748 }
749 sqe_hdr->total = skb->len;
750 /* Set SQE identifier which will be used later for freeing SKB */
751 sqe_hdr->sqe_id = sq->head;
752
753 /* Offload TCP/UDP checksum to HW */
754 if (skb->ip_summed == CHECKSUM_PARTIAL) {
755 sqe_hdr->ol3ptr = skb_network_offset(skb);
756 sqe_hdr->ol4ptr = skb_transport_offset(skb);
757 /* get vlan protocol Ethertype */
758 if (eth_type_vlan(skb->protocol))
759 skb->protocol = vlan_get_protocol(skb);
760
761 if (skb->protocol == htons(ETH_P_IP)) {
762 proto = ip_hdr(skb)->protocol;
763 /* In case of TSO, HW needs this to be explicitly set.
764 * So set this always, instead of adding a check.
765 */
766 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM;
767 } else if (skb->protocol == htons(ETH_P_IPV6)) {
768 proto = ipv6_hdr(skb)->nexthdr;
769 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6;
770 }
771
772 if (proto == IPPROTO_TCP)
773 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM;
774 else if (proto == IPPROTO_UDP)
775 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM;
776 }
777 }
778
otx2_dma_map_tso_skb(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int sqe,int hdr_len)779 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf,
780 struct otx2_snd_queue *sq,
781 struct sk_buff *skb, int sqe, int hdr_len)
782 {
783 int num_segs = skb_shinfo(skb)->nr_frags + 1;
784 struct sg_list *sg = &sq->sg[sqe];
785 u64 dma_addr;
786 int seg, len;
787
788 sg->num_segs = 0;
789
790 /* Get payload length at skb->data */
791 len = skb_headlen(skb) - hdr_len;
792
793 for (seg = 0; seg < num_segs; seg++) {
794 /* Skip skb->data, if there is no payload */
795 if (!seg && !len)
796 continue;
797 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
798 if (dma_mapping_error(pfvf->dev, dma_addr))
799 goto unmap;
800
801 /* Save DMA mapping info for later unmapping */
802 sg->dma_addr[sg->num_segs] = dma_addr;
803 sg->size[sg->num_segs] = len;
804 sg->num_segs++;
805 }
806 return 0;
807 unmap:
808 otx2_dma_unmap_skb_frags(pfvf, sg);
809 return -EINVAL;
810 }
811
otx2_tso_frag_dma_addr(struct otx2_snd_queue * sq,struct sk_buff * skb,int seg,u64 seg_addr,int hdr_len,int sqe)812 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq,
813 struct sk_buff *skb, int seg,
814 u64 seg_addr, int hdr_len, int sqe)
815 {
816 struct sg_list *sg = &sq->sg[sqe];
817 const skb_frag_t *frag;
818 int offset;
819
820 if (seg < 0)
821 return sg->dma_addr[0] + (seg_addr - (u64)skb->data);
822
823 frag = &skb_shinfo(skb)->frags[seg];
824 offset = seg_addr - (u64)skb_frag_address(frag);
825 if (skb_headlen(skb) - hdr_len)
826 seg++;
827 return sg->dma_addr[seg] + offset;
828 }
829
otx2_sqe_tso_add_sg(struct otx2_snd_queue * sq,struct sg_list * list,int * offset)830 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq,
831 struct sg_list *list, int *offset)
832 {
833 struct nix_sqe_sg_s *sg = NULL;
834 u16 *sg_lens = NULL;
835 u64 *iova = NULL;
836 int seg;
837
838 /* Add SG descriptors with buffer addresses */
839 for (seg = 0; seg < list->num_segs; seg++) {
840 if ((seg % MAX_SEGS_PER_SG) == 0) {
841 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
842 sg->ld_type = NIX_SEND_LDTYPE_LDD;
843 sg->subdc = NIX_SUBDC_SG;
844 sg->segs = 0;
845 sg_lens = (void *)sg;
846 iova = (void *)sg + sizeof(*sg);
847 /* Next subdc always starts at a 16byte boundary.
848 * So if sg->segs is whether 2 or 3, offset += 16bytes.
849 */
850 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
851 *offset += sizeof(*sg) + (3 * sizeof(u64));
852 else
853 *offset += sizeof(*sg) + sizeof(u64);
854 }
855 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg];
856 *iova++ = list->dma_addr[seg];
857 sg->segs++;
858 }
859 }
860
otx2_sq_append_tso(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)861 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
862 struct sk_buff *skb, u16 qidx)
863 {
864 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx);
865 int hdr_len, tcp_data, seg_len, pkt_len, offset;
866 struct nix_sqe_hdr_s *sqe_hdr;
867 int first_sqe = sq->head;
868 struct sg_list list;
869 struct tso_t tso;
870
871 hdr_len = tso_start(skb, &tso);
872
873 /* Map SKB's fragments to DMA.
874 * It's done here to avoid mapping for every TSO segment's packet.
875 */
876 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) {
877 dev_kfree_skb_any(skb);
878 return;
879 }
880
881 netdev_tx_sent_queue(txq, skb->len);
882
883 tcp_data = skb->len - hdr_len;
884 while (tcp_data > 0) {
885 char *hdr;
886
887 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data);
888 tcp_data -= seg_len;
889
890 /* Set SQE's SEND_HDR */
891 memset(sq->sqe_base, 0, sq->sqe_size);
892 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
893 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
894 offset = sizeof(*sqe_hdr);
895
896 /* Add TSO segment's pkt header */
897 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE);
898 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0);
899 list.dma_addr[0] =
900 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE);
901 list.size[0] = hdr_len;
902 list.num_segs = 1;
903
904 /* Add TSO segment's payload data fragments */
905 pkt_len = hdr_len;
906 while (seg_len > 0) {
907 int size;
908
909 size = min_t(int, tso.size, seg_len);
910
911 list.size[list.num_segs] = size;
912 list.dma_addr[list.num_segs] =
913 otx2_tso_frag_dma_addr(sq, skb,
914 tso.next_frag_idx - 1,
915 (u64)tso.data, hdr_len,
916 first_sqe);
917 list.num_segs++;
918 pkt_len += size;
919 seg_len -= size;
920 tso_build_data(skb, &tso, size);
921 }
922 sqe_hdr->total = pkt_len;
923 otx2_sqe_tso_add_sg(sq, &list, &offset);
924
925 /* DMA mappings and skb needs to be freed only after last
926 * TSO segment is transmitted out. So set 'PNC' only for
927 * last segment. Also point last segment's sqe_id to first
928 * segment's SQE index where skb address and DMA mappings
929 * are saved.
930 */
931 if (!tcp_data) {
932 sqe_hdr->pnc = 1;
933 sqe_hdr->sqe_id = first_sqe;
934 sq->sg[first_sqe].skb = (u64)skb;
935 } else {
936 sqe_hdr->pnc = 0;
937 }
938
939 sqe_hdr->sizem1 = (offset / 16) - 1;
940
941 /* Flush SQE to HW */
942 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
943 }
944 }
945
is_hw_tso_supported(struct otx2_nic * pfvf,struct sk_buff * skb)946 static bool is_hw_tso_supported(struct otx2_nic *pfvf,
947 struct sk_buff *skb)
948 {
949 int payload_len, last_seg_size;
950
951 if (test_bit(HW_TSO, &pfvf->hw.cap_flag))
952 return true;
953
954 /* On 96xx A0, HW TSO not supported */
955 if (!is_96xx_B0(pfvf->pdev))
956 return false;
957
958 /* HW has an issue due to which when the payload of the last LSO
959 * segment is shorter than 16 bytes, some header fields may not
960 * be correctly modified, hence don't offload such TSO segments.
961 */
962
963 payload_len = skb->len - skb_tcp_all_headers(skb);
964 last_seg_size = payload_len % skb_shinfo(skb)->gso_size;
965 if (last_seg_size && last_seg_size < 16)
966 return false;
967
968 return true;
969 }
970
otx2_get_sqe_count(struct otx2_nic * pfvf,struct sk_buff * skb)971 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb)
972 {
973 if (!skb_shinfo(skb)->gso_size)
974 return 1;
975
976 /* HW TSO */
977 if (is_hw_tso_supported(pfvf, skb))
978 return 1;
979
980 /* SW TSO */
981 return skb_shinfo(skb)->gso_segs;
982 }
983
otx2_validate_network_transport(struct sk_buff * skb)984 static bool otx2_validate_network_transport(struct sk_buff *skb)
985 {
986 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) ||
987 (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) {
988 struct udphdr *udph = udp_hdr(skb);
989
990 if (udph->source == htons(PTP_PORT) &&
991 udph->dest == htons(PTP_PORT))
992 return true;
993 }
994
995 return false;
996 }
997
otx2_ptp_is_sync(struct sk_buff * skb,int * offset,bool * udp_csum_crt)998 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, bool *udp_csum_crt)
999 {
1000 struct ethhdr *eth = (struct ethhdr *)(skb->data);
1001 u16 nix_offload_hlen = 0, inner_vhlen = 0;
1002 bool udp_hdr_present = false, is_sync;
1003 u8 *data = skb->data, *msgtype;
1004 __be16 proto = eth->h_proto;
1005 int network_depth = 0;
1006
1007 /* NIX is programmed to offload outer VLAN header
1008 * in case of single vlan protocol field holds Network header ETH_IP/V6
1009 * in case of stacked vlan protocol field holds Inner vlan (8100)
1010 */
1011 if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX &&
1012 skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) {
1013 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
1014 /* Get vlan protocol */
1015 proto = __vlan_get_protocol(skb, eth->h_proto, NULL);
1016 /* SKB APIs like skb_transport_offset does not include
1017 * offloaded vlan header length. Need to explicitly add
1018 * the length
1019 */
1020 nix_offload_hlen = VLAN_HLEN;
1021 inner_vhlen = VLAN_HLEN;
1022 } else if (skb->vlan_proto == htons(ETH_P_8021Q)) {
1023 nix_offload_hlen = VLAN_HLEN;
1024 }
1025 } else if (eth_type_vlan(eth->h_proto)) {
1026 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
1027 }
1028
1029 switch (ntohs(proto)) {
1030 case ETH_P_1588:
1031 if (network_depth)
1032 *offset = network_depth;
1033 else
1034 *offset = ETH_HLEN + nix_offload_hlen +
1035 inner_vhlen;
1036 break;
1037 case ETH_P_IP:
1038 case ETH_P_IPV6:
1039 if (!otx2_validate_network_transport(skb))
1040 return false;
1041
1042 *offset = nix_offload_hlen + skb_transport_offset(skb) +
1043 sizeof(struct udphdr);
1044 udp_hdr_present = true;
1045
1046 }
1047
1048 msgtype = data + *offset;
1049 /* Check PTP messageId is SYNC or not */
1050 is_sync = !(*msgtype & 0xf);
1051 if (is_sync)
1052 *udp_csum_crt = udp_hdr_present;
1053 else
1054 *offset = 0;
1055
1056 return is_sync;
1057 }
1058
otx2_set_txtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,struct otx2_snd_queue * sq,int * offset)1059 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb,
1060 struct otx2_snd_queue *sq, int *offset)
1061 {
1062 struct ethhdr *eth = (struct ethhdr *)(skb->data);
1063 struct ptpv2_tstamp *origin_tstamp;
1064 bool udp_csum_crt = false;
1065 unsigned int udphoff;
1066 struct timespec64 ts;
1067 int ptp_offset = 0;
1068 __wsum skb_csum;
1069 u64 iova;
1070
1071 if (unlikely(!skb_shinfo(skb)->gso_size &&
1072 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
1073 if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC &&
1074 otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum_crt))) {
1075 origin_tstamp = (struct ptpv2_tstamp *)
1076 ((u8 *)skb->data + ptp_offset +
1077 PTP_SYNC_SEC_OFFSET);
1078 ts = ns_to_timespec64(pfvf->ptp->tstamp);
1079 origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff);
1080 origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff);
1081 origin_tstamp->nanoseconds = htonl(ts.tv_nsec);
1082 /* Point to correction field in PTP packet */
1083 ptp_offset += 8;
1084
1085 /* When user disables hw checksum, stack calculates the csum,
1086 * but it does not cover ptp timestamp which is added later.
1087 * Recalculate the checksum manually considering the timestamp.
1088 */
1089 if (udp_csum_crt) {
1090 struct udphdr *uh = udp_hdr(skb);
1091
1092 if (skb->ip_summed != CHECKSUM_PARTIAL && uh->check != 0) {
1093 udphoff = skb_transport_offset(skb);
1094 uh->check = 0;
1095 skb_csum = skb_checksum(skb, udphoff, skb->len - udphoff,
1096 0);
1097 if (ntohs(eth->h_proto) == ETH_P_IPV6)
1098 uh->check = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1099 &ipv6_hdr(skb)->daddr,
1100 skb->len - udphoff,
1101 ipv6_hdr(skb)->nexthdr,
1102 skb_csum);
1103 else
1104 uh->check = csum_tcpudp_magic(ip_hdr(skb)->saddr,
1105 ip_hdr(skb)->daddr,
1106 skb->len - udphoff,
1107 IPPROTO_UDP,
1108 skb_csum);
1109 }
1110 }
1111 } else {
1112 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1113 }
1114 iova = sq->timestamps->iova + (sq->head * sizeof(u64));
1115 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova,
1116 ptp_offset, pfvf->ptp->base_ns, udp_csum_crt);
1117 } else {
1118 skb_tx_timestamp(skb);
1119 }
1120 }
1121
otx2_sq_append_skb(struct net_device * netdev,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)1122 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
1123 struct sk_buff *skb, u16 qidx)
1124 {
1125 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
1126 struct otx2_nic *pfvf = netdev_priv(netdev);
1127 int offset, num_segs, free_desc;
1128 struct nix_sqe_hdr_s *sqe_hdr;
1129
1130 /* Check if there is enough room between producer
1131 * and consumer index.
1132 */
1133 free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
1134 if (free_desc < sq->sqe_thresh)
1135 return false;
1136
1137 if (free_desc < otx2_get_sqe_count(pfvf, skb))
1138 return false;
1139
1140 num_segs = skb_shinfo(skb)->nr_frags + 1;
1141
1142 /* If SKB doesn't fit in a single SQE, linearize it.
1143 * TODO: Consider adding JUMP descriptor instead.
1144 */
1145 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
1146 if (__skb_linearize(skb)) {
1147 dev_kfree_skb_any(skb);
1148 return true;
1149 }
1150 num_segs = skb_shinfo(skb)->nr_frags + 1;
1151 }
1152
1153 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) {
1154 /* Insert vlan tag before giving pkt to tso */
1155 if (skb_vlan_tag_present(skb))
1156 skb = __vlan_hwaccel_push_inside(skb);
1157 otx2_sq_append_tso(pfvf, sq, skb, qidx);
1158 return true;
1159 }
1160
1161 /* Set SQE's SEND_HDR.
1162 * Do not clear the first 64bit as it contains constant info.
1163 */
1164 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1165 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1166 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
1167 offset = sizeof(*sqe_hdr);
1168
1169 /* Add extended header if needed */
1170 otx2_sqe_add_ext(pfvf, sq, skb, &offset);
1171
1172 /* Add SG subdesc with data frags */
1173 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
1174 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
1175 return false;
1176 }
1177
1178 otx2_set_txtstamp(pfvf, skb, sq, &offset);
1179
1180 sqe_hdr->sizem1 = (offset / 16) - 1;
1181
1182 netdev_tx_sent_queue(txq, skb->len);
1183
1184 /* Flush SQE to HW */
1185 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1186
1187 return true;
1188 }
1189 EXPORT_SYMBOL(otx2_sq_append_skb);
1190
otx2_cleanup_rx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1191 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1192 {
1193 struct nix_cqe_rx_s *cqe;
1194 int processed_cqe = 0;
1195 u64 iova, pa;
1196
1197 if (pfvf->xdp_prog)
1198 xdp_rxq_info_unreg(&cq->xdp_rxq);
1199
1200 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1201 return;
1202
1203 while (cq->pend_cqe) {
1204 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq);
1205 processed_cqe++;
1206 cq->pend_cqe--;
1207
1208 if (!cqe)
1209 continue;
1210 if (cqe->sg.segs > 1) {
1211 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx);
1212 continue;
1213 }
1214 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1215 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1216 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE);
1217 put_page(virt_to_page(phys_to_virt(pa)));
1218 }
1219
1220 /* Free CQEs to HW */
1221 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1222 ((u64)cq->cq_idx << 32) | processed_cqe);
1223 }
1224
otx2_cleanup_tx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1225 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1226 {
1227 int tx_pkts = 0, tx_bytes = 0;
1228 struct sk_buff *skb = NULL;
1229 struct otx2_snd_queue *sq;
1230 struct nix_cqe_tx_s *cqe;
1231 struct netdev_queue *txq;
1232 int processed_cqe = 0;
1233 struct sg_list *sg;
1234 int qidx;
1235
1236 qidx = cq->cq_idx - pfvf->hw.rx_queues;
1237 sq = &pfvf->qset.sq[qidx];
1238
1239 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1240 return;
1241
1242 while (cq->pend_cqe) {
1243 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
1244 processed_cqe++;
1245 cq->pend_cqe--;
1246
1247 if (!cqe)
1248 continue;
1249 sg = &sq->sg[cqe->comp.sqe_id];
1250 skb = (struct sk_buff *)sg->skb;
1251 if (skb) {
1252 tx_bytes += skb->len;
1253 tx_pkts++;
1254 otx2_dma_unmap_skb_frags(pfvf, sg);
1255 dev_kfree_skb_any(skb);
1256 sg->skb = (u64)NULL;
1257 }
1258 }
1259
1260 if (likely(tx_pkts)) {
1261 if (qidx >= pfvf->hw.tx_queues)
1262 qidx -= pfvf->hw.xdp_queues;
1263 txq = netdev_get_tx_queue(pfvf->netdev, qidx);
1264 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1265 }
1266 /* Free CQEs to HW */
1267 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1268 ((u64)cq->cq_idx << 32) | processed_cqe);
1269 }
1270
otx2_rxtx_enable(struct otx2_nic * pfvf,bool enable)1271 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable)
1272 {
1273 struct msg_req *msg;
1274 int err;
1275
1276 mutex_lock(&pfvf->mbox.lock);
1277 if (enable)
1278 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox);
1279 else
1280 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox);
1281
1282 if (!msg) {
1283 mutex_unlock(&pfvf->mbox.lock);
1284 return -ENOMEM;
1285 }
1286
1287 err = otx2_sync_mbox_msg(&pfvf->mbox);
1288 mutex_unlock(&pfvf->mbox.lock);
1289 return err;
1290 }
1291
otx2_free_pending_sqe(struct otx2_nic * pfvf)1292 void otx2_free_pending_sqe(struct otx2_nic *pfvf)
1293 {
1294 int tx_pkts = 0, tx_bytes = 0;
1295 struct sk_buff *skb = NULL;
1296 struct otx2_snd_queue *sq;
1297 struct netdev_queue *txq;
1298 struct sg_list *sg;
1299 int sq_idx, sqe;
1300
1301 for (sq_idx = 0; sq_idx < pfvf->hw.tx_queues; sq_idx++) {
1302 sq = &pfvf->qset.sq[sq_idx];
1303 for (sqe = 0; sqe < sq->sqe_cnt; sqe++) {
1304 sg = &sq->sg[sqe];
1305 skb = (struct sk_buff *)sg->skb;
1306 if (skb) {
1307 tx_bytes += skb->len;
1308 tx_pkts++;
1309 otx2_dma_unmap_skb_frags(pfvf, sg);
1310 dev_kfree_skb_any(skb);
1311 sg->skb = (u64)NULL;
1312 }
1313 }
1314
1315 if (!tx_pkts)
1316 continue;
1317 txq = netdev_get_tx_queue(pfvf->netdev, sq_idx);
1318 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1319 tx_pkts = 0;
1320 tx_bytes = 0;
1321 }
1322 }
1323
otx2_xdp_sqe_add_sg(struct otx2_snd_queue * sq,u64 dma_addr,int len,int * offset)1324 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr,
1325 int len, int *offset)
1326 {
1327 struct nix_sqe_sg_s *sg = NULL;
1328 u64 *iova = NULL;
1329
1330 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
1331 sg->ld_type = NIX_SEND_LDTYPE_LDD;
1332 sg->subdc = NIX_SUBDC_SG;
1333 sg->segs = 1;
1334 sg->seg1_size = len;
1335 iova = (void *)sg + sizeof(*sg);
1336 *iova = dma_addr;
1337 *offset += sizeof(*sg) + sizeof(u64);
1338
1339 sq->sg[sq->head].dma_addr[0] = dma_addr;
1340 sq->sg[sq->head].size[0] = len;
1341 sq->sg[sq->head].num_segs = 1;
1342 }
1343
otx2_xdp_sq_append_pkt(struct otx2_nic * pfvf,u64 iova,int len,u16 qidx)1344 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx)
1345 {
1346 struct nix_sqe_hdr_s *sqe_hdr;
1347 struct otx2_snd_queue *sq;
1348 int offset, free_sqe;
1349
1350 sq = &pfvf->qset.sq[qidx];
1351 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
1352 if (free_sqe < sq->sqe_thresh)
1353 return false;
1354
1355 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1356
1357 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1358
1359 if (!sqe_hdr->total) {
1360 sqe_hdr->aura = sq->aura_id;
1361 sqe_hdr->df = 1;
1362 sqe_hdr->sq = qidx;
1363 sqe_hdr->pnc = 1;
1364 }
1365 sqe_hdr->total = len;
1366 sqe_hdr->sqe_id = sq->head;
1367
1368 offset = sizeof(*sqe_hdr);
1369
1370 otx2_xdp_sqe_add_sg(sq, iova, len, &offset);
1371 sqe_hdr->sizem1 = (offset / 16) - 1;
1372 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1373
1374 return true;
1375 }
1376
otx2_xdp_rcv_pkt_handler(struct otx2_nic * pfvf,struct bpf_prog * prog,struct nix_cqe_rx_s * cqe,struct otx2_cq_queue * cq,bool * need_xdp_flush)1377 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
1378 struct bpf_prog *prog,
1379 struct nix_cqe_rx_s *cqe,
1380 struct otx2_cq_queue *cq,
1381 bool *need_xdp_flush)
1382 {
1383 unsigned char *hard_start, *data;
1384 int qidx = cq->cq_idx;
1385 struct xdp_buff xdp;
1386 struct page *page;
1387 u64 iova, pa;
1388 u32 act;
1389 int err;
1390
1391 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1392 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1393 page = virt_to_page(phys_to_virt(pa));
1394
1395 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq);
1396
1397 data = (unsigned char *)phys_to_virt(pa);
1398 hard_start = page_address(page);
1399 xdp_prepare_buff(&xdp, hard_start, data - hard_start,
1400 cqe->sg.seg_size, false);
1401
1402 act = bpf_prog_run_xdp(prog, &xdp);
1403
1404 switch (act) {
1405 case XDP_PASS:
1406 break;
1407 case XDP_TX:
1408 qidx += pfvf->hw.tx_queues;
1409 cq->pool_ptrs++;
1410 return otx2_xdp_sq_append_pkt(pfvf, iova,
1411 cqe->sg.seg_size, qidx);
1412 case XDP_REDIRECT:
1413 cq->pool_ptrs++;
1414 err = xdp_do_redirect(pfvf->netdev, &xdp, prog);
1415
1416 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1417 DMA_FROM_DEVICE);
1418 if (!err) {
1419 *need_xdp_flush = true;
1420 return true;
1421 }
1422 put_page(page);
1423 break;
1424 default:
1425 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act);
1426 break;
1427 case XDP_ABORTED:
1428 trace_xdp_exception(pfvf->netdev, prog, act);
1429 break;
1430 case XDP_DROP:
1431 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1432 DMA_FROM_DEVICE);
1433 put_page(page);
1434 cq->pool_ptrs++;
1435 return true;
1436 }
1437 return false;
1438 }
1439