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1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <net/tso.h>
11 
12 #include "otx2_reg.h"
13 #include "otx2_common.h"
14 #include "otx2_struct.h"
15 #include "cn10k.h"
16 
otx2_nix_rq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)17 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
18 				 struct otx2_nic *pfvf, int qidx)
19 {
20 	u64 incr = (u64)qidx << 32;
21 	u64 *ptr;
22 
23 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
24 	stats->bytes = otx2_atomic64_add(incr, ptr);
25 
26 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
27 	stats->pkts = otx2_atomic64_add(incr, ptr);
28 }
29 
otx2_nix_sq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)30 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
31 				 struct otx2_nic *pfvf, int qidx)
32 {
33 	u64 incr = (u64)qidx << 32;
34 	u64 *ptr;
35 
36 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
37 	stats->bytes = otx2_atomic64_add(incr, ptr);
38 
39 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
40 	stats->pkts = otx2_atomic64_add(incr, ptr);
41 }
42 
otx2_update_lmac_stats(struct otx2_nic * pfvf)43 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
44 {
45 	struct msg_req *req;
46 
47 	if (!netif_running(pfvf->netdev))
48 		return;
49 
50 	mutex_lock(&pfvf->mbox.lock);
51 	req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
52 	if (!req) {
53 		mutex_unlock(&pfvf->mbox.lock);
54 		return;
55 	}
56 
57 	otx2_sync_mbox_msg(&pfvf->mbox);
58 	mutex_unlock(&pfvf->mbox.lock);
59 }
60 
otx2_update_lmac_fec_stats(struct otx2_nic * pfvf)61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
62 {
63 	struct msg_req *req;
64 
65 	if (!netif_running(pfvf->netdev))
66 		return;
67 	mutex_lock(&pfvf->mbox.lock);
68 	req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
69 	if (req)
70 		otx2_sync_mbox_msg(&pfvf->mbox);
71 	mutex_unlock(&pfvf->mbox.lock);
72 }
73 
otx2_update_rq_stats(struct otx2_nic * pfvf,int qidx)74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
75 {
76 	struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
77 
78 	if (!pfvf->qset.rq)
79 		return 0;
80 
81 	otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
82 	return 1;
83 }
84 
otx2_update_sq_stats(struct otx2_nic * pfvf,int qidx)85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
86 {
87 	struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
88 
89 	if (!pfvf->qset.sq)
90 		return 0;
91 
92 	otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
93 	return 1;
94 }
95 
otx2_get_dev_stats(struct otx2_nic * pfvf)96 void otx2_get_dev_stats(struct otx2_nic *pfvf)
97 {
98 	struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
99 
100 	dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
101 	dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
102 	dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
103 	dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
104 	dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
105 	dev_stats->rx_frames = dev_stats->rx_bcast_frames +
106 			       dev_stats->rx_mcast_frames +
107 			       dev_stats->rx_ucast_frames;
108 
109 	dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
110 	dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
111 	dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
112 	dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
113 	dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
114 	dev_stats->tx_frames = dev_stats->tx_bcast_frames +
115 			       dev_stats->tx_mcast_frames +
116 			       dev_stats->tx_ucast_frames;
117 }
118 
otx2_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)119 void otx2_get_stats64(struct net_device *netdev,
120 		      struct rtnl_link_stats64 *stats)
121 {
122 	struct otx2_nic *pfvf = netdev_priv(netdev);
123 	struct otx2_dev_stats *dev_stats;
124 
125 	otx2_get_dev_stats(pfvf);
126 
127 	dev_stats = &pfvf->hw.dev_stats;
128 	stats->rx_bytes = dev_stats->rx_bytes;
129 	stats->rx_packets = dev_stats->rx_frames;
130 	stats->rx_dropped = dev_stats->rx_drops;
131 	stats->multicast = dev_stats->rx_mcast_frames;
132 
133 	stats->tx_bytes = dev_stats->tx_bytes;
134 	stats->tx_packets = dev_stats->tx_frames;
135 	stats->tx_dropped = dev_stats->tx_drops;
136 }
137 EXPORT_SYMBOL(otx2_get_stats64);
138 
139 /* Sync MAC address with RVU AF */
otx2_hw_set_mac_addr(struct otx2_nic * pfvf,u8 * mac)140 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
141 {
142 	struct nix_set_mac_addr *req;
143 	int err;
144 
145 	mutex_lock(&pfvf->mbox.lock);
146 	req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
147 	if (!req) {
148 		mutex_unlock(&pfvf->mbox.lock);
149 		return -ENOMEM;
150 	}
151 
152 	ether_addr_copy(req->mac_addr, mac);
153 
154 	err = otx2_sync_mbox_msg(&pfvf->mbox);
155 	mutex_unlock(&pfvf->mbox.lock);
156 	return err;
157 }
158 
otx2_hw_get_mac_addr(struct otx2_nic * pfvf,struct net_device * netdev)159 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
160 				struct net_device *netdev)
161 {
162 	struct nix_get_mac_addr_rsp *rsp;
163 	struct mbox_msghdr *msghdr;
164 	struct msg_req *req;
165 	int err;
166 
167 	mutex_lock(&pfvf->mbox.lock);
168 	req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
169 	if (!req) {
170 		mutex_unlock(&pfvf->mbox.lock);
171 		return -ENOMEM;
172 	}
173 
174 	err = otx2_sync_mbox_msg(&pfvf->mbox);
175 	if (err) {
176 		mutex_unlock(&pfvf->mbox.lock);
177 		return err;
178 	}
179 
180 	msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
181 	if (IS_ERR(msghdr)) {
182 		mutex_unlock(&pfvf->mbox.lock);
183 		return PTR_ERR(msghdr);
184 	}
185 	rsp = (struct nix_get_mac_addr_rsp *)msghdr;
186 	eth_hw_addr_set(netdev, rsp->mac_addr);
187 	mutex_unlock(&pfvf->mbox.lock);
188 
189 	return 0;
190 }
191 
otx2_set_mac_address(struct net_device * netdev,void * p)192 int otx2_set_mac_address(struct net_device *netdev, void *p)
193 {
194 	struct otx2_nic *pfvf = netdev_priv(netdev);
195 	struct sockaddr *addr = p;
196 
197 	if (!is_valid_ether_addr(addr->sa_data))
198 		return -EADDRNOTAVAIL;
199 
200 	if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
201 		eth_hw_addr_set(netdev, addr->sa_data);
202 		/* update dmac field in vlan offload rule */
203 		if (netif_running(netdev) &&
204 		    pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
205 			otx2_install_rxvlan_offload_flow(pfvf);
206 		/* update dmac address in ntuple and DMAC filter list */
207 		if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
208 			otx2_dmacflt_update_pfmac_flow(pfvf);
209 	} else {
210 		return -EPERM;
211 	}
212 
213 	return 0;
214 }
215 EXPORT_SYMBOL(otx2_set_mac_address);
216 
otx2_hw_set_mtu(struct otx2_nic * pfvf,int mtu)217 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
218 {
219 	struct nix_frs_cfg *req;
220 	u16 maxlen;
221 	int err;
222 
223 	maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
224 
225 	mutex_lock(&pfvf->mbox.lock);
226 	req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
227 	if (!req) {
228 		mutex_unlock(&pfvf->mbox.lock);
229 		return -ENOMEM;
230 	}
231 
232 	req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
233 
234 	/* Use max receive length supported by hardware for loopback devices */
235 	if (is_otx2_lbkvf(pfvf->pdev))
236 		req->maxlen = maxlen;
237 
238 	err = otx2_sync_mbox_msg(&pfvf->mbox);
239 	mutex_unlock(&pfvf->mbox.lock);
240 	return err;
241 }
242 
otx2_config_pause_frm(struct otx2_nic * pfvf)243 int otx2_config_pause_frm(struct otx2_nic *pfvf)
244 {
245 	struct cgx_pause_frm_cfg *req;
246 	int err;
247 
248 	if (is_otx2_lbkvf(pfvf->pdev))
249 		return 0;
250 
251 	mutex_lock(&pfvf->mbox.lock);
252 	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
253 	if (!req) {
254 		err = -ENOMEM;
255 		goto unlock;
256 	}
257 
258 	req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
259 	req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
260 	req->set = 1;
261 
262 	err = otx2_sync_mbox_msg(&pfvf->mbox);
263 unlock:
264 	mutex_unlock(&pfvf->mbox.lock);
265 	return err;
266 }
267 EXPORT_SYMBOL(otx2_config_pause_frm);
268 
otx2_set_flowkey_cfg(struct otx2_nic * pfvf)269 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
270 {
271 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
272 	struct nix_rss_flowkey_cfg_rsp *rsp;
273 	struct nix_rss_flowkey_cfg *req;
274 	int err;
275 
276 	mutex_lock(&pfvf->mbox.lock);
277 	req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
278 	if (!req) {
279 		mutex_unlock(&pfvf->mbox.lock);
280 		return -ENOMEM;
281 	}
282 	req->mcam_index = -1; /* Default or reserved index */
283 	req->flowkey_cfg = rss->flowkey_cfg;
284 	req->group = DEFAULT_RSS_CONTEXT_GROUP;
285 
286 	err = otx2_sync_mbox_msg(&pfvf->mbox);
287 	if (err)
288 		goto fail;
289 
290 	rsp = (struct nix_rss_flowkey_cfg_rsp *)
291 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
292 	if (IS_ERR(rsp)) {
293 		err = PTR_ERR(rsp);
294 		goto fail;
295 	}
296 
297 	pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
298 fail:
299 	mutex_unlock(&pfvf->mbox.lock);
300 	return err;
301 }
302 
otx2_set_rss_table(struct otx2_nic * pfvf,int ctx_id)303 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
304 {
305 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
306 	const int index = rss->rss_size * ctx_id;
307 	struct mbox *mbox = &pfvf->mbox;
308 	struct otx2_rss_ctx *rss_ctx;
309 	struct nix_aq_enq_req *aq;
310 	int idx, err;
311 
312 	mutex_lock(&mbox->lock);
313 	rss_ctx = rss->rss_ctx[ctx_id];
314 	/* Get memory to put this msg */
315 	for (idx = 0; idx < rss->rss_size; idx++) {
316 		aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
317 		if (!aq) {
318 			/* The shared memory buffer can be full.
319 			 * Flush it and retry
320 			 */
321 			err = otx2_sync_mbox_msg(mbox);
322 			if (err) {
323 				mutex_unlock(&mbox->lock);
324 				return err;
325 			}
326 			aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
327 			if (!aq) {
328 				mutex_unlock(&mbox->lock);
329 				return -ENOMEM;
330 			}
331 		}
332 
333 		aq->rss.rq = rss_ctx->ind_tbl[idx];
334 
335 		/* Fill AQ info */
336 		aq->qidx = index + idx;
337 		aq->ctype = NIX_AQ_CTYPE_RSS;
338 		aq->op = NIX_AQ_INSTOP_INIT;
339 	}
340 	err = otx2_sync_mbox_msg(mbox);
341 	mutex_unlock(&mbox->lock);
342 	return err;
343 }
344 
otx2_set_rss_key(struct otx2_nic * pfvf)345 void otx2_set_rss_key(struct otx2_nic *pfvf)
346 {
347 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
348 	u64 *key = (u64 *)&rss->key[4];
349 	int idx;
350 
351 	/* 352bit or 44byte key needs to be configured as below
352 	 * NIX_LF_RX_SECRETX0 = key<351:288>
353 	 * NIX_LF_RX_SECRETX1 = key<287:224>
354 	 * NIX_LF_RX_SECRETX2 = key<223:160>
355 	 * NIX_LF_RX_SECRETX3 = key<159:96>
356 	 * NIX_LF_RX_SECRETX4 = key<95:32>
357 	 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
358 	 */
359 	otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
360 		     (u64)(*((u32 *)&rss->key)) << 32);
361 	idx = sizeof(rss->key) / sizeof(u64);
362 	while (idx > 0) {
363 		idx--;
364 		otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
365 	}
366 }
367 
otx2_rss_init(struct otx2_nic * pfvf)368 int otx2_rss_init(struct otx2_nic *pfvf)
369 {
370 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
371 	struct otx2_rss_ctx *rss_ctx;
372 	int idx, ret = 0;
373 
374 	rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
375 
376 	/* Init RSS key if it is not setup already */
377 	if (!rss->enable)
378 		netdev_rss_key_fill(rss->key, sizeof(rss->key));
379 	otx2_set_rss_key(pfvf);
380 
381 	if (!netif_is_rxfh_configured(pfvf->netdev)) {
382 		/* Set RSS group 0 as default indirection table */
383 		rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
384 								  GFP_KERNEL);
385 		if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
386 			return -ENOMEM;
387 
388 		rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
389 		for (idx = 0; idx < rss->rss_size; idx++)
390 			rss_ctx->ind_tbl[idx] =
391 				ethtool_rxfh_indir_default(idx,
392 							   pfvf->hw.rx_queues);
393 	}
394 	ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
395 	if (ret)
396 		return ret;
397 
398 	/* Flowkey or hash config to be used for generating flow tag */
399 	rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
400 			   NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
401 			   NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
402 			   NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
403 			   NIX_FLOW_KEY_TYPE_IPV4_PROTO;
404 
405 	ret = otx2_set_flowkey_cfg(pfvf);
406 	if (ret)
407 		return ret;
408 
409 	rss->enable = true;
410 	return 0;
411 }
412 
413 /* Setup UDP segmentation algorithm in HW */
otx2_setup_udp_segmentation(struct nix_lso_format_cfg * lso,bool v4)414 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
415 {
416 	struct nix_lso_format *field;
417 
418 	field = (struct nix_lso_format *)&lso->fields[0];
419 	lso->field_mask = GENMASK(18, 0);
420 
421 	/* IP's Length field */
422 	field->layer = NIX_TXLAYER_OL3;
423 	/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
424 	field->offset = v4 ? 2 : 4;
425 	field->sizem1 = 1; /* i.e 2 bytes */
426 	field->alg = NIX_LSOALG_ADD_PAYLEN;
427 	field++;
428 
429 	/* No ID field in IPv6 header */
430 	if (v4) {
431 		/* Increment IPID */
432 		field->layer = NIX_TXLAYER_OL3;
433 		field->offset = 4;
434 		field->sizem1 = 1; /* i.e 2 bytes */
435 		field->alg = NIX_LSOALG_ADD_SEGNUM;
436 		field++;
437 	}
438 
439 	/* Update length in UDP header */
440 	field->layer = NIX_TXLAYER_OL4;
441 	field->offset = 4;
442 	field->sizem1 = 1;
443 	field->alg = NIX_LSOALG_ADD_PAYLEN;
444 }
445 
446 /* Setup segmentation algorithms in HW and retrieve algorithm index */
otx2_setup_segmentation(struct otx2_nic * pfvf)447 void otx2_setup_segmentation(struct otx2_nic *pfvf)
448 {
449 	struct nix_lso_format_cfg_rsp *rsp;
450 	struct nix_lso_format_cfg *lso;
451 	struct otx2_hw *hw = &pfvf->hw;
452 	int err;
453 
454 	mutex_lock(&pfvf->mbox.lock);
455 
456 	/* UDPv4 segmentation */
457 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
458 	if (!lso)
459 		goto fail;
460 
461 	/* Setup UDP/IP header fields that HW should update per segment */
462 	otx2_setup_udp_segmentation(lso, true);
463 
464 	err = otx2_sync_mbox_msg(&pfvf->mbox);
465 	if (err)
466 		goto fail;
467 
468 	rsp = (struct nix_lso_format_cfg_rsp *)
469 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
470 	if (IS_ERR(rsp))
471 		goto fail;
472 
473 	hw->lso_udpv4_idx = rsp->lso_format_idx;
474 
475 	/* UDPv6 segmentation */
476 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
477 	if (!lso)
478 		goto fail;
479 
480 	/* Setup UDP/IP header fields that HW should update per segment */
481 	otx2_setup_udp_segmentation(lso, false);
482 
483 	err = otx2_sync_mbox_msg(&pfvf->mbox);
484 	if (err)
485 		goto fail;
486 
487 	rsp = (struct nix_lso_format_cfg_rsp *)
488 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
489 	if (IS_ERR(rsp))
490 		goto fail;
491 
492 	hw->lso_udpv6_idx = rsp->lso_format_idx;
493 	mutex_unlock(&pfvf->mbox.lock);
494 	return;
495 fail:
496 	mutex_unlock(&pfvf->mbox.lock);
497 	netdev_info(pfvf->netdev,
498 		    "Failed to get LSO index for UDP GSO offload, disabling\n");
499 	pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
500 }
501 
otx2_config_irq_coalescing(struct otx2_nic * pfvf,int qidx)502 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
503 {
504 	/* Configure CQE interrupt coalescing parameters
505 	 *
506 	 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
507 	 * set 1 less than cq_ecount_wait. And cq_time_wait is in
508 	 * usecs, convert that to 100ns count.
509 	 */
510 	otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
511 		     ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
512 		     ((u64)pfvf->hw.cq_qcount_wait << 32) |
513 		     (pfvf->hw.cq_ecount_wait - 1));
514 }
515 
__otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)516 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
517 			     dma_addr_t *dma)
518 {
519 	u8 *buf;
520 
521 	buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
522 	if (unlikely(!buf))
523 		return -ENOMEM;
524 
525 	*dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
526 				    DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
527 	if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
528 		page_frag_free(buf);
529 		return -ENOMEM;
530 	}
531 
532 	return 0;
533 }
534 
otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)535 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
536 		    dma_addr_t *dma)
537 {
538 	int ret;
539 
540 	local_bh_disable();
541 	ret = __otx2_alloc_rbuf(pfvf, pool, dma);
542 	local_bh_enable();
543 	return ret;
544 }
545 
otx2_alloc_buffer(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,dma_addr_t * dma)546 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
547 		      dma_addr_t *dma)
548 {
549 	if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) {
550 		struct refill_work *work;
551 		struct delayed_work *dwork;
552 
553 		work = &pfvf->refill_wrk[cq->cq_idx];
554 		dwork = &work->pool_refill_work;
555 		/* Schedule a task if no other task is running */
556 		if (!cq->refill_task_sched) {
557 			cq->refill_task_sched = true;
558 			schedule_delayed_work(dwork,
559 					      msecs_to_jiffies(100));
560 		}
561 		return -ENOMEM;
562 	}
563 	return 0;
564 }
565 
otx2_tx_timeout(struct net_device * netdev,unsigned int txq)566 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
567 {
568 	struct otx2_nic *pfvf = netdev_priv(netdev);
569 
570 	schedule_work(&pfvf->reset_task);
571 }
572 EXPORT_SYMBOL(otx2_tx_timeout);
573 
otx2_get_mac_from_af(struct net_device * netdev)574 void otx2_get_mac_from_af(struct net_device *netdev)
575 {
576 	struct otx2_nic *pfvf = netdev_priv(netdev);
577 	int err;
578 
579 	err = otx2_hw_get_mac_addr(pfvf, netdev);
580 	if (err)
581 		dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
582 
583 	/* If AF doesn't provide a valid MAC, generate a random one */
584 	if (!is_valid_ether_addr(netdev->dev_addr))
585 		eth_hw_addr_random(netdev);
586 }
587 EXPORT_SYMBOL(otx2_get_mac_from_af);
588 
otx2_txschq_config(struct otx2_nic * pfvf,int lvl,int prio,bool txschq_for_pfc)589 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc)
590 {
591 	u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC];
592 	struct otx2_hw *hw = &pfvf->hw;
593 	struct nix_txschq_config *req;
594 	u64 schq, parent;
595 	u64 dwrr_val;
596 
597 	dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
598 
599 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
600 	if (!req)
601 		return -ENOMEM;
602 
603 	req->lvl = lvl;
604 	req->num_regs = 1;
605 
606 	schq_list = hw->txschq_list;
607 #ifdef CONFIG_DCB
608 	if (txschq_for_pfc)
609 		schq_list = pfvf->pfc_schq_list;
610 #endif
611 
612 	schq = schq_list[lvl][prio];
613 	/* Set topology e.t.c configuration */
614 	if (lvl == NIX_TXSCH_LVL_SMQ) {
615 		req->reg[0] = NIX_AF_SMQX_CFG(schq);
616 		req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
617 		req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
618 				  (0x2ULL << 36);
619 		req->num_regs++;
620 		/* MDQ config */
621 		parent = schq_list[NIX_TXSCH_LVL_TL4][prio];
622 		req->reg[1] = NIX_AF_MDQX_PARENT(schq);
623 		req->regval[1] = parent << 16;
624 		req->num_regs++;
625 		/* Set DWRR quantum */
626 		req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
627 		req->regval[2] =  dwrr_val;
628 	} else if (lvl == NIX_TXSCH_LVL_TL4) {
629 		parent = schq_list[NIX_TXSCH_LVL_TL3][prio];
630 		req->reg[0] = NIX_AF_TL4X_PARENT(schq);
631 		req->regval[0] = parent << 16;
632 		req->num_regs++;
633 		req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
634 		req->regval[1] = dwrr_val;
635 	} else if (lvl == NIX_TXSCH_LVL_TL3) {
636 		parent = schq_list[NIX_TXSCH_LVL_TL2][prio];
637 		req->reg[0] = NIX_AF_TL3X_PARENT(schq);
638 		req->regval[0] = parent << 16;
639 		req->num_regs++;
640 		req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
641 		req->regval[1] = dwrr_val;
642 		if (lvl == hw->txschq_link_cfg_lvl) {
643 			req->num_regs++;
644 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
645 			/* Enable this queue and backpressure
646 			 * and set relative channel
647 			 */
648 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
649 		}
650 	} else if (lvl == NIX_TXSCH_LVL_TL2) {
651 		parent = schq_list[NIX_TXSCH_LVL_TL1][prio];
652 		req->reg[0] = NIX_AF_TL2X_PARENT(schq);
653 		req->regval[0] = parent << 16;
654 
655 		req->num_regs++;
656 		req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
657 		req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
658 
659 		if (lvl == hw->txschq_link_cfg_lvl) {
660 			req->num_regs++;
661 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
662 			/* Enable this queue and backpressure
663 			 * and set relative channel
664 			 */
665 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
666 		}
667 	} else if (lvl == NIX_TXSCH_LVL_TL1) {
668 		/* Default config for TL1.
669 		 * For VF this is always ignored.
670 		 */
671 
672 		/* On CN10K, if RR_WEIGHT is greater than 16384, HW will
673 		 * clip it to 16384, so configuring a 24bit max value
674 		 * will work on both OTx2 and CN10K.
675 		 */
676 		req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
677 		req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
678 
679 		req->num_regs++;
680 		req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
681 		req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
682 
683 		req->num_regs++;
684 		req->reg[2] = NIX_AF_TL1X_CIR(schq);
685 		req->regval[2] = 0;
686 	}
687 
688 	return otx2_sync_mbox_msg(&pfvf->mbox);
689 }
690 EXPORT_SYMBOL(otx2_txschq_config);
691 
otx2_smq_flush(struct otx2_nic * pfvf,int smq)692 int otx2_smq_flush(struct otx2_nic *pfvf, int smq)
693 {
694 	struct nix_txschq_config *req;
695 	int rc;
696 
697 	mutex_lock(&pfvf->mbox.lock);
698 
699 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
700 	if (!req) {
701 		mutex_unlock(&pfvf->mbox.lock);
702 		return -ENOMEM;
703 	}
704 
705 	req->lvl = NIX_TXSCH_LVL_SMQ;
706 	req->reg[0] = NIX_AF_SMQX_CFG(smq);
707 	req->regval[0] |= BIT_ULL(49);
708 	req->num_regs++;
709 
710 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
711 	mutex_unlock(&pfvf->mbox.lock);
712 	return rc;
713 }
714 EXPORT_SYMBOL(otx2_smq_flush);
715 
otx2_txsch_alloc(struct otx2_nic * pfvf)716 int otx2_txsch_alloc(struct otx2_nic *pfvf)
717 {
718 	struct nix_txsch_alloc_req *req;
719 	struct nix_txsch_alloc_rsp *rsp;
720 	int lvl, schq, rc;
721 
722 	/* Get memory to put this msg */
723 	req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
724 	if (!req)
725 		return -ENOMEM;
726 
727 	/* Request one schq per level */
728 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
729 		req->schq[lvl] = 1;
730 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
731 	if (rc)
732 		return rc;
733 
734 	rsp = (struct nix_txsch_alloc_rsp *)
735 	      otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
736 	if (IS_ERR(rsp))
737 		return PTR_ERR(rsp);
738 
739 	/* Setup transmit scheduler list */
740 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
741 		for (schq = 0; schq < rsp->schq[lvl]; schq++)
742 			pfvf->hw.txschq_list[lvl][schq] =
743 				rsp->schq_list[lvl][schq];
744 
745 	pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
746 
747 	return 0;
748 }
749 
otx2_txschq_free_one(struct otx2_nic * pfvf,u16 lvl,u16 schq)750 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
751 {
752 	struct nix_txsch_free_req *free_req;
753 	int err;
754 
755 	mutex_lock(&pfvf->mbox.lock);
756 
757 	free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
758 	if (!free_req) {
759 		mutex_unlock(&pfvf->mbox.lock);
760 		netdev_err(pfvf->netdev,
761 			   "Failed alloc txschq free req\n");
762 		return;
763 	}
764 
765 	free_req->schq_lvl = lvl;
766 	free_req->schq = schq;
767 
768 	err = otx2_sync_mbox_msg(&pfvf->mbox);
769 	if (err) {
770 		netdev_err(pfvf->netdev,
771 			   "Failed stop txschq %d at level %d\n", schq, lvl);
772 	}
773 
774 	mutex_unlock(&pfvf->mbox.lock);
775 }
776 EXPORT_SYMBOL(otx2_txschq_free_one);
777 
otx2_txschq_stop(struct otx2_nic * pfvf)778 void otx2_txschq_stop(struct otx2_nic *pfvf)
779 {
780 	int lvl, schq;
781 
782 	/* free non QOS TLx nodes */
783 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
784 		otx2_txschq_free_one(pfvf, lvl,
785 				     pfvf->hw.txschq_list[lvl][0]);
786 
787 	/* Clear the txschq list */
788 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
789 		for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
790 			pfvf->hw.txschq_list[lvl][schq] = 0;
791 	}
792 
793 }
794 
otx2_sqb_flush(struct otx2_nic * pfvf)795 void otx2_sqb_flush(struct otx2_nic *pfvf)
796 {
797 	int qidx, sqe_tail, sqe_head;
798 	struct otx2_snd_queue *sq;
799 	u64 incr, *ptr, val;
800 
801 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
802 	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
803 		sq = &pfvf->qset.sq[qidx];
804 		if (!sq->sqb_ptrs)
805 			continue;
806 
807 		incr = (u64)qidx << 32;
808 		val = otx2_atomic64_add(incr, ptr);
809 		sqe_head = (val >> 20) & 0x3F;
810 		sqe_tail = (val >> 28) & 0x3F;
811 		if (sqe_head != sqe_tail)
812 			usleep_range(50, 60);
813 	}
814 }
815 
816 /* RED and drop levels of CQ on packet reception.
817  * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
818  */
819 #define RQ_PASS_LVL_CQ(skid, qsize)	((((skid) + 16) * 256) / (qsize))
820 #define RQ_DROP_LVL_CQ(skid, qsize)	(((skid) * 256) / (qsize))
821 
822 /* RED and drop levels of AURA for packet reception.
823  * For AURA level is measure of fullness (0x0 = empty, 255 = full).
824  * Eg: For RQ length 1K, for pass/drop level 204/230.
825  * RED accepts pkts if free pointers > 102 & <= 205.
826  * Drops pkts if free pointers < 102.
827  */
828 #define RQ_BP_LVL_AURA   (255 - ((85 * 256) / 100)) /* BP when 85% is full */
829 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
830 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
831 
otx2_rq_init(struct otx2_nic * pfvf,u16 qidx,u16 lpb_aura)832 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
833 {
834 	struct otx2_qset *qset = &pfvf->qset;
835 	struct nix_aq_enq_req *aq;
836 
837 	/* Get memory to put this msg */
838 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
839 	if (!aq)
840 		return -ENOMEM;
841 
842 	aq->rq.cq = qidx;
843 	aq->rq.ena = 1;
844 	aq->rq.pb_caching = 1;
845 	aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
846 	aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
847 	aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
848 	aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
849 	aq->rq.qint_idx = 0;
850 	aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
851 	aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
852 	aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
853 	aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
854 	aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
855 	aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
856 
857 	/* Fill AQ info */
858 	aq->qidx = qidx;
859 	aq->ctype = NIX_AQ_CTYPE_RQ;
860 	aq->op = NIX_AQ_INSTOP_INIT;
861 
862 	return otx2_sync_mbox_msg(&pfvf->mbox);
863 }
864 
otx2_sq_aq_init(void * dev,u16 qidx,u16 sqb_aura)865 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
866 {
867 	struct otx2_nic *pfvf = dev;
868 	struct otx2_snd_queue *sq;
869 	struct nix_aq_enq_req *aq;
870 
871 	sq = &pfvf->qset.sq[qidx];
872 	sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
873 	/* Get memory to put this msg */
874 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
875 	if (!aq)
876 		return -ENOMEM;
877 
878 	aq->sq.cq = pfvf->hw.rx_queues + qidx;
879 	aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
880 	aq->sq.cq_ena = 1;
881 	aq->sq.ena = 1;
882 	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
883 	aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
884 	aq->sq.default_chan = pfvf->hw.tx_chan_base;
885 	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
886 	aq->sq.sqb_aura = sqb_aura;
887 	aq->sq.sq_int_ena = NIX_SQINT_BITS;
888 	aq->sq.qint_idx = 0;
889 	/* Due pipelining impact minimum 2000 unused SQ CQE's
890 	 * need to maintain to avoid CQ overflow.
891 	 */
892 	aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
893 
894 	/* Fill AQ info */
895 	aq->qidx = qidx;
896 	aq->ctype = NIX_AQ_CTYPE_SQ;
897 	aq->op = NIX_AQ_INSTOP_INIT;
898 
899 	return otx2_sync_mbox_msg(&pfvf->mbox);
900 }
901 
otx2_sq_init(struct otx2_nic * pfvf,u16 qidx,u16 sqb_aura)902 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
903 {
904 	struct otx2_qset *qset = &pfvf->qset;
905 	struct otx2_snd_queue *sq;
906 	struct otx2_pool *pool;
907 	int err;
908 
909 	pool = &pfvf->qset.pool[sqb_aura];
910 	sq = &qset->sq[qidx];
911 	sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
912 	sq->sqe_cnt = qset->sqe_cnt;
913 
914 	err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
915 	if (err)
916 		return err;
917 
918 	if (qidx < pfvf->hw.tx_queues) {
919 		err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
920 				 TSO_HEADER_SIZE);
921 		if (err)
922 			return err;
923 	}
924 
925 	sq->sqe_base = sq->sqe->base;
926 	sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
927 	if (!sq->sg)
928 		return -ENOMEM;
929 
930 	if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
931 		err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
932 				 sizeof(*sq->timestamps));
933 		if (err) {
934 			kfree(sq->sg);
935 			sq->sg = NULL;
936 			return err;
937 		}
938 	}
939 
940 	sq->head = 0;
941 	sq->cons_head = 0;
942 	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
943 	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
944 	/* Set SQE threshold to 10% of total SQEs */
945 	sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
946 	sq->aura_id = sqb_aura;
947 	sq->aura_fc_addr = pool->fc_addr->base;
948 	sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
949 
950 	sq->stats.bytes = 0;
951 	sq->stats.pkts = 0;
952 
953 	err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
954 	if (err) {
955 		kfree(sq->sg);
956 		sq->sg = NULL;
957 		return err;
958 	}
959 
960 	return 0;
961 
962 }
963 
otx2_cq_init(struct otx2_nic * pfvf,u16 qidx)964 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
965 {
966 	struct otx2_qset *qset = &pfvf->qset;
967 	int err, pool_id, non_xdp_queues;
968 	struct nix_aq_enq_req *aq;
969 	struct otx2_cq_queue *cq;
970 
971 	cq = &qset->cq[qidx];
972 	cq->cq_idx = qidx;
973 	non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
974 	if (qidx < pfvf->hw.rx_queues) {
975 		cq->cq_type = CQ_RX;
976 		cq->cint_idx = qidx;
977 		cq->cqe_cnt = qset->rqe_cnt;
978 		if (pfvf->xdp_prog)
979 			xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
980 	} else if (qidx < non_xdp_queues) {
981 		cq->cq_type = CQ_TX;
982 		cq->cint_idx = qidx - pfvf->hw.rx_queues;
983 		cq->cqe_cnt = qset->sqe_cnt;
984 	} else {
985 		if (pfvf->hw.xdp_queues &&
986 		    qidx < non_xdp_queues + pfvf->hw.xdp_queues) {
987 			cq->cq_type = CQ_XDP;
988 			cq->cint_idx = qidx - non_xdp_queues;
989 			cq->cqe_cnt = qset->sqe_cnt;
990 		} else {
991 			cq->cq_type = CQ_QOS;
992 			cq->cint_idx = qidx - non_xdp_queues -
993 				       pfvf->hw.xdp_queues;
994 			cq->cqe_cnt = qset->sqe_cnt;
995 		}
996 	}
997 	cq->cqe_size = pfvf->qset.xqe_size;
998 
999 	/* Allocate memory for CQEs */
1000 	err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
1001 	if (err)
1002 		return err;
1003 
1004 	/* Save CQE CPU base for faster reference */
1005 	cq->cqe_base = cq->cqe->base;
1006 	/* In case where all RQs auras point to single pool,
1007 	 * all CQs receive buffer pool also point to same pool.
1008 	 */
1009 	pool_id = ((cq->cq_type == CQ_RX) &&
1010 		   (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
1011 	cq->rbpool = &qset->pool[pool_id];
1012 	cq->refill_task_sched = false;
1013 
1014 	/* Get memory to put this msg */
1015 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
1016 	if (!aq)
1017 		return -ENOMEM;
1018 
1019 	aq->cq.ena = 1;
1020 	aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
1021 	aq->cq.caching = 1;
1022 	aq->cq.base = cq->cqe->iova;
1023 	aq->cq.cint_idx = cq->cint_idx;
1024 	aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
1025 	aq->cq.qint_idx = 0;
1026 	aq->cq.avg_level = 255;
1027 
1028 	if (qidx < pfvf->hw.rx_queues) {
1029 		aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
1030 		aq->cq.drop_ena = 1;
1031 
1032 		if (!is_otx2_lbkvf(pfvf->pdev)) {
1033 			/* Enable receive CQ backpressure */
1034 			aq->cq.bp_ena = 1;
1035 #ifdef CONFIG_DCB
1036 			aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
1037 #else
1038 			aq->cq.bpid = pfvf->bpid[0];
1039 #endif
1040 
1041 			/* Set backpressure level is same as cq pass level */
1042 			aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
1043 		}
1044 	}
1045 
1046 	/* Fill AQ info */
1047 	aq->qidx = qidx;
1048 	aq->ctype = NIX_AQ_CTYPE_CQ;
1049 	aq->op = NIX_AQ_INSTOP_INIT;
1050 
1051 	return otx2_sync_mbox_msg(&pfvf->mbox);
1052 }
1053 
otx2_pool_refill_task(struct work_struct * work)1054 static void otx2_pool_refill_task(struct work_struct *work)
1055 {
1056 	struct otx2_cq_queue *cq;
1057 	struct otx2_pool *rbpool;
1058 	struct refill_work *wrk;
1059 	int qidx, free_ptrs = 0;
1060 	struct otx2_nic *pfvf;
1061 	dma_addr_t bufptr;
1062 
1063 	wrk = container_of(work, struct refill_work, pool_refill_work.work);
1064 	pfvf = wrk->pf;
1065 	qidx = wrk - pfvf->refill_wrk;
1066 	cq = &pfvf->qset.cq[qidx];
1067 	rbpool = cq->rbpool;
1068 	free_ptrs = cq->pool_ptrs;
1069 
1070 	while (cq->pool_ptrs) {
1071 		if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
1072 			/* Schedule a WQ if we fails to free atleast half of the
1073 			 * pointers else enable napi for this RQ.
1074 			 */
1075 			if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) {
1076 				struct delayed_work *dwork;
1077 
1078 				dwork = &wrk->pool_refill_work;
1079 				schedule_delayed_work(dwork,
1080 						      msecs_to_jiffies(100));
1081 			} else {
1082 				cq->refill_task_sched = false;
1083 			}
1084 			return;
1085 		}
1086 		pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
1087 		cq->pool_ptrs--;
1088 	}
1089 	cq->refill_task_sched = false;
1090 }
1091 
otx2_config_nix_queues(struct otx2_nic * pfvf)1092 int otx2_config_nix_queues(struct otx2_nic *pfvf)
1093 {
1094 	int qidx, err;
1095 
1096 	/* Initialize RX queues */
1097 	for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1098 		u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1099 
1100 		err = otx2_rq_init(pfvf, qidx, lpb_aura);
1101 		if (err)
1102 			return err;
1103 	}
1104 
1105 	/* Initialize TX queues */
1106 	for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) {
1107 		u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1108 
1109 		err = otx2_sq_init(pfvf, qidx, sqb_aura);
1110 		if (err)
1111 			return err;
1112 	}
1113 
1114 	/* Initialize completion queues */
1115 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1116 		err = otx2_cq_init(pfvf, qidx);
1117 		if (err)
1118 			return err;
1119 	}
1120 
1121 	pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1122 							   NIX_LF_CQ_OP_STATUS);
1123 
1124 	/* Initialize work queue for receive buffer refill */
1125 	pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1126 					sizeof(struct refill_work), GFP_KERNEL);
1127 	if (!pfvf->refill_wrk)
1128 		return -ENOMEM;
1129 
1130 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1131 		pfvf->refill_wrk[qidx].pf = pfvf;
1132 		INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1133 				  otx2_pool_refill_task);
1134 	}
1135 	return 0;
1136 }
1137 
otx2_config_nix(struct otx2_nic * pfvf)1138 int otx2_config_nix(struct otx2_nic *pfvf)
1139 {
1140 	struct nix_lf_alloc_req  *nixlf;
1141 	struct nix_lf_alloc_rsp *rsp;
1142 	int err;
1143 
1144 	pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1145 
1146 	/* Get memory to put this msg */
1147 	nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1148 	if (!nixlf)
1149 		return -ENOMEM;
1150 
1151 	/* Set RQ/SQ/CQ counts */
1152 	nixlf->rq_cnt = pfvf->hw.rx_queues;
1153 	nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf);
1154 	nixlf->cq_cnt = pfvf->qset.cq_cnt;
1155 	nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1156 	nixlf->rss_grps = MAX_RSS_GROUPS;
1157 	nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1158 	/* We don't know absolute NPA LF idx attached.
1159 	 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1160 	 * NPA LF attached to this RVU PF/VF.
1161 	 */
1162 	nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1163 	/* Disable alignment pad, enable L2 length check,
1164 	 * enable L4 TCP/UDP checksum verification.
1165 	 */
1166 	nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1167 
1168 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1169 	if (err)
1170 		return err;
1171 
1172 	rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1173 							   &nixlf->hdr);
1174 	if (IS_ERR(rsp))
1175 		return PTR_ERR(rsp);
1176 
1177 	if (rsp->qints < 1)
1178 		return -ENXIO;
1179 
1180 	return rsp->hdr.rc;
1181 }
1182 
otx2_sq_free_sqbs(struct otx2_nic * pfvf)1183 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1184 {
1185 	struct otx2_qset *qset = &pfvf->qset;
1186 	struct otx2_hw *hw = &pfvf->hw;
1187 	struct otx2_snd_queue *sq;
1188 	int sqb, qidx;
1189 	u64 iova, pa;
1190 
1191 	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
1192 		sq = &qset->sq[qidx];
1193 		if (!sq->sqb_ptrs)
1194 			continue;
1195 		for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1196 			if (!sq->sqb_ptrs[sqb])
1197 				continue;
1198 			iova = sq->sqb_ptrs[sqb];
1199 			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1200 			dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1201 					     DMA_FROM_DEVICE,
1202 					     DMA_ATTR_SKIP_CPU_SYNC);
1203 			put_page(virt_to_page(phys_to_virt(pa)));
1204 		}
1205 		sq->sqb_count = 0;
1206 	}
1207 }
1208 
otx2_free_aura_ptr(struct otx2_nic * pfvf,int type)1209 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1210 {
1211 	int pool_id, pool_start = 0, pool_end = 0, size = 0;
1212 	u64 iova, pa;
1213 
1214 	if (type == AURA_NIX_SQ) {
1215 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1216 		pool_end =  pool_start + pfvf->hw.sqpool_cnt;
1217 		size = pfvf->hw.sqb_size;
1218 	}
1219 	if (type == AURA_NIX_RQ) {
1220 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1221 		pool_end = pfvf->hw.rqpool_cnt;
1222 		size = pfvf->rbsize;
1223 	}
1224 
1225 	/* Free SQB and RQB pointers from the aura pool */
1226 	for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1227 		iova = otx2_aura_allocptr(pfvf, pool_id);
1228 		while (iova) {
1229 			if (type == AURA_NIX_RQ)
1230 				iova -= OTX2_HEAD_ROOM;
1231 
1232 			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1233 			dma_unmap_page_attrs(pfvf->dev, iova, size,
1234 					     DMA_FROM_DEVICE,
1235 					     DMA_ATTR_SKIP_CPU_SYNC);
1236 			put_page(virt_to_page(phys_to_virt(pa)));
1237 			iova = otx2_aura_allocptr(pfvf, pool_id);
1238 		}
1239 	}
1240 }
1241 
otx2_aura_pool_free(struct otx2_nic * pfvf)1242 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1243 {
1244 	struct otx2_pool *pool;
1245 	int pool_id;
1246 
1247 	if (!pfvf->qset.pool)
1248 		return;
1249 
1250 	for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1251 		pool = &pfvf->qset.pool[pool_id];
1252 		qmem_free(pfvf->dev, pool->stack);
1253 		qmem_free(pfvf->dev, pool->fc_addr);
1254 	}
1255 	devm_kfree(pfvf->dev, pfvf->qset.pool);
1256 	pfvf->qset.pool = NULL;
1257 }
1258 
otx2_aura_init(struct otx2_nic * pfvf,int aura_id,int pool_id,int numptrs)1259 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1260 		   int pool_id, int numptrs)
1261 {
1262 	struct npa_aq_enq_req *aq;
1263 	struct otx2_pool *pool;
1264 	int err;
1265 
1266 	pool = &pfvf->qset.pool[pool_id];
1267 
1268 	/* Allocate memory for HW to update Aura count.
1269 	 * Alloc one cache line, so that it fits all FC_STYPE modes.
1270 	 */
1271 	if (!pool->fc_addr) {
1272 		err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1273 		if (err)
1274 			return err;
1275 	}
1276 
1277 	/* Initialize this aura's context via AF */
1278 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1279 	if (!aq) {
1280 		/* Shared mbox memory buffer is full, flush it and retry */
1281 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1282 		if (err)
1283 			return err;
1284 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1285 		if (!aq)
1286 			return -ENOMEM;
1287 	}
1288 
1289 	aq->aura_id = aura_id;
1290 	/* Will be filled by AF with correct pool context address */
1291 	aq->aura.pool_addr = pool_id;
1292 	aq->aura.pool_caching = 1;
1293 	aq->aura.shift = ilog2(numptrs) - 8;
1294 	aq->aura.count = numptrs;
1295 	aq->aura.limit = numptrs;
1296 	aq->aura.avg_level = 255;
1297 	aq->aura.ena = 1;
1298 	aq->aura.fc_ena = 1;
1299 	aq->aura.fc_addr = pool->fc_addr->iova;
1300 	aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1301 
1302 	/* Enable backpressure for RQ aura */
1303 	if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1304 		aq->aura.bp_ena = 0;
1305 		/* If NIX1 LF is attached then specify NIX1_RX.
1306 		 *
1307 		 * Below NPA_AURA_S[BP_ENA] is set according to the
1308 		 * NPA_BPINTF_E enumeration given as:
1309 		 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1310 		 * NIX0_RX is 0x0 + 0*0x1 = 0
1311 		 * NIX1_RX is 0x0 + 1*0x1 = 1
1312 		 * But in HRM it is given that
1313 		 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1314 		 * NIX-RX based on [BP] level. One bit per NIX-RX; index
1315 		 * enumerated by NPA_BPINTF_E."
1316 		 */
1317 		if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1318 			aq->aura.bp_ena = 1;
1319 #ifdef CONFIG_DCB
1320 		aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1321 #else
1322 		aq->aura.nix0_bpid = pfvf->bpid[0];
1323 #endif
1324 
1325 		/* Set backpressure level for RQ's Aura */
1326 		aq->aura.bp = RQ_BP_LVL_AURA;
1327 	}
1328 
1329 	/* Fill AQ info */
1330 	aq->ctype = NPA_AQ_CTYPE_AURA;
1331 	aq->op = NPA_AQ_INSTOP_INIT;
1332 
1333 	return 0;
1334 }
1335 
otx2_pool_init(struct otx2_nic * pfvf,u16 pool_id,int stack_pages,int numptrs,int buf_size)1336 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1337 		   int stack_pages, int numptrs, int buf_size)
1338 {
1339 	struct npa_aq_enq_req *aq;
1340 	struct otx2_pool *pool;
1341 	int err;
1342 
1343 	pool = &pfvf->qset.pool[pool_id];
1344 	/* Alloc memory for stack which is used to store buffer pointers */
1345 	err = qmem_alloc(pfvf->dev, &pool->stack,
1346 			 stack_pages, pfvf->hw.stack_pg_bytes);
1347 	if (err)
1348 		return err;
1349 
1350 	pool->rbsize = buf_size;
1351 
1352 	/* Initialize this pool's context via AF */
1353 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1354 	if (!aq) {
1355 		/* Shared mbox memory buffer is full, flush it and retry */
1356 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1357 		if (err) {
1358 			qmem_free(pfvf->dev, pool->stack);
1359 			return err;
1360 		}
1361 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1362 		if (!aq) {
1363 			qmem_free(pfvf->dev, pool->stack);
1364 			return -ENOMEM;
1365 		}
1366 	}
1367 
1368 	aq->aura_id = pool_id;
1369 	aq->pool.stack_base = pool->stack->iova;
1370 	aq->pool.stack_caching = 1;
1371 	aq->pool.ena = 1;
1372 	aq->pool.buf_size = buf_size / 128;
1373 	aq->pool.stack_max_pages = stack_pages;
1374 	aq->pool.shift = ilog2(numptrs) - 8;
1375 	aq->pool.ptr_start = 0;
1376 	aq->pool.ptr_end = ~0ULL;
1377 
1378 	/* Fill AQ info */
1379 	aq->ctype = NPA_AQ_CTYPE_POOL;
1380 	aq->op = NPA_AQ_INSTOP_INIT;
1381 
1382 	return 0;
1383 }
1384 
otx2_sq_aura_pool_init(struct otx2_nic * pfvf)1385 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1386 {
1387 	int qidx, pool_id, stack_pages, num_sqbs;
1388 	struct otx2_qset *qset = &pfvf->qset;
1389 	struct otx2_hw *hw = &pfvf->hw;
1390 	struct otx2_snd_queue *sq;
1391 	struct otx2_pool *pool;
1392 	dma_addr_t bufptr;
1393 	int err, ptr;
1394 
1395 	/* Calculate number of SQBs needed.
1396 	 *
1397 	 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1398 	 * Last SQE is used for pointing to next SQB.
1399 	 */
1400 	num_sqbs = (hw->sqb_size / 128) - 1;
1401 	num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1402 
1403 	/* Get no of stack pages needed */
1404 	stack_pages =
1405 		(num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1406 
1407 	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1408 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1409 		/* Initialize aura context */
1410 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1411 		if (err)
1412 			goto fail;
1413 
1414 		/* Initialize pool context */
1415 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1416 				     num_sqbs, hw->sqb_size);
1417 		if (err)
1418 			goto fail;
1419 	}
1420 
1421 	/* Flush accumulated messages */
1422 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1423 	if (err)
1424 		goto fail;
1425 
1426 	/* Allocate pointers and free them to aura/pool */
1427 	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1428 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1429 		pool = &pfvf->qset.pool[pool_id];
1430 
1431 		sq = &qset->sq[qidx];
1432 		sq->sqb_count = 0;
1433 		sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1434 		if (!sq->sqb_ptrs) {
1435 			err = -ENOMEM;
1436 			goto err_mem;
1437 		}
1438 
1439 		for (ptr = 0; ptr < num_sqbs; ptr++) {
1440 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1441 			if (err)
1442 				goto err_mem;
1443 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1444 			sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1445 		}
1446 	}
1447 
1448 err_mem:
1449 	return err ? -ENOMEM : 0;
1450 
1451 fail:
1452 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1453 	otx2_aura_pool_free(pfvf);
1454 	return err;
1455 }
1456 
otx2_rq_aura_pool_init(struct otx2_nic * pfvf)1457 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1458 {
1459 	struct otx2_hw *hw = &pfvf->hw;
1460 	int stack_pages, pool_id, rq;
1461 	struct otx2_pool *pool;
1462 	int err, ptr, num_ptrs;
1463 	dma_addr_t bufptr;
1464 
1465 	num_ptrs = pfvf->qset.rqe_cnt;
1466 
1467 	stack_pages =
1468 		(num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1469 
1470 	for (rq = 0; rq < hw->rx_queues; rq++) {
1471 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1472 		/* Initialize aura context */
1473 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1474 		if (err)
1475 			goto fail;
1476 	}
1477 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1478 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1479 				     num_ptrs, pfvf->rbsize);
1480 		if (err)
1481 			goto fail;
1482 	}
1483 
1484 	/* Flush accumulated messages */
1485 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1486 	if (err)
1487 		goto fail;
1488 
1489 	/* Allocate pointers and free them to aura/pool */
1490 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1491 		pool = &pfvf->qset.pool[pool_id];
1492 		for (ptr = 0; ptr < num_ptrs; ptr++) {
1493 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1494 			if (err)
1495 				return -ENOMEM;
1496 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1497 						   bufptr + OTX2_HEAD_ROOM);
1498 		}
1499 	}
1500 	return 0;
1501 fail:
1502 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1503 	otx2_aura_pool_free(pfvf);
1504 	return err;
1505 }
1506 
otx2_config_npa(struct otx2_nic * pfvf)1507 int otx2_config_npa(struct otx2_nic *pfvf)
1508 {
1509 	struct otx2_qset *qset = &pfvf->qset;
1510 	struct npa_lf_alloc_req  *npalf;
1511 	struct otx2_hw *hw = &pfvf->hw;
1512 	int aura_cnt;
1513 
1514 	/* Pool - Stack of free buffer pointers
1515 	 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1516 	 */
1517 
1518 	if (!hw->pool_cnt)
1519 		return -EINVAL;
1520 
1521 	qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1522 				  sizeof(struct otx2_pool), GFP_KERNEL);
1523 	if (!qset->pool)
1524 		return -ENOMEM;
1525 
1526 	/* Get memory to put this msg */
1527 	npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1528 	if (!npalf)
1529 		return -ENOMEM;
1530 
1531 	/* Set aura and pool counts */
1532 	npalf->nr_pools = hw->pool_cnt;
1533 	aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1534 	npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1535 
1536 	return otx2_sync_mbox_msg(&pfvf->mbox);
1537 }
1538 
otx2_detach_resources(struct mbox * mbox)1539 int otx2_detach_resources(struct mbox *mbox)
1540 {
1541 	struct rsrc_detach *detach;
1542 
1543 	mutex_lock(&mbox->lock);
1544 	detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1545 	if (!detach) {
1546 		mutex_unlock(&mbox->lock);
1547 		return -ENOMEM;
1548 	}
1549 
1550 	/* detach all */
1551 	detach->partial = false;
1552 
1553 	/* Send detach request to AF */
1554 	otx2_mbox_msg_send(&mbox->mbox, 0);
1555 	mutex_unlock(&mbox->lock);
1556 	return 0;
1557 }
1558 EXPORT_SYMBOL(otx2_detach_resources);
1559 
otx2_attach_npa_nix(struct otx2_nic * pfvf)1560 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1561 {
1562 	struct rsrc_attach *attach;
1563 	struct msg_req *msix;
1564 	int err;
1565 
1566 	mutex_lock(&pfvf->mbox.lock);
1567 	/* Get memory to put this msg */
1568 	attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1569 	if (!attach) {
1570 		mutex_unlock(&pfvf->mbox.lock);
1571 		return -ENOMEM;
1572 	}
1573 
1574 	attach->npalf = true;
1575 	attach->nixlf = true;
1576 
1577 	/* Send attach request to AF */
1578 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1579 	if (err) {
1580 		mutex_unlock(&pfvf->mbox.lock);
1581 		return err;
1582 	}
1583 
1584 	pfvf->nix_blkaddr = BLKADDR_NIX0;
1585 
1586 	/* If the platform has two NIX blocks then LF may be
1587 	 * allocated from NIX1.
1588 	 */
1589 	if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1590 		pfvf->nix_blkaddr = BLKADDR_NIX1;
1591 
1592 	/* Get NPA and NIX MSIX vector offsets */
1593 	msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1594 	if (!msix) {
1595 		mutex_unlock(&pfvf->mbox.lock);
1596 		return -ENOMEM;
1597 	}
1598 
1599 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1600 	if (err) {
1601 		mutex_unlock(&pfvf->mbox.lock);
1602 		return err;
1603 	}
1604 	mutex_unlock(&pfvf->mbox.lock);
1605 
1606 	if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1607 	    pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1608 		dev_err(pfvf->dev,
1609 			"RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1610 		return -EINVAL;
1611 	}
1612 
1613 	return 0;
1614 }
1615 EXPORT_SYMBOL(otx2_attach_npa_nix);
1616 
otx2_ctx_disable(struct mbox * mbox,int type,bool npa)1617 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1618 {
1619 	struct hwctx_disable_req *req;
1620 
1621 	mutex_lock(&mbox->lock);
1622 	/* Request AQ to disable this context */
1623 	if (npa)
1624 		req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1625 	else
1626 		req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1627 
1628 	if (!req) {
1629 		mutex_unlock(&mbox->lock);
1630 		return;
1631 	}
1632 
1633 	req->ctype = type;
1634 
1635 	if (otx2_sync_mbox_msg(mbox))
1636 		dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1637 			__func__);
1638 
1639 	mutex_unlock(&mbox->lock);
1640 }
1641 
otx2_nix_config_bp(struct otx2_nic * pfvf,bool enable)1642 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1643 {
1644 	struct nix_bp_cfg_req *req;
1645 
1646 	if (enable)
1647 		req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1648 	else
1649 		req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1650 
1651 	if (!req)
1652 		return -ENOMEM;
1653 
1654 	req->chan_base = 0;
1655 #ifdef CONFIG_DCB
1656 	req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
1657 	req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
1658 #else
1659 	req->chan_cnt =  1;
1660 	req->bpid_per_chan = 0;
1661 #endif
1662 
1663 
1664 	return otx2_sync_mbox_msg(&pfvf->mbox);
1665 }
1666 EXPORT_SYMBOL(otx2_nix_config_bp);
1667 
1668 /* Mbox message handlers */
mbox_handler_cgx_stats(struct otx2_nic * pfvf,struct cgx_stats_rsp * rsp)1669 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1670 			    struct cgx_stats_rsp *rsp)
1671 {
1672 	int id;
1673 
1674 	for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1675 		pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1676 	for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1677 		pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1678 }
1679 
mbox_handler_cgx_fec_stats(struct otx2_nic * pfvf,struct cgx_fec_stats_rsp * rsp)1680 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1681 				struct cgx_fec_stats_rsp *rsp)
1682 {
1683 	pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1684 	pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1685 }
1686 
mbox_handler_npa_lf_alloc(struct otx2_nic * pfvf,struct npa_lf_alloc_rsp * rsp)1687 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1688 			       struct npa_lf_alloc_rsp *rsp)
1689 {
1690 	pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1691 	pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1692 }
1693 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1694 
mbox_handler_nix_lf_alloc(struct otx2_nic * pfvf,struct nix_lf_alloc_rsp * rsp)1695 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1696 			       struct nix_lf_alloc_rsp *rsp)
1697 {
1698 	pfvf->hw.sqb_size = rsp->sqb_size;
1699 	pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1700 	pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1701 	pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1702 	pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1703 	pfvf->hw.cgx_links = rsp->cgx_links;
1704 	pfvf->hw.lbk_links = rsp->lbk_links;
1705 	pfvf->hw.tx_link = rsp->tx_link;
1706 }
1707 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1708 
mbox_handler_msix_offset(struct otx2_nic * pfvf,struct msix_offset_rsp * rsp)1709 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1710 			      struct msix_offset_rsp *rsp)
1711 {
1712 	pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1713 	pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1714 }
1715 EXPORT_SYMBOL(mbox_handler_msix_offset);
1716 
mbox_handler_nix_bp_enable(struct otx2_nic * pfvf,struct nix_bp_cfg_rsp * rsp)1717 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1718 				struct nix_bp_cfg_rsp *rsp)
1719 {
1720 	int chan, chan_id;
1721 
1722 	for (chan = 0; chan < rsp->chan_cnt; chan++) {
1723 		chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1724 		pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1725 	}
1726 }
1727 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1728 
otx2_free_cints(struct otx2_nic * pfvf,int n)1729 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1730 {
1731 	struct otx2_qset *qset = &pfvf->qset;
1732 	struct otx2_hw *hw = &pfvf->hw;
1733 	int irq, qidx;
1734 
1735 	for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1736 	     qidx < n;
1737 	     qidx++, irq++) {
1738 		int vector = pci_irq_vector(pfvf->pdev, irq);
1739 
1740 		irq_set_affinity_hint(vector, NULL);
1741 		free_cpumask_var(hw->affinity_mask[irq]);
1742 		free_irq(vector, &qset->napi[qidx]);
1743 	}
1744 }
1745 
otx2_set_cints_affinity(struct otx2_nic * pfvf)1746 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1747 {
1748 	struct otx2_hw *hw = &pfvf->hw;
1749 	int vec, cpu, irq, cint;
1750 
1751 	vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1752 	cpu = cpumask_first(cpu_online_mask);
1753 
1754 	/* CQ interrupts */
1755 	for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1756 		if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1757 			return;
1758 
1759 		cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1760 
1761 		irq = pci_irq_vector(pfvf->pdev, vec);
1762 		irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1763 
1764 		cpu = cpumask_next(cpu, cpu_online_mask);
1765 		if (unlikely(cpu >= nr_cpu_ids))
1766 			cpu = 0;
1767 	}
1768 }
1769 
otx2_get_max_mtu(struct otx2_nic * pfvf)1770 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1771 {
1772 	struct nix_hw_info *rsp;
1773 	struct msg_req *req;
1774 	u16 max_mtu;
1775 	int rc;
1776 
1777 	mutex_lock(&pfvf->mbox.lock);
1778 
1779 	req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1780 	if (!req) {
1781 		rc =  -ENOMEM;
1782 		goto out;
1783 	}
1784 
1785 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
1786 	if (!rc) {
1787 		rsp = (struct nix_hw_info *)
1788 		       otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1789 
1790 		/* HW counts VLAN insertion bytes (8 for double tag)
1791 		 * irrespective of whether SQE is requesting to insert VLAN
1792 		 * in the packet or not. Hence these 8 bytes have to be
1793 		 * discounted from max packet size otherwise HW will throw
1794 		 * SMQ errors
1795 		 */
1796 		max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1797 
1798 		/* Also save DWRR MTU, needed for DWRR weight calculation */
1799 		pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu;
1800 		if (!pfvf->hw.dwrr_mtu)
1801 			pfvf->hw.dwrr_mtu = 1;
1802 	}
1803 
1804 out:
1805 	mutex_unlock(&pfvf->mbox.lock);
1806 	if (rc) {
1807 		dev_warn(pfvf->dev,
1808 			 "Failed to get MTU from hardware setting default value(1500)\n");
1809 		max_mtu = 1500;
1810 	}
1811 	return max_mtu;
1812 }
1813 EXPORT_SYMBOL(otx2_get_max_mtu);
1814 
otx2_handle_ntuple_tc_features(struct net_device * netdev,netdev_features_t features)1815 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features)
1816 {
1817 	netdev_features_t changed = features ^ netdev->features;
1818 	struct otx2_nic *pfvf = netdev_priv(netdev);
1819 	bool ntuple = !!(features & NETIF_F_NTUPLE);
1820 	bool tc = !!(features & NETIF_F_HW_TC);
1821 
1822 	if ((changed & NETIF_F_NTUPLE) && !ntuple)
1823 		otx2_destroy_ntuple_flows(pfvf);
1824 
1825 	if ((changed & NETIF_F_NTUPLE) && ntuple) {
1826 		if (!pfvf->flow_cfg->max_flows) {
1827 			netdev_err(netdev,
1828 				   "Can't enable NTUPLE, MCAM entries not allocated\n");
1829 			return -EINVAL;
1830 		}
1831 	}
1832 
1833 	if ((changed & NETIF_F_HW_TC) && tc) {
1834 		if (!pfvf->flow_cfg->max_flows) {
1835 			netdev_err(netdev,
1836 				   "Can't enable TC, MCAM entries not allocated\n");
1837 			return -EINVAL;
1838 		}
1839 	}
1840 
1841 	if ((changed & NETIF_F_HW_TC) && !tc &&
1842 	    pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) {
1843 		netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1844 		return -EBUSY;
1845 	}
1846 
1847 	if ((changed & NETIF_F_NTUPLE) && ntuple &&
1848 	    (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) {
1849 		netdev_err(netdev,
1850 			   "Can't enable NTUPLE when TC is active, disable TC and retry\n");
1851 		return -EINVAL;
1852 	}
1853 
1854 	if ((changed & NETIF_F_HW_TC) && tc &&
1855 	    (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) {
1856 		netdev_err(netdev,
1857 			   "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n");
1858 		return -EINVAL;
1859 	}
1860 
1861 	return 0;
1862 }
1863 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
1864 
1865 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
1866 int __weak								\
1867 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf,		\
1868 				struct _req_type *req,			\
1869 				struct _rsp_type *rsp)			\
1870 {									\
1871 	/* Nothing to do here */					\
1872 	return 0;							\
1873 }									\
1874 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1875 MBOX_UP_CGX_MESSAGES
1876 MBOX_UP_MCS_MESSAGES
1877 #undef M
1878