1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44 #include <linux/android_kabi.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
pci_slot_name(const struct pci_slot * slot)84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 };
135
136 /**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153 };
154
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
157
158 /*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
167 /*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
171 typedef int __bitwise pci_power_t;
172
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
180
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
183
pci_power_name(pci_power_t state)184 static inline const char *pci_power_name(pci_power_t state)
185 {
186 return pci_power_names[1 + (__force int) state];
187 }
188
189 /**
190 * typedef pci_channel_state_t
191 *
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
195 */
196 typedef unsigned int __bitwise pci_channel_state_t;
197
198 enum {
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207 };
208
209 typedef unsigned int __bitwise pcie_reset_state_t;
210
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220 };
221
222 typedef unsigned short __bitwise pci_dev_flags_t;
223 enum pci_dev_flags {
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248 };
249
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253 };
254
255 typedef unsigned short __bitwise pci_bus_flags_t;
256 enum pci_bus_flags {
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
261 };
262
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
270 PCIE_LNK_X12 = 0x0c,
271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
274 };
275
276 /* See matching string table in pci_speed_string() */
277 enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
304 };
305
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
309 struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
313 };
314
315 struct irq_affinity;
316 struct pcie_link_state;
317 struct pci_sriov;
318 struct pci_p2pdma;
319 struct rcec_ea;
320
321 /* The pci_dev structure describes PCI devices */
322 struct pci_dev {
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
326
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
330
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
342 #endif
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
346 #endif
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
364 struct device_dma_parameters dma_parms;
365
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 unsigned int imm_ready:1; /* Supports Immediate Readiness */
370 u8 pm_cap; /* PM capability offset */
371 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 can be generated */
373 unsigned int pme_poll:1; /* Poll device's PME status bit */
374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
382 unsigned int wakeup_prepared:1;
383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
387 user sysfs */
388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 bit manually */
390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
392
393 #ifdef CONFIG_PCIEASPM
394 struct pcie_link_state *link_state; /* ASPM link state */
395 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 supported from root to here */
397 u16 l1ss; /* L1SS Capability pointer */
398 #endif
399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
401
402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
404
405 int cfg_size; /* Size of config space */
406
407 /*
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
410 */
411 unsigned int irq;
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413
414 bool match_driver; /* Skip attaching driver */
415
416 unsigned int transparent:1; /* Subtractive decode bridge */
417 unsigned int io_window:1; /* Bridge has I/O window */
418 unsigned int pref_window:1; /* Bridge has pref mem window */
419 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
420 unsigned int multifunction:1; /* Multi-function device */
421
422 unsigned int is_busmaster:1; /* Is busmaster */
423 unsigned int no_msi:1; /* May not use MSI */
424 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
425 unsigned int block_cfg_access:1; /* Config space access blocked */
426 unsigned int broken_parity_status:1; /* Generates false positive parity */
427 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
428 unsigned int msi_enabled:1;
429 unsigned int msix_enabled:1;
430 unsigned int ari_enabled:1; /* ARI forwarding */
431 unsigned int ats_enabled:1; /* Address Translation Svc */
432 unsigned int pasid_enabled:1; /* Process Address Space ID */
433 unsigned int pri_enabled:1; /* Page Request Interface */
434 unsigned int is_managed:1; /* Managed via devres */
435 unsigned int is_msi_managed:1; /* MSI release via devres installed */
436 unsigned int needs_freset:1; /* Requires fundamental reset */
437 unsigned int state_saved:1;
438 unsigned int is_physfn:1;
439 unsigned int is_virtfn:1;
440 unsigned int is_hotplug_bridge:1;
441 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
442 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
443 /*
444 * Devices marked being untrusted are the ones that can potentially
445 * execute DMA attacks and similar. They are typically connected
446 * through external ports such as Thunderbolt but not limited to
447 * that. When an IOMMU is enabled they should be getting full
448 * mappings to make sure they cannot access arbitrary memory.
449 */
450 unsigned int untrusted:1;
451 /*
452 * Info from the platform, e.g., ACPI or device tree, may mark a
453 * device as "external-facing". An external-facing device is
454 * itself internal but devices downstream from it are external.
455 */
456 unsigned int external_facing:1;
457 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
458 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
459 unsigned int irq_managed:1;
460 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
461 unsigned int is_probed:1; /* Device probing in progress */
462 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
463 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
464 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
465 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
466 pci_dev_flags_t dev_flags;
467 atomic_t enable_cnt; /* pci_enable_device has been called */
468
469 u32 saved_config_space[16]; /* Config space saved at suspend time */
470 struct hlist_head saved_cap_space;
471 int rom_attr_enabled; /* Display of ROM attribute enabled? */
472 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
473 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
474
475 #ifdef CONFIG_HOTPLUG_PCI_PCIE
476 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
477 #endif
478 #ifdef CONFIG_PCIE_PTM
479 u16 ptm_cap; /* PTM Capability */
480 unsigned int ptm_root:1;
481 unsigned int ptm_enabled:1;
482 u8 ptm_granularity;
483 #endif
484 #ifdef CONFIG_PCI_MSI
485 void __iomem *msix_base;
486 raw_spinlock_t msi_lock;
487 #endif
488 struct pci_vpd vpd;
489 #ifdef CONFIG_PCIE_DPC
490 u16 dpc_cap;
491 unsigned int dpc_rp_extensions:1;
492 u8 dpc_rp_log_size;
493 #endif
494 #ifdef CONFIG_PCI_ATS
495 union {
496 struct pci_sriov *sriov; /* PF: SR-IOV info */
497 struct pci_dev *physfn; /* VF: related PF */
498 };
499 u16 ats_cap; /* ATS Capability offset */
500 u8 ats_stu; /* ATS Smallest Translation Unit */
501 #endif
502 #ifdef CONFIG_PCI_PRI
503 u16 pri_cap; /* PRI Capability offset */
504 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
505 unsigned int pasid_required:1; /* PRG Response PASID Required */
506 #endif
507 #ifdef CONFIG_PCI_PASID
508 u16 pasid_cap; /* PASID Capability offset */
509 u16 pasid_features;
510 #endif
511 #ifdef CONFIG_PCI_P2PDMA
512 struct pci_p2pdma __rcu *p2pdma;
513 #endif
514 u16 acs_cap; /* ACS Capability offset */
515 phys_addr_t rom; /* Physical address if not from BAR */
516 size_t romlen; /* Length if not from BAR */
517 /*
518 * Driver name to force a match. Do not set directly, because core
519 * frees it. Use driver_set_override() to set or clear it.
520 */
521 const char *driver_override;
522
523 unsigned long priv_flags; /* Private flags for the PCI driver */
524
525 /* These methods index pci_reset_fn_methods[] */
526 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
527
528 ANDROID_KABI_RESERVE(1);
529 ANDROID_KABI_RESERVE(2);
530 ANDROID_KABI_RESERVE(3);
531 ANDROID_KABI_RESERVE(4);
532 };
533
pci_physfn(struct pci_dev * dev)534 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
535 {
536 #ifdef CONFIG_PCI_IOV
537 if (dev->is_virtfn)
538 dev = dev->physfn;
539 #endif
540 return dev;
541 }
542
543 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
544
545 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
546 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
547
pci_channel_offline(struct pci_dev * pdev)548 static inline int pci_channel_offline(struct pci_dev *pdev)
549 {
550 return (pdev->error_state != pci_channel_io_normal);
551 }
552
553 /*
554 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
555 * Group number is limited to a 16-bit value, therefore (int)-1 is
556 * not a valid PCI domain number, and can be used as a sentinel
557 * value indicating ->domain_nr is not set by the driver (and
558 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
559 * pci_bus_find_domain_nr()).
560 */
561 #define PCI_DOMAIN_NR_NOT_SET (-1)
562
563 struct pci_host_bridge {
564 struct device dev;
565 struct pci_bus *bus; /* Root bus */
566 struct pci_ops *ops;
567 struct pci_ops *child_ops;
568 void *sysdata;
569 int busnr;
570 int domain_nr;
571 struct list_head windows; /* resource_entry */
572 struct list_head dma_ranges; /* dma ranges resource list */
573 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
574 int (*map_irq)(const struct pci_dev *, u8, u8);
575 void (*release_fn)(struct pci_host_bridge *);
576 void *release_data;
577 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
578 unsigned int no_ext_tags:1; /* No Extended Tags */
579 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
580 unsigned int native_aer:1; /* OS may use PCIe AER */
581 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
582 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
583 unsigned int native_pme:1; /* OS may use PCIe PME */
584 unsigned int native_ltr:1; /* OS may use PCIe LTR */
585 unsigned int native_dpc:1; /* OS may use PCIe DPC */
586 unsigned int preserve_config:1; /* Preserve FW resource setup */
587 unsigned int size_windows:1; /* Enable root bus sizing */
588 unsigned int msi_domain:1; /* Bridge wants MSI domain */
589
590 /* Resource alignment requirements */
591 resource_size_t (*align_resource)(struct pci_dev *dev,
592 const struct resource *res,
593 resource_size_t start,
594 resource_size_t size,
595 resource_size_t align);
596
597 ANDROID_KABI_RESERVE(1);
598 ANDROID_KABI_RESERVE(2);
599
600 unsigned long private[] ____cacheline_aligned;
601 };
602
603 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
604
pci_host_bridge_priv(struct pci_host_bridge * bridge)605 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
606 {
607 return (void *)bridge->private;
608 }
609
pci_host_bridge_from_priv(void * priv)610 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
611 {
612 return container_of(priv, struct pci_host_bridge, private);
613 }
614
615 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
616 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
617 size_t priv);
618 void pci_free_host_bridge(struct pci_host_bridge *bridge);
619 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
620
621 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
622 void (*release_fn)(struct pci_host_bridge *),
623 void *release_data);
624
625 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
626
627 /*
628 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
629 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
630 * buses below host bridges or subtractive decode bridges) go in the list.
631 * Use pci_bus_for_each_resource() to iterate through all the resources.
632 */
633
634 /*
635 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
636 * and there's no way to program the bridge with the details of the window.
637 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
638 * decode bit set, because they are explicit and can be programmed with _SRS.
639 */
640 #define PCI_SUBTRACTIVE_DECODE 0x1
641
642 struct pci_bus_resource {
643 struct list_head list;
644 struct resource *res;
645 unsigned int flags;
646 };
647
648 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
649
650 struct pci_bus {
651 struct list_head node; /* Node in list of buses */
652 struct pci_bus *parent; /* Parent bus this bridge is on */
653 struct list_head children; /* List of child buses */
654 struct list_head devices; /* List of devices on this bus */
655 struct pci_dev *self; /* Bridge device as seen by parent */
656 struct list_head slots; /* List of slots on this bus;
657 protected by pci_slot_mutex */
658 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
659 struct list_head resources; /* Address space routed to this bus */
660 struct resource busn_res; /* Bus numbers routed to this bus */
661
662 struct pci_ops *ops; /* Configuration access functions */
663 void *sysdata; /* Hook for sys-specific extension */
664 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
665
666 unsigned char number; /* Bus number */
667 unsigned char primary; /* Number of primary bridge */
668 unsigned char max_bus_speed; /* enum pci_bus_speed */
669 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670 #ifdef CONFIG_PCI_DOMAINS_GENERIC
671 int domain_nr;
672 #endif
673
674 char name[48];
675
676 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
677 pci_bus_flags_t bus_flags; /* Inherited by child buses */
678 struct device *bridge;
679 struct device dev;
680 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
681 struct bin_attribute *legacy_mem; /* Legacy mem */
682 unsigned int is_added:1;
683 unsigned int unsafe_warn:1; /* warned about RW1C config write */
684
685 ANDROID_KABI_RESERVE(1);
686 ANDROID_KABI_RESERVE(2);
687 ANDROID_KABI_RESERVE(3);
688 ANDROID_KABI_RESERVE(4);
689 };
690
691 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
692
pci_dev_id(struct pci_dev * dev)693 static inline u16 pci_dev_id(struct pci_dev *dev)
694 {
695 return PCI_DEVID(dev->bus->number, dev->devfn);
696 }
697
698 /*
699 * Returns true if the PCI bus is root (behind host-PCI bridge),
700 * false otherwise
701 *
702 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
703 * This is incorrect because "virtual" buses added for SR-IOV (via
704 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
705 */
pci_is_root_bus(struct pci_bus * pbus)706 static inline bool pci_is_root_bus(struct pci_bus *pbus)
707 {
708 return !(pbus->parent);
709 }
710
711 /**
712 * pci_is_bridge - check if the PCI device is a bridge
713 * @dev: PCI device
714 *
715 * Return true if the PCI device is bridge whether it has subordinate
716 * or not.
717 */
pci_is_bridge(struct pci_dev * dev)718 static inline bool pci_is_bridge(struct pci_dev *dev)
719 {
720 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
721 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
722 }
723
724 #define for_each_pci_bridge(dev, bus) \
725 list_for_each_entry(dev, &bus->devices, bus_list) \
726 if (!pci_is_bridge(dev)) {} else
727
pci_upstream_bridge(struct pci_dev * dev)728 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
729 {
730 dev = pci_physfn(dev);
731 if (pci_is_root_bus(dev->bus))
732 return NULL;
733
734 return dev->bus->self;
735 }
736
737 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)738 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
739 {
740 return pci_dev->msi_enabled || pci_dev->msix_enabled;
741 }
742 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)743 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
744 #endif
745
746 /* Error values that may be returned by PCI functions */
747 #define PCIBIOS_SUCCESSFUL 0x00
748 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
749 #define PCIBIOS_BAD_VENDOR_ID 0x83
750 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
751 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
752 #define PCIBIOS_SET_FAILED 0x88
753 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
754
755 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)756 static inline int pcibios_err_to_errno(int err)
757 {
758 if (err <= PCIBIOS_SUCCESSFUL)
759 return err; /* Assume already errno */
760
761 switch (err) {
762 case PCIBIOS_FUNC_NOT_SUPPORTED:
763 return -ENOENT;
764 case PCIBIOS_BAD_VENDOR_ID:
765 return -ENOTTY;
766 case PCIBIOS_DEVICE_NOT_FOUND:
767 return -ENODEV;
768 case PCIBIOS_BAD_REGISTER_NUMBER:
769 return -EFAULT;
770 case PCIBIOS_SET_FAILED:
771 return -EIO;
772 case PCIBIOS_BUFFER_TOO_SMALL:
773 return -ENOSPC;
774 }
775
776 return -ERANGE;
777 }
778
779 /* Low-level architecture-dependent routines */
780
781 struct pci_ops {
782 int (*add_bus)(struct pci_bus *bus);
783 void (*remove_bus)(struct pci_bus *bus);
784 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
785 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
786 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
787
788 ANDROID_KABI_RESERVE(1);
789 };
790
791 /*
792 * ACPI needs to be able to access PCI config space before we've done a
793 * PCI bus scan and created pci_bus structures.
794 */
795 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
796 int reg, int len, u32 *val);
797 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
798 int reg, int len, u32 val);
799
800 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
801 typedef u64 pci_bus_addr_t;
802 #else
803 typedef u32 pci_bus_addr_t;
804 #endif
805
806 struct pci_bus_region {
807 pci_bus_addr_t start;
808 pci_bus_addr_t end;
809 };
810
811 struct pci_dynids {
812 spinlock_t lock; /* Protects list, index */
813 struct list_head list; /* For IDs added at runtime */
814 };
815
816
817 /*
818 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
819 * a set of callbacks in struct pci_error_handlers, that device driver
820 * will be notified of PCI bus errors, and will be driven to recovery
821 * when an error occurs.
822 */
823
824 typedef unsigned int __bitwise pci_ers_result_t;
825
826 enum pci_ers_result {
827 /* No result/none/not supported in device driver */
828 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
829
830 /* Device driver can recover without slot reset */
831 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
832
833 /* Device driver wants slot to be reset */
834 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
835
836 /* Device has completely failed, is unrecoverable */
837 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
838
839 /* Device driver is fully recovered and operational */
840 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
841
842 /* No AER capabilities registered for the driver */
843 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
844 };
845
846 /* PCI bus error event callbacks */
847 struct pci_error_handlers {
848 /* PCI bus error detected on this device */
849 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
850 pci_channel_state_t error);
851
852 /* MMIO has been re-enabled, but not DMA */
853 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
854
855 /* PCI slot has been reset */
856 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
857
858 /* PCI function reset prepare or completed */
859 void (*reset_prepare)(struct pci_dev *dev);
860 void (*reset_done)(struct pci_dev *dev);
861
862 /* Device driver may resume normal operations */
863 void (*resume)(struct pci_dev *dev);
864
865 ANDROID_KABI_RESERVE(1);
866 };
867
868
869 struct module;
870
871 /**
872 * struct pci_driver - PCI driver structure
873 * @node: List of driver structures.
874 * @name: Driver name.
875 * @id_table: Pointer to table of device IDs the driver is
876 * interested in. Most drivers should export this
877 * table using MODULE_DEVICE_TABLE(pci,...).
878 * @probe: This probing function gets called (during execution
879 * of pci_register_driver() for already existing
880 * devices or later if a new device gets inserted) for
881 * all PCI devices which match the ID table and are not
882 * "owned" by the other drivers yet. This function gets
883 * passed a "struct pci_dev \*" for each device whose
884 * entry in the ID table matches the device. The probe
885 * function returns zero when the driver chooses to
886 * take "ownership" of the device or an error code
887 * (negative number) otherwise.
888 * The probe function always gets called from process
889 * context, so it can sleep.
890 * @remove: The remove() function gets called whenever a device
891 * being handled by this driver is removed (either during
892 * deregistration of the driver or when it's manually
893 * pulled out of a hot-pluggable slot).
894 * The remove function always gets called from process
895 * context, so it can sleep.
896 * @suspend: Put device into low power state.
897 * @resume: Wake device from low power state.
898 * (Please see Documentation/power/pci.rst for descriptions
899 * of PCI Power Management and the related functions.)
900 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
901 * Intended to stop any idling DMA operations.
902 * Useful for enabling wake-on-lan (NIC) or changing
903 * the power state of a device before reboot.
904 * e.g. drivers/net/e100.c.
905 * @sriov_configure: Optional driver callback to allow configuration of
906 * number of VFs to enable via sysfs "sriov_numvfs" file.
907 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
908 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
909 * This will change MSI-X Table Size in the VF Message Control
910 * registers.
911 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
912 * MSI-X vectors available for distribution to the VFs.
913 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
914 * @groups: Sysfs attribute groups.
915 * @dev_groups: Attributes attached to the device that will be
916 * created once it is bound to the driver.
917 * @driver: Driver model structure.
918 * @dynids: List of dynamically added device IDs.
919 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
920 * For most device drivers, no need to care about this flag
921 * as long as all DMAs are handled through the kernel DMA API.
922 * For some special ones, for example VFIO drivers, they know
923 * how to manage the DMA themselves and set this flag so that
924 * the IOMMU layer will allow them to setup and manage their
925 * own I/O address space.
926 */
927 struct pci_driver {
928 struct list_head node;
929 const char *name;
930 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
931 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
932 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
933 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
934 int (*resume)(struct pci_dev *dev); /* Device woken up */
935 void (*shutdown)(struct pci_dev *dev);
936 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
937 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
938 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
939 const struct pci_error_handlers *err_handler;
940 const struct attribute_group **groups;
941 const struct attribute_group **dev_groups;
942 struct device_driver driver;
943 struct pci_dynids dynids;
944 bool driver_managed_dma;
945
946 ANDROID_KABI_RESERVE(1);
947 ANDROID_KABI_RESERVE(2);
948 ANDROID_KABI_RESERVE(3);
949 ANDROID_KABI_RESERVE(4);
950 };
951
to_pci_driver(struct device_driver * drv)952 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
953 {
954 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
955 }
956
957 /**
958 * PCI_DEVICE - macro used to describe a specific PCI device
959 * @vend: the 16 bit PCI Vendor ID
960 * @dev: the 16 bit PCI Device ID
961 *
962 * This macro is used to create a struct pci_device_id that matches a
963 * specific device. The subvendor and subdevice fields will be set to
964 * PCI_ANY_ID.
965 */
966 #define PCI_DEVICE(vend,dev) \
967 .vendor = (vend), .device = (dev), \
968 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
969
970 /**
971 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
972 * override_only flags.
973 * @vend: the 16 bit PCI Vendor ID
974 * @dev: the 16 bit PCI Device ID
975 * @driver_override: the 32 bit PCI Device override_only
976 *
977 * This macro is used to create a struct pci_device_id that matches only a
978 * driver_override device. The subvendor and subdevice fields will be set to
979 * PCI_ANY_ID.
980 */
981 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
982 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
983 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
984
985 /**
986 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
987 * "driver_override" PCI device.
988 * @vend: the 16 bit PCI Vendor ID
989 * @dev: the 16 bit PCI Device ID
990 *
991 * This macro is used to create a struct pci_device_id that matches a
992 * specific device. The subvendor and subdevice fields will be set to
993 * PCI_ANY_ID and the driver_override will be set to
994 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
995 */
996 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
997 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
998
999 /**
1000 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
1001 * @vend: the 16 bit PCI Vendor ID
1002 * @dev: the 16 bit PCI Device ID
1003 * @subvend: the 16 bit PCI Subvendor ID
1004 * @subdev: the 16 bit PCI Subdevice ID
1005 *
1006 * This macro is used to create a struct pci_device_id that matches a
1007 * specific device with subsystem information.
1008 */
1009 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1010 .vendor = (vend), .device = (dev), \
1011 .subvendor = (subvend), .subdevice = (subdev)
1012
1013 /**
1014 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1015 * @dev_class: the class, subclass, prog-if triple for this device
1016 * @dev_class_mask: the class mask for this device
1017 *
1018 * This macro is used to create a struct pci_device_id that matches a
1019 * specific PCI class. The vendor, device, subvendor, and subdevice
1020 * fields will be set to PCI_ANY_ID.
1021 */
1022 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1023 .class = (dev_class), .class_mask = (dev_class_mask), \
1024 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1025 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1026
1027 /**
1028 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1029 * @vend: the vendor name
1030 * @dev: the 16 bit PCI Device ID
1031 *
1032 * This macro is used to create a struct pci_device_id that matches a
1033 * specific PCI device. The subvendor, and subdevice fields will be set
1034 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1035 * private data.
1036 */
1037 #define PCI_VDEVICE(vend, dev) \
1038 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1039 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1040
1041 /**
1042 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1043 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1044 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1045 * @data: the driver data to be filled
1046 *
1047 * This macro is used to create a struct pci_device_id that matches a
1048 * specific PCI device. The subvendor, and subdevice fields will be set
1049 * to PCI_ANY_ID.
1050 */
1051 #define PCI_DEVICE_DATA(vend, dev, data) \
1052 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1053 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1054 .driver_data = (kernel_ulong_t)(data)
1055
1056 enum {
1057 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1058 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1059 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1060 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1061 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1062 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1063 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1064 };
1065
1066 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1067 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1068 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1069 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1070
1071 /* These external functions are only available when PCI support is enabled */
1072 #ifdef CONFIG_PCI
1073
1074 extern unsigned int pci_flags;
1075
pci_set_flags(int flags)1076 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1077 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1078 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1079 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1080
1081 void pcie_bus_configure_settings(struct pci_bus *bus);
1082
1083 enum pcie_bus_config_types {
1084 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1085 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1086 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1087 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1088 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1089 };
1090
1091 extern enum pcie_bus_config_types pcie_bus_config;
1092
1093 extern struct bus_type pci_bus_type;
1094
1095 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1096 * code, or PCI core code. */
1097 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1098 /* Some device drivers need know if PCI is initiated */
1099 int no_pci_devices(void);
1100
1101 void pcibios_resource_survey_bus(struct pci_bus *bus);
1102 void pcibios_bus_add_device(struct pci_dev *pdev);
1103 void pcibios_add_bus(struct pci_bus *bus);
1104 void pcibios_remove_bus(struct pci_bus *bus);
1105 void pcibios_fixup_bus(struct pci_bus *);
1106 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1107 /* Architecture-specific versions may override this (weak) */
1108 char *pcibios_setup(char *str);
1109
1110 /* Used only when drivers/pci/setup.c is used */
1111 resource_size_t pcibios_align_resource(void *, const struct resource *,
1112 resource_size_t,
1113 resource_size_t);
1114
1115 /* Weak but can be overridden by arch */
1116 void pci_fixup_cardbus(struct pci_bus *);
1117
1118 /* Generic PCI functions used internally */
1119
1120 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1121 struct resource *res);
1122 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1123 struct pci_bus_region *region);
1124 void pcibios_scan_specific_bus(int busn);
1125 struct pci_bus *pci_find_bus(int domain, int busnr);
1126 void pci_bus_add_devices(const struct pci_bus *bus);
1127 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1128 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1129 struct pci_ops *ops, void *sysdata,
1130 struct list_head *resources);
1131 int pci_host_probe(struct pci_host_bridge *bridge);
1132 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1133 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1134 void pci_bus_release_busn_res(struct pci_bus *b);
1135 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1136 struct pci_ops *ops, void *sysdata,
1137 struct list_head *resources);
1138 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1139 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1140 int busnr);
1141 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1142 const char *name,
1143 struct hotplug_slot *hotplug);
1144 void pci_destroy_slot(struct pci_slot *slot);
1145 #ifdef CONFIG_SYSFS
1146 void pci_dev_assign_slot(struct pci_dev *dev);
1147 #else
pci_dev_assign_slot(struct pci_dev * dev)1148 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1149 #endif
1150 int pci_scan_slot(struct pci_bus *bus, int devfn);
1151 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1152 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1153 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1154 void pci_bus_add_device(struct pci_dev *dev);
1155 void pci_read_bridge_bases(struct pci_bus *child);
1156 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1157 struct resource *res);
1158 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1159 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1160 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1161 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1162 void pci_dev_put(struct pci_dev *dev);
1163 void pci_remove_bus(struct pci_bus *b);
1164 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1165 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1166 void pci_stop_root_bus(struct pci_bus *bus);
1167 void pci_remove_root_bus(struct pci_bus *bus);
1168 void pci_setup_cardbus(struct pci_bus *bus);
1169 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1170 void pci_sort_breadthfirst(void);
1171 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1172 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1173
1174 /* Generic PCI functions exported to card drivers */
1175
1176 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1177 u8 pci_find_capability(struct pci_dev *dev, int cap);
1178 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1179 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1180 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1181 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1182 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1183 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1184 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1185 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1186
1187 u64 pci_get_dsn(struct pci_dev *dev);
1188
1189 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1190 struct pci_dev *from);
1191 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1192 unsigned int ss_vendor, unsigned int ss_device,
1193 struct pci_dev *from);
1194 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1195 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1196 unsigned int devfn);
1197 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1198 int pci_dev_present(const struct pci_device_id *ids);
1199
1200 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1201 int where, u8 *val);
1202 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1203 int where, u16 *val);
1204 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1205 int where, u32 *val);
1206 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1207 int where, u8 val);
1208 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1209 int where, u16 val);
1210 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1211 int where, u32 val);
1212
1213 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1214 int where, int size, u32 *val);
1215 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1216 int where, int size, u32 val);
1217 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1218 int where, int size, u32 *val);
1219 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1220 int where, int size, u32 val);
1221
1222 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1223
1224 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1225 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1226 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1227 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1228 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1229 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1230
1231 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1232 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1233 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1234 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1235 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1236 u16 clear, u16 set);
1237 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1238 u32 clear, u32 set);
1239
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1240 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1241 u16 set)
1242 {
1243 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1244 }
1245
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1246 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1247 u32 set)
1248 {
1249 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1250 }
1251
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1252 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1253 u16 clear)
1254 {
1255 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1256 }
1257
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1258 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1259 u32 clear)
1260 {
1261 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1262 }
1263
1264 /* User-space driven config access */
1265 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1266 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1267 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1268 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1269 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1270 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1271
1272 int __must_check pci_enable_device(struct pci_dev *dev);
1273 int __must_check pci_enable_device_io(struct pci_dev *dev);
1274 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1275 int __must_check pci_reenable_device(struct pci_dev *);
1276 int __must_check pcim_enable_device(struct pci_dev *pdev);
1277 void pcim_pin_device(struct pci_dev *pdev);
1278
pci_intx_mask_supported(struct pci_dev * pdev)1279 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1280 {
1281 /*
1282 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1283 * writable and no quirk has marked the feature broken.
1284 */
1285 return !pdev->broken_intx_masking;
1286 }
1287
pci_is_enabled(struct pci_dev * pdev)1288 static inline int pci_is_enabled(struct pci_dev *pdev)
1289 {
1290 return (atomic_read(&pdev->enable_cnt) > 0);
1291 }
1292
pci_is_managed(struct pci_dev * pdev)1293 static inline int pci_is_managed(struct pci_dev *pdev)
1294 {
1295 return pdev->is_managed;
1296 }
1297
1298 void pci_disable_device(struct pci_dev *dev);
1299
1300 extern unsigned int pcibios_max_latency;
1301 void pci_set_master(struct pci_dev *dev);
1302 void pci_clear_master(struct pci_dev *dev);
1303
1304 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1305 int pci_set_cacheline_size(struct pci_dev *dev);
1306 int __must_check pci_set_mwi(struct pci_dev *dev);
1307 int __must_check pcim_set_mwi(struct pci_dev *dev);
1308 int pci_try_set_mwi(struct pci_dev *dev);
1309 void pci_clear_mwi(struct pci_dev *dev);
1310 void pci_disable_parity(struct pci_dev *dev);
1311 void pci_intx(struct pci_dev *dev, int enable);
1312 bool pci_check_and_mask_intx(struct pci_dev *dev);
1313 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1314 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1315 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1316 int pcix_get_max_mmrbc(struct pci_dev *dev);
1317 int pcix_get_mmrbc(struct pci_dev *dev);
1318 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1319 int pcie_get_readrq(struct pci_dev *dev);
1320 int pcie_set_readrq(struct pci_dev *dev, int rq);
1321 int pcie_get_mps(struct pci_dev *dev);
1322 int pcie_set_mps(struct pci_dev *dev, int mps);
1323 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1324 enum pci_bus_speed *speed,
1325 enum pcie_link_width *width);
1326 void pcie_print_link_status(struct pci_dev *dev);
1327 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1328 int pcie_flr(struct pci_dev *dev);
1329 int __pci_reset_function_locked(struct pci_dev *dev);
1330 int pci_reset_function(struct pci_dev *dev);
1331 int pci_reset_function_locked(struct pci_dev *dev);
1332 int pci_try_reset_function(struct pci_dev *dev);
1333 int pci_probe_reset_slot(struct pci_slot *slot);
1334 int pci_probe_reset_bus(struct pci_bus *bus);
1335 int pci_reset_bus(struct pci_dev *dev);
1336 void pci_reset_secondary_bus(struct pci_dev *dev);
1337 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1338 void pci_update_resource(struct pci_dev *dev, int resno);
1339 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1340 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1341 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1342 static inline int pci_rebar_bytes_to_size(u64 bytes)
1343 {
1344 bytes = roundup_pow_of_two(bytes);
1345
1346 /* Return BAR size as defined in the resizable BAR specification */
1347 return max(ilog2(bytes), 20) - 20;
1348 }
1349
1350 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1351 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1352 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1353 bool pci_device_is_present(struct pci_dev *pdev);
1354 void pci_ignore_hotplug(struct pci_dev *dev);
1355 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1356 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1357
1358 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1359 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1360 const char *fmt, ...);
1361 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1362
1363 /* ROM control related routines */
1364 int pci_enable_rom(struct pci_dev *pdev);
1365 void pci_disable_rom(struct pci_dev *pdev);
1366 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1367 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1368
1369 /* Power management related routines */
1370 int pci_save_state(struct pci_dev *dev);
1371 void pci_restore_state(struct pci_dev *dev);
1372 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1373 int pci_load_saved_state(struct pci_dev *dev,
1374 struct pci_saved_state *state);
1375 int pci_load_and_free_saved_state(struct pci_dev *dev,
1376 struct pci_saved_state **state);
1377 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1378 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1379 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1380 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1381 void pci_pme_active(struct pci_dev *dev, bool enable);
1382 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1383 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1384 int pci_prepare_to_sleep(struct pci_dev *dev);
1385 int pci_back_from_sleep(struct pci_dev *dev);
1386 bool pci_dev_run_wake(struct pci_dev *dev);
1387 void pci_d3cold_enable(struct pci_dev *dev);
1388 void pci_d3cold_disable(struct pci_dev *dev);
1389 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1390 void pci_resume_bus(struct pci_bus *bus);
1391 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1392
1393 /* For use by arch with custom probe code */
1394 void set_pcie_port_type(struct pci_dev *pdev);
1395 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1396
1397 /* Functions for PCI Hotplug drivers to use */
1398 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1399 unsigned int pci_rescan_bus(struct pci_bus *bus);
1400 void pci_lock_rescan_remove(void);
1401 void pci_unlock_rescan_remove(void);
1402
1403 /* Vital Product Data routines */
1404 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1405 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1406 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1407 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1408
1409 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1410 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1411 void pci_bus_assign_resources(const struct pci_bus *bus);
1412 void pci_bus_claim_resources(struct pci_bus *bus);
1413 void pci_bus_size_bridges(struct pci_bus *bus);
1414 int pci_claim_resource(struct pci_dev *, int);
1415 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1416 void pci_assign_unassigned_resources(void);
1417 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1418 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1419 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1420 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1421 void pdev_enable_device(struct pci_dev *);
1422 int pci_enable_resources(struct pci_dev *, int mask);
1423 void pci_assign_irq(struct pci_dev *dev);
1424 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1425 #define HAVE_PCI_REQ_REGIONS 2
1426 int __must_check pci_request_regions(struct pci_dev *, const char *);
1427 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1428 void pci_release_regions(struct pci_dev *);
1429 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1430 void pci_release_region(struct pci_dev *, int);
1431 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1432 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1433 void pci_release_selected_regions(struct pci_dev *, int);
1434
1435 /* drivers/pci/bus.c */
1436 void pci_add_resource(struct list_head *resources, struct resource *res);
1437 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1438 resource_size_t offset);
1439 void pci_free_resource_list(struct list_head *resources);
1440 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1441 unsigned int flags);
1442 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1443 void pci_bus_remove_resources(struct pci_bus *bus);
1444 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1445 int devm_request_pci_bus_resources(struct device *dev,
1446 struct list_head *resources);
1447
1448 /* Temporary until new and working PCI SBR API in place */
1449 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1450
1451 #define pci_bus_for_each_resource(bus, res, i) \
1452 for (i = 0; \
1453 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1454 i++)
1455
1456 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1457 struct resource *res, resource_size_t size,
1458 resource_size_t align, resource_size_t min,
1459 unsigned long type_mask,
1460 resource_size_t (*alignf)(void *,
1461 const struct resource *,
1462 resource_size_t,
1463 resource_size_t),
1464 void *alignf_data);
1465
1466
1467 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1468 resource_size_t size);
1469 unsigned long pci_address_to_pio(phys_addr_t addr);
1470 phys_addr_t pci_pio_to_address(unsigned long pio);
1471 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1472 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1473 phys_addr_t phys_addr);
1474 void pci_unmap_iospace(struct resource *res);
1475 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1476 resource_size_t offset,
1477 resource_size_t size);
1478 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1479 struct resource *res);
1480
pci_bus_address(struct pci_dev * pdev,int bar)1481 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1482 {
1483 struct pci_bus_region region;
1484
1485 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1486 return region.start;
1487 }
1488
1489 /* Proper probing supporting hot-pluggable devices */
1490 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1491 const char *mod_name);
1492
1493 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1494 #define pci_register_driver(driver) \
1495 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1496
1497 void pci_unregister_driver(struct pci_driver *dev);
1498
1499 /**
1500 * module_pci_driver() - Helper macro for registering a PCI driver
1501 * @__pci_driver: pci_driver struct
1502 *
1503 * Helper macro for PCI drivers which do not do anything special in module
1504 * init/exit. This eliminates a lot of boilerplate. Each module may only
1505 * use this macro once, and calling it replaces module_init() and module_exit()
1506 */
1507 #define module_pci_driver(__pci_driver) \
1508 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1509
1510 /**
1511 * builtin_pci_driver() - Helper macro for registering a PCI driver
1512 * @__pci_driver: pci_driver struct
1513 *
1514 * Helper macro for PCI drivers which do not do anything special in their
1515 * init code. This eliminates a lot of boilerplate. Each driver may only
1516 * use this macro once, and calling it replaces device_initcall(...)
1517 */
1518 #define builtin_pci_driver(__pci_driver) \
1519 builtin_driver(__pci_driver, pci_register_driver)
1520
1521 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1522 int pci_add_dynid(struct pci_driver *drv,
1523 unsigned int vendor, unsigned int device,
1524 unsigned int subvendor, unsigned int subdevice,
1525 unsigned int class, unsigned int class_mask,
1526 unsigned long driver_data);
1527 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1528 struct pci_dev *dev);
1529 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1530 int pass);
1531
1532 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1533 void *userdata);
1534 int pci_cfg_space_size(struct pci_dev *dev);
1535 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1536 void pci_setup_bridge(struct pci_bus *bus);
1537 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1538 unsigned long type);
1539
1540 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1541 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1542
1543 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1544 unsigned int command_bits, u32 flags);
1545
1546 /*
1547 * Virtual interrupts allow for more interrupts to be allocated
1548 * than the device has interrupts for. These are not programmed
1549 * into the device's MSI-X table and must be handled by some
1550 * other driver means.
1551 */
1552 #define PCI_IRQ_VIRTUAL (1 << 4)
1553
1554 #define PCI_IRQ_ALL_TYPES \
1555 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1556
1557 #include <linux/dmapool.h>
1558
1559 struct msix_entry {
1560 u32 vector; /* Kernel uses to write allocated vector */
1561 u16 entry; /* Driver uses to specify entry, OS writes */
1562 };
1563
1564 #ifdef CONFIG_PCI_MSI
1565 int pci_msi_vec_count(struct pci_dev *dev);
1566 void pci_disable_msi(struct pci_dev *dev);
1567 int pci_msix_vec_count(struct pci_dev *dev);
1568 void pci_disable_msix(struct pci_dev *dev);
1569 void pci_restore_msi_state(struct pci_dev *dev);
1570 int pci_msi_enabled(void);
1571 int pci_enable_msi(struct pci_dev *dev);
1572 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1573 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1574 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1575 struct msix_entry *entries, int nvec)
1576 {
1577 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1578 if (rc < 0)
1579 return rc;
1580 return 0;
1581 }
1582 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1583 unsigned int max_vecs, unsigned int flags,
1584 struct irq_affinity *affd);
1585
1586 void pci_free_irq_vectors(struct pci_dev *dev);
1587 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1588 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1589
1590 #else
pci_msi_vec_count(struct pci_dev * dev)1591 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1592 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1593 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1594 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1595 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1596 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1597 static inline int pci_enable_msi(struct pci_dev *dev)
1598 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1599 static inline int pci_enable_msix_range(struct pci_dev *dev,
1600 struct msix_entry *entries, int minvec, int maxvec)
1601 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1602 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1603 struct msix_entry *entries, int nvec)
1604 { return -ENOSYS; }
1605
1606 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1607 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1608 unsigned int max_vecs, unsigned int flags,
1609 struct irq_affinity *aff_desc)
1610 {
1611 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1612 return 1;
1613 return -ENOSPC;
1614 }
1615
pci_free_irq_vectors(struct pci_dev * dev)1616 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1617 {
1618 }
1619
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1620 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1621 {
1622 if (WARN_ON_ONCE(nr > 0))
1623 return -EINVAL;
1624 return dev->irq;
1625 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1626 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1627 int vec)
1628 {
1629 return cpu_possible_mask;
1630 }
1631 #endif
1632
1633 /**
1634 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1635 * @d: the INTx IRQ domain
1636 * @node: the DT node for the device whose interrupt we're translating
1637 * @intspec: the interrupt specifier data from the DT
1638 * @intsize: the number of entries in @intspec
1639 * @out_hwirq: pointer at which to write the hwirq number
1640 * @out_type: pointer at which to write the interrupt type
1641 *
1642 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1643 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1644 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1645 * INTx value to obtain the hwirq number.
1646 *
1647 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1648 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1649 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1650 struct device_node *node,
1651 const u32 *intspec,
1652 unsigned int intsize,
1653 unsigned long *out_hwirq,
1654 unsigned int *out_type)
1655 {
1656 const u32 intx = intspec[0];
1657
1658 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1659 return -EINVAL;
1660
1661 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1662 return 0;
1663 }
1664
1665 #ifdef CONFIG_PCIEPORTBUS
1666 extern bool pcie_ports_disabled;
1667 extern bool pcie_ports_native;
1668 #else
1669 #define pcie_ports_disabled true
1670 #define pcie_ports_native false
1671 #endif
1672
1673 #define PCIE_LINK_STATE_L0S BIT(0)
1674 #define PCIE_LINK_STATE_L1 BIT(1)
1675 #define PCIE_LINK_STATE_CLKPM BIT(2)
1676 #define PCIE_LINK_STATE_L1_1 BIT(3)
1677 #define PCIE_LINK_STATE_L1_2 BIT(4)
1678 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1679 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1680
1681 #ifdef CONFIG_PCIEASPM
1682 int pci_disable_link_state(struct pci_dev *pdev, int state);
1683 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1684 void pcie_no_aspm(void);
1685 bool pcie_aspm_support_enabled(void);
1686 bool pcie_aspm_enabled(struct pci_dev *pdev);
1687 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1688 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1689 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1690 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1691 { return 0; }
pcie_no_aspm(void)1692 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1693 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1694 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1695 #endif
1696
1697 #ifdef CONFIG_PCIEAER
1698 bool pci_aer_available(void);
1699 #else
pci_aer_available(void)1700 static inline bool pci_aer_available(void) { return false; }
1701 #endif
1702
1703 bool pci_ats_disabled(void);
1704
1705 #ifdef CONFIG_PCIE_PTM
1706 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1707 void pci_disable_ptm(struct pci_dev *dev);
1708 bool pcie_ptm_enabled(struct pci_dev *dev);
1709 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1710 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1711 { return -EINVAL; }
pci_disable_ptm(struct pci_dev * dev)1712 static inline void pci_disable_ptm(struct pci_dev *dev) { }
pcie_ptm_enabled(struct pci_dev * dev)1713 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1714 { return false; }
1715 #endif
1716
1717 void pci_cfg_access_lock(struct pci_dev *dev);
1718 bool pci_cfg_access_trylock(struct pci_dev *dev);
1719 void pci_cfg_access_unlock(struct pci_dev *dev);
1720
1721 void pci_dev_lock(struct pci_dev *dev);
1722 int pci_dev_trylock(struct pci_dev *dev);
1723 void pci_dev_unlock(struct pci_dev *dev);
1724
1725 /*
1726 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1727 * a PCI domain is defined to be a set of PCI buses which share
1728 * configuration space.
1729 */
1730 #ifdef CONFIG_PCI_DOMAINS
1731 extern int pci_domains_supported;
1732 #else
1733 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1734 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1735 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1736 #endif /* CONFIG_PCI_DOMAINS */
1737
1738 /*
1739 * Generic implementation for PCI domain support. If your
1740 * architecture does not need custom management of PCI
1741 * domains then this implementation will be used
1742 */
1743 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1744 static inline int pci_domain_nr(struct pci_bus *bus)
1745 {
1746 return bus->domain_nr;
1747 }
1748 #ifdef CONFIG_ACPI
1749 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1750 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1751 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1752 { return 0; }
1753 #endif
1754 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1755 #endif
1756
1757 /* Some architectures require additional setup to direct VGA traffic */
1758 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1759 unsigned int command_bits, u32 flags);
1760 void pci_register_set_vga_state(arch_set_vga_state_t func);
1761
1762 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1763 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1764 {
1765 return pci_request_selected_regions(pdev,
1766 pci_select_bars(pdev, IORESOURCE_IO), name);
1767 }
1768
1769 static inline void
pci_release_io_regions(struct pci_dev * pdev)1770 pci_release_io_regions(struct pci_dev *pdev)
1771 {
1772 return pci_release_selected_regions(pdev,
1773 pci_select_bars(pdev, IORESOURCE_IO));
1774 }
1775
1776 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1777 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1778 {
1779 return pci_request_selected_regions(pdev,
1780 pci_select_bars(pdev, IORESOURCE_MEM), name);
1781 }
1782
1783 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1784 pci_release_mem_regions(struct pci_dev *pdev)
1785 {
1786 return pci_release_selected_regions(pdev,
1787 pci_select_bars(pdev, IORESOURCE_MEM));
1788 }
1789
1790 #else /* CONFIG_PCI is not enabled */
1791
pci_set_flags(int flags)1792 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1793 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1794 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1795 static inline int pci_has_flag(int flag) { return 0; }
1796
1797 /*
1798 * If the system does not have PCI, clearly these return errors. Define
1799 * these as simple inline functions to avoid hair in drivers.
1800 */
1801 #define _PCI_NOP(o, s, t) \
1802 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1803 int where, t val) \
1804 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1805
1806 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1807 _PCI_NOP(o, word, u16 x) \
1808 _PCI_NOP(o, dword, u32 x)
1809 _PCI_NOP_ALL(read, *)
1810 _PCI_NOP_ALL(write,)
1811
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1812 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1813 unsigned int device,
1814 struct pci_dev *from)
1815 { return NULL; }
1816
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1817 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1818 unsigned int device,
1819 unsigned int ss_vendor,
1820 unsigned int ss_device,
1821 struct pci_dev *from)
1822 { return NULL; }
1823
pci_get_class(unsigned int class,struct pci_dev * from)1824 static inline struct pci_dev *pci_get_class(unsigned int class,
1825 struct pci_dev *from)
1826 { return NULL; }
1827
1828
pci_dev_present(const struct pci_device_id * ids)1829 static inline int pci_dev_present(const struct pci_device_id *ids)
1830 { return 0; }
1831
1832 #define no_pci_devices() (1)
1833 #define pci_dev_put(dev) do { } while (0)
1834
pci_set_master(struct pci_dev * dev)1835 static inline void pci_set_master(struct pci_dev *dev) { }
pci_clear_master(struct pci_dev * dev)1836 static inline void pci_clear_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1837 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1838 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1839 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1840 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1841 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1842 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1843 struct module *owner,
1844 const char *mod_name)
1845 { return 0; }
pci_register_driver(struct pci_driver * drv)1846 static inline int pci_register_driver(struct pci_driver *drv)
1847 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1848 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1849 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1850 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1851 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1852 int cap)
1853 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1854 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1855 { return 0; }
1856
pci_get_dsn(struct pci_dev * dev)1857 static inline u64 pci_get_dsn(struct pci_dev *dev)
1858 { return 0; }
1859
1860 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1861 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1862 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1863 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1864 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1865 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1866 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1867 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1868 pm_message_t state)
1869 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1870 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1871 int enable)
1872 { return 0; }
1873
pci_find_resource(struct pci_dev * dev,struct resource * res)1874 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1875 struct resource *res)
1876 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1877 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1878 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1879 static inline void pci_release_regions(struct pci_dev *dev) { }
1880
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1881 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1882 phys_addr_t addr, resource_size_t size)
1883 { return -EINVAL; }
1884
pci_address_to_pio(phys_addr_t addr)1885 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1886
pci_find_next_bus(const struct pci_bus * from)1887 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1888 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1889 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1890 unsigned int devfn)
1891 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1892 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1893 unsigned int bus, unsigned int devfn)
1894 { return NULL; }
1895
pci_domain_nr(struct pci_bus * bus)1896 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1897 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1898
1899 #define dev_is_pci(d) (false)
1900 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1901 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1902 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1903 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1904 struct device_node *node,
1905 const u32 *intspec,
1906 unsigned int intsize,
1907 unsigned long *out_hwirq,
1908 unsigned int *out_type)
1909 { return -EINVAL; }
1910
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1911 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1912 struct pci_dev *dev)
1913 { return NULL; }
pci_ats_disabled(void)1914 static inline bool pci_ats_disabled(void) { return true; }
1915
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1916 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1917 {
1918 return -EINVAL;
1919 }
1920
1921 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1922 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1923 unsigned int max_vecs, unsigned int flags,
1924 struct irq_affinity *aff_desc)
1925 {
1926 return -ENOSPC;
1927 }
1928 #endif /* CONFIG_PCI */
1929
1930 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1931 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1932 unsigned int max_vecs, unsigned int flags)
1933 {
1934 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1935 NULL);
1936 }
1937
1938 /* Include architecture-dependent settings and functions */
1939
1940 #include <asm/pci.h>
1941
1942 /*
1943 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1944 * is expected to be an offset within that region.
1945 *
1946 */
1947 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1948 struct vm_area_struct *vma,
1949 enum pci_mmap_state mmap_state, int write_combine);
1950
1951 #ifndef arch_can_pci_mmap_wc
1952 #define arch_can_pci_mmap_wc() 0
1953 #endif
1954
1955 #ifndef arch_can_pci_mmap_io
1956 #define arch_can_pci_mmap_io() 0
1957 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1958 #else
1959 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1960 #endif
1961
1962 #ifndef pci_root_bus_fwnode
1963 #define pci_root_bus_fwnode(bus) NULL
1964 #endif
1965
1966 /*
1967 * These helpers provide future and backwards compatibility
1968 * for accessing popular PCI BAR info
1969 */
1970 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1971 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1972 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1973 #define pci_resource_len(dev,bar) \
1974 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1975 \
1976 (pci_resource_end((dev), (bar)) - \
1977 pci_resource_start((dev), (bar)) + 1))
1978
1979 /*
1980 * Similar to the helpers above, these manipulate per-pci_dev
1981 * driver-specific data. They are really just a wrapper around
1982 * the generic device structure functions of these calls.
1983 */
pci_get_drvdata(struct pci_dev * pdev)1984 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1985 {
1986 return dev_get_drvdata(&pdev->dev);
1987 }
1988
pci_set_drvdata(struct pci_dev * pdev,void * data)1989 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1990 {
1991 dev_set_drvdata(&pdev->dev, data);
1992 }
1993
pci_name(const struct pci_dev * pdev)1994 static inline const char *pci_name(const struct pci_dev *pdev)
1995 {
1996 return dev_name(&pdev->dev);
1997 }
1998
1999 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2000 const struct resource *rsrc,
2001 resource_size_t *start, resource_size_t *end);
2002
2003 /*
2004 * The world is not perfect and supplies us with broken PCI devices.
2005 * For at least a part of these bugs we need a work-around, so both
2006 * generic (drivers/pci/quirks.c) and per-architecture code can define
2007 * fixup hooks to be called for particular buggy devices.
2008 */
2009
2010 struct pci_fixup {
2011 u16 vendor; /* Or PCI_ANY_ID */
2012 u16 device; /* Or PCI_ANY_ID */
2013 u32 class; /* Or PCI_ANY_ID */
2014 unsigned int class_shift; /* should be 0, 8, 16 */
2015 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2016 int hook_offset;
2017 #else
2018 void (*hook)(struct pci_dev *dev);
2019 #endif
2020 };
2021
2022 enum pci_fixup_pass {
2023 pci_fixup_early, /* Before probing BARs */
2024 pci_fixup_header, /* After reading configuration header */
2025 pci_fixup_final, /* Final phase of device fixups */
2026 pci_fixup_enable, /* pci_enable_device() time */
2027 pci_fixup_resume, /* pci_device_resume() */
2028 pci_fixup_suspend, /* pci_device_suspend() */
2029 pci_fixup_resume_early, /* pci_device_resume_early() */
2030 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2031 };
2032
2033 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2034 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2035 class_shift, hook) \
2036 __ADDRESSABLE(hook) \
2037 asm(".section " #sec ", \"a\" \n" \
2038 ".balign 16 \n" \
2039 ".short " #vendor ", " #device " \n" \
2040 ".long " #class ", " #class_shift " \n" \
2041 ".long " #hook " - . \n" \
2042 ".previous \n");
2043
2044 /*
2045 * Clang's LTO may rename static functions in C, but has no way to
2046 * handle such renamings when referenced from inline asm. To work
2047 * around this, create global C stubs for these cases.
2048 */
2049 #ifdef CONFIG_LTO_CLANG
2050 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2051 class_shift, hook, stub) \
2052 void stub(struct pci_dev *dev); \
2053 void stub(struct pci_dev *dev) \
2054 { \
2055 hook(dev); \
2056 } \
2057 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2058 class_shift, stub)
2059 #else
2060 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2061 class_shift, hook, stub) \
2062 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2063 class_shift, hook)
2064 #endif
2065
2066 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2067 class_shift, hook) \
2068 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2069 class_shift, hook, __UNIQUE_ID(hook))
2070 #else
2071 /* Anonymous variables would be nice... */
2072 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2073 class_shift, hook) \
2074 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2075 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2076 = { vendor, device, class, class_shift, hook };
2077 #endif
2078
2079 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2080 class_shift, hook) \
2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2082 hook, vendor, device, class, class_shift, hook)
2083 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2084 class_shift, hook) \
2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2086 hook, vendor, device, class, class_shift, hook)
2087 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2088 class_shift, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2090 hook, vendor, device, class, class_shift, hook)
2091 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2092 class_shift, hook) \
2093 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2094 hook, vendor, device, class, class_shift, hook)
2095 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2096 class_shift, hook) \
2097 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2098 resume##hook, vendor, device, class, class_shift, hook)
2099 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2100 class_shift, hook) \
2101 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2102 resume_early##hook, vendor, device, class, class_shift, hook)
2103 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2104 class_shift, hook) \
2105 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2106 suspend##hook, vendor, device, class, class_shift, hook)
2107 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2108 class_shift, hook) \
2109 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2110 suspend_late##hook, vendor, device, class, class_shift, hook)
2111
2112 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2113 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2114 hook, vendor, device, PCI_ANY_ID, 0, hook)
2115 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2116 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2117 hook, vendor, device, PCI_ANY_ID, 0, hook)
2118 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2119 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2120 hook, vendor, device, PCI_ANY_ID, 0, hook)
2121 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2122 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2123 hook, vendor, device, PCI_ANY_ID, 0, hook)
2124 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2125 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2126 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2127 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2128 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2129 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2130 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2131 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2132 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2133 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2134 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2135 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2136
2137 #ifdef CONFIG_PCI_QUIRKS
2138 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2139 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2140 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2141 struct pci_dev *dev) { }
2142 #endif
2143
2144 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2145 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2146 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2147 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2148 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2149 const char *name);
2150 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2151
2152 extern int pci_pci_problems;
2153 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2154 #define PCIPCI_TRITON 2
2155 #define PCIPCI_NATOMA 4
2156 #define PCIPCI_VIAETBF 8
2157 #define PCIPCI_VSFX 16
2158 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2159 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2160
2161 extern unsigned long pci_cardbus_io_size;
2162 extern unsigned long pci_cardbus_mem_size;
2163 extern u8 pci_dfl_cache_line_size;
2164 extern u8 pci_cache_line_size;
2165
2166 /* Architecture-specific versions may override these (weak) */
2167 void pcibios_disable_device(struct pci_dev *dev);
2168 void pcibios_set_master(struct pci_dev *dev);
2169 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2170 enum pcie_reset_state state);
2171 int pcibios_device_add(struct pci_dev *dev);
2172 void pcibios_release_device(struct pci_dev *dev);
2173 #ifdef CONFIG_PCI
2174 void pcibios_penalize_isa_irq(int irq, int active);
2175 #else
pcibios_penalize_isa_irq(int irq,int active)2176 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2177 #endif
2178 int pcibios_alloc_irq(struct pci_dev *dev);
2179 void pcibios_free_irq(struct pci_dev *dev);
2180 resource_size_t pcibios_default_alignment(void);
2181
2182 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2183 void __init pci_mmcfg_early_init(void);
2184 void __init pci_mmcfg_late_init(void);
2185 #else
pci_mmcfg_early_init(void)2186 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2187 static inline void pci_mmcfg_late_init(void) { }
2188 #endif
2189
2190 int pci_ext_cfg_avail(void);
2191
2192 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2193 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2194
2195 #ifdef CONFIG_PCI_IOV
2196 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2197 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2198 int pci_iov_vf_id(struct pci_dev *dev);
2199 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2200 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2201 void pci_disable_sriov(struct pci_dev *dev);
2202
2203 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2204 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2205 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2206 int pci_num_vf(struct pci_dev *dev);
2207 int pci_vfs_assigned(struct pci_dev *dev);
2208 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2209 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2210 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2211 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2212 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2213
2214 /* Arch may override these (weak) */
2215 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2216 int pcibios_sriov_disable(struct pci_dev *pdev);
2217 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2218 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2219 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2220 {
2221 return -ENOSYS;
2222 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2223 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2224 {
2225 return -ENOSYS;
2226 }
2227
pci_iov_vf_id(struct pci_dev * dev)2228 static inline int pci_iov_vf_id(struct pci_dev *dev)
2229 {
2230 return -ENOSYS;
2231 }
2232
pci_iov_get_pf_drvdata(struct pci_dev * dev,struct pci_driver * pf_driver)2233 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2234 struct pci_driver *pf_driver)
2235 {
2236 return ERR_PTR(-EINVAL);
2237 }
2238
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2239 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2240 { return -ENODEV; }
2241
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2242 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2243 struct pci_dev *virtfn, int id)
2244 {
2245 return -ENODEV;
2246 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2247 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2248 {
2249 return -ENOSYS;
2250 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2251 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2252 int id) { }
pci_disable_sriov(struct pci_dev * dev)2253 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2254 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2255 static inline int pci_vfs_assigned(struct pci_dev *dev)
2256 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2257 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2258 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2259 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2260 { return 0; }
2261 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2262 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2263 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2264 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2265 #endif
2266
2267 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2268 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2269 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2270 #endif
2271
2272 /**
2273 * pci_pcie_cap - get the saved PCIe capability offset
2274 * @dev: PCI device
2275 *
2276 * PCIe capability offset is calculated at PCI device initialization
2277 * time and saved in the data structure. This function returns saved
2278 * PCIe capability offset. Using this instead of pci_find_capability()
2279 * reduces unnecessary search in the PCI configuration space. If you
2280 * need to calculate PCIe capability offset from raw device for some
2281 * reasons, please use pci_find_capability() instead.
2282 */
pci_pcie_cap(struct pci_dev * dev)2283 static inline int pci_pcie_cap(struct pci_dev *dev)
2284 {
2285 return dev->pcie_cap;
2286 }
2287
2288 /**
2289 * pci_is_pcie - check if the PCI device is PCI Express capable
2290 * @dev: PCI device
2291 *
2292 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2293 */
pci_is_pcie(struct pci_dev * dev)2294 static inline bool pci_is_pcie(struct pci_dev *dev)
2295 {
2296 return pci_pcie_cap(dev);
2297 }
2298
2299 /**
2300 * pcie_caps_reg - get the PCIe Capabilities Register
2301 * @dev: PCI device
2302 */
pcie_caps_reg(const struct pci_dev * dev)2303 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2304 {
2305 return dev->pcie_flags_reg;
2306 }
2307
2308 /**
2309 * pci_pcie_type - get the PCIe device/port type
2310 * @dev: PCI device
2311 */
pci_pcie_type(const struct pci_dev * dev)2312 static inline int pci_pcie_type(const struct pci_dev *dev)
2313 {
2314 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2315 }
2316
2317 /**
2318 * pcie_find_root_port - Get the PCIe root port device
2319 * @dev: PCI device
2320 *
2321 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2322 * for a given PCI/PCIe Device.
2323 */
pcie_find_root_port(struct pci_dev * dev)2324 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2325 {
2326 while (dev) {
2327 if (pci_is_pcie(dev) &&
2328 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2329 return dev;
2330 dev = pci_upstream_bridge(dev);
2331 }
2332
2333 return NULL;
2334 }
2335
2336 void pci_request_acs(void);
2337 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2338 bool pci_acs_path_enabled(struct pci_dev *start,
2339 struct pci_dev *end, u16 acs_flags);
2340 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2341
2342 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2343 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2344
2345 /* Large Resource Data Type Tag Item Names */
2346 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2347 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2348 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2349
2350 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2351 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2352 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2353
2354 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2355 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2356 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2357 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2358 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2359
2360 /**
2361 * pci_vpd_alloc - Allocate buffer and read VPD into it
2362 * @dev: PCI device
2363 * @size: pointer to field where VPD length is returned
2364 *
2365 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2366 */
2367 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2368
2369 /**
2370 * pci_vpd_find_id_string - Locate id string in VPD
2371 * @buf: Pointer to buffered VPD data
2372 * @len: The length of the buffer area in which to search
2373 * @size: Pointer to field where length of id string is returned
2374 *
2375 * Returns the index of the id string or -ENOENT if not found.
2376 */
2377 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2378
2379 /**
2380 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2381 * @buf: Pointer to buffered VPD data
2382 * @len: The length of the buffer area in which to search
2383 * @kw: The keyword to search for
2384 * @size: Pointer to field where length of found keyword data is returned
2385 *
2386 * Returns the index of the information field keyword data or -ENOENT if
2387 * not found.
2388 */
2389 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2390 const char *kw, unsigned int *size);
2391
2392 /**
2393 * pci_vpd_check_csum - Check VPD checksum
2394 * @buf: Pointer to buffered VPD data
2395 * @len: VPD size
2396 *
2397 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2398 */
2399 int pci_vpd_check_csum(const void *buf, unsigned int len);
2400
2401 /* PCI <-> OF binding helpers */
2402 #ifdef CONFIG_OF
2403 struct device_node;
2404 struct irq_domain;
2405 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2406 bool pci_host_of_has_msi_map(struct device *dev);
2407
2408 /* Arch may override this (weak) */
2409 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2410
2411 #else /* CONFIG_OF */
2412 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2413 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2414 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2415 #endif /* CONFIG_OF */
2416
2417 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2418 pci_device_to_OF_node(const struct pci_dev *pdev)
2419 {
2420 return pdev ? pdev->dev.of_node : NULL;
2421 }
2422
pci_bus_to_OF_node(struct pci_bus * bus)2423 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2424 {
2425 return bus ? bus->dev.of_node : NULL;
2426 }
2427
2428 #ifdef CONFIG_ACPI
2429 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2430
2431 void
2432 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2433 bool pci_pr3_present(struct pci_dev *pdev);
2434 #else
2435 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2436 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2437 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2438 #endif
2439
2440 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2441 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2442 {
2443 return pdev->dev.archdata.edev;
2444 }
2445 #endif
2446
2447 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2448 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2449 int pci_for_each_dma_alias(struct pci_dev *pdev,
2450 int (*fn)(struct pci_dev *pdev,
2451 u16 alias, void *data), void *data);
2452
2453 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2454 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2455 {
2456 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2457 }
pci_clear_dev_assigned(struct pci_dev * pdev)2458 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2459 {
2460 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2461 }
pci_is_dev_assigned(struct pci_dev * pdev)2462 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2463 {
2464 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2465 }
2466
2467 /**
2468 * pci_ari_enabled - query ARI forwarding status
2469 * @bus: the PCI bus
2470 *
2471 * Returns true if ARI forwarding is enabled.
2472 */
pci_ari_enabled(struct pci_bus * bus)2473 static inline bool pci_ari_enabled(struct pci_bus *bus)
2474 {
2475 return bus->self && bus->self->ari_enabled;
2476 }
2477
2478 /**
2479 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2480 * @pdev: PCI device to check
2481 *
2482 * Walk upwards from @pdev and check for each encountered bridge if it's part
2483 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2484 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2485 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2486 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2487 {
2488 struct pci_dev *parent = pdev;
2489
2490 if (pdev->is_thunderbolt)
2491 return true;
2492
2493 while ((parent = pci_upstream_bridge(parent)))
2494 if (parent->is_thunderbolt)
2495 return true;
2496
2497 return false;
2498 }
2499
2500 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2501 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2502 #endif
2503
2504 #include <linux/dma-mapping.h>
2505
2506 #define pci_printk(level, pdev, fmt, arg...) \
2507 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2508
2509 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2510 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2511 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2512 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2513 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2514 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2515 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2516 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2517
2518 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2519 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2520
2521 #define pci_info_ratelimited(pdev, fmt, arg...) \
2522 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2523
2524 #define pci_WARN(pdev, condition, fmt, arg...) \
2525 WARN(condition, "%s %s: " fmt, \
2526 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2527
2528 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2529 WARN_ONCE(condition, "%s %s: " fmt, \
2530 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2531
2532 #endif /* LINUX_PCI_H */
2533