1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Most ISHTP provider device and ISHTP logic declarations
4 *
5 * Copyright (c) 2003-2016, Intel Corporation.
6 */
7
8 #ifndef _ISHTP_DEV_H_
9 #define _ISHTP_DEV_H_
10
11 #include <linux/types.h>
12 #include <linux/spinlock.h>
13 #include <linux/intel-ish-client-if.h>
14 #include "bus.h"
15 #include "hbm.h"
16
17 #define IPC_PAYLOAD_SIZE 128
18 #define ISHTP_RD_MSG_BUF_SIZE IPC_PAYLOAD_SIZE
19 #define IPC_FULL_MSG_SIZE 132
20
21 /* Number of messages to be held in ISR->BH FIFO */
22 #define RD_INT_FIFO_SIZE 64
23
24 /*
25 * Number of IPC messages to be held in Tx FIFO, to be sent by ISR -
26 * Tx complete interrupt or RX_COMPLETE handler
27 */
28 #define IPC_TX_FIFO_SIZE 512
29
30 /*
31 * Number of Maximum ISHTP Clients
32 */
33 #define ISHTP_CLIENTS_MAX 256
34
35 /*
36 * Number of File descriptors/handles
37 * that can be opened to the driver.
38 *
39 * Limit to 255: 256 Total Clients
40 * minus internal client for ISHTP Bus Messages
41 */
42 #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1)
43
44 /* Internal Clients Number */
45 #define ISHTP_HOST_CLIENT_ID_ANY (-1)
46 #define ISHTP_HBM_HOST_CLIENT_ID 0
47
48 #define MAX_DMA_DELAY 20
49
50 /* ISHTP device states */
51 enum ishtp_dev_state {
52 ISHTP_DEV_INITIALIZING = 0,
53 ISHTP_DEV_INIT_CLIENTS,
54 ISHTP_DEV_ENABLED,
55 ISHTP_DEV_RESETTING,
56 ISHTP_DEV_DISABLED,
57 ISHTP_DEV_POWER_DOWN,
58 ISHTP_DEV_POWER_UP
59 };
60 const char *ishtp_dev_state_str(int state);
61
62 struct ishtp_cl;
63
64 /**
65 * struct ishtp_fw_client - representation of fw client
66 *
67 * @props - client properties
68 * @client_id - fw client id
69 */
70 struct ishtp_fw_client {
71 struct ishtp_client_properties props;
72 uint8_t client_id;
73 };
74
75 /*
76 * Control info for IPC messages ISHTP/IPC sending FIFO -
77 * list with inline data buffer
78 * This structure will be filled with parameters submitted
79 * by the caller glue layer
80 * 'buf' may be pointing to the external buffer or to 'inline_data'
81 * 'offset' will be initialized to 0 by submitting
82 *
83 * 'ipc_send_compl' is intended for use by clients that send fragmented
84 * messages. When a fragment is sent down to IPC msg regs,
85 * it will be called.
86 * If it has more fragments to send, it will do it. With last fragment
87 * it will send appropriate ISHTP "message-complete" flag.
88 * It will remove the outstanding message
89 * (mark outstanding buffer as available).
90 * If counting flow control is in work and there are more flow control
91 * credits, it can put the next client message queued in cl.
92 * structure for IPC processing.
93 *
94 */
95 struct wr_msg_ctl_info {
96 /* Will be called with 'ipc_send_compl_prm' as parameter */
97 void (*ipc_send_compl)(void *);
98
99 void *ipc_send_compl_prm;
100 size_t length;
101 struct list_head link;
102 unsigned char inline_data[IPC_FULL_MSG_SIZE];
103 };
104
105 /*
106 * The ISHTP layer talks to hardware IPC message using the following
107 * callbacks
108 */
109 struct ishtp_hw_ops {
110 int (*hw_reset)(struct ishtp_device *dev);
111 int (*ipc_reset)(struct ishtp_device *dev);
112 uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length,
113 int busy);
114 int (*write)(struct ishtp_device *dev,
115 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
116 unsigned char *msg, int length);
117 uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev);
118 int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer,
119 unsigned long buffer_length);
120 uint32_t (*get_fw_status)(struct ishtp_device *dev);
121 void (*sync_fw_clock)(struct ishtp_device *dev);
122 bool (*dma_no_cache_snooping)(struct ishtp_device *dev);
123 };
124
125 /**
126 * struct ishtp_device - ISHTP private device struct
127 */
128 struct ishtp_device {
129 struct device *devc; /* pointer to lowest device */
130 struct pci_dev *pdev; /* PCI device to get device ids */
131
132 /* waitq for waiting for suspend response */
133 wait_queue_head_t suspend_wait;
134 bool suspend_flag; /* Suspend is active */
135
136 /* waitq for waiting for resume response */
137 wait_queue_head_t resume_wait;
138 bool resume_flag; /*Resume is active */
139
140 /*
141 * lock for the device, for everything that doesn't have
142 * a dedicated spinlock
143 */
144 spinlock_t device_lock;
145
146 bool recvd_hw_ready;
147 struct hbm_version version;
148 int transfer_path; /* Choice of transfer path: IPC or DMA */
149
150 /* ishtp device states */
151 enum ishtp_dev_state dev_state;
152 enum ishtp_hbm_state hbm_state;
153
154 /* driver read queue */
155 struct ishtp_cl_rb read_list;
156 spinlock_t read_list_spinlock;
157
158 /* list of ishtp_cl's */
159 struct list_head cl_list;
160 spinlock_t cl_list_lock;
161 long open_handle_count;
162
163 /* List of bus devices */
164 struct list_head device_list;
165 spinlock_t device_list_lock;
166
167 /* waiting queues for receive message from FW */
168 wait_queue_head_t wait_hw_ready;
169 wait_queue_head_t wait_hbm_recvd_msg;
170
171 /* FIFO for input messages for BH processing */
172 unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE];
173 unsigned int rd_msg_fifo_head, rd_msg_fifo_tail;
174 spinlock_t rd_msg_spinlock;
175 struct work_struct bh_hbm_work;
176
177 /* IPC write queue */
178 struct list_head wr_processing_list, wr_free_list;
179 /* For both processing list and free list */
180 spinlock_t wr_processing_spinlock;
181
182 struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/
183 DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX);
184 DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX);
185 uint8_t fw_clients_num;
186 uint8_t fw_client_presentation_num;
187 uint8_t fw_client_index;
188 spinlock_t fw_clients_lock;
189
190 /* TX DMA buffers and slots */
191 int ishtp_host_dma_enabled;
192 void *ishtp_host_dma_tx_buf;
193 unsigned int ishtp_host_dma_tx_buf_size;
194 uint64_t ishtp_host_dma_tx_buf_phys;
195 int ishtp_dma_num_slots;
196
197 /* map of 4k blocks in Tx dma buf: 0-free, 1-used */
198 uint8_t *ishtp_dma_tx_map;
199 spinlock_t ishtp_dma_tx_lock;
200
201 /* RX DMA buffers and slots */
202 void *ishtp_host_dma_rx_buf;
203 unsigned int ishtp_host_dma_rx_buf_size;
204 uint64_t ishtp_host_dma_rx_buf_phys;
205
206 /* Dump to trace buffers if enabled*/
207 ishtp_print_log print_log;
208
209 /* Debug stats */
210 unsigned int ipc_rx_cnt;
211 unsigned long long ipc_rx_bytes_cnt;
212 unsigned int ipc_tx_cnt;
213 unsigned long long ipc_tx_bytes_cnt;
214
215 const struct ishtp_hw_ops *ops;
216 size_t mtu;
217 uint32_t ishtp_msg_hdr;
218 char hw[] __aligned(sizeof(void *));
219 };
220
ishtp_secs_to_jiffies(unsigned long sec)221 static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec)
222 {
223 return msecs_to_jiffies(sec * MSEC_PER_SEC);
224 }
225
226 /*
227 * Register Access Function
228 */
ish_ipc_reset(struct ishtp_device * dev)229 static inline int ish_ipc_reset(struct ishtp_device *dev)
230 {
231 return dev->ops->ipc_reset(dev);
232 }
233
234 /* Exported function */
235 void ishtp_device_init(struct ishtp_device *dev);
236 int ishtp_start(struct ishtp_device *dev);
237
238 #endif /*_ISHTP_DEV_H_*/
239