1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 72 }; 73 74 enum { 75 MLX5_SHARED_RESOURCE_UID = 0xffff, 76 }; 77 78 enum { 79 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 80 }; 81 82 enum { 83 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 84 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 85 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 86 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 87 }; 88 89 enum { 90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 128 MLX5_CMD_OP_RESUME_VHCA = 0x116, 129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 132 MLX5_CMD_OP_CREATE_MKEY = 0x200, 133 MLX5_CMD_OP_QUERY_MKEY = 0x201, 134 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 140 MLX5_CMD_OP_CREATE_EQ = 0x301, 141 MLX5_CMD_OP_DESTROY_EQ = 0x302, 142 MLX5_CMD_OP_QUERY_EQ = 0x303, 143 MLX5_CMD_OP_GEN_EQE = 0x304, 144 MLX5_CMD_OP_CREATE_CQ = 0x400, 145 MLX5_CMD_OP_DESTROY_CQ = 0x401, 146 MLX5_CMD_OP_QUERY_CQ = 0x402, 147 MLX5_CMD_OP_MODIFY_CQ = 0x403, 148 MLX5_CMD_OP_CREATE_QP = 0x500, 149 MLX5_CMD_OP_DESTROY_QP = 0x501, 150 MLX5_CMD_OP_RST2INIT_QP = 0x502, 151 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 152 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 153 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 155 MLX5_CMD_OP_2ERR_QP = 0x507, 156 MLX5_CMD_OP_2RST_QP = 0x50a, 157 MLX5_CMD_OP_QUERY_QP = 0x50b, 158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 160 MLX5_CMD_OP_CREATE_PSV = 0x600, 161 MLX5_CMD_OP_DESTROY_PSV = 0x601, 162 MLX5_CMD_OP_CREATE_SRQ = 0x700, 163 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 164 MLX5_CMD_OP_QUERY_SRQ = 0x702, 165 MLX5_CMD_OP_ARM_RQ = 0x703, 166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 170 MLX5_CMD_OP_CREATE_DCT = 0x710, 171 MLX5_CMD_OP_DESTROY_DCT = 0x711, 172 MLX5_CMD_OP_DRAIN_DCT = 0x712, 173 MLX5_CMD_OP_QUERY_DCT = 0x713, 174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 175 MLX5_CMD_OP_CREATE_XRQ = 0x717, 176 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 177 MLX5_CMD_OP_QUERY_XRQ = 0x719, 178 MLX5_CMD_OP_ARM_XRQ = 0x71a, 179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 212 MLX5_CMD_OP_ALLOC_PD = 0x800, 213 MLX5_CMD_OP_DEALLOC_PD = 0x801, 214 MLX5_CMD_OP_ALLOC_UAR = 0x802, 215 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 217 MLX5_CMD_OP_ACCESS_REG = 0x805, 218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 221 MLX5_CMD_OP_MAD_IFC = 0x50d, 222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 224 MLX5_CMD_OP_NOP = 0x80d, 225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 239 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 241 MLX5_CMD_OP_CREATE_LAG = 0x840, 242 MLX5_CMD_OP_MODIFY_LAG = 0x841, 243 MLX5_CMD_OP_QUERY_LAG = 0x842, 244 MLX5_CMD_OP_DESTROY_LAG = 0x843, 245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 247 MLX5_CMD_OP_CREATE_TIR = 0x900, 248 MLX5_CMD_OP_MODIFY_TIR = 0x901, 249 MLX5_CMD_OP_DESTROY_TIR = 0x902, 250 MLX5_CMD_OP_QUERY_TIR = 0x903, 251 MLX5_CMD_OP_CREATE_SQ = 0x904, 252 MLX5_CMD_OP_MODIFY_SQ = 0x905, 253 MLX5_CMD_OP_DESTROY_SQ = 0x906, 254 MLX5_CMD_OP_QUERY_SQ = 0x907, 255 MLX5_CMD_OP_CREATE_RQ = 0x908, 256 MLX5_CMD_OP_MODIFY_RQ = 0x909, 257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 258 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 259 MLX5_CMD_OP_QUERY_RQ = 0x90b, 260 MLX5_CMD_OP_CREATE_RMP = 0x90c, 261 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 262 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 263 MLX5_CMD_OP_QUERY_RMP = 0x90f, 264 MLX5_CMD_OP_CREATE_TIS = 0x912, 265 MLX5_CMD_OP_MODIFY_TIS = 0x913, 266 MLX5_CMD_OP_DESTROY_TIS = 0x914, 267 MLX5_CMD_OP_QUERY_TIS = 0x915, 268 MLX5_CMD_OP_CREATE_RQT = 0x916, 269 MLX5_CMD_OP_MODIFY_RQT = 0x917, 270 MLX5_CMD_OP_DESTROY_RQT = 0x918, 271 MLX5_CMD_OP_QUERY_RQT = 0x919, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 301 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 303 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 305 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 308 MLX5_CMD_OP_MAX 309 }; 310 311 /* Valid range for general commands that don't work over an object */ 312 enum { 313 MLX5_CMD_OP_GENERAL_START = 0xb00, 314 MLX5_CMD_OP_GENERAL_END = 0xd00, 315 }; 316 317 struct mlx5_ifc_flow_table_fields_supported_bits { 318 u8 outer_dmac[0x1]; 319 u8 outer_smac[0x1]; 320 u8 outer_ether_type[0x1]; 321 u8 outer_ip_version[0x1]; 322 u8 outer_first_prio[0x1]; 323 u8 outer_first_cfi[0x1]; 324 u8 outer_first_vid[0x1]; 325 u8 outer_ipv4_ttl[0x1]; 326 u8 outer_second_prio[0x1]; 327 u8 outer_second_cfi[0x1]; 328 u8 outer_second_vid[0x1]; 329 u8 reserved_at_b[0x1]; 330 u8 outer_sip[0x1]; 331 u8 outer_dip[0x1]; 332 u8 outer_frag[0x1]; 333 u8 outer_ip_protocol[0x1]; 334 u8 outer_ip_ecn[0x1]; 335 u8 outer_ip_dscp[0x1]; 336 u8 outer_udp_sport[0x1]; 337 u8 outer_udp_dport[0x1]; 338 u8 outer_tcp_sport[0x1]; 339 u8 outer_tcp_dport[0x1]; 340 u8 outer_tcp_flags[0x1]; 341 u8 outer_gre_protocol[0x1]; 342 u8 outer_gre_key[0x1]; 343 u8 outer_vxlan_vni[0x1]; 344 u8 outer_geneve_vni[0x1]; 345 u8 outer_geneve_oam[0x1]; 346 u8 outer_geneve_protocol_type[0x1]; 347 u8 outer_geneve_opt_len[0x1]; 348 u8 source_vhca_port[0x1]; 349 u8 source_eswitch_port[0x1]; 350 351 u8 inner_dmac[0x1]; 352 u8 inner_smac[0x1]; 353 u8 inner_ether_type[0x1]; 354 u8 inner_ip_version[0x1]; 355 u8 inner_first_prio[0x1]; 356 u8 inner_first_cfi[0x1]; 357 u8 inner_first_vid[0x1]; 358 u8 reserved_at_27[0x1]; 359 u8 inner_second_prio[0x1]; 360 u8 inner_second_cfi[0x1]; 361 u8 inner_second_vid[0x1]; 362 u8 reserved_at_2b[0x1]; 363 u8 inner_sip[0x1]; 364 u8 inner_dip[0x1]; 365 u8 inner_frag[0x1]; 366 u8 inner_ip_protocol[0x1]; 367 u8 inner_ip_ecn[0x1]; 368 u8 inner_ip_dscp[0x1]; 369 u8 inner_udp_sport[0x1]; 370 u8 inner_udp_dport[0x1]; 371 u8 inner_tcp_sport[0x1]; 372 u8 inner_tcp_dport[0x1]; 373 u8 inner_tcp_flags[0x1]; 374 u8 reserved_at_37[0x9]; 375 376 u8 geneve_tlv_option_0_data[0x1]; 377 u8 geneve_tlv_option_0_exist[0x1]; 378 u8 reserved_at_42[0x3]; 379 u8 outer_first_mpls_over_udp[0x4]; 380 u8 outer_first_mpls_over_gre[0x4]; 381 u8 inner_first_mpls[0x4]; 382 u8 outer_first_mpls[0x4]; 383 u8 reserved_at_55[0x2]; 384 u8 outer_esp_spi[0x1]; 385 u8 reserved_at_58[0x2]; 386 u8 bth_dst_qp[0x1]; 387 u8 reserved_at_5b[0x5]; 388 389 u8 reserved_at_60[0x18]; 390 u8 metadata_reg_c_7[0x1]; 391 u8 metadata_reg_c_6[0x1]; 392 u8 metadata_reg_c_5[0x1]; 393 u8 metadata_reg_c_4[0x1]; 394 u8 metadata_reg_c_3[0x1]; 395 u8 metadata_reg_c_2[0x1]; 396 u8 metadata_reg_c_1[0x1]; 397 u8 metadata_reg_c_0[0x1]; 398 }; 399 400 struct mlx5_ifc_flow_table_fields_supported_2_bits { 401 u8 reserved_at_0[0xe]; 402 u8 bth_opcode[0x1]; 403 u8 reserved_at_f[0x11]; 404 405 u8 reserved_at_20[0x60]; 406 }; 407 408 struct mlx5_ifc_flow_table_prop_layout_bits { 409 u8 ft_support[0x1]; 410 u8 reserved_at_1[0x1]; 411 u8 flow_counter[0x1]; 412 u8 flow_modify_en[0x1]; 413 u8 modify_root[0x1]; 414 u8 identified_miss_table_mode[0x1]; 415 u8 flow_table_modify[0x1]; 416 u8 reformat[0x1]; 417 u8 decap[0x1]; 418 u8 reserved_at_9[0x1]; 419 u8 pop_vlan[0x1]; 420 u8 push_vlan[0x1]; 421 u8 reserved_at_c[0x1]; 422 u8 pop_vlan_2[0x1]; 423 u8 push_vlan_2[0x1]; 424 u8 reformat_and_vlan_action[0x1]; 425 u8 reserved_at_10[0x1]; 426 u8 sw_owner[0x1]; 427 u8 reformat_l3_tunnel_to_l2[0x1]; 428 u8 reformat_l2_to_l3_tunnel[0x1]; 429 u8 reformat_and_modify_action[0x1]; 430 u8 ignore_flow_level[0x1]; 431 u8 reserved_at_16[0x1]; 432 u8 table_miss_action_domain[0x1]; 433 u8 termination_table[0x1]; 434 u8 reformat_and_fwd_to_table[0x1]; 435 u8 reserved_at_1a[0x2]; 436 u8 ipsec_encrypt[0x1]; 437 u8 ipsec_decrypt[0x1]; 438 u8 sw_owner_v2[0x1]; 439 u8 reserved_at_1f[0x1]; 440 441 u8 termination_table_raw_traffic[0x1]; 442 u8 reserved_at_21[0x1]; 443 u8 log_max_ft_size[0x6]; 444 u8 log_max_modify_header_context[0x8]; 445 u8 max_modify_header_actions[0x8]; 446 u8 max_ft_level[0x8]; 447 448 u8 reserved_at_40[0x6]; 449 u8 execute_aso[0x1]; 450 u8 reserved_at_47[0x19]; 451 452 u8 reserved_at_60[0x2]; 453 u8 reformat_insert[0x1]; 454 u8 reformat_remove[0x1]; 455 u8 macsec_encrypt[0x1]; 456 u8 macsec_decrypt[0x1]; 457 u8 reserved_at_66[0x2]; 458 u8 reformat_add_macsec[0x1]; 459 u8 reformat_remove_macsec[0x1]; 460 u8 reserved_at_6a[0xe]; 461 u8 log_max_ft_num[0x8]; 462 463 u8 reserved_at_80[0x10]; 464 u8 log_max_flow_counter[0x8]; 465 u8 log_max_destination[0x8]; 466 467 u8 reserved_at_a0[0x18]; 468 u8 log_max_flow[0x8]; 469 470 u8 reserved_at_c0[0x40]; 471 472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 473 474 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 475 }; 476 477 struct mlx5_ifc_odp_per_transport_service_cap_bits { 478 u8 send[0x1]; 479 u8 receive[0x1]; 480 u8 write[0x1]; 481 u8 read[0x1]; 482 u8 atomic[0x1]; 483 u8 srq_receive[0x1]; 484 u8 reserved_at_6[0x1a]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 ip_version[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_at_c0[0x10]; 529 u8 ipv4_ihl[0x4]; 530 u8 reserved_at_c4[0x4]; 531 532 u8 ttl_hoplimit[0x8]; 533 534 u8 udp_sport[0x10]; 535 u8 udp_dport[0x10]; 536 537 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 538 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 540 }; 541 542 struct mlx5_ifc_nvgre_key_bits { 543 u8 hi[0x18]; 544 u8 lo[0x8]; 545 }; 546 547 union mlx5_ifc_gre_key_bits { 548 struct mlx5_ifc_nvgre_key_bits nvgre; 549 u8 key[0x20]; 550 }; 551 552 struct mlx5_ifc_fte_match_set_misc_bits { 553 u8 gre_c_present[0x1]; 554 u8 reserved_at_1[0x1]; 555 u8 gre_k_present[0x1]; 556 u8 gre_s_present[0x1]; 557 u8 source_vhca_port[0x4]; 558 u8 source_sqn[0x18]; 559 560 u8 source_eswitch_owner_vhca_id[0x10]; 561 u8 source_port[0x10]; 562 563 u8 outer_second_prio[0x3]; 564 u8 outer_second_cfi[0x1]; 565 u8 outer_second_vid[0xc]; 566 u8 inner_second_prio[0x3]; 567 u8 inner_second_cfi[0x1]; 568 u8 inner_second_vid[0xc]; 569 570 u8 outer_second_cvlan_tag[0x1]; 571 u8 inner_second_cvlan_tag[0x1]; 572 u8 outer_second_svlan_tag[0x1]; 573 u8 inner_second_svlan_tag[0x1]; 574 u8 reserved_at_64[0xc]; 575 u8 gre_protocol[0x10]; 576 577 union mlx5_ifc_gre_key_bits gre_key; 578 579 u8 vxlan_vni[0x18]; 580 u8 bth_opcode[0x8]; 581 582 u8 geneve_vni[0x18]; 583 u8 reserved_at_d8[0x6]; 584 u8 geneve_tlv_option_0_exist[0x1]; 585 u8 geneve_oam[0x1]; 586 587 u8 reserved_at_e0[0xc]; 588 u8 outer_ipv6_flow_label[0x14]; 589 590 u8 reserved_at_100[0xc]; 591 u8 inner_ipv6_flow_label[0x14]; 592 593 u8 reserved_at_120[0xa]; 594 u8 geneve_opt_len[0x6]; 595 u8 geneve_protocol_type[0x10]; 596 597 u8 reserved_at_140[0x8]; 598 u8 bth_dst_qp[0x18]; 599 u8 reserved_at_160[0x20]; 600 u8 outer_esp_spi[0x20]; 601 u8 reserved_at_1a0[0x60]; 602 }; 603 604 struct mlx5_ifc_fte_match_mpls_bits { 605 u8 mpls_label[0x14]; 606 u8 mpls_exp[0x3]; 607 u8 mpls_s_bos[0x1]; 608 u8 mpls_ttl[0x8]; 609 }; 610 611 struct mlx5_ifc_fte_match_set_misc2_bits { 612 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 613 614 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 615 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 617 618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 619 620 u8 metadata_reg_c_7[0x20]; 621 622 u8 metadata_reg_c_6[0x20]; 623 624 u8 metadata_reg_c_5[0x20]; 625 626 u8 metadata_reg_c_4[0x20]; 627 628 u8 metadata_reg_c_3[0x20]; 629 630 u8 metadata_reg_c_2[0x20]; 631 632 u8 metadata_reg_c_1[0x20]; 633 634 u8 metadata_reg_c_0[0x20]; 635 636 u8 metadata_reg_a[0x20]; 637 638 u8 reserved_at_1a0[0x8]; 639 640 u8 macsec_syndrome[0x8]; 641 642 u8 reserved_at_1b0[0x50]; 643 }; 644 645 struct mlx5_ifc_fte_match_set_misc3_bits { 646 u8 inner_tcp_seq_num[0x20]; 647 648 u8 outer_tcp_seq_num[0x20]; 649 650 u8 inner_tcp_ack_num[0x20]; 651 652 u8 outer_tcp_ack_num[0x20]; 653 654 u8 reserved_at_80[0x8]; 655 u8 outer_vxlan_gpe_vni[0x18]; 656 657 u8 outer_vxlan_gpe_next_protocol[0x8]; 658 u8 outer_vxlan_gpe_flags[0x8]; 659 u8 reserved_at_b0[0x10]; 660 661 u8 icmp_header_data[0x20]; 662 663 u8 icmpv6_header_data[0x20]; 664 665 u8 icmp_type[0x8]; 666 u8 icmp_code[0x8]; 667 u8 icmpv6_type[0x8]; 668 u8 icmpv6_code[0x8]; 669 670 u8 geneve_tlv_option_0_data[0x20]; 671 672 u8 gtpu_teid[0x20]; 673 674 u8 gtpu_msg_type[0x8]; 675 u8 gtpu_msg_flags[0x8]; 676 u8 reserved_at_170[0x10]; 677 678 u8 gtpu_dw_2[0x20]; 679 680 u8 gtpu_first_ext_dw_0[0x20]; 681 682 u8 gtpu_dw_0[0x20]; 683 684 u8 reserved_at_1e0[0x20]; 685 }; 686 687 struct mlx5_ifc_fte_match_set_misc4_bits { 688 u8 prog_sample_field_value_0[0x20]; 689 690 u8 prog_sample_field_id_0[0x20]; 691 692 u8 prog_sample_field_value_1[0x20]; 693 694 u8 prog_sample_field_id_1[0x20]; 695 696 u8 prog_sample_field_value_2[0x20]; 697 698 u8 prog_sample_field_id_2[0x20]; 699 700 u8 prog_sample_field_value_3[0x20]; 701 702 u8 prog_sample_field_id_3[0x20]; 703 704 u8 reserved_at_100[0x100]; 705 }; 706 707 struct mlx5_ifc_fte_match_set_misc5_bits { 708 u8 macsec_tag_0[0x20]; 709 710 u8 macsec_tag_1[0x20]; 711 712 u8 macsec_tag_2[0x20]; 713 714 u8 macsec_tag_3[0x20]; 715 716 u8 tunnel_header_0[0x20]; 717 718 u8 tunnel_header_1[0x20]; 719 720 u8 tunnel_header_2[0x20]; 721 722 u8 tunnel_header_3[0x20]; 723 724 u8 reserved_at_100[0x100]; 725 }; 726 727 struct mlx5_ifc_cmd_pas_bits { 728 u8 pa_h[0x20]; 729 730 u8 pa_l[0x14]; 731 u8 reserved_at_34[0xc]; 732 }; 733 734 struct mlx5_ifc_uint64_bits { 735 u8 hi[0x20]; 736 737 u8 lo[0x20]; 738 }; 739 740 enum { 741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 743 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 744 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 745 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 746 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 747 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 748 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 749 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 750 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 751 }; 752 753 struct mlx5_ifc_ads_bits { 754 u8 fl[0x1]; 755 u8 free_ar[0x1]; 756 u8 reserved_at_2[0xe]; 757 u8 pkey_index[0x10]; 758 759 u8 reserved_at_20[0x8]; 760 u8 grh[0x1]; 761 u8 mlid[0x7]; 762 u8 rlid[0x10]; 763 764 u8 ack_timeout[0x5]; 765 u8 reserved_at_45[0x3]; 766 u8 src_addr_index[0x8]; 767 u8 reserved_at_50[0x4]; 768 u8 stat_rate[0x4]; 769 u8 hop_limit[0x8]; 770 771 u8 reserved_at_60[0x4]; 772 u8 tclass[0x8]; 773 u8 flow_label[0x14]; 774 775 u8 rgid_rip[16][0x8]; 776 777 u8 reserved_at_100[0x4]; 778 u8 f_dscp[0x1]; 779 u8 f_ecn[0x1]; 780 u8 reserved_at_106[0x1]; 781 u8 f_eth_prio[0x1]; 782 u8 ecn[0x2]; 783 u8 dscp[0x6]; 784 u8 udp_sport[0x10]; 785 786 u8 dei_cfi[0x1]; 787 u8 eth_prio[0x3]; 788 u8 sl[0x4]; 789 u8 vhca_port_num[0x8]; 790 u8 rmac_47_32[0x10]; 791 792 u8 rmac_31_0[0x20]; 793 }; 794 795 struct mlx5_ifc_flow_table_nic_cap_bits { 796 u8 nic_rx_multi_path_tirs[0x1]; 797 u8 nic_rx_multi_path_tirs_fts[0x1]; 798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 799 u8 reserved_at_3[0x4]; 800 u8 sw_owner_reformat_supported[0x1]; 801 u8 reserved_at_8[0x18]; 802 803 u8 encap_general_header[0x1]; 804 u8 reserved_at_21[0xa]; 805 u8 log_max_packet_reformat_context[0x5]; 806 u8 reserved_at_30[0x6]; 807 u8 max_encap_header_size[0xa]; 808 u8 reserved_at_40[0x1c0]; 809 810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 813 814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 821 822 u8 reserved_at_e00[0x700]; 823 824 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 825 826 u8 reserved_at_1580[0x280]; 827 828 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 829 830 u8 reserved_at_1880[0x780]; 831 832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 833 834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 835 836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 837 838 u8 reserved_at_20c0[0x5f40]; 839 }; 840 841 struct mlx5_ifc_port_selection_cap_bits { 842 u8 reserved_at_0[0x10]; 843 u8 port_select_flow_table[0x1]; 844 u8 reserved_at_11[0x1]; 845 u8 port_select_flow_table_bypass[0x1]; 846 u8 reserved_at_13[0xd]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 851 852 u8 reserved_at_400[0x7c00]; 853 }; 854 855 enum { 856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 864 }; 865 866 struct mlx5_ifc_flow_table_eswitch_cap_bits { 867 u8 fdb_to_vport_reg_c_id[0x8]; 868 u8 reserved_at_8[0xd]; 869 u8 fdb_modify_header_fwd_to_table[0x1]; 870 u8 fdb_ipv4_ttl_modify[0x1]; 871 u8 flow_source[0x1]; 872 u8 reserved_at_18[0x2]; 873 u8 multi_fdb_encap[0x1]; 874 u8 egress_acl_forward_to_vport[0x1]; 875 u8 fdb_multi_path_to_table[0x1]; 876 u8 reserved_at_1d[0x3]; 877 878 u8 reserved_at_20[0x1e0]; 879 880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 881 882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 885 886 u8 reserved_at_800[0x1000]; 887 888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 889 890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 891 892 u8 sw_steering_uplink_icm_address_rx[0x40]; 893 894 u8 sw_steering_uplink_icm_address_tx[0x40]; 895 896 u8 reserved_at_1900[0x6700]; 897 }; 898 899 enum { 900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 901 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 902 }; 903 904 struct mlx5_ifc_e_switch_cap_bits { 905 u8 vport_svlan_strip[0x1]; 906 u8 vport_cvlan_strip[0x1]; 907 u8 vport_svlan_insert[0x1]; 908 u8 vport_cvlan_insert_if_not_exist[0x1]; 909 u8 vport_cvlan_insert_overwrite[0x1]; 910 u8 reserved_at_5[0x1]; 911 u8 vport_cvlan_insert_always[0x1]; 912 u8 esw_shared_ingress_acl[0x1]; 913 u8 esw_uplink_ingress_acl[0x1]; 914 u8 root_ft_on_other_esw[0x1]; 915 u8 reserved_at_a[0xf]; 916 u8 esw_functions_changed[0x1]; 917 u8 reserved_at_1a[0x1]; 918 u8 ecpf_vport_exists[0x1]; 919 u8 counter_eswitch_affinity[0x1]; 920 u8 merged_eswitch[0x1]; 921 u8 nic_vport_node_guid_modify[0x1]; 922 u8 nic_vport_port_guid_modify[0x1]; 923 924 u8 vxlan_encap_decap[0x1]; 925 u8 nvgre_encap_decap[0x1]; 926 u8 reserved_at_22[0x1]; 927 u8 log_max_fdb_encap_uplink[0x5]; 928 u8 reserved_at_21[0x3]; 929 u8 log_max_packet_reformat_context[0x5]; 930 u8 reserved_2b[0x6]; 931 u8 max_encap_header_size[0xa]; 932 933 u8 reserved_at_40[0xb]; 934 u8 log_max_esw_sf[0x5]; 935 u8 esw_sf_base_id[0x10]; 936 937 u8 reserved_at_60[0x7a0]; 938 939 }; 940 941 struct mlx5_ifc_qos_cap_bits { 942 u8 packet_pacing[0x1]; 943 u8 esw_scheduling[0x1]; 944 u8 esw_bw_share[0x1]; 945 u8 esw_rate_limit[0x1]; 946 u8 reserved_at_4[0x1]; 947 u8 packet_pacing_burst_bound[0x1]; 948 u8 packet_pacing_typical_size[0x1]; 949 u8 reserved_at_7[0x1]; 950 u8 nic_sq_scheduling[0x1]; 951 u8 nic_bw_share[0x1]; 952 u8 nic_rate_limit[0x1]; 953 u8 packet_pacing_uid[0x1]; 954 u8 log_esw_max_sched_depth[0x4]; 955 u8 reserved_at_10[0x10]; 956 957 u8 reserved_at_20[0xb]; 958 u8 log_max_qos_nic_queue_group[0x5]; 959 u8 reserved_at_30[0x10]; 960 961 u8 packet_pacing_max_rate[0x20]; 962 963 u8 packet_pacing_min_rate[0x20]; 964 965 u8 reserved_at_80[0x10]; 966 u8 packet_pacing_rate_table_size[0x10]; 967 968 u8 esw_element_type[0x10]; 969 u8 esw_tsar_type[0x10]; 970 971 u8 reserved_at_c0[0x10]; 972 u8 max_qos_para_vport[0x10]; 973 974 u8 max_tsar_bw_share[0x20]; 975 976 u8 reserved_at_100[0x20]; 977 978 u8 reserved_at_120[0x3]; 979 u8 log_meter_aso_granularity[0x5]; 980 u8 reserved_at_128[0x3]; 981 u8 log_meter_aso_max_alloc[0x5]; 982 u8 reserved_at_130[0x3]; 983 u8 log_max_num_meter_aso[0x5]; 984 u8 reserved_at_138[0x8]; 985 986 u8 reserved_at_140[0x6c0]; 987 }; 988 989 struct mlx5_ifc_debug_cap_bits { 990 u8 core_dump_general[0x1]; 991 u8 core_dump_qp[0x1]; 992 u8 reserved_at_2[0x7]; 993 u8 resource_dump[0x1]; 994 u8 reserved_at_a[0x16]; 995 996 u8 reserved_at_20[0x2]; 997 u8 stall_detect[0x1]; 998 u8 reserved_at_23[0x1d]; 999 1000 u8 reserved_at_40[0x7c0]; 1001 }; 1002 1003 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1004 u8 csum_cap[0x1]; 1005 u8 vlan_cap[0x1]; 1006 u8 lro_cap[0x1]; 1007 u8 lro_psh_flag[0x1]; 1008 u8 lro_time_stamp[0x1]; 1009 u8 reserved_at_5[0x2]; 1010 u8 wqe_vlan_insert[0x1]; 1011 u8 self_lb_en_modifiable[0x1]; 1012 u8 reserved_at_9[0x2]; 1013 u8 max_lso_cap[0x5]; 1014 u8 multi_pkt_send_wqe[0x2]; 1015 u8 wqe_inline_mode[0x2]; 1016 u8 rss_ind_tbl_cap[0x4]; 1017 u8 reg_umr_sq[0x1]; 1018 u8 scatter_fcs[0x1]; 1019 u8 enhanced_multi_pkt_send_wqe[0x1]; 1020 u8 tunnel_lso_const_out_ip_id[0x1]; 1021 u8 tunnel_lro_gre[0x1]; 1022 u8 tunnel_lro_vxlan[0x1]; 1023 u8 tunnel_stateless_gre[0x1]; 1024 u8 tunnel_stateless_vxlan[0x1]; 1025 1026 u8 swp[0x1]; 1027 u8 swp_csum[0x1]; 1028 u8 swp_lso[0x1]; 1029 u8 cqe_checksum_full[0x1]; 1030 u8 tunnel_stateless_geneve_tx[0x1]; 1031 u8 tunnel_stateless_mpls_over_udp[0x1]; 1032 u8 tunnel_stateless_mpls_over_gre[0x1]; 1033 u8 tunnel_stateless_vxlan_gpe[0x1]; 1034 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1035 u8 tunnel_stateless_ip_over_ip[0x1]; 1036 u8 insert_trailer[0x1]; 1037 u8 reserved_at_2b[0x1]; 1038 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1039 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1040 u8 reserved_at_2e[0x2]; 1041 u8 max_vxlan_udp_ports[0x8]; 1042 u8 reserved_at_38[0x6]; 1043 u8 max_geneve_opt_len[0x1]; 1044 u8 tunnel_stateless_geneve_rx[0x1]; 1045 1046 u8 reserved_at_40[0x10]; 1047 u8 lro_min_mss_size[0x10]; 1048 1049 u8 reserved_at_60[0x120]; 1050 1051 u8 lro_timer_supported_periods[4][0x20]; 1052 1053 u8 reserved_at_200[0x600]; 1054 }; 1055 1056 enum { 1057 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1058 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1059 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1060 }; 1061 1062 struct mlx5_ifc_roce_cap_bits { 1063 u8 roce_apm[0x1]; 1064 u8 reserved_at_1[0x3]; 1065 u8 sw_r_roce_src_udp_port[0x1]; 1066 u8 fl_rc_qp_when_roce_disabled[0x1]; 1067 u8 fl_rc_qp_when_roce_enabled[0x1]; 1068 u8 reserved_at_7[0x17]; 1069 u8 qp_ts_format[0x2]; 1070 1071 u8 reserved_at_20[0x60]; 1072 1073 u8 reserved_at_80[0xc]; 1074 u8 l3_type[0x4]; 1075 u8 reserved_at_90[0x8]; 1076 u8 roce_version[0x8]; 1077 1078 u8 reserved_at_a0[0x10]; 1079 u8 r_roce_dest_udp_port[0x10]; 1080 1081 u8 r_roce_max_src_udp_port[0x10]; 1082 u8 r_roce_min_src_udp_port[0x10]; 1083 1084 u8 reserved_at_e0[0x10]; 1085 u8 roce_address_table_size[0x10]; 1086 1087 u8 reserved_at_100[0x700]; 1088 }; 1089 1090 struct mlx5_ifc_sync_steering_in_bits { 1091 u8 opcode[0x10]; 1092 u8 uid[0x10]; 1093 1094 u8 reserved_at_20[0x10]; 1095 u8 op_mod[0x10]; 1096 1097 u8 reserved_at_40[0xc0]; 1098 }; 1099 1100 struct mlx5_ifc_sync_steering_out_bits { 1101 u8 status[0x8]; 1102 u8 reserved_at_8[0x18]; 1103 1104 u8 syndrome[0x20]; 1105 1106 u8 reserved_at_40[0x40]; 1107 }; 1108 1109 struct mlx5_ifc_device_mem_cap_bits { 1110 u8 memic[0x1]; 1111 u8 reserved_at_1[0x1f]; 1112 1113 u8 reserved_at_20[0xb]; 1114 u8 log_min_memic_alloc_size[0x5]; 1115 u8 reserved_at_30[0x8]; 1116 u8 log_max_memic_addr_alignment[0x8]; 1117 1118 u8 memic_bar_start_addr[0x40]; 1119 1120 u8 memic_bar_size[0x20]; 1121 1122 u8 max_memic_size[0x20]; 1123 1124 u8 steering_sw_icm_start_address[0x40]; 1125 1126 u8 reserved_at_100[0x8]; 1127 u8 log_header_modify_sw_icm_size[0x8]; 1128 u8 reserved_at_110[0x2]; 1129 u8 log_sw_icm_alloc_granularity[0x6]; 1130 u8 log_steering_sw_icm_size[0x8]; 1131 1132 u8 reserved_at_120[0x18]; 1133 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1134 1135 u8 header_modify_sw_icm_start_address[0x40]; 1136 1137 u8 reserved_at_180[0x40]; 1138 1139 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1140 1141 u8 memic_operations[0x20]; 1142 1143 u8 reserved_at_220[0x5e0]; 1144 }; 1145 1146 struct mlx5_ifc_device_event_cap_bits { 1147 u8 user_affiliated_events[4][0x40]; 1148 1149 u8 user_unaffiliated_events[4][0x40]; 1150 }; 1151 1152 struct mlx5_ifc_virtio_emulation_cap_bits { 1153 u8 desc_tunnel_offload_type[0x1]; 1154 u8 eth_frame_offload_type[0x1]; 1155 u8 virtio_version_1_0[0x1]; 1156 u8 device_features_bits_mask[0xd]; 1157 u8 event_mode[0x8]; 1158 u8 virtio_queue_type[0x8]; 1159 1160 u8 max_tunnel_desc[0x10]; 1161 u8 reserved_at_30[0x3]; 1162 u8 log_doorbell_stride[0x5]; 1163 u8 reserved_at_38[0x3]; 1164 u8 log_doorbell_bar_size[0x5]; 1165 1166 u8 doorbell_bar_offset[0x40]; 1167 1168 u8 max_emulated_devices[0x8]; 1169 u8 max_num_virtio_queues[0x18]; 1170 1171 u8 reserved_at_a0[0x60]; 1172 1173 u8 umem_1_buffer_param_a[0x20]; 1174 1175 u8 umem_1_buffer_param_b[0x20]; 1176 1177 u8 umem_2_buffer_param_a[0x20]; 1178 1179 u8 umem_2_buffer_param_b[0x20]; 1180 1181 u8 umem_3_buffer_param_a[0x20]; 1182 1183 u8 umem_3_buffer_param_b[0x20]; 1184 1185 u8 reserved_at_1c0[0x640]; 1186 }; 1187 1188 enum { 1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1197 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1198 }; 1199 1200 enum { 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1209 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1210 }; 1211 1212 struct mlx5_ifc_atomic_caps_bits { 1213 u8 reserved_at_0[0x40]; 1214 1215 u8 atomic_req_8B_endianness_mode[0x2]; 1216 u8 reserved_at_42[0x4]; 1217 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1218 1219 u8 reserved_at_47[0x19]; 1220 1221 u8 reserved_at_60[0x20]; 1222 1223 u8 reserved_at_80[0x10]; 1224 u8 atomic_operations[0x10]; 1225 1226 u8 reserved_at_a0[0x10]; 1227 u8 atomic_size_qp[0x10]; 1228 1229 u8 reserved_at_c0[0x10]; 1230 u8 atomic_size_dc[0x10]; 1231 1232 u8 reserved_at_e0[0x720]; 1233 }; 1234 1235 struct mlx5_ifc_odp_cap_bits { 1236 u8 reserved_at_0[0x40]; 1237 1238 u8 sig[0x1]; 1239 u8 reserved_at_41[0x1f]; 1240 1241 u8 reserved_at_60[0x20]; 1242 1243 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1244 1245 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1246 1247 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1248 1249 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1250 1251 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1252 1253 u8 reserved_at_120[0x6E0]; 1254 }; 1255 1256 struct mlx5_ifc_calc_op { 1257 u8 reserved_at_0[0x10]; 1258 u8 reserved_at_10[0x9]; 1259 u8 op_swap_endianness[0x1]; 1260 u8 op_min[0x1]; 1261 u8 op_xor[0x1]; 1262 u8 op_or[0x1]; 1263 u8 op_and[0x1]; 1264 u8 op_max[0x1]; 1265 u8 op_add[0x1]; 1266 }; 1267 1268 struct mlx5_ifc_vector_calc_cap_bits { 1269 u8 calc_matrix[0x1]; 1270 u8 reserved_at_1[0x1f]; 1271 u8 reserved_at_20[0x8]; 1272 u8 max_vec_count[0x8]; 1273 u8 reserved_at_30[0xd]; 1274 u8 max_chunk_size[0x3]; 1275 struct mlx5_ifc_calc_op calc0; 1276 struct mlx5_ifc_calc_op calc1; 1277 struct mlx5_ifc_calc_op calc2; 1278 struct mlx5_ifc_calc_op calc3; 1279 1280 u8 reserved_at_c0[0x720]; 1281 }; 1282 1283 struct mlx5_ifc_tls_cap_bits { 1284 u8 tls_1_2_aes_gcm_128[0x1]; 1285 u8 tls_1_3_aes_gcm_128[0x1]; 1286 u8 tls_1_2_aes_gcm_256[0x1]; 1287 u8 tls_1_3_aes_gcm_256[0x1]; 1288 u8 reserved_at_4[0x1c]; 1289 1290 u8 reserved_at_20[0x7e0]; 1291 }; 1292 1293 struct mlx5_ifc_ipsec_cap_bits { 1294 u8 ipsec_full_offload[0x1]; 1295 u8 ipsec_crypto_offload[0x1]; 1296 u8 ipsec_esn[0x1]; 1297 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1298 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1299 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1300 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1301 u8 reserved_at_7[0x4]; 1302 u8 log_max_ipsec_offload[0x5]; 1303 u8 reserved_at_10[0x10]; 1304 1305 u8 min_log_ipsec_full_replay_window[0x8]; 1306 u8 max_log_ipsec_full_replay_window[0x8]; 1307 u8 reserved_at_30[0x7d0]; 1308 }; 1309 1310 struct mlx5_ifc_macsec_cap_bits { 1311 u8 macsec_epn[0x1]; 1312 u8 reserved_at_1[0x2]; 1313 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1314 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1315 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1316 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1317 u8 reserved_at_7[0x4]; 1318 u8 log_max_macsec_offload[0x5]; 1319 u8 reserved_at_10[0x10]; 1320 1321 u8 min_log_macsec_full_replay_window[0x8]; 1322 u8 max_log_macsec_full_replay_window[0x8]; 1323 u8 reserved_at_30[0x10]; 1324 1325 u8 reserved_at_40[0x7c0]; 1326 }; 1327 1328 enum { 1329 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1330 MLX5_WQ_TYPE_CYCLIC = 0x1, 1331 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1332 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1333 }; 1334 1335 enum { 1336 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1337 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1338 }; 1339 1340 enum { 1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1345 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1346 }; 1347 1348 enum { 1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1354 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1355 }; 1356 1357 enum { 1358 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1359 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1360 }; 1361 1362 enum { 1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1365 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1366 }; 1367 1368 enum { 1369 MLX5_CAP_PORT_TYPE_IB = 0x0, 1370 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1371 }; 1372 1373 enum { 1374 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1375 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1376 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1377 }; 1378 1379 enum { 1380 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1381 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1382 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1383 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1384 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1385 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1386 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1387 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1388 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1389 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1390 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1391 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1392 }; 1393 1394 enum { 1395 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1396 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1397 }; 1398 1399 #define MLX5_FC_BULK_SIZE_FACTOR 128 1400 1401 enum mlx5_fc_bulk_alloc_bitmask { 1402 MLX5_FC_BULK_128 = (1 << 0), 1403 MLX5_FC_BULK_256 = (1 << 1), 1404 MLX5_FC_BULK_512 = (1 << 2), 1405 MLX5_FC_BULK_1024 = (1 << 3), 1406 MLX5_FC_BULK_2048 = (1 << 4), 1407 MLX5_FC_BULK_4096 = (1 << 5), 1408 MLX5_FC_BULK_8192 = (1 << 6), 1409 MLX5_FC_BULK_16384 = (1 << 7), 1410 }; 1411 1412 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1413 1414 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1415 1416 enum { 1417 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1418 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1419 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1420 }; 1421 1422 struct mlx5_ifc_cmd_hca_cap_bits { 1423 u8 reserved_at_0[0x10]; 1424 u8 shared_object_to_user_object_allowed[0x1]; 1425 u8 reserved_at_13[0xe]; 1426 u8 vhca_resource_manager[0x1]; 1427 1428 u8 hca_cap_2[0x1]; 1429 u8 create_lag_when_not_master_up[0x1]; 1430 u8 dtor[0x1]; 1431 u8 event_on_vhca_state_teardown_request[0x1]; 1432 u8 event_on_vhca_state_in_use[0x1]; 1433 u8 event_on_vhca_state_active[0x1]; 1434 u8 event_on_vhca_state_allocated[0x1]; 1435 u8 event_on_vhca_state_invalid[0x1]; 1436 u8 reserved_at_28[0x8]; 1437 u8 vhca_id[0x10]; 1438 1439 u8 reserved_at_40[0x40]; 1440 1441 u8 log_max_srq_sz[0x8]; 1442 u8 log_max_qp_sz[0x8]; 1443 u8 event_cap[0x1]; 1444 u8 reserved_at_91[0x2]; 1445 u8 isolate_vl_tc_new[0x1]; 1446 u8 reserved_at_94[0x4]; 1447 u8 prio_tag_required[0x1]; 1448 u8 reserved_at_99[0x2]; 1449 u8 log_max_qp[0x5]; 1450 1451 u8 reserved_at_a0[0x3]; 1452 u8 ece_support[0x1]; 1453 u8 reserved_at_a4[0x5]; 1454 u8 reg_c_preserve[0x1]; 1455 u8 reserved_at_aa[0x1]; 1456 u8 log_max_srq[0x5]; 1457 u8 reserved_at_b0[0x1]; 1458 u8 uplink_follow[0x1]; 1459 u8 ts_cqe_to_dest_cqn[0x1]; 1460 u8 reserved_at_b3[0x7]; 1461 u8 shampo[0x1]; 1462 u8 reserved_at_bb[0x5]; 1463 1464 u8 max_sgl_for_optimized_performance[0x8]; 1465 u8 log_max_cq_sz[0x8]; 1466 u8 relaxed_ordering_write_umr[0x1]; 1467 u8 relaxed_ordering_read_umr[0x1]; 1468 u8 reserved_at_d2[0x7]; 1469 u8 virtio_net_device_emualtion_manager[0x1]; 1470 u8 virtio_blk_device_emualtion_manager[0x1]; 1471 u8 log_max_cq[0x5]; 1472 1473 u8 log_max_eq_sz[0x8]; 1474 u8 relaxed_ordering_write[0x1]; 1475 u8 relaxed_ordering_read[0x1]; 1476 u8 log_max_mkey[0x6]; 1477 u8 reserved_at_f0[0x8]; 1478 u8 dump_fill_mkey[0x1]; 1479 u8 reserved_at_f9[0x2]; 1480 u8 fast_teardown[0x1]; 1481 u8 log_max_eq[0x4]; 1482 1483 u8 max_indirection[0x8]; 1484 u8 fixed_buffer_size[0x1]; 1485 u8 log_max_mrw_sz[0x7]; 1486 u8 force_teardown[0x1]; 1487 u8 reserved_at_111[0x1]; 1488 u8 log_max_bsf_list_size[0x6]; 1489 u8 umr_extended_translation_offset[0x1]; 1490 u8 null_mkey[0x1]; 1491 u8 log_max_klm_list_size[0x6]; 1492 1493 u8 reserved_at_120[0xa]; 1494 u8 log_max_ra_req_dc[0x6]; 1495 u8 reserved_at_130[0x2]; 1496 u8 eth_wqe_too_small[0x1]; 1497 u8 reserved_at_133[0x6]; 1498 u8 vnic_env_cq_overrun[0x1]; 1499 u8 log_max_ra_res_dc[0x6]; 1500 1501 u8 reserved_at_140[0x5]; 1502 u8 release_all_pages[0x1]; 1503 u8 must_not_use[0x1]; 1504 u8 reserved_at_147[0x2]; 1505 u8 roce_accl[0x1]; 1506 u8 log_max_ra_req_qp[0x6]; 1507 u8 reserved_at_150[0xa]; 1508 u8 log_max_ra_res_qp[0x6]; 1509 1510 u8 end_pad[0x1]; 1511 u8 cc_query_allowed[0x1]; 1512 u8 cc_modify_allowed[0x1]; 1513 u8 start_pad[0x1]; 1514 u8 cache_line_128byte[0x1]; 1515 u8 reserved_at_165[0x4]; 1516 u8 rts2rts_qp_counters_set_id[0x1]; 1517 u8 reserved_at_16a[0x2]; 1518 u8 vnic_env_int_rq_oob[0x1]; 1519 u8 sbcam_reg[0x1]; 1520 u8 reserved_at_16e[0x1]; 1521 u8 qcam_reg[0x1]; 1522 u8 gid_table_size[0x10]; 1523 1524 u8 out_of_seq_cnt[0x1]; 1525 u8 vport_counters[0x1]; 1526 u8 retransmission_q_counters[0x1]; 1527 u8 debug[0x1]; 1528 u8 modify_rq_counter_set_id[0x1]; 1529 u8 rq_delay_drop[0x1]; 1530 u8 max_qp_cnt[0xa]; 1531 u8 pkey_table_size[0x10]; 1532 1533 u8 vport_group_manager[0x1]; 1534 u8 vhca_group_manager[0x1]; 1535 u8 ib_virt[0x1]; 1536 u8 eth_virt[0x1]; 1537 u8 vnic_env_queue_counters[0x1]; 1538 u8 ets[0x1]; 1539 u8 nic_flow_table[0x1]; 1540 u8 eswitch_manager[0x1]; 1541 u8 device_memory[0x1]; 1542 u8 mcam_reg[0x1]; 1543 u8 pcam_reg[0x1]; 1544 u8 local_ca_ack_delay[0x5]; 1545 u8 port_module_event[0x1]; 1546 u8 enhanced_error_q_counters[0x1]; 1547 u8 ports_check[0x1]; 1548 u8 reserved_at_1b3[0x1]; 1549 u8 disable_link_up[0x1]; 1550 u8 beacon_led[0x1]; 1551 u8 port_type[0x2]; 1552 u8 num_ports[0x8]; 1553 1554 u8 reserved_at_1c0[0x1]; 1555 u8 pps[0x1]; 1556 u8 pps_modify[0x1]; 1557 u8 log_max_msg[0x5]; 1558 u8 reserved_at_1c8[0x4]; 1559 u8 max_tc[0x4]; 1560 u8 temp_warn_event[0x1]; 1561 u8 dcbx[0x1]; 1562 u8 general_notification_event[0x1]; 1563 u8 reserved_at_1d3[0x2]; 1564 u8 fpga[0x1]; 1565 u8 rol_s[0x1]; 1566 u8 rol_g[0x1]; 1567 u8 reserved_at_1d8[0x1]; 1568 u8 wol_s[0x1]; 1569 u8 wol_g[0x1]; 1570 u8 wol_a[0x1]; 1571 u8 wol_b[0x1]; 1572 u8 wol_m[0x1]; 1573 u8 wol_u[0x1]; 1574 u8 wol_p[0x1]; 1575 1576 u8 stat_rate_support[0x10]; 1577 u8 reserved_at_1f0[0x1]; 1578 u8 pci_sync_for_fw_update_event[0x1]; 1579 u8 reserved_at_1f2[0x6]; 1580 u8 init2_lag_tx_port_affinity[0x1]; 1581 u8 reserved_at_1fa[0x3]; 1582 u8 cqe_version[0x4]; 1583 1584 u8 compact_address_vector[0x1]; 1585 u8 striding_rq[0x1]; 1586 u8 reserved_at_202[0x1]; 1587 u8 ipoib_enhanced_offloads[0x1]; 1588 u8 ipoib_basic_offloads[0x1]; 1589 u8 reserved_at_205[0x1]; 1590 u8 repeated_block_disabled[0x1]; 1591 u8 umr_modify_entity_size_disabled[0x1]; 1592 u8 umr_modify_atomic_disabled[0x1]; 1593 u8 umr_indirect_mkey_disabled[0x1]; 1594 u8 umr_fence[0x2]; 1595 u8 dc_req_scat_data_cqe[0x1]; 1596 u8 reserved_at_20d[0x2]; 1597 u8 drain_sigerr[0x1]; 1598 u8 cmdif_checksum[0x2]; 1599 u8 sigerr_cqe[0x1]; 1600 u8 reserved_at_213[0x1]; 1601 u8 wq_signature[0x1]; 1602 u8 sctr_data_cqe[0x1]; 1603 u8 reserved_at_216[0x1]; 1604 u8 sho[0x1]; 1605 u8 tph[0x1]; 1606 u8 rf[0x1]; 1607 u8 dct[0x1]; 1608 u8 qos[0x1]; 1609 u8 eth_net_offloads[0x1]; 1610 u8 roce[0x1]; 1611 u8 atomic[0x1]; 1612 u8 reserved_at_21f[0x1]; 1613 1614 u8 cq_oi[0x1]; 1615 u8 cq_resize[0x1]; 1616 u8 cq_moderation[0x1]; 1617 u8 reserved_at_223[0x3]; 1618 u8 cq_eq_remap[0x1]; 1619 u8 pg[0x1]; 1620 u8 block_lb_mc[0x1]; 1621 u8 reserved_at_229[0x1]; 1622 u8 scqe_break_moderation[0x1]; 1623 u8 cq_period_start_from_cqe[0x1]; 1624 u8 cd[0x1]; 1625 u8 reserved_at_22d[0x1]; 1626 u8 apm[0x1]; 1627 u8 vector_calc[0x1]; 1628 u8 umr_ptr_rlky[0x1]; 1629 u8 imaicl[0x1]; 1630 u8 qp_packet_based[0x1]; 1631 u8 reserved_at_233[0x3]; 1632 u8 qkv[0x1]; 1633 u8 pkv[0x1]; 1634 u8 set_deth_sqpn[0x1]; 1635 u8 reserved_at_239[0x3]; 1636 u8 xrc[0x1]; 1637 u8 ud[0x1]; 1638 u8 uc[0x1]; 1639 u8 rc[0x1]; 1640 1641 u8 uar_4k[0x1]; 1642 u8 reserved_at_241[0x7]; 1643 u8 fl_rc_qp_when_roce_disabled[0x1]; 1644 u8 regexp_params[0x1]; 1645 u8 uar_sz[0x6]; 1646 u8 port_selection_cap[0x1]; 1647 u8 reserved_at_248[0x1]; 1648 u8 umem_uid_0[0x1]; 1649 u8 reserved_at_250[0x5]; 1650 u8 log_pg_sz[0x8]; 1651 1652 u8 bf[0x1]; 1653 u8 driver_version[0x1]; 1654 u8 pad_tx_eth_packet[0x1]; 1655 u8 reserved_at_263[0x3]; 1656 u8 mkey_by_name[0x1]; 1657 u8 reserved_at_267[0x4]; 1658 1659 u8 log_bf_reg_size[0x5]; 1660 1661 u8 reserved_at_270[0x6]; 1662 u8 lag_dct[0x2]; 1663 u8 lag_tx_port_affinity[0x1]; 1664 u8 lag_native_fdb_selection[0x1]; 1665 u8 reserved_at_27a[0x1]; 1666 u8 lag_master[0x1]; 1667 u8 num_lag_ports[0x4]; 1668 1669 u8 reserved_at_280[0x10]; 1670 u8 max_wqe_sz_sq[0x10]; 1671 1672 u8 reserved_at_2a0[0x10]; 1673 u8 max_wqe_sz_rq[0x10]; 1674 1675 u8 max_flow_counter_31_16[0x10]; 1676 u8 max_wqe_sz_sq_dc[0x10]; 1677 1678 u8 reserved_at_2e0[0x7]; 1679 u8 max_qp_mcg[0x19]; 1680 1681 u8 reserved_at_300[0x10]; 1682 u8 flow_counter_bulk_alloc[0x8]; 1683 u8 log_max_mcg[0x8]; 1684 1685 u8 reserved_at_320[0x3]; 1686 u8 log_max_transport_domain[0x5]; 1687 u8 reserved_at_328[0x3]; 1688 u8 log_max_pd[0x5]; 1689 u8 reserved_at_330[0xb]; 1690 u8 log_max_xrcd[0x5]; 1691 1692 u8 nic_receive_steering_discard[0x1]; 1693 u8 receive_discard_vport_down[0x1]; 1694 u8 transmit_discard_vport_down[0x1]; 1695 u8 eq_overrun_count[0x1]; 1696 u8 reserved_at_344[0x1]; 1697 u8 invalid_command_count[0x1]; 1698 u8 quota_exceeded_count[0x1]; 1699 u8 reserved_at_347[0x1]; 1700 u8 log_max_flow_counter_bulk[0x8]; 1701 u8 max_flow_counter_15_0[0x10]; 1702 1703 1704 u8 reserved_at_360[0x3]; 1705 u8 log_max_rq[0x5]; 1706 u8 reserved_at_368[0x3]; 1707 u8 log_max_sq[0x5]; 1708 u8 reserved_at_370[0x3]; 1709 u8 log_max_tir[0x5]; 1710 u8 reserved_at_378[0x3]; 1711 u8 log_max_tis[0x5]; 1712 1713 u8 basic_cyclic_rcv_wqe[0x1]; 1714 u8 reserved_at_381[0x2]; 1715 u8 log_max_rmp[0x5]; 1716 u8 reserved_at_388[0x3]; 1717 u8 log_max_rqt[0x5]; 1718 u8 reserved_at_390[0x3]; 1719 u8 log_max_rqt_size[0x5]; 1720 u8 reserved_at_398[0x3]; 1721 u8 log_max_tis_per_sq[0x5]; 1722 1723 u8 ext_stride_num_range[0x1]; 1724 u8 roce_rw_supported[0x1]; 1725 u8 log_max_current_uc_list_wr_supported[0x1]; 1726 u8 log_max_stride_sz_rq[0x5]; 1727 u8 reserved_at_3a8[0x3]; 1728 u8 log_min_stride_sz_rq[0x5]; 1729 u8 reserved_at_3b0[0x3]; 1730 u8 log_max_stride_sz_sq[0x5]; 1731 u8 reserved_at_3b8[0x3]; 1732 u8 log_min_stride_sz_sq[0x5]; 1733 1734 u8 hairpin[0x1]; 1735 u8 reserved_at_3c1[0x2]; 1736 u8 log_max_hairpin_queues[0x5]; 1737 u8 reserved_at_3c8[0x3]; 1738 u8 log_max_hairpin_wq_data_sz[0x5]; 1739 u8 reserved_at_3d0[0x3]; 1740 u8 log_max_hairpin_num_packets[0x5]; 1741 u8 reserved_at_3d8[0x3]; 1742 u8 log_max_wq_sz[0x5]; 1743 1744 u8 nic_vport_change_event[0x1]; 1745 u8 disable_local_lb_uc[0x1]; 1746 u8 disable_local_lb_mc[0x1]; 1747 u8 log_min_hairpin_wq_data_sz[0x5]; 1748 u8 reserved_at_3e8[0x2]; 1749 u8 vhca_state[0x1]; 1750 u8 log_max_vlan_list[0x5]; 1751 u8 reserved_at_3f0[0x3]; 1752 u8 log_max_current_mc_list[0x5]; 1753 u8 reserved_at_3f8[0x3]; 1754 u8 log_max_current_uc_list[0x5]; 1755 1756 u8 general_obj_types[0x40]; 1757 1758 u8 sq_ts_format[0x2]; 1759 u8 rq_ts_format[0x2]; 1760 u8 steering_format_version[0x4]; 1761 u8 create_qp_start_hint[0x18]; 1762 1763 u8 reserved_at_460[0x1]; 1764 u8 ats[0x1]; 1765 u8 reserved_at_462[0x1]; 1766 u8 log_max_uctx[0x5]; 1767 u8 reserved_at_468[0x2]; 1768 u8 ipsec_offload[0x1]; 1769 u8 log_max_umem[0x5]; 1770 u8 max_num_eqs[0x10]; 1771 1772 u8 reserved_at_480[0x1]; 1773 u8 tls_tx[0x1]; 1774 u8 tls_rx[0x1]; 1775 u8 log_max_l2_table[0x5]; 1776 u8 reserved_at_488[0x8]; 1777 u8 log_uar_page_sz[0x10]; 1778 1779 u8 reserved_at_4a0[0x20]; 1780 u8 device_frequency_mhz[0x20]; 1781 u8 device_frequency_khz[0x20]; 1782 1783 u8 reserved_at_500[0x20]; 1784 u8 num_of_uars_per_page[0x20]; 1785 1786 u8 flex_parser_protocols[0x20]; 1787 1788 u8 max_geneve_tlv_options[0x8]; 1789 u8 reserved_at_568[0x3]; 1790 u8 max_geneve_tlv_option_data_len[0x5]; 1791 u8 reserved_at_570[0x9]; 1792 u8 adv_virtualization[0x1]; 1793 u8 reserved_at_57a[0x6]; 1794 1795 u8 reserved_at_580[0xb]; 1796 u8 log_max_dci_stream_channels[0x5]; 1797 u8 reserved_at_590[0x3]; 1798 u8 log_max_dci_errored_streams[0x5]; 1799 u8 reserved_at_598[0x8]; 1800 1801 u8 reserved_at_5a0[0x10]; 1802 u8 enhanced_cqe_compression[0x1]; 1803 u8 reserved_at_5b1[0x2]; 1804 u8 log_max_dek[0x5]; 1805 u8 reserved_at_5b8[0x4]; 1806 u8 mini_cqe_resp_stride_index[0x1]; 1807 u8 cqe_128_always[0x1]; 1808 u8 cqe_compression_128[0x1]; 1809 u8 cqe_compression[0x1]; 1810 1811 u8 cqe_compression_timeout[0x10]; 1812 u8 cqe_compression_max_num[0x10]; 1813 1814 u8 reserved_at_5e0[0x8]; 1815 u8 flex_parser_id_gtpu_dw_0[0x4]; 1816 u8 reserved_at_5ec[0x4]; 1817 u8 tag_matching[0x1]; 1818 u8 rndv_offload_rc[0x1]; 1819 u8 rndv_offload_dc[0x1]; 1820 u8 log_tag_matching_list_sz[0x5]; 1821 u8 reserved_at_5f8[0x3]; 1822 u8 log_max_xrq[0x5]; 1823 1824 u8 affiliate_nic_vport_criteria[0x8]; 1825 u8 native_port_num[0x8]; 1826 u8 num_vhca_ports[0x8]; 1827 u8 flex_parser_id_gtpu_teid[0x4]; 1828 u8 reserved_at_61c[0x2]; 1829 u8 sw_owner_id[0x1]; 1830 u8 reserved_at_61f[0x1]; 1831 1832 u8 max_num_of_monitor_counters[0x10]; 1833 u8 num_ppcnt_monitor_counters[0x10]; 1834 1835 u8 max_num_sf[0x10]; 1836 u8 num_q_monitor_counters[0x10]; 1837 1838 u8 reserved_at_660[0x20]; 1839 1840 u8 sf[0x1]; 1841 u8 sf_set_partition[0x1]; 1842 u8 reserved_at_682[0x1]; 1843 u8 log_max_sf[0x5]; 1844 u8 apu[0x1]; 1845 u8 reserved_at_689[0x4]; 1846 u8 migration[0x1]; 1847 u8 reserved_at_68e[0x2]; 1848 u8 log_min_sf_size[0x8]; 1849 u8 max_num_sf_partitions[0x8]; 1850 1851 u8 uctx_cap[0x20]; 1852 1853 u8 reserved_at_6c0[0x4]; 1854 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1855 u8 flex_parser_id_icmp_dw1[0x4]; 1856 u8 flex_parser_id_icmp_dw0[0x4]; 1857 u8 flex_parser_id_icmpv6_dw1[0x4]; 1858 u8 flex_parser_id_icmpv6_dw0[0x4]; 1859 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1860 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1861 1862 u8 max_num_match_definer[0x10]; 1863 u8 sf_base_id[0x10]; 1864 1865 u8 flex_parser_id_gtpu_dw_2[0x4]; 1866 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1867 u8 num_total_dynamic_vf_msix[0x18]; 1868 u8 reserved_at_720[0x14]; 1869 u8 dynamic_msix_table_size[0xc]; 1870 u8 reserved_at_740[0xc]; 1871 u8 min_dynamic_vf_msix_table_size[0x4]; 1872 u8 reserved_at_750[0x4]; 1873 u8 max_dynamic_vf_msix_table_size[0xc]; 1874 1875 u8 reserved_at_760[0x20]; 1876 u8 vhca_tunnel_commands[0x40]; 1877 u8 match_definer_format_supported[0x40]; 1878 }; 1879 1880 struct mlx5_ifc_cmd_hca_cap_2_bits { 1881 u8 reserved_at_0[0xa0]; 1882 1883 u8 max_reformat_insert_size[0x8]; 1884 u8 max_reformat_insert_offset[0x8]; 1885 u8 max_reformat_remove_size[0x8]; 1886 u8 max_reformat_remove_offset[0x8]; 1887 1888 u8 reserved_at_c0[0xe0]; 1889 1890 u8 reserved_at_1a0[0xb]; 1891 u8 log_min_mkey_entity_size[0x5]; 1892 u8 reserved_at_1b0[0x10]; 1893 1894 u8 reserved_at_1c0[0x60]; 1895 1896 u8 reserved_at_220[0x1]; 1897 u8 sw_vhca_id_valid[0x1]; 1898 u8 sw_vhca_id[0xe]; 1899 u8 reserved_at_230[0x10]; 1900 1901 u8 reserved_at_240[0xb]; 1902 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1903 u8 reserved_at_250[0x10]; 1904 1905 u8 reserved_at_260[0x5a0]; 1906 }; 1907 1908 enum mlx5_ifc_flow_destination_type { 1909 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1910 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1911 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1912 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1913 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1914 }; 1915 1916 enum mlx5_flow_table_miss_action { 1917 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1918 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1919 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1920 }; 1921 1922 struct mlx5_ifc_dest_format_struct_bits { 1923 u8 destination_type[0x8]; 1924 u8 destination_id[0x18]; 1925 1926 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1927 u8 packet_reformat[0x1]; 1928 u8 reserved_at_22[0xe]; 1929 u8 destination_eswitch_owner_vhca_id[0x10]; 1930 }; 1931 1932 struct mlx5_ifc_flow_counter_list_bits { 1933 u8 flow_counter_id[0x20]; 1934 1935 u8 reserved_at_20[0x20]; 1936 }; 1937 1938 struct mlx5_ifc_extended_dest_format_bits { 1939 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1940 1941 u8 packet_reformat_id[0x20]; 1942 1943 u8 reserved_at_60[0x20]; 1944 }; 1945 1946 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1947 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1948 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1949 }; 1950 1951 struct mlx5_ifc_fte_match_param_bits { 1952 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1953 1954 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1955 1956 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1957 1958 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1959 1960 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1961 1962 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1963 1964 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1965 1966 u8 reserved_at_e00[0x200]; 1967 }; 1968 1969 enum { 1970 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1971 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1972 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1973 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1974 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1975 }; 1976 1977 struct mlx5_ifc_rx_hash_field_select_bits { 1978 u8 l3_prot_type[0x1]; 1979 u8 l4_prot_type[0x1]; 1980 u8 selected_fields[0x1e]; 1981 }; 1982 1983 enum { 1984 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1985 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1986 }; 1987 1988 enum { 1989 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1990 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1991 }; 1992 1993 struct mlx5_ifc_wq_bits { 1994 u8 wq_type[0x4]; 1995 u8 wq_signature[0x1]; 1996 u8 end_padding_mode[0x2]; 1997 u8 cd_slave[0x1]; 1998 u8 reserved_at_8[0x18]; 1999 2000 u8 hds_skip_first_sge[0x1]; 2001 u8 log2_hds_buf_size[0x3]; 2002 u8 reserved_at_24[0x7]; 2003 u8 page_offset[0x5]; 2004 u8 lwm[0x10]; 2005 2006 u8 reserved_at_40[0x8]; 2007 u8 pd[0x18]; 2008 2009 u8 reserved_at_60[0x8]; 2010 u8 uar_page[0x18]; 2011 2012 u8 dbr_addr[0x40]; 2013 2014 u8 hw_counter[0x20]; 2015 2016 u8 sw_counter[0x20]; 2017 2018 u8 reserved_at_100[0xc]; 2019 u8 log_wq_stride[0x4]; 2020 u8 reserved_at_110[0x3]; 2021 u8 log_wq_pg_sz[0x5]; 2022 u8 reserved_at_118[0x3]; 2023 u8 log_wq_sz[0x5]; 2024 2025 u8 dbr_umem_valid[0x1]; 2026 u8 wq_umem_valid[0x1]; 2027 u8 reserved_at_122[0x1]; 2028 u8 log_hairpin_num_packets[0x5]; 2029 u8 reserved_at_128[0x3]; 2030 u8 log_hairpin_data_sz[0x5]; 2031 2032 u8 reserved_at_130[0x4]; 2033 u8 log_wqe_num_of_strides[0x4]; 2034 u8 two_byte_shift_en[0x1]; 2035 u8 reserved_at_139[0x4]; 2036 u8 log_wqe_stride_size[0x3]; 2037 2038 u8 reserved_at_140[0x80]; 2039 2040 u8 headers_mkey[0x20]; 2041 2042 u8 shampo_enable[0x1]; 2043 u8 reserved_at_1e1[0x4]; 2044 u8 log_reservation_size[0x3]; 2045 u8 reserved_at_1e8[0x5]; 2046 u8 log_max_num_of_packets_per_reservation[0x3]; 2047 u8 reserved_at_1f0[0x6]; 2048 u8 log_headers_entry_size[0x2]; 2049 u8 reserved_at_1f8[0x4]; 2050 u8 log_headers_buffer_entry_num[0x4]; 2051 2052 u8 reserved_at_200[0x400]; 2053 2054 struct mlx5_ifc_cmd_pas_bits pas[]; 2055 }; 2056 2057 struct mlx5_ifc_rq_num_bits { 2058 u8 reserved_at_0[0x8]; 2059 u8 rq_num[0x18]; 2060 }; 2061 2062 struct mlx5_ifc_mac_address_layout_bits { 2063 u8 reserved_at_0[0x10]; 2064 u8 mac_addr_47_32[0x10]; 2065 2066 u8 mac_addr_31_0[0x20]; 2067 }; 2068 2069 struct mlx5_ifc_vlan_layout_bits { 2070 u8 reserved_at_0[0x14]; 2071 u8 vlan[0x0c]; 2072 2073 u8 reserved_at_20[0x20]; 2074 }; 2075 2076 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2077 u8 reserved_at_0[0xa0]; 2078 2079 u8 min_time_between_cnps[0x20]; 2080 2081 u8 reserved_at_c0[0x12]; 2082 u8 cnp_dscp[0x6]; 2083 u8 reserved_at_d8[0x4]; 2084 u8 cnp_prio_mode[0x1]; 2085 u8 cnp_802p_prio[0x3]; 2086 2087 u8 reserved_at_e0[0x720]; 2088 }; 2089 2090 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2091 u8 reserved_at_0[0x60]; 2092 2093 u8 reserved_at_60[0x4]; 2094 u8 clamp_tgt_rate[0x1]; 2095 u8 reserved_at_65[0x3]; 2096 u8 clamp_tgt_rate_after_time_inc[0x1]; 2097 u8 reserved_at_69[0x17]; 2098 2099 u8 reserved_at_80[0x20]; 2100 2101 u8 rpg_time_reset[0x20]; 2102 2103 u8 rpg_byte_reset[0x20]; 2104 2105 u8 rpg_threshold[0x20]; 2106 2107 u8 rpg_max_rate[0x20]; 2108 2109 u8 rpg_ai_rate[0x20]; 2110 2111 u8 rpg_hai_rate[0x20]; 2112 2113 u8 rpg_gd[0x20]; 2114 2115 u8 rpg_min_dec_fac[0x20]; 2116 2117 u8 rpg_min_rate[0x20]; 2118 2119 u8 reserved_at_1c0[0xe0]; 2120 2121 u8 rate_to_set_on_first_cnp[0x20]; 2122 2123 u8 dce_tcp_g[0x20]; 2124 2125 u8 dce_tcp_rtt[0x20]; 2126 2127 u8 rate_reduce_monitor_period[0x20]; 2128 2129 u8 reserved_at_320[0x20]; 2130 2131 u8 initial_alpha_value[0x20]; 2132 2133 u8 reserved_at_360[0x4a0]; 2134 }; 2135 2136 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2137 u8 reserved_at_0[0x80]; 2138 2139 u8 rppp_max_rps[0x20]; 2140 2141 u8 rpg_time_reset[0x20]; 2142 2143 u8 rpg_byte_reset[0x20]; 2144 2145 u8 rpg_threshold[0x20]; 2146 2147 u8 rpg_max_rate[0x20]; 2148 2149 u8 rpg_ai_rate[0x20]; 2150 2151 u8 rpg_hai_rate[0x20]; 2152 2153 u8 rpg_gd[0x20]; 2154 2155 u8 rpg_min_dec_fac[0x20]; 2156 2157 u8 rpg_min_rate[0x20]; 2158 2159 u8 reserved_at_1c0[0x640]; 2160 }; 2161 2162 enum { 2163 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2164 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2165 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2166 }; 2167 2168 struct mlx5_ifc_resize_field_select_bits { 2169 u8 resize_field_select[0x20]; 2170 }; 2171 2172 struct mlx5_ifc_resource_dump_bits { 2173 u8 more_dump[0x1]; 2174 u8 inline_dump[0x1]; 2175 u8 reserved_at_2[0xa]; 2176 u8 seq_num[0x4]; 2177 u8 segment_type[0x10]; 2178 2179 u8 reserved_at_20[0x10]; 2180 u8 vhca_id[0x10]; 2181 2182 u8 index1[0x20]; 2183 2184 u8 index2[0x20]; 2185 2186 u8 num_of_obj1[0x10]; 2187 u8 num_of_obj2[0x10]; 2188 2189 u8 reserved_at_a0[0x20]; 2190 2191 u8 device_opaque[0x40]; 2192 2193 u8 mkey[0x20]; 2194 2195 u8 size[0x20]; 2196 2197 u8 address[0x40]; 2198 2199 u8 inline_data[52][0x20]; 2200 }; 2201 2202 struct mlx5_ifc_resource_dump_menu_record_bits { 2203 u8 reserved_at_0[0x4]; 2204 u8 num_of_obj2_supports_active[0x1]; 2205 u8 num_of_obj2_supports_all[0x1]; 2206 u8 must_have_num_of_obj2[0x1]; 2207 u8 support_num_of_obj2[0x1]; 2208 u8 num_of_obj1_supports_active[0x1]; 2209 u8 num_of_obj1_supports_all[0x1]; 2210 u8 must_have_num_of_obj1[0x1]; 2211 u8 support_num_of_obj1[0x1]; 2212 u8 must_have_index2[0x1]; 2213 u8 support_index2[0x1]; 2214 u8 must_have_index1[0x1]; 2215 u8 support_index1[0x1]; 2216 u8 segment_type[0x10]; 2217 2218 u8 segment_name[4][0x20]; 2219 2220 u8 index1_name[4][0x20]; 2221 2222 u8 index2_name[4][0x20]; 2223 }; 2224 2225 struct mlx5_ifc_resource_dump_segment_header_bits { 2226 u8 length_dw[0x10]; 2227 u8 segment_type[0x10]; 2228 }; 2229 2230 struct mlx5_ifc_resource_dump_command_segment_bits { 2231 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2232 2233 u8 segment_called[0x10]; 2234 u8 vhca_id[0x10]; 2235 2236 u8 index1[0x20]; 2237 2238 u8 index2[0x20]; 2239 2240 u8 num_of_obj1[0x10]; 2241 u8 num_of_obj2[0x10]; 2242 }; 2243 2244 struct mlx5_ifc_resource_dump_error_segment_bits { 2245 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2246 2247 u8 reserved_at_20[0x10]; 2248 u8 syndrome_id[0x10]; 2249 2250 u8 reserved_at_40[0x40]; 2251 2252 u8 error[8][0x20]; 2253 }; 2254 2255 struct mlx5_ifc_resource_dump_info_segment_bits { 2256 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2257 2258 u8 reserved_at_20[0x18]; 2259 u8 dump_version[0x8]; 2260 2261 u8 hw_version[0x20]; 2262 2263 u8 fw_version[0x20]; 2264 }; 2265 2266 struct mlx5_ifc_resource_dump_menu_segment_bits { 2267 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2268 2269 u8 reserved_at_20[0x10]; 2270 u8 num_of_records[0x10]; 2271 2272 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2273 }; 2274 2275 struct mlx5_ifc_resource_dump_resource_segment_bits { 2276 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2277 2278 u8 reserved_at_20[0x20]; 2279 2280 u8 index1[0x20]; 2281 2282 u8 index2[0x20]; 2283 2284 u8 payload[][0x20]; 2285 }; 2286 2287 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2288 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2289 }; 2290 2291 struct mlx5_ifc_menu_resource_dump_response_bits { 2292 struct mlx5_ifc_resource_dump_info_segment_bits info; 2293 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2294 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2295 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2296 }; 2297 2298 enum { 2299 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2300 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2301 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2302 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2303 }; 2304 2305 struct mlx5_ifc_modify_field_select_bits { 2306 u8 modify_field_select[0x20]; 2307 }; 2308 2309 struct mlx5_ifc_field_select_r_roce_np_bits { 2310 u8 field_select_r_roce_np[0x20]; 2311 }; 2312 2313 struct mlx5_ifc_field_select_r_roce_rp_bits { 2314 u8 field_select_r_roce_rp[0x20]; 2315 }; 2316 2317 enum { 2318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2323 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2324 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2325 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2326 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2327 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2328 }; 2329 2330 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2331 u8 field_select_8021qaurp[0x20]; 2332 }; 2333 2334 struct mlx5_ifc_phys_layer_cntrs_bits { 2335 u8 time_since_last_clear_high[0x20]; 2336 2337 u8 time_since_last_clear_low[0x20]; 2338 2339 u8 symbol_errors_high[0x20]; 2340 2341 u8 symbol_errors_low[0x20]; 2342 2343 u8 sync_headers_errors_high[0x20]; 2344 2345 u8 sync_headers_errors_low[0x20]; 2346 2347 u8 edpl_bip_errors_lane0_high[0x20]; 2348 2349 u8 edpl_bip_errors_lane0_low[0x20]; 2350 2351 u8 edpl_bip_errors_lane1_high[0x20]; 2352 2353 u8 edpl_bip_errors_lane1_low[0x20]; 2354 2355 u8 edpl_bip_errors_lane2_high[0x20]; 2356 2357 u8 edpl_bip_errors_lane2_low[0x20]; 2358 2359 u8 edpl_bip_errors_lane3_high[0x20]; 2360 2361 u8 edpl_bip_errors_lane3_low[0x20]; 2362 2363 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2364 2365 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2366 2367 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2368 2369 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2370 2371 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2372 2373 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2374 2375 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2376 2377 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2378 2379 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2380 2381 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2382 2383 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2384 2385 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2386 2387 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2388 2389 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2390 2391 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2392 2393 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2394 2395 u8 rs_fec_corrected_blocks_high[0x20]; 2396 2397 u8 rs_fec_corrected_blocks_low[0x20]; 2398 2399 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2400 2401 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2402 2403 u8 rs_fec_no_errors_blocks_high[0x20]; 2404 2405 u8 rs_fec_no_errors_blocks_low[0x20]; 2406 2407 u8 rs_fec_single_error_blocks_high[0x20]; 2408 2409 u8 rs_fec_single_error_blocks_low[0x20]; 2410 2411 u8 rs_fec_corrected_symbols_total_high[0x20]; 2412 2413 u8 rs_fec_corrected_symbols_total_low[0x20]; 2414 2415 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2416 2417 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2418 2419 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2420 2421 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2422 2423 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2424 2425 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2426 2427 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2428 2429 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2430 2431 u8 link_down_events[0x20]; 2432 2433 u8 successful_recovery_events[0x20]; 2434 2435 u8 reserved_at_640[0x180]; 2436 }; 2437 2438 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2439 u8 time_since_last_clear_high[0x20]; 2440 2441 u8 time_since_last_clear_low[0x20]; 2442 2443 u8 phy_received_bits_high[0x20]; 2444 2445 u8 phy_received_bits_low[0x20]; 2446 2447 u8 phy_symbol_errors_high[0x20]; 2448 2449 u8 phy_symbol_errors_low[0x20]; 2450 2451 u8 phy_corrected_bits_high[0x20]; 2452 2453 u8 phy_corrected_bits_low[0x20]; 2454 2455 u8 phy_corrected_bits_lane0_high[0x20]; 2456 2457 u8 phy_corrected_bits_lane0_low[0x20]; 2458 2459 u8 phy_corrected_bits_lane1_high[0x20]; 2460 2461 u8 phy_corrected_bits_lane1_low[0x20]; 2462 2463 u8 phy_corrected_bits_lane2_high[0x20]; 2464 2465 u8 phy_corrected_bits_lane2_low[0x20]; 2466 2467 u8 phy_corrected_bits_lane3_high[0x20]; 2468 2469 u8 phy_corrected_bits_lane3_low[0x20]; 2470 2471 u8 reserved_at_200[0x5c0]; 2472 }; 2473 2474 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2475 u8 symbol_error_counter[0x10]; 2476 2477 u8 link_error_recovery_counter[0x8]; 2478 2479 u8 link_downed_counter[0x8]; 2480 2481 u8 port_rcv_errors[0x10]; 2482 2483 u8 port_rcv_remote_physical_errors[0x10]; 2484 2485 u8 port_rcv_switch_relay_errors[0x10]; 2486 2487 u8 port_xmit_discards[0x10]; 2488 2489 u8 port_xmit_constraint_errors[0x8]; 2490 2491 u8 port_rcv_constraint_errors[0x8]; 2492 2493 u8 reserved_at_70[0x8]; 2494 2495 u8 link_overrun_errors[0x8]; 2496 2497 u8 reserved_at_80[0x10]; 2498 2499 u8 vl_15_dropped[0x10]; 2500 2501 u8 reserved_at_a0[0x80]; 2502 2503 u8 port_xmit_wait[0x20]; 2504 }; 2505 2506 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2507 u8 transmit_queue_high[0x20]; 2508 2509 u8 transmit_queue_low[0x20]; 2510 2511 u8 no_buffer_discard_uc_high[0x20]; 2512 2513 u8 no_buffer_discard_uc_low[0x20]; 2514 2515 u8 reserved_at_80[0x740]; 2516 }; 2517 2518 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2519 u8 wred_discard_high[0x20]; 2520 2521 u8 wred_discard_low[0x20]; 2522 2523 u8 ecn_marked_tc_high[0x20]; 2524 2525 u8 ecn_marked_tc_low[0x20]; 2526 2527 u8 reserved_at_80[0x740]; 2528 }; 2529 2530 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2531 u8 rx_octets_high[0x20]; 2532 2533 u8 rx_octets_low[0x20]; 2534 2535 u8 reserved_at_40[0xc0]; 2536 2537 u8 rx_frames_high[0x20]; 2538 2539 u8 rx_frames_low[0x20]; 2540 2541 u8 tx_octets_high[0x20]; 2542 2543 u8 tx_octets_low[0x20]; 2544 2545 u8 reserved_at_180[0xc0]; 2546 2547 u8 tx_frames_high[0x20]; 2548 2549 u8 tx_frames_low[0x20]; 2550 2551 u8 rx_pause_high[0x20]; 2552 2553 u8 rx_pause_low[0x20]; 2554 2555 u8 rx_pause_duration_high[0x20]; 2556 2557 u8 rx_pause_duration_low[0x20]; 2558 2559 u8 tx_pause_high[0x20]; 2560 2561 u8 tx_pause_low[0x20]; 2562 2563 u8 tx_pause_duration_high[0x20]; 2564 2565 u8 tx_pause_duration_low[0x20]; 2566 2567 u8 rx_pause_transition_high[0x20]; 2568 2569 u8 rx_pause_transition_low[0x20]; 2570 2571 u8 rx_discards_high[0x20]; 2572 2573 u8 rx_discards_low[0x20]; 2574 2575 u8 device_stall_minor_watermark_cnt_high[0x20]; 2576 2577 u8 device_stall_minor_watermark_cnt_low[0x20]; 2578 2579 u8 device_stall_critical_watermark_cnt_high[0x20]; 2580 2581 u8 device_stall_critical_watermark_cnt_low[0x20]; 2582 2583 u8 reserved_at_480[0x340]; 2584 }; 2585 2586 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2587 u8 port_transmit_wait_high[0x20]; 2588 2589 u8 port_transmit_wait_low[0x20]; 2590 2591 u8 reserved_at_40[0x100]; 2592 2593 u8 rx_buffer_almost_full_high[0x20]; 2594 2595 u8 rx_buffer_almost_full_low[0x20]; 2596 2597 u8 rx_buffer_full_high[0x20]; 2598 2599 u8 rx_buffer_full_low[0x20]; 2600 2601 u8 rx_icrc_encapsulated_high[0x20]; 2602 2603 u8 rx_icrc_encapsulated_low[0x20]; 2604 2605 u8 reserved_at_200[0x5c0]; 2606 }; 2607 2608 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2609 u8 dot3stats_alignment_errors_high[0x20]; 2610 2611 u8 dot3stats_alignment_errors_low[0x20]; 2612 2613 u8 dot3stats_fcs_errors_high[0x20]; 2614 2615 u8 dot3stats_fcs_errors_low[0x20]; 2616 2617 u8 dot3stats_single_collision_frames_high[0x20]; 2618 2619 u8 dot3stats_single_collision_frames_low[0x20]; 2620 2621 u8 dot3stats_multiple_collision_frames_high[0x20]; 2622 2623 u8 dot3stats_multiple_collision_frames_low[0x20]; 2624 2625 u8 dot3stats_sqe_test_errors_high[0x20]; 2626 2627 u8 dot3stats_sqe_test_errors_low[0x20]; 2628 2629 u8 dot3stats_deferred_transmissions_high[0x20]; 2630 2631 u8 dot3stats_deferred_transmissions_low[0x20]; 2632 2633 u8 dot3stats_late_collisions_high[0x20]; 2634 2635 u8 dot3stats_late_collisions_low[0x20]; 2636 2637 u8 dot3stats_excessive_collisions_high[0x20]; 2638 2639 u8 dot3stats_excessive_collisions_low[0x20]; 2640 2641 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2642 2643 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2644 2645 u8 dot3stats_carrier_sense_errors_high[0x20]; 2646 2647 u8 dot3stats_carrier_sense_errors_low[0x20]; 2648 2649 u8 dot3stats_frame_too_longs_high[0x20]; 2650 2651 u8 dot3stats_frame_too_longs_low[0x20]; 2652 2653 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2654 2655 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2656 2657 u8 dot3stats_symbol_errors_high[0x20]; 2658 2659 u8 dot3stats_symbol_errors_low[0x20]; 2660 2661 u8 dot3control_in_unknown_opcodes_high[0x20]; 2662 2663 u8 dot3control_in_unknown_opcodes_low[0x20]; 2664 2665 u8 dot3in_pause_frames_high[0x20]; 2666 2667 u8 dot3in_pause_frames_low[0x20]; 2668 2669 u8 dot3out_pause_frames_high[0x20]; 2670 2671 u8 dot3out_pause_frames_low[0x20]; 2672 2673 u8 reserved_at_400[0x3c0]; 2674 }; 2675 2676 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2677 u8 ether_stats_drop_events_high[0x20]; 2678 2679 u8 ether_stats_drop_events_low[0x20]; 2680 2681 u8 ether_stats_octets_high[0x20]; 2682 2683 u8 ether_stats_octets_low[0x20]; 2684 2685 u8 ether_stats_pkts_high[0x20]; 2686 2687 u8 ether_stats_pkts_low[0x20]; 2688 2689 u8 ether_stats_broadcast_pkts_high[0x20]; 2690 2691 u8 ether_stats_broadcast_pkts_low[0x20]; 2692 2693 u8 ether_stats_multicast_pkts_high[0x20]; 2694 2695 u8 ether_stats_multicast_pkts_low[0x20]; 2696 2697 u8 ether_stats_crc_align_errors_high[0x20]; 2698 2699 u8 ether_stats_crc_align_errors_low[0x20]; 2700 2701 u8 ether_stats_undersize_pkts_high[0x20]; 2702 2703 u8 ether_stats_undersize_pkts_low[0x20]; 2704 2705 u8 ether_stats_oversize_pkts_high[0x20]; 2706 2707 u8 ether_stats_oversize_pkts_low[0x20]; 2708 2709 u8 ether_stats_fragments_high[0x20]; 2710 2711 u8 ether_stats_fragments_low[0x20]; 2712 2713 u8 ether_stats_jabbers_high[0x20]; 2714 2715 u8 ether_stats_jabbers_low[0x20]; 2716 2717 u8 ether_stats_collisions_high[0x20]; 2718 2719 u8 ether_stats_collisions_low[0x20]; 2720 2721 u8 ether_stats_pkts64octets_high[0x20]; 2722 2723 u8 ether_stats_pkts64octets_low[0x20]; 2724 2725 u8 ether_stats_pkts65to127octets_high[0x20]; 2726 2727 u8 ether_stats_pkts65to127octets_low[0x20]; 2728 2729 u8 ether_stats_pkts128to255octets_high[0x20]; 2730 2731 u8 ether_stats_pkts128to255octets_low[0x20]; 2732 2733 u8 ether_stats_pkts256to511octets_high[0x20]; 2734 2735 u8 ether_stats_pkts256to511octets_low[0x20]; 2736 2737 u8 ether_stats_pkts512to1023octets_high[0x20]; 2738 2739 u8 ether_stats_pkts512to1023octets_low[0x20]; 2740 2741 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2742 2743 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2744 2745 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2746 2747 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2748 2749 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2750 2751 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2752 2753 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2754 2755 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2756 2757 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2758 2759 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2760 2761 u8 reserved_at_540[0x280]; 2762 }; 2763 2764 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2765 u8 if_in_octets_high[0x20]; 2766 2767 u8 if_in_octets_low[0x20]; 2768 2769 u8 if_in_ucast_pkts_high[0x20]; 2770 2771 u8 if_in_ucast_pkts_low[0x20]; 2772 2773 u8 if_in_discards_high[0x20]; 2774 2775 u8 if_in_discards_low[0x20]; 2776 2777 u8 if_in_errors_high[0x20]; 2778 2779 u8 if_in_errors_low[0x20]; 2780 2781 u8 if_in_unknown_protos_high[0x20]; 2782 2783 u8 if_in_unknown_protos_low[0x20]; 2784 2785 u8 if_out_octets_high[0x20]; 2786 2787 u8 if_out_octets_low[0x20]; 2788 2789 u8 if_out_ucast_pkts_high[0x20]; 2790 2791 u8 if_out_ucast_pkts_low[0x20]; 2792 2793 u8 if_out_discards_high[0x20]; 2794 2795 u8 if_out_discards_low[0x20]; 2796 2797 u8 if_out_errors_high[0x20]; 2798 2799 u8 if_out_errors_low[0x20]; 2800 2801 u8 if_in_multicast_pkts_high[0x20]; 2802 2803 u8 if_in_multicast_pkts_low[0x20]; 2804 2805 u8 if_in_broadcast_pkts_high[0x20]; 2806 2807 u8 if_in_broadcast_pkts_low[0x20]; 2808 2809 u8 if_out_multicast_pkts_high[0x20]; 2810 2811 u8 if_out_multicast_pkts_low[0x20]; 2812 2813 u8 if_out_broadcast_pkts_high[0x20]; 2814 2815 u8 if_out_broadcast_pkts_low[0x20]; 2816 2817 u8 reserved_at_340[0x480]; 2818 }; 2819 2820 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2821 u8 a_frames_transmitted_ok_high[0x20]; 2822 2823 u8 a_frames_transmitted_ok_low[0x20]; 2824 2825 u8 a_frames_received_ok_high[0x20]; 2826 2827 u8 a_frames_received_ok_low[0x20]; 2828 2829 u8 a_frame_check_sequence_errors_high[0x20]; 2830 2831 u8 a_frame_check_sequence_errors_low[0x20]; 2832 2833 u8 a_alignment_errors_high[0x20]; 2834 2835 u8 a_alignment_errors_low[0x20]; 2836 2837 u8 a_octets_transmitted_ok_high[0x20]; 2838 2839 u8 a_octets_transmitted_ok_low[0x20]; 2840 2841 u8 a_octets_received_ok_high[0x20]; 2842 2843 u8 a_octets_received_ok_low[0x20]; 2844 2845 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2846 2847 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2848 2849 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2850 2851 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2852 2853 u8 a_multicast_frames_received_ok_high[0x20]; 2854 2855 u8 a_multicast_frames_received_ok_low[0x20]; 2856 2857 u8 a_broadcast_frames_received_ok_high[0x20]; 2858 2859 u8 a_broadcast_frames_received_ok_low[0x20]; 2860 2861 u8 a_in_range_length_errors_high[0x20]; 2862 2863 u8 a_in_range_length_errors_low[0x20]; 2864 2865 u8 a_out_of_range_length_field_high[0x20]; 2866 2867 u8 a_out_of_range_length_field_low[0x20]; 2868 2869 u8 a_frame_too_long_errors_high[0x20]; 2870 2871 u8 a_frame_too_long_errors_low[0x20]; 2872 2873 u8 a_symbol_error_during_carrier_high[0x20]; 2874 2875 u8 a_symbol_error_during_carrier_low[0x20]; 2876 2877 u8 a_mac_control_frames_transmitted_high[0x20]; 2878 2879 u8 a_mac_control_frames_transmitted_low[0x20]; 2880 2881 u8 a_mac_control_frames_received_high[0x20]; 2882 2883 u8 a_mac_control_frames_received_low[0x20]; 2884 2885 u8 a_unsupported_opcodes_received_high[0x20]; 2886 2887 u8 a_unsupported_opcodes_received_low[0x20]; 2888 2889 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2890 2891 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2892 2893 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2894 2895 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2896 2897 u8 reserved_at_4c0[0x300]; 2898 }; 2899 2900 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2901 u8 life_time_counter_high[0x20]; 2902 2903 u8 life_time_counter_low[0x20]; 2904 2905 u8 rx_errors[0x20]; 2906 2907 u8 tx_errors[0x20]; 2908 2909 u8 l0_to_recovery_eieos[0x20]; 2910 2911 u8 l0_to_recovery_ts[0x20]; 2912 2913 u8 l0_to_recovery_framing[0x20]; 2914 2915 u8 l0_to_recovery_retrain[0x20]; 2916 2917 u8 crc_error_dllp[0x20]; 2918 2919 u8 crc_error_tlp[0x20]; 2920 2921 u8 tx_overflow_buffer_pkt_high[0x20]; 2922 2923 u8 tx_overflow_buffer_pkt_low[0x20]; 2924 2925 u8 outbound_stalled_reads[0x20]; 2926 2927 u8 outbound_stalled_writes[0x20]; 2928 2929 u8 outbound_stalled_reads_events[0x20]; 2930 2931 u8 outbound_stalled_writes_events[0x20]; 2932 2933 u8 reserved_at_200[0x5c0]; 2934 }; 2935 2936 struct mlx5_ifc_cmd_inter_comp_event_bits { 2937 u8 command_completion_vector[0x20]; 2938 2939 u8 reserved_at_20[0xc0]; 2940 }; 2941 2942 struct mlx5_ifc_stall_vl_event_bits { 2943 u8 reserved_at_0[0x18]; 2944 u8 port_num[0x1]; 2945 u8 reserved_at_19[0x3]; 2946 u8 vl[0x4]; 2947 2948 u8 reserved_at_20[0xa0]; 2949 }; 2950 2951 struct mlx5_ifc_db_bf_congestion_event_bits { 2952 u8 event_subtype[0x8]; 2953 u8 reserved_at_8[0x8]; 2954 u8 congestion_level[0x8]; 2955 u8 reserved_at_18[0x8]; 2956 2957 u8 reserved_at_20[0xa0]; 2958 }; 2959 2960 struct mlx5_ifc_gpio_event_bits { 2961 u8 reserved_at_0[0x60]; 2962 2963 u8 gpio_event_hi[0x20]; 2964 2965 u8 gpio_event_lo[0x20]; 2966 2967 u8 reserved_at_a0[0x40]; 2968 }; 2969 2970 struct mlx5_ifc_port_state_change_event_bits { 2971 u8 reserved_at_0[0x40]; 2972 2973 u8 port_num[0x4]; 2974 u8 reserved_at_44[0x1c]; 2975 2976 u8 reserved_at_60[0x80]; 2977 }; 2978 2979 struct mlx5_ifc_dropped_packet_logged_bits { 2980 u8 reserved_at_0[0xe0]; 2981 }; 2982 2983 struct mlx5_ifc_default_timeout_bits { 2984 u8 to_multiplier[0x3]; 2985 u8 reserved_at_3[0x9]; 2986 u8 to_value[0x14]; 2987 }; 2988 2989 struct mlx5_ifc_dtor_reg_bits { 2990 u8 reserved_at_0[0x20]; 2991 2992 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2993 2994 u8 reserved_at_40[0x60]; 2995 2996 struct mlx5_ifc_default_timeout_bits health_poll_to; 2997 2998 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2999 3000 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3001 3002 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3003 3004 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3005 3006 struct mlx5_ifc_default_timeout_bits tear_down_to; 3007 3008 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3009 3010 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3011 3012 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3013 3014 u8 reserved_at_1c0[0x40]; 3015 }; 3016 3017 enum { 3018 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3019 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3020 }; 3021 3022 struct mlx5_ifc_cq_error_bits { 3023 u8 reserved_at_0[0x8]; 3024 u8 cqn[0x18]; 3025 3026 u8 reserved_at_20[0x20]; 3027 3028 u8 reserved_at_40[0x18]; 3029 u8 syndrome[0x8]; 3030 3031 u8 reserved_at_60[0x80]; 3032 }; 3033 3034 struct mlx5_ifc_rdma_page_fault_event_bits { 3035 u8 bytes_committed[0x20]; 3036 3037 u8 r_key[0x20]; 3038 3039 u8 reserved_at_40[0x10]; 3040 u8 packet_len[0x10]; 3041 3042 u8 rdma_op_len[0x20]; 3043 3044 u8 rdma_va[0x40]; 3045 3046 u8 reserved_at_c0[0x5]; 3047 u8 rdma[0x1]; 3048 u8 write[0x1]; 3049 u8 requestor[0x1]; 3050 u8 qp_number[0x18]; 3051 }; 3052 3053 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3054 u8 bytes_committed[0x20]; 3055 3056 u8 reserved_at_20[0x10]; 3057 u8 wqe_index[0x10]; 3058 3059 u8 reserved_at_40[0x10]; 3060 u8 len[0x10]; 3061 3062 u8 reserved_at_60[0x60]; 3063 3064 u8 reserved_at_c0[0x5]; 3065 u8 rdma[0x1]; 3066 u8 write_read[0x1]; 3067 u8 requestor[0x1]; 3068 u8 qpn[0x18]; 3069 }; 3070 3071 struct mlx5_ifc_qp_events_bits { 3072 u8 reserved_at_0[0xa0]; 3073 3074 u8 type[0x8]; 3075 u8 reserved_at_a8[0x18]; 3076 3077 u8 reserved_at_c0[0x8]; 3078 u8 qpn_rqn_sqn[0x18]; 3079 }; 3080 3081 struct mlx5_ifc_dct_events_bits { 3082 u8 reserved_at_0[0xc0]; 3083 3084 u8 reserved_at_c0[0x8]; 3085 u8 dct_number[0x18]; 3086 }; 3087 3088 struct mlx5_ifc_comp_event_bits { 3089 u8 reserved_at_0[0xc0]; 3090 3091 u8 reserved_at_c0[0x8]; 3092 u8 cq_number[0x18]; 3093 }; 3094 3095 enum { 3096 MLX5_QPC_STATE_RST = 0x0, 3097 MLX5_QPC_STATE_INIT = 0x1, 3098 MLX5_QPC_STATE_RTR = 0x2, 3099 MLX5_QPC_STATE_RTS = 0x3, 3100 MLX5_QPC_STATE_SQER = 0x4, 3101 MLX5_QPC_STATE_ERR = 0x6, 3102 MLX5_QPC_STATE_SQD = 0x7, 3103 MLX5_QPC_STATE_SUSPENDED = 0x9, 3104 }; 3105 3106 enum { 3107 MLX5_QPC_ST_RC = 0x0, 3108 MLX5_QPC_ST_UC = 0x1, 3109 MLX5_QPC_ST_UD = 0x2, 3110 MLX5_QPC_ST_XRC = 0x3, 3111 MLX5_QPC_ST_DCI = 0x5, 3112 MLX5_QPC_ST_QP0 = 0x7, 3113 MLX5_QPC_ST_QP1 = 0x8, 3114 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3115 MLX5_QPC_ST_REG_UMR = 0xc, 3116 }; 3117 3118 enum { 3119 MLX5_QPC_PM_STATE_ARMED = 0x0, 3120 MLX5_QPC_PM_STATE_REARM = 0x1, 3121 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3122 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3123 }; 3124 3125 enum { 3126 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3127 }; 3128 3129 enum { 3130 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3131 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3132 }; 3133 3134 enum { 3135 MLX5_QPC_MTU_256_BYTES = 0x1, 3136 MLX5_QPC_MTU_512_BYTES = 0x2, 3137 MLX5_QPC_MTU_1K_BYTES = 0x3, 3138 MLX5_QPC_MTU_2K_BYTES = 0x4, 3139 MLX5_QPC_MTU_4K_BYTES = 0x5, 3140 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3141 }; 3142 3143 enum { 3144 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3145 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3146 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3147 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3148 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3149 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3150 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3151 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3152 }; 3153 3154 enum { 3155 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3156 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3157 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3158 }; 3159 3160 enum { 3161 MLX5_QPC_CS_RES_DISABLE = 0x0, 3162 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3163 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3164 }; 3165 3166 enum { 3167 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3168 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3169 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3170 }; 3171 3172 struct mlx5_ifc_qpc_bits { 3173 u8 state[0x4]; 3174 u8 lag_tx_port_affinity[0x4]; 3175 u8 st[0x8]; 3176 u8 reserved_at_10[0x2]; 3177 u8 isolate_vl_tc[0x1]; 3178 u8 pm_state[0x2]; 3179 u8 reserved_at_15[0x1]; 3180 u8 req_e2e_credit_mode[0x2]; 3181 u8 offload_type[0x4]; 3182 u8 end_padding_mode[0x2]; 3183 u8 reserved_at_1e[0x2]; 3184 3185 u8 wq_signature[0x1]; 3186 u8 block_lb_mc[0x1]; 3187 u8 atomic_like_write_en[0x1]; 3188 u8 latency_sensitive[0x1]; 3189 u8 reserved_at_24[0x1]; 3190 u8 drain_sigerr[0x1]; 3191 u8 reserved_at_26[0x2]; 3192 u8 pd[0x18]; 3193 3194 u8 mtu[0x3]; 3195 u8 log_msg_max[0x5]; 3196 u8 reserved_at_48[0x1]; 3197 u8 log_rq_size[0x4]; 3198 u8 log_rq_stride[0x3]; 3199 u8 no_sq[0x1]; 3200 u8 log_sq_size[0x4]; 3201 u8 reserved_at_55[0x3]; 3202 u8 ts_format[0x2]; 3203 u8 reserved_at_5a[0x1]; 3204 u8 rlky[0x1]; 3205 u8 ulp_stateless_offload_mode[0x4]; 3206 3207 u8 counter_set_id[0x8]; 3208 u8 uar_page[0x18]; 3209 3210 u8 reserved_at_80[0x8]; 3211 u8 user_index[0x18]; 3212 3213 u8 reserved_at_a0[0x3]; 3214 u8 log_page_size[0x5]; 3215 u8 remote_qpn[0x18]; 3216 3217 struct mlx5_ifc_ads_bits primary_address_path; 3218 3219 struct mlx5_ifc_ads_bits secondary_address_path; 3220 3221 u8 log_ack_req_freq[0x4]; 3222 u8 reserved_at_384[0x4]; 3223 u8 log_sra_max[0x3]; 3224 u8 reserved_at_38b[0x2]; 3225 u8 retry_count[0x3]; 3226 u8 rnr_retry[0x3]; 3227 u8 reserved_at_393[0x1]; 3228 u8 fre[0x1]; 3229 u8 cur_rnr_retry[0x3]; 3230 u8 cur_retry_count[0x3]; 3231 u8 reserved_at_39b[0x5]; 3232 3233 u8 reserved_at_3a0[0x20]; 3234 3235 u8 reserved_at_3c0[0x8]; 3236 u8 next_send_psn[0x18]; 3237 3238 u8 reserved_at_3e0[0x3]; 3239 u8 log_num_dci_stream_channels[0x5]; 3240 u8 cqn_snd[0x18]; 3241 3242 u8 reserved_at_400[0x3]; 3243 u8 log_num_dci_errored_streams[0x5]; 3244 u8 deth_sqpn[0x18]; 3245 3246 u8 reserved_at_420[0x20]; 3247 3248 u8 reserved_at_440[0x8]; 3249 u8 last_acked_psn[0x18]; 3250 3251 u8 reserved_at_460[0x8]; 3252 u8 ssn[0x18]; 3253 3254 u8 reserved_at_480[0x8]; 3255 u8 log_rra_max[0x3]; 3256 u8 reserved_at_48b[0x1]; 3257 u8 atomic_mode[0x4]; 3258 u8 rre[0x1]; 3259 u8 rwe[0x1]; 3260 u8 rae[0x1]; 3261 u8 reserved_at_493[0x1]; 3262 u8 page_offset[0x6]; 3263 u8 reserved_at_49a[0x3]; 3264 u8 cd_slave_receive[0x1]; 3265 u8 cd_slave_send[0x1]; 3266 u8 cd_master[0x1]; 3267 3268 u8 reserved_at_4a0[0x3]; 3269 u8 min_rnr_nak[0x5]; 3270 u8 next_rcv_psn[0x18]; 3271 3272 u8 reserved_at_4c0[0x8]; 3273 u8 xrcd[0x18]; 3274 3275 u8 reserved_at_4e0[0x8]; 3276 u8 cqn_rcv[0x18]; 3277 3278 u8 dbr_addr[0x40]; 3279 3280 u8 q_key[0x20]; 3281 3282 u8 reserved_at_560[0x5]; 3283 u8 rq_type[0x3]; 3284 u8 srqn_rmpn_xrqn[0x18]; 3285 3286 u8 reserved_at_580[0x8]; 3287 u8 rmsn[0x18]; 3288 3289 u8 hw_sq_wqebb_counter[0x10]; 3290 u8 sw_sq_wqebb_counter[0x10]; 3291 3292 u8 hw_rq_counter[0x20]; 3293 3294 u8 sw_rq_counter[0x20]; 3295 3296 u8 reserved_at_600[0x20]; 3297 3298 u8 reserved_at_620[0xf]; 3299 u8 cgs[0x1]; 3300 u8 cs_req[0x8]; 3301 u8 cs_res[0x8]; 3302 3303 u8 dc_access_key[0x40]; 3304 3305 u8 reserved_at_680[0x3]; 3306 u8 dbr_umem_valid[0x1]; 3307 3308 u8 reserved_at_684[0xbc]; 3309 }; 3310 3311 struct mlx5_ifc_roce_addr_layout_bits { 3312 u8 source_l3_address[16][0x8]; 3313 3314 u8 reserved_at_80[0x3]; 3315 u8 vlan_valid[0x1]; 3316 u8 vlan_id[0xc]; 3317 u8 source_mac_47_32[0x10]; 3318 3319 u8 source_mac_31_0[0x20]; 3320 3321 u8 reserved_at_c0[0x14]; 3322 u8 roce_l3_type[0x4]; 3323 u8 roce_version[0x8]; 3324 3325 u8 reserved_at_e0[0x20]; 3326 }; 3327 3328 struct mlx5_ifc_shampo_cap_bits { 3329 u8 reserved_at_0[0x3]; 3330 u8 shampo_log_max_reservation_size[0x5]; 3331 u8 reserved_at_8[0x3]; 3332 u8 shampo_log_min_reservation_size[0x5]; 3333 u8 shampo_min_mss_size[0x10]; 3334 3335 u8 reserved_at_20[0x3]; 3336 u8 shampo_max_log_headers_entry_size[0x5]; 3337 u8 reserved_at_28[0x18]; 3338 3339 u8 reserved_at_40[0x7c0]; 3340 }; 3341 3342 union mlx5_ifc_hca_cap_union_bits { 3343 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3344 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3345 struct mlx5_ifc_odp_cap_bits odp_cap; 3346 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3347 struct mlx5_ifc_roce_cap_bits roce_cap; 3348 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3349 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3350 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3351 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3352 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3353 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3354 struct mlx5_ifc_qos_cap_bits qos_cap; 3355 struct mlx5_ifc_debug_cap_bits debug_cap; 3356 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3357 struct mlx5_ifc_tls_cap_bits tls_cap; 3358 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3359 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3360 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3361 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3362 u8 reserved_at_0[0x8000]; 3363 }; 3364 3365 enum { 3366 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3367 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3368 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3369 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3370 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3371 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3372 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3373 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3374 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3375 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3376 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3377 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3378 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3379 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3380 }; 3381 3382 enum { 3383 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3384 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3385 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3386 }; 3387 3388 enum { 3389 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3390 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3391 }; 3392 3393 struct mlx5_ifc_vlan_bits { 3394 u8 ethtype[0x10]; 3395 u8 prio[0x3]; 3396 u8 cfi[0x1]; 3397 u8 vid[0xc]; 3398 }; 3399 3400 enum { 3401 MLX5_FLOW_METER_COLOR_RED = 0x0, 3402 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3403 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3404 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3405 }; 3406 3407 enum { 3408 MLX5_EXE_ASO_FLOW_METER = 0x2, 3409 }; 3410 3411 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3412 u8 return_reg_id[0x4]; 3413 u8 aso_type[0x4]; 3414 u8 reserved_at_8[0x14]; 3415 u8 action[0x1]; 3416 u8 init_color[0x2]; 3417 u8 meter_id[0x1]; 3418 }; 3419 3420 union mlx5_ifc_exe_aso_ctrl { 3421 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3422 }; 3423 3424 struct mlx5_ifc_execute_aso_bits { 3425 u8 valid[0x1]; 3426 u8 reserved_at_1[0x7]; 3427 u8 aso_object_id[0x18]; 3428 3429 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3430 }; 3431 3432 struct mlx5_ifc_flow_context_bits { 3433 struct mlx5_ifc_vlan_bits push_vlan; 3434 3435 u8 group_id[0x20]; 3436 3437 u8 reserved_at_40[0x8]; 3438 u8 flow_tag[0x18]; 3439 3440 u8 reserved_at_60[0x10]; 3441 u8 action[0x10]; 3442 3443 u8 extended_destination[0x1]; 3444 u8 reserved_at_81[0x1]; 3445 u8 flow_source[0x2]; 3446 u8 encrypt_decrypt_type[0x4]; 3447 u8 destination_list_size[0x18]; 3448 3449 u8 reserved_at_a0[0x8]; 3450 u8 flow_counter_list_size[0x18]; 3451 3452 u8 packet_reformat_id[0x20]; 3453 3454 u8 modify_header_id[0x20]; 3455 3456 struct mlx5_ifc_vlan_bits push_vlan_2; 3457 3458 u8 encrypt_decrypt_obj_id[0x20]; 3459 u8 reserved_at_140[0xc0]; 3460 3461 struct mlx5_ifc_fte_match_param_bits match_value; 3462 3463 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3464 3465 u8 reserved_at_1300[0x500]; 3466 3467 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3468 }; 3469 3470 enum { 3471 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3472 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3473 }; 3474 3475 struct mlx5_ifc_xrc_srqc_bits { 3476 u8 state[0x4]; 3477 u8 log_xrc_srq_size[0x4]; 3478 u8 reserved_at_8[0x18]; 3479 3480 u8 wq_signature[0x1]; 3481 u8 cont_srq[0x1]; 3482 u8 reserved_at_22[0x1]; 3483 u8 rlky[0x1]; 3484 u8 basic_cyclic_rcv_wqe[0x1]; 3485 u8 log_rq_stride[0x3]; 3486 u8 xrcd[0x18]; 3487 3488 u8 page_offset[0x6]; 3489 u8 reserved_at_46[0x1]; 3490 u8 dbr_umem_valid[0x1]; 3491 u8 cqn[0x18]; 3492 3493 u8 reserved_at_60[0x20]; 3494 3495 u8 user_index_equal_xrc_srqn[0x1]; 3496 u8 reserved_at_81[0x1]; 3497 u8 log_page_size[0x6]; 3498 u8 user_index[0x18]; 3499 3500 u8 reserved_at_a0[0x20]; 3501 3502 u8 reserved_at_c0[0x8]; 3503 u8 pd[0x18]; 3504 3505 u8 lwm[0x10]; 3506 u8 wqe_cnt[0x10]; 3507 3508 u8 reserved_at_100[0x40]; 3509 3510 u8 db_record_addr_h[0x20]; 3511 3512 u8 db_record_addr_l[0x1e]; 3513 u8 reserved_at_17e[0x2]; 3514 3515 u8 reserved_at_180[0x80]; 3516 }; 3517 3518 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3519 u8 counter_error_queues[0x20]; 3520 3521 u8 total_error_queues[0x20]; 3522 3523 u8 send_queue_priority_update_flow[0x20]; 3524 3525 u8 reserved_at_60[0x20]; 3526 3527 u8 nic_receive_steering_discard[0x40]; 3528 3529 u8 receive_discard_vport_down[0x40]; 3530 3531 u8 transmit_discard_vport_down[0x40]; 3532 3533 u8 async_eq_overrun[0x20]; 3534 3535 u8 comp_eq_overrun[0x20]; 3536 3537 u8 reserved_at_180[0x20]; 3538 3539 u8 invalid_command[0x20]; 3540 3541 u8 quota_exceeded_command[0x20]; 3542 3543 u8 internal_rq_out_of_buffer[0x20]; 3544 3545 u8 cq_overrun[0x20]; 3546 3547 u8 eth_wqe_too_small[0x20]; 3548 3549 u8 reserved_at_220[0xdc0]; 3550 }; 3551 3552 struct mlx5_ifc_traffic_counter_bits { 3553 u8 packets[0x40]; 3554 3555 u8 octets[0x40]; 3556 }; 3557 3558 struct mlx5_ifc_tisc_bits { 3559 u8 strict_lag_tx_port_affinity[0x1]; 3560 u8 tls_en[0x1]; 3561 u8 reserved_at_2[0x2]; 3562 u8 lag_tx_port_affinity[0x04]; 3563 3564 u8 reserved_at_8[0x4]; 3565 u8 prio[0x4]; 3566 u8 reserved_at_10[0x10]; 3567 3568 u8 reserved_at_20[0x100]; 3569 3570 u8 reserved_at_120[0x8]; 3571 u8 transport_domain[0x18]; 3572 3573 u8 reserved_at_140[0x8]; 3574 u8 underlay_qpn[0x18]; 3575 3576 u8 reserved_at_160[0x8]; 3577 u8 pd[0x18]; 3578 3579 u8 reserved_at_180[0x380]; 3580 }; 3581 3582 enum { 3583 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3584 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3585 }; 3586 3587 enum { 3588 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3589 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3590 }; 3591 3592 enum { 3593 MLX5_RX_HASH_FN_NONE = 0x0, 3594 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3595 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3596 }; 3597 3598 enum { 3599 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3600 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3601 }; 3602 3603 struct mlx5_ifc_tirc_bits { 3604 u8 reserved_at_0[0x20]; 3605 3606 u8 disp_type[0x4]; 3607 u8 tls_en[0x1]; 3608 u8 reserved_at_25[0x1b]; 3609 3610 u8 reserved_at_40[0x40]; 3611 3612 u8 reserved_at_80[0x4]; 3613 u8 lro_timeout_period_usecs[0x10]; 3614 u8 packet_merge_mask[0x4]; 3615 u8 lro_max_ip_payload_size[0x8]; 3616 3617 u8 reserved_at_a0[0x40]; 3618 3619 u8 reserved_at_e0[0x8]; 3620 u8 inline_rqn[0x18]; 3621 3622 u8 rx_hash_symmetric[0x1]; 3623 u8 reserved_at_101[0x1]; 3624 u8 tunneled_offload_en[0x1]; 3625 u8 reserved_at_103[0x5]; 3626 u8 indirect_table[0x18]; 3627 3628 u8 rx_hash_fn[0x4]; 3629 u8 reserved_at_124[0x2]; 3630 u8 self_lb_block[0x2]; 3631 u8 transport_domain[0x18]; 3632 3633 u8 rx_hash_toeplitz_key[10][0x20]; 3634 3635 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3636 3637 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3638 3639 u8 reserved_at_2c0[0x4c0]; 3640 }; 3641 3642 enum { 3643 MLX5_SRQC_STATE_GOOD = 0x0, 3644 MLX5_SRQC_STATE_ERROR = 0x1, 3645 }; 3646 3647 struct mlx5_ifc_srqc_bits { 3648 u8 state[0x4]; 3649 u8 log_srq_size[0x4]; 3650 u8 reserved_at_8[0x18]; 3651 3652 u8 wq_signature[0x1]; 3653 u8 cont_srq[0x1]; 3654 u8 reserved_at_22[0x1]; 3655 u8 rlky[0x1]; 3656 u8 reserved_at_24[0x1]; 3657 u8 log_rq_stride[0x3]; 3658 u8 xrcd[0x18]; 3659 3660 u8 page_offset[0x6]; 3661 u8 reserved_at_46[0x2]; 3662 u8 cqn[0x18]; 3663 3664 u8 reserved_at_60[0x20]; 3665 3666 u8 reserved_at_80[0x2]; 3667 u8 log_page_size[0x6]; 3668 u8 reserved_at_88[0x18]; 3669 3670 u8 reserved_at_a0[0x20]; 3671 3672 u8 reserved_at_c0[0x8]; 3673 u8 pd[0x18]; 3674 3675 u8 lwm[0x10]; 3676 u8 wqe_cnt[0x10]; 3677 3678 u8 reserved_at_100[0x40]; 3679 3680 u8 dbr_addr[0x40]; 3681 3682 u8 reserved_at_180[0x80]; 3683 }; 3684 3685 enum { 3686 MLX5_SQC_STATE_RST = 0x0, 3687 MLX5_SQC_STATE_RDY = 0x1, 3688 MLX5_SQC_STATE_ERR = 0x3, 3689 }; 3690 3691 struct mlx5_ifc_sqc_bits { 3692 u8 rlky[0x1]; 3693 u8 cd_master[0x1]; 3694 u8 fre[0x1]; 3695 u8 flush_in_error_en[0x1]; 3696 u8 allow_multi_pkt_send_wqe[0x1]; 3697 u8 min_wqe_inline_mode[0x3]; 3698 u8 state[0x4]; 3699 u8 reg_umr[0x1]; 3700 u8 allow_swp[0x1]; 3701 u8 hairpin[0x1]; 3702 u8 reserved_at_f[0xb]; 3703 u8 ts_format[0x2]; 3704 u8 reserved_at_1c[0x4]; 3705 3706 u8 reserved_at_20[0x8]; 3707 u8 user_index[0x18]; 3708 3709 u8 reserved_at_40[0x8]; 3710 u8 cqn[0x18]; 3711 3712 u8 reserved_at_60[0x8]; 3713 u8 hairpin_peer_rq[0x18]; 3714 3715 u8 reserved_at_80[0x10]; 3716 u8 hairpin_peer_vhca[0x10]; 3717 3718 u8 reserved_at_a0[0x20]; 3719 3720 u8 reserved_at_c0[0x8]; 3721 u8 ts_cqe_to_dest_cqn[0x18]; 3722 3723 u8 reserved_at_e0[0x10]; 3724 u8 packet_pacing_rate_limit_index[0x10]; 3725 u8 tis_lst_sz[0x10]; 3726 u8 qos_queue_group_id[0x10]; 3727 3728 u8 reserved_at_120[0x40]; 3729 3730 u8 reserved_at_160[0x8]; 3731 u8 tis_num_0[0x18]; 3732 3733 struct mlx5_ifc_wq_bits wq; 3734 }; 3735 3736 enum { 3737 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3738 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3739 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3740 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3741 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3742 }; 3743 3744 enum { 3745 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3746 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3747 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3748 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3749 }; 3750 3751 struct mlx5_ifc_scheduling_context_bits { 3752 u8 element_type[0x8]; 3753 u8 reserved_at_8[0x18]; 3754 3755 u8 element_attributes[0x20]; 3756 3757 u8 parent_element_id[0x20]; 3758 3759 u8 reserved_at_60[0x40]; 3760 3761 u8 bw_share[0x20]; 3762 3763 u8 max_average_bw[0x20]; 3764 3765 u8 reserved_at_e0[0x120]; 3766 }; 3767 3768 struct mlx5_ifc_rqtc_bits { 3769 u8 reserved_at_0[0xa0]; 3770 3771 u8 reserved_at_a0[0x5]; 3772 u8 list_q_type[0x3]; 3773 u8 reserved_at_a8[0x8]; 3774 u8 rqt_max_size[0x10]; 3775 3776 u8 rq_vhca_id_format[0x1]; 3777 u8 reserved_at_c1[0xf]; 3778 u8 rqt_actual_size[0x10]; 3779 3780 u8 reserved_at_e0[0x6a0]; 3781 3782 struct mlx5_ifc_rq_num_bits rq_num[]; 3783 }; 3784 3785 enum { 3786 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3787 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3788 }; 3789 3790 enum { 3791 MLX5_RQC_STATE_RST = 0x0, 3792 MLX5_RQC_STATE_RDY = 0x1, 3793 MLX5_RQC_STATE_ERR = 0x3, 3794 }; 3795 3796 enum { 3797 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3798 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3799 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3800 }; 3801 3802 enum { 3803 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3804 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3805 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3806 }; 3807 3808 struct mlx5_ifc_rqc_bits { 3809 u8 rlky[0x1]; 3810 u8 delay_drop_en[0x1]; 3811 u8 scatter_fcs[0x1]; 3812 u8 vsd[0x1]; 3813 u8 mem_rq_type[0x4]; 3814 u8 state[0x4]; 3815 u8 reserved_at_c[0x1]; 3816 u8 flush_in_error_en[0x1]; 3817 u8 hairpin[0x1]; 3818 u8 reserved_at_f[0xb]; 3819 u8 ts_format[0x2]; 3820 u8 reserved_at_1c[0x4]; 3821 3822 u8 reserved_at_20[0x8]; 3823 u8 user_index[0x18]; 3824 3825 u8 reserved_at_40[0x8]; 3826 u8 cqn[0x18]; 3827 3828 u8 counter_set_id[0x8]; 3829 u8 reserved_at_68[0x18]; 3830 3831 u8 reserved_at_80[0x8]; 3832 u8 rmpn[0x18]; 3833 3834 u8 reserved_at_a0[0x8]; 3835 u8 hairpin_peer_sq[0x18]; 3836 3837 u8 reserved_at_c0[0x10]; 3838 u8 hairpin_peer_vhca[0x10]; 3839 3840 u8 reserved_at_e0[0x46]; 3841 u8 shampo_no_match_alignment_granularity[0x2]; 3842 u8 reserved_at_128[0x6]; 3843 u8 shampo_match_criteria_type[0x2]; 3844 u8 reservation_timeout[0x10]; 3845 3846 u8 reserved_at_140[0x40]; 3847 3848 struct mlx5_ifc_wq_bits wq; 3849 }; 3850 3851 enum { 3852 MLX5_RMPC_STATE_RDY = 0x1, 3853 MLX5_RMPC_STATE_ERR = 0x3, 3854 }; 3855 3856 struct mlx5_ifc_rmpc_bits { 3857 u8 reserved_at_0[0x8]; 3858 u8 state[0x4]; 3859 u8 reserved_at_c[0x14]; 3860 3861 u8 basic_cyclic_rcv_wqe[0x1]; 3862 u8 reserved_at_21[0x1f]; 3863 3864 u8 reserved_at_40[0x140]; 3865 3866 struct mlx5_ifc_wq_bits wq; 3867 }; 3868 3869 enum { 3870 VHCA_ID_TYPE_HW = 0, 3871 VHCA_ID_TYPE_SW = 1, 3872 }; 3873 3874 struct mlx5_ifc_nic_vport_context_bits { 3875 u8 reserved_at_0[0x5]; 3876 u8 min_wqe_inline_mode[0x3]; 3877 u8 reserved_at_8[0x15]; 3878 u8 disable_mc_local_lb[0x1]; 3879 u8 disable_uc_local_lb[0x1]; 3880 u8 roce_en[0x1]; 3881 3882 u8 arm_change_event[0x1]; 3883 u8 reserved_at_21[0x1a]; 3884 u8 event_on_mtu[0x1]; 3885 u8 event_on_promisc_change[0x1]; 3886 u8 event_on_vlan_change[0x1]; 3887 u8 event_on_mc_address_change[0x1]; 3888 u8 event_on_uc_address_change[0x1]; 3889 3890 u8 vhca_id_type[0x1]; 3891 u8 reserved_at_41[0xb]; 3892 u8 affiliation_criteria[0x4]; 3893 u8 affiliated_vhca_id[0x10]; 3894 3895 u8 reserved_at_60[0xd0]; 3896 3897 u8 mtu[0x10]; 3898 3899 u8 system_image_guid[0x40]; 3900 u8 port_guid[0x40]; 3901 u8 node_guid[0x40]; 3902 3903 u8 reserved_at_200[0x140]; 3904 u8 qkey_violation_counter[0x10]; 3905 u8 reserved_at_350[0x430]; 3906 3907 u8 promisc_uc[0x1]; 3908 u8 promisc_mc[0x1]; 3909 u8 promisc_all[0x1]; 3910 u8 reserved_at_783[0x2]; 3911 u8 allowed_list_type[0x3]; 3912 u8 reserved_at_788[0xc]; 3913 u8 allowed_list_size[0xc]; 3914 3915 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3916 3917 u8 reserved_at_7e0[0x20]; 3918 3919 u8 current_uc_mac_address[][0x40]; 3920 }; 3921 3922 enum { 3923 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3924 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3925 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3926 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3927 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3928 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3929 }; 3930 3931 struct mlx5_ifc_mkc_bits { 3932 u8 reserved_at_0[0x1]; 3933 u8 free[0x1]; 3934 u8 reserved_at_2[0x1]; 3935 u8 access_mode_4_2[0x3]; 3936 u8 reserved_at_6[0x7]; 3937 u8 relaxed_ordering_write[0x1]; 3938 u8 reserved_at_e[0x1]; 3939 u8 small_fence_on_rdma_read_response[0x1]; 3940 u8 umr_en[0x1]; 3941 u8 a[0x1]; 3942 u8 rw[0x1]; 3943 u8 rr[0x1]; 3944 u8 lw[0x1]; 3945 u8 lr[0x1]; 3946 u8 access_mode_1_0[0x2]; 3947 u8 reserved_at_18[0x2]; 3948 u8 ma_translation_mode[0x2]; 3949 u8 reserved_at_1c[0x4]; 3950 3951 u8 qpn[0x18]; 3952 u8 mkey_7_0[0x8]; 3953 3954 u8 reserved_at_40[0x20]; 3955 3956 u8 length64[0x1]; 3957 u8 bsf_en[0x1]; 3958 u8 sync_umr[0x1]; 3959 u8 reserved_at_63[0x2]; 3960 u8 expected_sigerr_count[0x1]; 3961 u8 reserved_at_66[0x1]; 3962 u8 en_rinval[0x1]; 3963 u8 pd[0x18]; 3964 3965 u8 start_addr[0x40]; 3966 3967 u8 len[0x40]; 3968 3969 u8 bsf_octword_size[0x20]; 3970 3971 u8 reserved_at_120[0x80]; 3972 3973 u8 translations_octword_size[0x20]; 3974 3975 u8 reserved_at_1c0[0x19]; 3976 u8 relaxed_ordering_read[0x1]; 3977 u8 reserved_at_1d9[0x1]; 3978 u8 log_page_size[0x5]; 3979 3980 u8 reserved_at_1e0[0x20]; 3981 }; 3982 3983 struct mlx5_ifc_pkey_bits { 3984 u8 reserved_at_0[0x10]; 3985 u8 pkey[0x10]; 3986 }; 3987 3988 struct mlx5_ifc_array128_auto_bits { 3989 u8 array128_auto[16][0x8]; 3990 }; 3991 3992 struct mlx5_ifc_hca_vport_context_bits { 3993 u8 field_select[0x20]; 3994 3995 u8 reserved_at_20[0xe0]; 3996 3997 u8 sm_virt_aware[0x1]; 3998 u8 has_smi[0x1]; 3999 u8 has_raw[0x1]; 4000 u8 grh_required[0x1]; 4001 u8 reserved_at_104[0xc]; 4002 u8 port_physical_state[0x4]; 4003 u8 vport_state_policy[0x4]; 4004 u8 port_state[0x4]; 4005 u8 vport_state[0x4]; 4006 4007 u8 reserved_at_120[0x20]; 4008 4009 u8 system_image_guid[0x40]; 4010 4011 u8 port_guid[0x40]; 4012 4013 u8 node_guid[0x40]; 4014 4015 u8 cap_mask1[0x20]; 4016 4017 u8 cap_mask1_field_select[0x20]; 4018 4019 u8 cap_mask2[0x20]; 4020 4021 u8 cap_mask2_field_select[0x20]; 4022 4023 u8 reserved_at_280[0x80]; 4024 4025 u8 lid[0x10]; 4026 u8 reserved_at_310[0x4]; 4027 u8 init_type_reply[0x4]; 4028 u8 lmc[0x3]; 4029 u8 subnet_timeout[0x5]; 4030 4031 u8 sm_lid[0x10]; 4032 u8 sm_sl[0x4]; 4033 u8 reserved_at_334[0xc]; 4034 4035 u8 qkey_violation_counter[0x10]; 4036 u8 pkey_violation_counter[0x10]; 4037 4038 u8 reserved_at_360[0xca0]; 4039 }; 4040 4041 struct mlx5_ifc_esw_vport_context_bits { 4042 u8 fdb_to_vport_reg_c[0x1]; 4043 u8 reserved_at_1[0x2]; 4044 u8 vport_svlan_strip[0x1]; 4045 u8 vport_cvlan_strip[0x1]; 4046 u8 vport_svlan_insert[0x1]; 4047 u8 vport_cvlan_insert[0x2]; 4048 u8 fdb_to_vport_reg_c_id[0x8]; 4049 u8 reserved_at_10[0x10]; 4050 4051 u8 reserved_at_20[0x20]; 4052 4053 u8 svlan_cfi[0x1]; 4054 u8 svlan_pcp[0x3]; 4055 u8 svlan_id[0xc]; 4056 u8 cvlan_cfi[0x1]; 4057 u8 cvlan_pcp[0x3]; 4058 u8 cvlan_id[0xc]; 4059 4060 u8 reserved_at_60[0x720]; 4061 4062 u8 sw_steering_vport_icm_address_rx[0x40]; 4063 4064 u8 sw_steering_vport_icm_address_tx[0x40]; 4065 }; 4066 4067 enum { 4068 MLX5_EQC_STATUS_OK = 0x0, 4069 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4070 }; 4071 4072 enum { 4073 MLX5_EQC_ST_ARMED = 0x9, 4074 MLX5_EQC_ST_FIRED = 0xa, 4075 }; 4076 4077 struct mlx5_ifc_eqc_bits { 4078 u8 status[0x4]; 4079 u8 reserved_at_4[0x9]; 4080 u8 ec[0x1]; 4081 u8 oi[0x1]; 4082 u8 reserved_at_f[0x5]; 4083 u8 st[0x4]; 4084 u8 reserved_at_18[0x8]; 4085 4086 u8 reserved_at_20[0x20]; 4087 4088 u8 reserved_at_40[0x14]; 4089 u8 page_offset[0x6]; 4090 u8 reserved_at_5a[0x6]; 4091 4092 u8 reserved_at_60[0x3]; 4093 u8 log_eq_size[0x5]; 4094 u8 uar_page[0x18]; 4095 4096 u8 reserved_at_80[0x20]; 4097 4098 u8 reserved_at_a0[0x14]; 4099 u8 intr[0xc]; 4100 4101 u8 reserved_at_c0[0x3]; 4102 u8 log_page_size[0x5]; 4103 u8 reserved_at_c8[0x18]; 4104 4105 u8 reserved_at_e0[0x60]; 4106 4107 u8 reserved_at_140[0x8]; 4108 u8 consumer_counter[0x18]; 4109 4110 u8 reserved_at_160[0x8]; 4111 u8 producer_counter[0x18]; 4112 4113 u8 reserved_at_180[0x80]; 4114 }; 4115 4116 enum { 4117 MLX5_DCTC_STATE_ACTIVE = 0x0, 4118 MLX5_DCTC_STATE_DRAINING = 0x1, 4119 MLX5_DCTC_STATE_DRAINED = 0x2, 4120 }; 4121 4122 enum { 4123 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4124 MLX5_DCTC_CS_RES_NA = 0x1, 4125 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4126 }; 4127 4128 enum { 4129 MLX5_DCTC_MTU_256_BYTES = 0x1, 4130 MLX5_DCTC_MTU_512_BYTES = 0x2, 4131 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4132 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4133 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4134 }; 4135 4136 struct mlx5_ifc_dctc_bits { 4137 u8 reserved_at_0[0x4]; 4138 u8 state[0x4]; 4139 u8 reserved_at_8[0x18]; 4140 4141 u8 reserved_at_20[0x8]; 4142 u8 user_index[0x18]; 4143 4144 u8 reserved_at_40[0x8]; 4145 u8 cqn[0x18]; 4146 4147 u8 counter_set_id[0x8]; 4148 u8 atomic_mode[0x4]; 4149 u8 rre[0x1]; 4150 u8 rwe[0x1]; 4151 u8 rae[0x1]; 4152 u8 atomic_like_write_en[0x1]; 4153 u8 latency_sensitive[0x1]; 4154 u8 rlky[0x1]; 4155 u8 free_ar[0x1]; 4156 u8 reserved_at_73[0xd]; 4157 4158 u8 reserved_at_80[0x8]; 4159 u8 cs_res[0x8]; 4160 u8 reserved_at_90[0x3]; 4161 u8 min_rnr_nak[0x5]; 4162 u8 reserved_at_98[0x8]; 4163 4164 u8 reserved_at_a0[0x8]; 4165 u8 srqn_xrqn[0x18]; 4166 4167 u8 reserved_at_c0[0x8]; 4168 u8 pd[0x18]; 4169 4170 u8 tclass[0x8]; 4171 u8 reserved_at_e8[0x4]; 4172 u8 flow_label[0x14]; 4173 4174 u8 dc_access_key[0x40]; 4175 4176 u8 reserved_at_140[0x5]; 4177 u8 mtu[0x3]; 4178 u8 port[0x8]; 4179 u8 pkey_index[0x10]; 4180 4181 u8 reserved_at_160[0x8]; 4182 u8 my_addr_index[0x8]; 4183 u8 reserved_at_170[0x8]; 4184 u8 hop_limit[0x8]; 4185 4186 u8 dc_access_key_violation_count[0x20]; 4187 4188 u8 reserved_at_1a0[0x14]; 4189 u8 dei_cfi[0x1]; 4190 u8 eth_prio[0x3]; 4191 u8 ecn[0x2]; 4192 u8 dscp[0x6]; 4193 4194 u8 reserved_at_1c0[0x20]; 4195 u8 ece[0x20]; 4196 }; 4197 4198 enum { 4199 MLX5_CQC_STATUS_OK = 0x0, 4200 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4201 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4202 }; 4203 4204 enum { 4205 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4206 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4207 }; 4208 4209 enum { 4210 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4211 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4212 MLX5_CQC_ST_FIRED = 0xa, 4213 }; 4214 4215 enum { 4216 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4217 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4218 MLX5_CQ_PERIOD_NUM_MODES 4219 }; 4220 4221 struct mlx5_ifc_cqc_bits { 4222 u8 status[0x4]; 4223 u8 reserved_at_4[0x2]; 4224 u8 dbr_umem_valid[0x1]; 4225 u8 apu_cq[0x1]; 4226 u8 cqe_sz[0x3]; 4227 u8 cc[0x1]; 4228 u8 reserved_at_c[0x1]; 4229 u8 scqe_break_moderation_en[0x1]; 4230 u8 oi[0x1]; 4231 u8 cq_period_mode[0x2]; 4232 u8 cqe_comp_en[0x1]; 4233 u8 mini_cqe_res_format[0x2]; 4234 u8 st[0x4]; 4235 u8 reserved_at_18[0x6]; 4236 u8 cqe_compression_layout[0x2]; 4237 4238 u8 reserved_at_20[0x20]; 4239 4240 u8 reserved_at_40[0x14]; 4241 u8 page_offset[0x6]; 4242 u8 reserved_at_5a[0x6]; 4243 4244 u8 reserved_at_60[0x3]; 4245 u8 log_cq_size[0x5]; 4246 u8 uar_page[0x18]; 4247 4248 u8 reserved_at_80[0x4]; 4249 u8 cq_period[0xc]; 4250 u8 cq_max_count[0x10]; 4251 4252 u8 c_eqn_or_apu_element[0x20]; 4253 4254 u8 reserved_at_c0[0x3]; 4255 u8 log_page_size[0x5]; 4256 u8 reserved_at_c8[0x18]; 4257 4258 u8 reserved_at_e0[0x20]; 4259 4260 u8 reserved_at_100[0x8]; 4261 u8 last_notified_index[0x18]; 4262 4263 u8 reserved_at_120[0x8]; 4264 u8 last_solicit_index[0x18]; 4265 4266 u8 reserved_at_140[0x8]; 4267 u8 consumer_counter[0x18]; 4268 4269 u8 reserved_at_160[0x8]; 4270 u8 producer_counter[0x18]; 4271 4272 u8 reserved_at_180[0x40]; 4273 4274 u8 dbr_addr[0x40]; 4275 }; 4276 4277 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4278 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4279 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4280 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4281 u8 reserved_at_0[0x800]; 4282 }; 4283 4284 struct mlx5_ifc_query_adapter_param_block_bits { 4285 u8 reserved_at_0[0xc0]; 4286 4287 u8 reserved_at_c0[0x8]; 4288 u8 ieee_vendor_id[0x18]; 4289 4290 u8 reserved_at_e0[0x10]; 4291 u8 vsd_vendor_id[0x10]; 4292 4293 u8 vsd[208][0x8]; 4294 4295 u8 vsd_contd_psid[16][0x8]; 4296 }; 4297 4298 enum { 4299 MLX5_XRQC_STATE_GOOD = 0x0, 4300 MLX5_XRQC_STATE_ERROR = 0x1, 4301 }; 4302 4303 enum { 4304 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4305 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4306 }; 4307 4308 enum { 4309 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4310 }; 4311 4312 struct mlx5_ifc_tag_matching_topology_context_bits { 4313 u8 log_matching_list_sz[0x4]; 4314 u8 reserved_at_4[0xc]; 4315 u8 append_next_index[0x10]; 4316 4317 u8 sw_phase_cnt[0x10]; 4318 u8 hw_phase_cnt[0x10]; 4319 4320 u8 reserved_at_40[0x40]; 4321 }; 4322 4323 struct mlx5_ifc_xrqc_bits { 4324 u8 state[0x4]; 4325 u8 rlkey[0x1]; 4326 u8 reserved_at_5[0xf]; 4327 u8 topology[0x4]; 4328 u8 reserved_at_18[0x4]; 4329 u8 offload[0x4]; 4330 4331 u8 reserved_at_20[0x8]; 4332 u8 user_index[0x18]; 4333 4334 u8 reserved_at_40[0x8]; 4335 u8 cqn[0x18]; 4336 4337 u8 reserved_at_60[0xa0]; 4338 4339 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4340 4341 u8 reserved_at_180[0x280]; 4342 4343 struct mlx5_ifc_wq_bits wq; 4344 }; 4345 4346 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4347 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4348 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4349 u8 reserved_at_0[0x20]; 4350 }; 4351 4352 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4353 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4354 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4355 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4356 u8 reserved_at_0[0x20]; 4357 }; 4358 4359 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4360 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4361 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4362 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4363 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4364 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4365 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4366 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4367 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4368 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4369 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4370 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4371 u8 reserved_at_0[0x7c0]; 4372 }; 4373 4374 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4375 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4376 u8 reserved_at_0[0x7c0]; 4377 }; 4378 4379 union mlx5_ifc_event_auto_bits { 4380 struct mlx5_ifc_comp_event_bits comp_event; 4381 struct mlx5_ifc_dct_events_bits dct_events; 4382 struct mlx5_ifc_qp_events_bits qp_events; 4383 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4384 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4385 struct mlx5_ifc_cq_error_bits cq_error; 4386 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4387 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4388 struct mlx5_ifc_gpio_event_bits gpio_event; 4389 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4390 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4391 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4392 u8 reserved_at_0[0xe0]; 4393 }; 4394 4395 struct mlx5_ifc_health_buffer_bits { 4396 u8 reserved_at_0[0x100]; 4397 4398 u8 assert_existptr[0x20]; 4399 4400 u8 assert_callra[0x20]; 4401 4402 u8 reserved_at_140[0x20]; 4403 4404 u8 time[0x20]; 4405 4406 u8 fw_version[0x20]; 4407 4408 u8 hw_id[0x20]; 4409 4410 u8 rfr[0x1]; 4411 u8 reserved_at_1c1[0x3]; 4412 u8 valid[0x1]; 4413 u8 severity[0x3]; 4414 u8 reserved_at_1c8[0x18]; 4415 4416 u8 irisc_index[0x8]; 4417 u8 synd[0x8]; 4418 u8 ext_synd[0x10]; 4419 }; 4420 4421 struct mlx5_ifc_register_loopback_control_bits { 4422 u8 no_lb[0x1]; 4423 u8 reserved_at_1[0x7]; 4424 u8 port[0x8]; 4425 u8 reserved_at_10[0x10]; 4426 4427 u8 reserved_at_20[0x60]; 4428 }; 4429 4430 struct mlx5_ifc_vport_tc_element_bits { 4431 u8 traffic_class[0x4]; 4432 u8 reserved_at_4[0xc]; 4433 u8 vport_number[0x10]; 4434 }; 4435 4436 struct mlx5_ifc_vport_element_bits { 4437 u8 reserved_at_0[0x10]; 4438 u8 vport_number[0x10]; 4439 }; 4440 4441 enum { 4442 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4443 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4444 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4445 }; 4446 4447 struct mlx5_ifc_tsar_element_bits { 4448 u8 reserved_at_0[0x8]; 4449 u8 tsar_type[0x8]; 4450 u8 reserved_at_10[0x10]; 4451 }; 4452 4453 enum { 4454 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4455 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4456 }; 4457 4458 struct mlx5_ifc_teardown_hca_out_bits { 4459 u8 status[0x8]; 4460 u8 reserved_at_8[0x18]; 4461 4462 u8 syndrome[0x20]; 4463 4464 u8 reserved_at_40[0x3f]; 4465 4466 u8 state[0x1]; 4467 }; 4468 4469 enum { 4470 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4471 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4472 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4473 }; 4474 4475 struct mlx5_ifc_teardown_hca_in_bits { 4476 u8 opcode[0x10]; 4477 u8 reserved_at_10[0x10]; 4478 4479 u8 reserved_at_20[0x10]; 4480 u8 op_mod[0x10]; 4481 4482 u8 reserved_at_40[0x10]; 4483 u8 profile[0x10]; 4484 4485 u8 reserved_at_60[0x20]; 4486 }; 4487 4488 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4489 u8 status[0x8]; 4490 u8 reserved_at_8[0x18]; 4491 4492 u8 syndrome[0x20]; 4493 4494 u8 reserved_at_40[0x40]; 4495 }; 4496 4497 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4498 u8 opcode[0x10]; 4499 u8 uid[0x10]; 4500 4501 u8 reserved_at_20[0x10]; 4502 u8 op_mod[0x10]; 4503 4504 u8 reserved_at_40[0x8]; 4505 u8 qpn[0x18]; 4506 4507 u8 reserved_at_60[0x20]; 4508 4509 u8 opt_param_mask[0x20]; 4510 4511 u8 reserved_at_a0[0x20]; 4512 4513 struct mlx5_ifc_qpc_bits qpc; 4514 4515 u8 reserved_at_800[0x80]; 4516 }; 4517 4518 struct mlx5_ifc_sqd2rts_qp_out_bits { 4519 u8 status[0x8]; 4520 u8 reserved_at_8[0x18]; 4521 4522 u8 syndrome[0x20]; 4523 4524 u8 reserved_at_40[0x40]; 4525 }; 4526 4527 struct mlx5_ifc_sqd2rts_qp_in_bits { 4528 u8 opcode[0x10]; 4529 u8 uid[0x10]; 4530 4531 u8 reserved_at_20[0x10]; 4532 u8 op_mod[0x10]; 4533 4534 u8 reserved_at_40[0x8]; 4535 u8 qpn[0x18]; 4536 4537 u8 reserved_at_60[0x20]; 4538 4539 u8 opt_param_mask[0x20]; 4540 4541 u8 reserved_at_a0[0x20]; 4542 4543 struct mlx5_ifc_qpc_bits qpc; 4544 4545 u8 reserved_at_800[0x80]; 4546 }; 4547 4548 struct mlx5_ifc_set_roce_address_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 4552 u8 syndrome[0x20]; 4553 4554 u8 reserved_at_40[0x40]; 4555 }; 4556 4557 struct mlx5_ifc_set_roce_address_in_bits { 4558 u8 opcode[0x10]; 4559 u8 reserved_at_10[0x10]; 4560 4561 u8 reserved_at_20[0x10]; 4562 u8 op_mod[0x10]; 4563 4564 u8 roce_address_index[0x10]; 4565 u8 reserved_at_50[0xc]; 4566 u8 vhca_port_num[0x4]; 4567 4568 u8 reserved_at_60[0x20]; 4569 4570 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4571 }; 4572 4573 struct mlx5_ifc_set_mad_demux_out_bits { 4574 u8 status[0x8]; 4575 u8 reserved_at_8[0x18]; 4576 4577 u8 syndrome[0x20]; 4578 4579 u8 reserved_at_40[0x40]; 4580 }; 4581 4582 enum { 4583 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4584 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4585 }; 4586 4587 struct mlx5_ifc_set_mad_demux_in_bits { 4588 u8 opcode[0x10]; 4589 u8 reserved_at_10[0x10]; 4590 4591 u8 reserved_at_20[0x10]; 4592 u8 op_mod[0x10]; 4593 4594 u8 reserved_at_40[0x20]; 4595 4596 u8 reserved_at_60[0x6]; 4597 u8 demux_mode[0x2]; 4598 u8 reserved_at_68[0x18]; 4599 }; 4600 4601 struct mlx5_ifc_set_l2_table_entry_out_bits { 4602 u8 status[0x8]; 4603 u8 reserved_at_8[0x18]; 4604 4605 u8 syndrome[0x20]; 4606 4607 u8 reserved_at_40[0x40]; 4608 }; 4609 4610 struct mlx5_ifc_set_l2_table_entry_in_bits { 4611 u8 opcode[0x10]; 4612 u8 reserved_at_10[0x10]; 4613 4614 u8 reserved_at_20[0x10]; 4615 u8 op_mod[0x10]; 4616 4617 u8 reserved_at_40[0x60]; 4618 4619 u8 reserved_at_a0[0x8]; 4620 u8 table_index[0x18]; 4621 4622 u8 reserved_at_c0[0x20]; 4623 4624 u8 reserved_at_e0[0x13]; 4625 u8 vlan_valid[0x1]; 4626 u8 vlan[0xc]; 4627 4628 struct mlx5_ifc_mac_address_layout_bits mac_address; 4629 4630 u8 reserved_at_140[0xc0]; 4631 }; 4632 4633 struct mlx5_ifc_set_issi_out_bits { 4634 u8 status[0x8]; 4635 u8 reserved_at_8[0x18]; 4636 4637 u8 syndrome[0x20]; 4638 4639 u8 reserved_at_40[0x40]; 4640 }; 4641 4642 struct mlx5_ifc_set_issi_in_bits { 4643 u8 opcode[0x10]; 4644 u8 reserved_at_10[0x10]; 4645 4646 u8 reserved_at_20[0x10]; 4647 u8 op_mod[0x10]; 4648 4649 u8 reserved_at_40[0x10]; 4650 u8 current_issi[0x10]; 4651 4652 u8 reserved_at_60[0x20]; 4653 }; 4654 4655 struct mlx5_ifc_set_hca_cap_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_at_40[0x40]; 4662 }; 4663 4664 struct mlx5_ifc_set_hca_cap_in_bits { 4665 u8 opcode[0x10]; 4666 u8 reserved_at_10[0x10]; 4667 4668 u8 reserved_at_20[0x10]; 4669 u8 op_mod[0x10]; 4670 4671 u8 other_function[0x1]; 4672 u8 reserved_at_41[0xf]; 4673 u8 function_id[0x10]; 4674 4675 u8 reserved_at_60[0x20]; 4676 4677 union mlx5_ifc_hca_cap_union_bits capability; 4678 }; 4679 4680 enum { 4681 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4682 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4683 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4684 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4685 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4686 }; 4687 4688 struct mlx5_ifc_set_fte_out_bits { 4689 u8 status[0x8]; 4690 u8 reserved_at_8[0x18]; 4691 4692 u8 syndrome[0x20]; 4693 4694 u8 reserved_at_40[0x40]; 4695 }; 4696 4697 struct mlx5_ifc_set_fte_in_bits { 4698 u8 opcode[0x10]; 4699 u8 reserved_at_10[0x10]; 4700 4701 u8 reserved_at_20[0x10]; 4702 u8 op_mod[0x10]; 4703 4704 u8 other_vport[0x1]; 4705 u8 reserved_at_41[0xf]; 4706 u8 vport_number[0x10]; 4707 4708 u8 reserved_at_60[0x20]; 4709 4710 u8 table_type[0x8]; 4711 u8 reserved_at_88[0x18]; 4712 4713 u8 reserved_at_a0[0x8]; 4714 u8 table_id[0x18]; 4715 4716 u8 ignore_flow_level[0x1]; 4717 u8 reserved_at_c1[0x17]; 4718 u8 modify_enable_mask[0x8]; 4719 4720 u8 reserved_at_e0[0x20]; 4721 4722 u8 flow_index[0x20]; 4723 4724 u8 reserved_at_120[0xe0]; 4725 4726 struct mlx5_ifc_flow_context_bits flow_context; 4727 }; 4728 4729 struct mlx5_ifc_rts2rts_qp_out_bits { 4730 u8 status[0x8]; 4731 u8 reserved_at_8[0x18]; 4732 4733 u8 syndrome[0x20]; 4734 4735 u8 reserved_at_40[0x20]; 4736 u8 ece[0x20]; 4737 }; 4738 4739 struct mlx5_ifc_rts2rts_qp_in_bits { 4740 u8 opcode[0x10]; 4741 u8 uid[0x10]; 4742 4743 u8 reserved_at_20[0x10]; 4744 u8 op_mod[0x10]; 4745 4746 u8 reserved_at_40[0x8]; 4747 u8 qpn[0x18]; 4748 4749 u8 reserved_at_60[0x20]; 4750 4751 u8 opt_param_mask[0x20]; 4752 4753 u8 ece[0x20]; 4754 4755 struct mlx5_ifc_qpc_bits qpc; 4756 4757 u8 reserved_at_800[0x80]; 4758 }; 4759 4760 struct mlx5_ifc_rtr2rts_qp_out_bits { 4761 u8 status[0x8]; 4762 u8 reserved_at_8[0x18]; 4763 4764 u8 syndrome[0x20]; 4765 4766 u8 reserved_at_40[0x20]; 4767 u8 ece[0x20]; 4768 }; 4769 4770 struct mlx5_ifc_rtr2rts_qp_in_bits { 4771 u8 opcode[0x10]; 4772 u8 uid[0x10]; 4773 4774 u8 reserved_at_20[0x10]; 4775 u8 op_mod[0x10]; 4776 4777 u8 reserved_at_40[0x8]; 4778 u8 qpn[0x18]; 4779 4780 u8 reserved_at_60[0x20]; 4781 4782 u8 opt_param_mask[0x20]; 4783 4784 u8 ece[0x20]; 4785 4786 struct mlx5_ifc_qpc_bits qpc; 4787 4788 u8 reserved_at_800[0x80]; 4789 }; 4790 4791 struct mlx5_ifc_rst2init_qp_out_bits { 4792 u8 status[0x8]; 4793 u8 reserved_at_8[0x18]; 4794 4795 u8 syndrome[0x20]; 4796 4797 u8 reserved_at_40[0x20]; 4798 u8 ece[0x20]; 4799 }; 4800 4801 struct mlx5_ifc_rst2init_qp_in_bits { 4802 u8 opcode[0x10]; 4803 u8 uid[0x10]; 4804 4805 u8 reserved_at_20[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 reserved_at_40[0x8]; 4809 u8 qpn[0x18]; 4810 4811 u8 reserved_at_60[0x20]; 4812 4813 u8 opt_param_mask[0x20]; 4814 4815 u8 ece[0x20]; 4816 4817 struct mlx5_ifc_qpc_bits qpc; 4818 4819 u8 reserved_at_800[0x80]; 4820 }; 4821 4822 struct mlx5_ifc_query_xrq_out_bits { 4823 u8 status[0x8]; 4824 u8 reserved_at_8[0x18]; 4825 4826 u8 syndrome[0x20]; 4827 4828 u8 reserved_at_40[0x40]; 4829 4830 struct mlx5_ifc_xrqc_bits xrq_context; 4831 }; 4832 4833 struct mlx5_ifc_query_xrq_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x8]; 4841 u8 xrqn[0x18]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_query_xrc_srq_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 4854 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4855 4856 u8 reserved_at_280[0x600]; 4857 4858 u8 pas[][0x40]; 4859 }; 4860 4861 struct mlx5_ifc_query_xrc_srq_in_bits { 4862 u8 opcode[0x10]; 4863 u8 reserved_at_10[0x10]; 4864 4865 u8 reserved_at_20[0x10]; 4866 u8 op_mod[0x10]; 4867 4868 u8 reserved_at_40[0x8]; 4869 u8 xrc_srqn[0x18]; 4870 4871 u8 reserved_at_60[0x20]; 4872 }; 4873 4874 enum { 4875 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4876 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4877 }; 4878 4879 struct mlx5_ifc_query_vport_state_out_bits { 4880 u8 status[0x8]; 4881 u8 reserved_at_8[0x18]; 4882 4883 u8 syndrome[0x20]; 4884 4885 u8 reserved_at_40[0x20]; 4886 4887 u8 reserved_at_60[0x18]; 4888 u8 admin_state[0x4]; 4889 u8 state[0x4]; 4890 }; 4891 4892 enum { 4893 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4894 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4895 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4896 }; 4897 4898 struct mlx5_ifc_arm_monitor_counter_in_bits { 4899 u8 opcode[0x10]; 4900 u8 uid[0x10]; 4901 4902 u8 reserved_at_20[0x10]; 4903 u8 op_mod[0x10]; 4904 4905 u8 reserved_at_40[0x20]; 4906 4907 u8 reserved_at_60[0x20]; 4908 }; 4909 4910 struct mlx5_ifc_arm_monitor_counter_out_bits { 4911 u8 status[0x8]; 4912 u8 reserved_at_8[0x18]; 4913 4914 u8 syndrome[0x20]; 4915 4916 u8 reserved_at_40[0x40]; 4917 }; 4918 4919 enum { 4920 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4921 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4922 }; 4923 4924 enum mlx5_monitor_counter_ppcnt { 4925 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4926 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4927 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4928 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4929 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4930 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4931 }; 4932 4933 enum { 4934 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4935 }; 4936 4937 struct mlx5_ifc_monitor_counter_output_bits { 4938 u8 reserved_at_0[0x4]; 4939 u8 type[0x4]; 4940 u8 reserved_at_8[0x8]; 4941 u8 counter[0x10]; 4942 4943 u8 counter_group_id[0x20]; 4944 }; 4945 4946 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4947 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4948 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4949 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4950 4951 struct mlx5_ifc_set_monitor_counter_in_bits { 4952 u8 opcode[0x10]; 4953 u8 uid[0x10]; 4954 4955 u8 reserved_at_20[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_at_40[0x10]; 4959 u8 num_of_counters[0x10]; 4960 4961 u8 reserved_at_60[0x20]; 4962 4963 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4964 }; 4965 4966 struct mlx5_ifc_set_monitor_counter_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_at_8[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_at_40[0x40]; 4973 }; 4974 4975 struct mlx5_ifc_query_vport_state_in_bits { 4976 u8 opcode[0x10]; 4977 u8 reserved_at_10[0x10]; 4978 4979 u8 reserved_at_20[0x10]; 4980 u8 op_mod[0x10]; 4981 4982 u8 other_vport[0x1]; 4983 u8 reserved_at_41[0xf]; 4984 u8 vport_number[0x10]; 4985 4986 u8 reserved_at_60[0x20]; 4987 }; 4988 4989 struct mlx5_ifc_query_vnic_env_out_bits { 4990 u8 status[0x8]; 4991 u8 reserved_at_8[0x18]; 4992 4993 u8 syndrome[0x20]; 4994 4995 u8 reserved_at_40[0x40]; 4996 4997 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4998 }; 4999 5000 enum { 5001 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5002 }; 5003 5004 struct mlx5_ifc_query_vnic_env_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_at_10[0x10]; 5007 5008 u8 reserved_at_20[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 other_vport[0x1]; 5012 u8 reserved_at_41[0xf]; 5013 u8 vport_number[0x10]; 5014 5015 u8 reserved_at_60[0x20]; 5016 }; 5017 5018 struct mlx5_ifc_query_vport_counter_out_bits { 5019 u8 status[0x8]; 5020 u8 reserved_at_8[0x18]; 5021 5022 u8 syndrome[0x20]; 5023 5024 u8 reserved_at_40[0x40]; 5025 5026 struct mlx5_ifc_traffic_counter_bits received_errors; 5027 5028 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5029 5030 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5031 5032 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5033 5034 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5035 5036 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5037 5038 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5039 5040 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5041 5042 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5043 5044 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5045 5046 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5047 5048 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5049 5050 u8 reserved_at_680[0xa00]; 5051 }; 5052 5053 enum { 5054 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5055 }; 5056 5057 struct mlx5_ifc_query_vport_counter_in_bits { 5058 u8 opcode[0x10]; 5059 u8 reserved_at_10[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 other_vport[0x1]; 5065 u8 reserved_at_41[0xb]; 5066 u8 port_num[0x4]; 5067 u8 vport_number[0x10]; 5068 5069 u8 reserved_at_60[0x60]; 5070 5071 u8 clear[0x1]; 5072 u8 reserved_at_c1[0x1f]; 5073 5074 u8 reserved_at_e0[0x20]; 5075 }; 5076 5077 struct mlx5_ifc_query_tis_out_bits { 5078 u8 status[0x8]; 5079 u8 reserved_at_8[0x18]; 5080 5081 u8 syndrome[0x20]; 5082 5083 u8 reserved_at_40[0x40]; 5084 5085 struct mlx5_ifc_tisc_bits tis_context; 5086 }; 5087 5088 struct mlx5_ifc_query_tis_in_bits { 5089 u8 opcode[0x10]; 5090 u8 reserved_at_10[0x10]; 5091 5092 u8 reserved_at_20[0x10]; 5093 u8 op_mod[0x10]; 5094 5095 u8 reserved_at_40[0x8]; 5096 u8 tisn[0x18]; 5097 5098 u8 reserved_at_60[0x20]; 5099 }; 5100 5101 struct mlx5_ifc_query_tir_out_bits { 5102 u8 status[0x8]; 5103 u8 reserved_at_8[0x18]; 5104 5105 u8 syndrome[0x20]; 5106 5107 u8 reserved_at_40[0xc0]; 5108 5109 struct mlx5_ifc_tirc_bits tir_context; 5110 }; 5111 5112 struct mlx5_ifc_query_tir_in_bits { 5113 u8 opcode[0x10]; 5114 u8 reserved_at_10[0x10]; 5115 5116 u8 reserved_at_20[0x10]; 5117 u8 op_mod[0x10]; 5118 5119 u8 reserved_at_40[0x8]; 5120 u8 tirn[0x18]; 5121 5122 u8 reserved_at_60[0x20]; 5123 }; 5124 5125 struct mlx5_ifc_query_srq_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_at_8[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_at_40[0x40]; 5132 5133 struct mlx5_ifc_srqc_bits srq_context_entry; 5134 5135 u8 reserved_at_280[0x600]; 5136 5137 u8 pas[][0x40]; 5138 }; 5139 5140 struct mlx5_ifc_query_srq_in_bits { 5141 u8 opcode[0x10]; 5142 u8 reserved_at_10[0x10]; 5143 5144 u8 reserved_at_20[0x10]; 5145 u8 op_mod[0x10]; 5146 5147 u8 reserved_at_40[0x8]; 5148 u8 srqn[0x18]; 5149 5150 u8 reserved_at_60[0x20]; 5151 }; 5152 5153 struct mlx5_ifc_query_sq_out_bits { 5154 u8 status[0x8]; 5155 u8 reserved_at_8[0x18]; 5156 5157 u8 syndrome[0x20]; 5158 5159 u8 reserved_at_40[0xc0]; 5160 5161 struct mlx5_ifc_sqc_bits sq_context; 5162 }; 5163 5164 struct mlx5_ifc_query_sq_in_bits { 5165 u8 opcode[0x10]; 5166 u8 reserved_at_10[0x10]; 5167 5168 u8 reserved_at_20[0x10]; 5169 u8 op_mod[0x10]; 5170 5171 u8 reserved_at_40[0x8]; 5172 u8 sqn[0x18]; 5173 5174 u8 reserved_at_60[0x20]; 5175 }; 5176 5177 struct mlx5_ifc_query_special_contexts_out_bits { 5178 u8 status[0x8]; 5179 u8 reserved_at_8[0x18]; 5180 5181 u8 syndrome[0x20]; 5182 5183 u8 dump_fill_mkey[0x20]; 5184 5185 u8 resd_lkey[0x20]; 5186 5187 u8 null_mkey[0x20]; 5188 5189 u8 reserved_at_a0[0x60]; 5190 }; 5191 5192 struct mlx5_ifc_query_special_contexts_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x40]; 5200 }; 5201 5202 struct mlx5_ifc_query_scheduling_element_out_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 reserved_at_40[0xc0]; 5210 5211 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5212 5213 u8 reserved_at_300[0x100]; 5214 }; 5215 5216 enum { 5217 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5218 SCHEDULING_HIERARCHY_NIC = 0x3, 5219 }; 5220 5221 struct mlx5_ifc_query_scheduling_element_in_bits { 5222 u8 opcode[0x10]; 5223 u8 reserved_at_10[0x10]; 5224 5225 u8 reserved_at_20[0x10]; 5226 u8 op_mod[0x10]; 5227 5228 u8 scheduling_hierarchy[0x8]; 5229 u8 reserved_at_48[0x18]; 5230 5231 u8 scheduling_element_id[0x20]; 5232 5233 u8 reserved_at_80[0x180]; 5234 }; 5235 5236 struct mlx5_ifc_query_rqt_out_bits { 5237 u8 status[0x8]; 5238 u8 reserved_at_8[0x18]; 5239 5240 u8 syndrome[0x20]; 5241 5242 u8 reserved_at_40[0xc0]; 5243 5244 struct mlx5_ifc_rqtc_bits rqt_context; 5245 }; 5246 5247 struct mlx5_ifc_query_rqt_in_bits { 5248 u8 opcode[0x10]; 5249 u8 reserved_at_10[0x10]; 5250 5251 u8 reserved_at_20[0x10]; 5252 u8 op_mod[0x10]; 5253 5254 u8 reserved_at_40[0x8]; 5255 u8 rqtn[0x18]; 5256 5257 u8 reserved_at_60[0x20]; 5258 }; 5259 5260 struct mlx5_ifc_query_rq_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_at_8[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_at_40[0xc0]; 5267 5268 struct mlx5_ifc_rqc_bits rq_context; 5269 }; 5270 5271 struct mlx5_ifc_query_rq_in_bits { 5272 u8 opcode[0x10]; 5273 u8 reserved_at_10[0x10]; 5274 5275 u8 reserved_at_20[0x10]; 5276 u8 op_mod[0x10]; 5277 5278 u8 reserved_at_40[0x8]; 5279 u8 rqn[0x18]; 5280 5281 u8 reserved_at_60[0x20]; 5282 }; 5283 5284 struct mlx5_ifc_query_roce_address_out_bits { 5285 u8 status[0x8]; 5286 u8 reserved_at_8[0x18]; 5287 5288 u8 syndrome[0x20]; 5289 5290 u8 reserved_at_40[0x40]; 5291 5292 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5293 }; 5294 5295 struct mlx5_ifc_query_roce_address_in_bits { 5296 u8 opcode[0x10]; 5297 u8 reserved_at_10[0x10]; 5298 5299 u8 reserved_at_20[0x10]; 5300 u8 op_mod[0x10]; 5301 5302 u8 roce_address_index[0x10]; 5303 u8 reserved_at_50[0xc]; 5304 u8 vhca_port_num[0x4]; 5305 5306 u8 reserved_at_60[0x20]; 5307 }; 5308 5309 struct mlx5_ifc_query_rmp_out_bits { 5310 u8 status[0x8]; 5311 u8 reserved_at_8[0x18]; 5312 5313 u8 syndrome[0x20]; 5314 5315 u8 reserved_at_40[0xc0]; 5316 5317 struct mlx5_ifc_rmpc_bits rmp_context; 5318 }; 5319 5320 struct mlx5_ifc_query_rmp_in_bits { 5321 u8 opcode[0x10]; 5322 u8 reserved_at_10[0x10]; 5323 5324 u8 reserved_at_20[0x10]; 5325 u8 op_mod[0x10]; 5326 5327 u8 reserved_at_40[0x8]; 5328 u8 rmpn[0x18]; 5329 5330 u8 reserved_at_60[0x20]; 5331 }; 5332 5333 struct mlx5_ifc_query_qp_out_bits { 5334 u8 status[0x8]; 5335 u8 reserved_at_8[0x18]; 5336 5337 u8 syndrome[0x20]; 5338 5339 u8 reserved_at_40[0x40]; 5340 5341 u8 opt_param_mask[0x20]; 5342 5343 u8 ece[0x20]; 5344 5345 struct mlx5_ifc_qpc_bits qpc; 5346 5347 u8 reserved_at_800[0x80]; 5348 5349 u8 pas[][0x40]; 5350 }; 5351 5352 struct mlx5_ifc_query_qp_in_bits { 5353 u8 opcode[0x10]; 5354 u8 reserved_at_10[0x10]; 5355 5356 u8 reserved_at_20[0x10]; 5357 u8 op_mod[0x10]; 5358 5359 u8 reserved_at_40[0x8]; 5360 u8 qpn[0x18]; 5361 5362 u8 reserved_at_60[0x20]; 5363 }; 5364 5365 struct mlx5_ifc_query_q_counter_out_bits { 5366 u8 status[0x8]; 5367 u8 reserved_at_8[0x18]; 5368 5369 u8 syndrome[0x20]; 5370 5371 u8 reserved_at_40[0x40]; 5372 5373 u8 rx_write_requests[0x20]; 5374 5375 u8 reserved_at_a0[0x20]; 5376 5377 u8 rx_read_requests[0x20]; 5378 5379 u8 reserved_at_e0[0x20]; 5380 5381 u8 rx_atomic_requests[0x20]; 5382 5383 u8 reserved_at_120[0x20]; 5384 5385 u8 rx_dct_connect[0x20]; 5386 5387 u8 reserved_at_160[0x20]; 5388 5389 u8 out_of_buffer[0x20]; 5390 5391 u8 reserved_at_1a0[0x20]; 5392 5393 u8 out_of_sequence[0x20]; 5394 5395 u8 reserved_at_1e0[0x20]; 5396 5397 u8 duplicate_request[0x20]; 5398 5399 u8 reserved_at_220[0x20]; 5400 5401 u8 rnr_nak_retry_err[0x20]; 5402 5403 u8 reserved_at_260[0x20]; 5404 5405 u8 packet_seq_err[0x20]; 5406 5407 u8 reserved_at_2a0[0x20]; 5408 5409 u8 implied_nak_seq_err[0x20]; 5410 5411 u8 reserved_at_2e0[0x20]; 5412 5413 u8 local_ack_timeout_err[0x20]; 5414 5415 u8 reserved_at_320[0xa0]; 5416 5417 u8 resp_local_length_error[0x20]; 5418 5419 u8 req_local_length_error[0x20]; 5420 5421 u8 resp_local_qp_error[0x20]; 5422 5423 u8 local_operation_error[0x20]; 5424 5425 u8 resp_local_protection[0x20]; 5426 5427 u8 req_local_protection[0x20]; 5428 5429 u8 resp_cqe_error[0x20]; 5430 5431 u8 req_cqe_error[0x20]; 5432 5433 u8 req_mw_binding[0x20]; 5434 5435 u8 req_bad_response[0x20]; 5436 5437 u8 req_remote_invalid_request[0x20]; 5438 5439 u8 resp_remote_invalid_request[0x20]; 5440 5441 u8 req_remote_access_errors[0x20]; 5442 5443 u8 resp_remote_access_errors[0x20]; 5444 5445 u8 req_remote_operation_errors[0x20]; 5446 5447 u8 req_transport_retries_exceeded[0x20]; 5448 5449 u8 cq_overflow[0x20]; 5450 5451 u8 resp_cqe_flush_error[0x20]; 5452 5453 u8 req_cqe_flush_error[0x20]; 5454 5455 u8 reserved_at_620[0x20]; 5456 5457 u8 roce_adp_retrans[0x20]; 5458 5459 u8 roce_adp_retrans_to[0x20]; 5460 5461 u8 roce_slow_restart[0x20]; 5462 5463 u8 roce_slow_restart_cnps[0x20]; 5464 5465 u8 roce_slow_restart_trans[0x20]; 5466 5467 u8 reserved_at_6e0[0x120]; 5468 }; 5469 5470 struct mlx5_ifc_query_q_counter_in_bits { 5471 u8 opcode[0x10]; 5472 u8 reserved_at_10[0x10]; 5473 5474 u8 reserved_at_20[0x10]; 5475 u8 op_mod[0x10]; 5476 5477 u8 reserved_at_40[0x80]; 5478 5479 u8 clear[0x1]; 5480 u8 reserved_at_c1[0x1f]; 5481 5482 u8 reserved_at_e0[0x18]; 5483 u8 counter_set_id[0x8]; 5484 }; 5485 5486 struct mlx5_ifc_query_pages_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_at_8[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 embedded_cpu_function[0x1]; 5493 u8 reserved_at_41[0xf]; 5494 u8 function_id[0x10]; 5495 5496 u8 num_pages[0x20]; 5497 }; 5498 5499 enum { 5500 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5501 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5502 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5503 }; 5504 5505 struct mlx5_ifc_query_pages_in_bits { 5506 u8 opcode[0x10]; 5507 u8 reserved_at_10[0x10]; 5508 5509 u8 reserved_at_20[0x10]; 5510 u8 op_mod[0x10]; 5511 5512 u8 embedded_cpu_function[0x1]; 5513 u8 reserved_at_41[0xf]; 5514 u8 function_id[0x10]; 5515 5516 u8 reserved_at_60[0x20]; 5517 }; 5518 5519 struct mlx5_ifc_query_nic_vport_context_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0x40]; 5526 5527 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5528 }; 5529 5530 struct mlx5_ifc_query_nic_vport_context_in_bits { 5531 u8 opcode[0x10]; 5532 u8 reserved_at_10[0x10]; 5533 5534 u8 reserved_at_20[0x10]; 5535 u8 op_mod[0x10]; 5536 5537 u8 other_vport[0x1]; 5538 u8 reserved_at_41[0xf]; 5539 u8 vport_number[0x10]; 5540 5541 u8 reserved_at_60[0x5]; 5542 u8 allowed_list_type[0x3]; 5543 u8 reserved_at_68[0x18]; 5544 }; 5545 5546 struct mlx5_ifc_query_mkey_out_bits { 5547 u8 status[0x8]; 5548 u8 reserved_at_8[0x18]; 5549 5550 u8 syndrome[0x20]; 5551 5552 u8 reserved_at_40[0x40]; 5553 5554 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5555 5556 u8 reserved_at_280[0x600]; 5557 5558 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5559 5560 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5561 }; 5562 5563 struct mlx5_ifc_query_mkey_in_bits { 5564 u8 opcode[0x10]; 5565 u8 reserved_at_10[0x10]; 5566 5567 u8 reserved_at_20[0x10]; 5568 u8 op_mod[0x10]; 5569 5570 u8 reserved_at_40[0x8]; 5571 u8 mkey_index[0x18]; 5572 5573 u8 pg_access[0x1]; 5574 u8 reserved_at_61[0x1f]; 5575 }; 5576 5577 struct mlx5_ifc_query_mad_demux_out_bits { 5578 u8 status[0x8]; 5579 u8 reserved_at_8[0x18]; 5580 5581 u8 syndrome[0x20]; 5582 5583 u8 reserved_at_40[0x40]; 5584 5585 u8 mad_dumux_parameters_block[0x20]; 5586 }; 5587 5588 struct mlx5_ifc_query_mad_demux_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_at_10[0x10]; 5591 5592 u8 reserved_at_20[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 reserved_at_40[0x40]; 5596 }; 5597 5598 struct mlx5_ifc_query_l2_table_entry_out_bits { 5599 u8 status[0x8]; 5600 u8 reserved_at_8[0x18]; 5601 5602 u8 syndrome[0x20]; 5603 5604 u8 reserved_at_40[0xa0]; 5605 5606 u8 reserved_at_e0[0x13]; 5607 u8 vlan_valid[0x1]; 5608 u8 vlan[0xc]; 5609 5610 struct mlx5_ifc_mac_address_layout_bits mac_address; 5611 5612 u8 reserved_at_140[0xc0]; 5613 }; 5614 5615 struct mlx5_ifc_query_l2_table_entry_in_bits { 5616 u8 opcode[0x10]; 5617 u8 reserved_at_10[0x10]; 5618 5619 u8 reserved_at_20[0x10]; 5620 u8 op_mod[0x10]; 5621 5622 u8 reserved_at_40[0x60]; 5623 5624 u8 reserved_at_a0[0x8]; 5625 u8 table_index[0x18]; 5626 5627 u8 reserved_at_c0[0x140]; 5628 }; 5629 5630 struct mlx5_ifc_query_issi_out_bits { 5631 u8 status[0x8]; 5632 u8 reserved_at_8[0x18]; 5633 5634 u8 syndrome[0x20]; 5635 5636 u8 reserved_at_40[0x10]; 5637 u8 current_issi[0x10]; 5638 5639 u8 reserved_at_60[0xa0]; 5640 5641 u8 reserved_at_100[76][0x8]; 5642 u8 supported_issi_dw0[0x20]; 5643 }; 5644 5645 struct mlx5_ifc_query_issi_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_at_10[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 reserved_at_40[0x40]; 5653 }; 5654 5655 struct mlx5_ifc_set_driver_version_out_bits { 5656 u8 status[0x8]; 5657 u8 reserved_0[0x18]; 5658 5659 u8 syndrome[0x20]; 5660 u8 reserved_1[0x40]; 5661 }; 5662 5663 struct mlx5_ifc_set_driver_version_in_bits { 5664 u8 opcode[0x10]; 5665 u8 reserved_0[0x10]; 5666 5667 u8 reserved_1[0x10]; 5668 u8 op_mod[0x10]; 5669 5670 u8 reserved_2[0x40]; 5671 u8 driver_version[64][0x8]; 5672 }; 5673 5674 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5675 u8 status[0x8]; 5676 u8 reserved_at_8[0x18]; 5677 5678 u8 syndrome[0x20]; 5679 5680 u8 reserved_at_40[0x40]; 5681 5682 struct mlx5_ifc_pkey_bits pkey[]; 5683 }; 5684 5685 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_at_10[0x10]; 5688 5689 u8 reserved_at_20[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 other_vport[0x1]; 5693 u8 reserved_at_41[0xb]; 5694 u8 port_num[0x4]; 5695 u8 vport_number[0x10]; 5696 5697 u8 reserved_at_60[0x10]; 5698 u8 pkey_index[0x10]; 5699 }; 5700 5701 enum { 5702 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5703 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5704 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5705 }; 5706 5707 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5708 u8 status[0x8]; 5709 u8 reserved_at_8[0x18]; 5710 5711 u8 syndrome[0x20]; 5712 5713 u8 reserved_at_40[0x20]; 5714 5715 u8 gids_num[0x10]; 5716 u8 reserved_at_70[0x10]; 5717 5718 struct mlx5_ifc_array128_auto_bits gid[]; 5719 }; 5720 5721 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5722 u8 opcode[0x10]; 5723 u8 reserved_at_10[0x10]; 5724 5725 u8 reserved_at_20[0x10]; 5726 u8 op_mod[0x10]; 5727 5728 u8 other_vport[0x1]; 5729 u8 reserved_at_41[0xb]; 5730 u8 port_num[0x4]; 5731 u8 vport_number[0x10]; 5732 5733 u8 reserved_at_60[0x10]; 5734 u8 gid_index[0x10]; 5735 }; 5736 5737 struct mlx5_ifc_query_hca_vport_context_out_bits { 5738 u8 status[0x8]; 5739 u8 reserved_at_8[0x18]; 5740 5741 u8 syndrome[0x20]; 5742 5743 u8 reserved_at_40[0x40]; 5744 5745 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5746 }; 5747 5748 struct mlx5_ifc_query_hca_vport_context_in_bits { 5749 u8 opcode[0x10]; 5750 u8 reserved_at_10[0x10]; 5751 5752 u8 reserved_at_20[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 other_vport[0x1]; 5756 u8 reserved_at_41[0xb]; 5757 u8 port_num[0x4]; 5758 u8 vport_number[0x10]; 5759 5760 u8 reserved_at_60[0x20]; 5761 }; 5762 5763 struct mlx5_ifc_query_hca_cap_out_bits { 5764 u8 status[0x8]; 5765 u8 reserved_at_8[0x18]; 5766 5767 u8 syndrome[0x20]; 5768 5769 u8 reserved_at_40[0x40]; 5770 5771 union mlx5_ifc_hca_cap_union_bits capability; 5772 }; 5773 5774 struct mlx5_ifc_query_hca_cap_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 other_function[0x1]; 5782 u8 reserved_at_41[0xf]; 5783 u8 function_id[0x10]; 5784 5785 u8 reserved_at_60[0x20]; 5786 }; 5787 5788 struct mlx5_ifc_other_hca_cap_bits { 5789 u8 roce[0x1]; 5790 u8 reserved_at_1[0x27f]; 5791 }; 5792 5793 struct mlx5_ifc_query_other_hca_cap_out_bits { 5794 u8 status[0x8]; 5795 u8 reserved_at_8[0x18]; 5796 5797 u8 syndrome[0x20]; 5798 5799 u8 reserved_at_40[0x40]; 5800 5801 struct mlx5_ifc_other_hca_cap_bits other_capability; 5802 }; 5803 5804 struct mlx5_ifc_query_other_hca_cap_in_bits { 5805 u8 opcode[0x10]; 5806 u8 reserved_at_10[0x10]; 5807 5808 u8 reserved_at_20[0x10]; 5809 u8 op_mod[0x10]; 5810 5811 u8 reserved_at_40[0x10]; 5812 u8 function_id[0x10]; 5813 5814 u8 reserved_at_60[0x20]; 5815 }; 5816 5817 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5818 u8 status[0x8]; 5819 u8 reserved_at_8[0x18]; 5820 5821 u8 syndrome[0x20]; 5822 5823 u8 reserved_at_40[0x40]; 5824 }; 5825 5826 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5827 u8 opcode[0x10]; 5828 u8 reserved_at_10[0x10]; 5829 5830 u8 reserved_at_20[0x10]; 5831 u8 op_mod[0x10]; 5832 5833 u8 reserved_at_40[0x10]; 5834 u8 function_id[0x10]; 5835 u8 field_select[0x20]; 5836 5837 struct mlx5_ifc_other_hca_cap_bits other_capability; 5838 }; 5839 5840 struct mlx5_ifc_flow_table_context_bits { 5841 u8 reformat_en[0x1]; 5842 u8 decap_en[0x1]; 5843 u8 sw_owner[0x1]; 5844 u8 termination_table[0x1]; 5845 u8 table_miss_action[0x4]; 5846 u8 level[0x8]; 5847 u8 reserved_at_10[0x8]; 5848 u8 log_size[0x8]; 5849 5850 u8 reserved_at_20[0x8]; 5851 u8 table_miss_id[0x18]; 5852 5853 u8 reserved_at_40[0x8]; 5854 u8 lag_master_next_table_id[0x18]; 5855 5856 u8 reserved_at_60[0x60]; 5857 5858 u8 sw_owner_icm_root_1[0x40]; 5859 5860 u8 sw_owner_icm_root_0[0x40]; 5861 5862 }; 5863 5864 struct mlx5_ifc_query_flow_table_out_bits { 5865 u8 status[0x8]; 5866 u8 reserved_at_8[0x18]; 5867 5868 u8 syndrome[0x20]; 5869 5870 u8 reserved_at_40[0x80]; 5871 5872 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5873 }; 5874 5875 struct mlx5_ifc_query_flow_table_in_bits { 5876 u8 opcode[0x10]; 5877 u8 reserved_at_10[0x10]; 5878 5879 u8 reserved_at_20[0x10]; 5880 u8 op_mod[0x10]; 5881 5882 u8 reserved_at_40[0x40]; 5883 5884 u8 table_type[0x8]; 5885 u8 reserved_at_88[0x18]; 5886 5887 u8 reserved_at_a0[0x8]; 5888 u8 table_id[0x18]; 5889 5890 u8 reserved_at_c0[0x140]; 5891 }; 5892 5893 struct mlx5_ifc_query_fte_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_at_8[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_at_40[0x1c0]; 5900 5901 struct mlx5_ifc_flow_context_bits flow_context; 5902 }; 5903 5904 struct mlx5_ifc_query_fte_in_bits { 5905 u8 opcode[0x10]; 5906 u8 reserved_at_10[0x10]; 5907 5908 u8 reserved_at_20[0x10]; 5909 u8 op_mod[0x10]; 5910 5911 u8 reserved_at_40[0x40]; 5912 5913 u8 table_type[0x8]; 5914 u8 reserved_at_88[0x18]; 5915 5916 u8 reserved_at_a0[0x8]; 5917 u8 table_id[0x18]; 5918 5919 u8 reserved_at_c0[0x40]; 5920 5921 u8 flow_index[0x20]; 5922 5923 u8 reserved_at_120[0xe0]; 5924 }; 5925 5926 struct mlx5_ifc_match_definer_format_0_bits { 5927 u8 reserved_at_0[0x100]; 5928 5929 u8 metadata_reg_c_0[0x20]; 5930 5931 u8 metadata_reg_c_1[0x20]; 5932 5933 u8 outer_dmac_47_16[0x20]; 5934 5935 u8 outer_dmac_15_0[0x10]; 5936 u8 outer_ethertype[0x10]; 5937 5938 u8 reserved_at_180[0x1]; 5939 u8 sx_sniffer[0x1]; 5940 u8 functional_lb[0x1]; 5941 u8 outer_ip_frag[0x1]; 5942 u8 outer_qp_type[0x2]; 5943 u8 outer_encap_type[0x2]; 5944 u8 port_number[0x2]; 5945 u8 outer_l3_type[0x2]; 5946 u8 outer_l4_type[0x2]; 5947 u8 outer_first_vlan_type[0x2]; 5948 u8 outer_first_vlan_prio[0x3]; 5949 u8 outer_first_vlan_cfi[0x1]; 5950 u8 outer_first_vlan_vid[0xc]; 5951 5952 u8 outer_l4_type_ext[0x4]; 5953 u8 reserved_at_1a4[0x2]; 5954 u8 outer_ipsec_layer[0x2]; 5955 u8 outer_l2_type[0x2]; 5956 u8 force_lb[0x1]; 5957 u8 outer_l2_ok[0x1]; 5958 u8 outer_l3_ok[0x1]; 5959 u8 outer_l4_ok[0x1]; 5960 u8 outer_second_vlan_type[0x2]; 5961 u8 outer_second_vlan_prio[0x3]; 5962 u8 outer_second_vlan_cfi[0x1]; 5963 u8 outer_second_vlan_vid[0xc]; 5964 5965 u8 outer_smac_47_16[0x20]; 5966 5967 u8 outer_smac_15_0[0x10]; 5968 u8 inner_ipv4_checksum_ok[0x1]; 5969 u8 inner_l4_checksum_ok[0x1]; 5970 u8 outer_ipv4_checksum_ok[0x1]; 5971 u8 outer_l4_checksum_ok[0x1]; 5972 u8 inner_l3_ok[0x1]; 5973 u8 inner_l4_ok[0x1]; 5974 u8 outer_l3_ok_duplicate[0x1]; 5975 u8 outer_l4_ok_duplicate[0x1]; 5976 u8 outer_tcp_cwr[0x1]; 5977 u8 outer_tcp_ece[0x1]; 5978 u8 outer_tcp_urg[0x1]; 5979 u8 outer_tcp_ack[0x1]; 5980 u8 outer_tcp_psh[0x1]; 5981 u8 outer_tcp_rst[0x1]; 5982 u8 outer_tcp_syn[0x1]; 5983 u8 outer_tcp_fin[0x1]; 5984 }; 5985 5986 struct mlx5_ifc_match_definer_format_22_bits { 5987 u8 reserved_at_0[0x100]; 5988 5989 u8 outer_ip_src_addr[0x20]; 5990 5991 u8 outer_ip_dest_addr[0x20]; 5992 5993 u8 outer_l4_sport[0x10]; 5994 u8 outer_l4_dport[0x10]; 5995 5996 u8 reserved_at_160[0x1]; 5997 u8 sx_sniffer[0x1]; 5998 u8 functional_lb[0x1]; 5999 u8 outer_ip_frag[0x1]; 6000 u8 outer_qp_type[0x2]; 6001 u8 outer_encap_type[0x2]; 6002 u8 port_number[0x2]; 6003 u8 outer_l3_type[0x2]; 6004 u8 outer_l4_type[0x2]; 6005 u8 outer_first_vlan_type[0x2]; 6006 u8 outer_first_vlan_prio[0x3]; 6007 u8 outer_first_vlan_cfi[0x1]; 6008 u8 outer_first_vlan_vid[0xc]; 6009 6010 u8 metadata_reg_c_0[0x20]; 6011 6012 u8 outer_dmac_47_16[0x20]; 6013 6014 u8 outer_smac_47_16[0x20]; 6015 6016 u8 outer_smac_15_0[0x10]; 6017 u8 outer_dmac_15_0[0x10]; 6018 }; 6019 6020 struct mlx5_ifc_match_definer_format_23_bits { 6021 u8 reserved_at_0[0x100]; 6022 6023 u8 inner_ip_src_addr[0x20]; 6024 6025 u8 inner_ip_dest_addr[0x20]; 6026 6027 u8 inner_l4_sport[0x10]; 6028 u8 inner_l4_dport[0x10]; 6029 6030 u8 reserved_at_160[0x1]; 6031 u8 sx_sniffer[0x1]; 6032 u8 functional_lb[0x1]; 6033 u8 inner_ip_frag[0x1]; 6034 u8 inner_qp_type[0x2]; 6035 u8 inner_encap_type[0x2]; 6036 u8 port_number[0x2]; 6037 u8 inner_l3_type[0x2]; 6038 u8 inner_l4_type[0x2]; 6039 u8 inner_first_vlan_type[0x2]; 6040 u8 inner_first_vlan_prio[0x3]; 6041 u8 inner_first_vlan_cfi[0x1]; 6042 u8 inner_first_vlan_vid[0xc]; 6043 6044 u8 tunnel_header_0[0x20]; 6045 6046 u8 inner_dmac_47_16[0x20]; 6047 6048 u8 inner_smac_47_16[0x20]; 6049 6050 u8 inner_smac_15_0[0x10]; 6051 u8 inner_dmac_15_0[0x10]; 6052 }; 6053 6054 struct mlx5_ifc_match_definer_format_29_bits { 6055 u8 reserved_at_0[0xc0]; 6056 6057 u8 outer_ip_dest_addr[0x80]; 6058 6059 u8 outer_ip_src_addr[0x80]; 6060 6061 u8 outer_l4_sport[0x10]; 6062 u8 outer_l4_dport[0x10]; 6063 6064 u8 reserved_at_1e0[0x20]; 6065 }; 6066 6067 struct mlx5_ifc_match_definer_format_30_bits { 6068 u8 reserved_at_0[0xa0]; 6069 6070 u8 outer_ip_dest_addr[0x80]; 6071 6072 u8 outer_ip_src_addr[0x80]; 6073 6074 u8 outer_dmac_47_16[0x20]; 6075 6076 u8 outer_smac_47_16[0x20]; 6077 6078 u8 outer_smac_15_0[0x10]; 6079 u8 outer_dmac_15_0[0x10]; 6080 }; 6081 6082 struct mlx5_ifc_match_definer_format_31_bits { 6083 u8 reserved_at_0[0xc0]; 6084 6085 u8 inner_ip_dest_addr[0x80]; 6086 6087 u8 inner_ip_src_addr[0x80]; 6088 6089 u8 inner_l4_sport[0x10]; 6090 u8 inner_l4_dport[0x10]; 6091 6092 u8 reserved_at_1e0[0x20]; 6093 }; 6094 6095 struct mlx5_ifc_match_definer_format_32_bits { 6096 u8 reserved_at_0[0xa0]; 6097 6098 u8 inner_ip_dest_addr[0x80]; 6099 6100 u8 inner_ip_src_addr[0x80]; 6101 6102 u8 inner_dmac_47_16[0x20]; 6103 6104 u8 inner_smac_47_16[0x20]; 6105 6106 u8 inner_smac_15_0[0x10]; 6107 u8 inner_dmac_15_0[0x10]; 6108 }; 6109 6110 struct mlx5_ifc_match_definer_bits { 6111 u8 modify_field_select[0x40]; 6112 6113 u8 reserved_at_40[0x40]; 6114 6115 u8 reserved_at_80[0x10]; 6116 u8 format_id[0x10]; 6117 6118 u8 reserved_at_a0[0x160]; 6119 6120 u8 match_mask[16][0x20]; 6121 }; 6122 6123 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6124 u8 opcode[0x10]; 6125 u8 uid[0x10]; 6126 6127 u8 vhca_tunnel_id[0x10]; 6128 u8 obj_type[0x10]; 6129 6130 u8 obj_id[0x20]; 6131 6132 u8 reserved_at_60[0x3]; 6133 u8 log_obj_range[0x5]; 6134 u8 reserved_at_68[0x18]; 6135 }; 6136 6137 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6138 u8 status[0x8]; 6139 u8 reserved_at_8[0x18]; 6140 6141 u8 syndrome[0x20]; 6142 6143 u8 obj_id[0x20]; 6144 6145 u8 reserved_at_60[0x20]; 6146 }; 6147 6148 struct mlx5_ifc_create_match_definer_in_bits { 6149 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6150 6151 struct mlx5_ifc_match_definer_bits obj_context; 6152 }; 6153 6154 struct mlx5_ifc_create_match_definer_out_bits { 6155 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6156 }; 6157 6158 enum { 6159 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6160 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6161 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6162 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6163 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6164 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6165 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6166 }; 6167 6168 struct mlx5_ifc_query_flow_group_out_bits { 6169 u8 status[0x8]; 6170 u8 reserved_at_8[0x18]; 6171 6172 u8 syndrome[0x20]; 6173 6174 u8 reserved_at_40[0xa0]; 6175 6176 u8 start_flow_index[0x20]; 6177 6178 u8 reserved_at_100[0x20]; 6179 6180 u8 end_flow_index[0x20]; 6181 6182 u8 reserved_at_140[0xa0]; 6183 6184 u8 reserved_at_1e0[0x18]; 6185 u8 match_criteria_enable[0x8]; 6186 6187 struct mlx5_ifc_fte_match_param_bits match_criteria; 6188 6189 u8 reserved_at_1200[0xe00]; 6190 }; 6191 6192 struct mlx5_ifc_query_flow_group_in_bits { 6193 u8 opcode[0x10]; 6194 u8 reserved_at_10[0x10]; 6195 6196 u8 reserved_at_20[0x10]; 6197 u8 op_mod[0x10]; 6198 6199 u8 reserved_at_40[0x40]; 6200 6201 u8 table_type[0x8]; 6202 u8 reserved_at_88[0x18]; 6203 6204 u8 reserved_at_a0[0x8]; 6205 u8 table_id[0x18]; 6206 6207 u8 group_id[0x20]; 6208 6209 u8 reserved_at_e0[0x120]; 6210 }; 6211 6212 struct mlx5_ifc_query_flow_counter_out_bits { 6213 u8 status[0x8]; 6214 u8 reserved_at_8[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 reserved_at_40[0x40]; 6219 6220 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6221 }; 6222 6223 struct mlx5_ifc_query_flow_counter_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_at_10[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 reserved_at_40[0x80]; 6231 6232 u8 clear[0x1]; 6233 u8 reserved_at_c1[0xf]; 6234 u8 num_of_counters[0x10]; 6235 6236 u8 flow_counter_id[0x20]; 6237 }; 6238 6239 struct mlx5_ifc_query_esw_vport_context_out_bits { 6240 u8 status[0x8]; 6241 u8 reserved_at_8[0x18]; 6242 6243 u8 syndrome[0x20]; 6244 6245 u8 reserved_at_40[0x40]; 6246 6247 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6248 }; 6249 6250 struct mlx5_ifc_query_esw_vport_context_in_bits { 6251 u8 opcode[0x10]; 6252 u8 reserved_at_10[0x10]; 6253 6254 u8 reserved_at_20[0x10]; 6255 u8 op_mod[0x10]; 6256 6257 u8 other_vport[0x1]; 6258 u8 reserved_at_41[0xf]; 6259 u8 vport_number[0x10]; 6260 6261 u8 reserved_at_60[0x20]; 6262 }; 6263 6264 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_at_40[0x40]; 6271 }; 6272 6273 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6274 u8 reserved_at_0[0x1b]; 6275 u8 fdb_to_vport_reg_c_id[0x1]; 6276 u8 vport_cvlan_insert[0x1]; 6277 u8 vport_svlan_insert[0x1]; 6278 u8 vport_cvlan_strip[0x1]; 6279 u8 vport_svlan_strip[0x1]; 6280 }; 6281 6282 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6283 u8 opcode[0x10]; 6284 u8 reserved_at_10[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 other_vport[0x1]; 6290 u8 reserved_at_41[0xf]; 6291 u8 vport_number[0x10]; 6292 6293 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6294 6295 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6296 }; 6297 6298 struct mlx5_ifc_query_eq_out_bits { 6299 u8 status[0x8]; 6300 u8 reserved_at_8[0x18]; 6301 6302 u8 syndrome[0x20]; 6303 6304 u8 reserved_at_40[0x40]; 6305 6306 struct mlx5_ifc_eqc_bits eq_context_entry; 6307 6308 u8 reserved_at_280[0x40]; 6309 6310 u8 event_bitmask[0x40]; 6311 6312 u8 reserved_at_300[0x580]; 6313 6314 u8 pas[][0x40]; 6315 }; 6316 6317 struct mlx5_ifc_query_eq_in_bits { 6318 u8 opcode[0x10]; 6319 u8 reserved_at_10[0x10]; 6320 6321 u8 reserved_at_20[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 reserved_at_40[0x18]; 6325 u8 eq_number[0x8]; 6326 6327 u8 reserved_at_60[0x20]; 6328 }; 6329 6330 struct mlx5_ifc_packet_reformat_context_in_bits { 6331 u8 reformat_type[0x8]; 6332 u8 reserved_at_8[0x4]; 6333 u8 reformat_param_0[0x4]; 6334 u8 reserved_at_10[0x6]; 6335 u8 reformat_data_size[0xa]; 6336 6337 u8 reformat_param_1[0x8]; 6338 u8 reserved_at_28[0x8]; 6339 u8 reformat_data[2][0x8]; 6340 6341 u8 more_reformat_data[][0x8]; 6342 }; 6343 6344 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6345 u8 status[0x8]; 6346 u8 reserved_at_8[0x18]; 6347 6348 u8 syndrome[0x20]; 6349 6350 u8 reserved_at_40[0xa0]; 6351 6352 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6353 }; 6354 6355 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_at_10[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 packet_reformat_id[0x20]; 6363 6364 u8 reserved_at_60[0xa0]; 6365 }; 6366 6367 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6368 u8 status[0x8]; 6369 u8 reserved_at_8[0x18]; 6370 6371 u8 syndrome[0x20]; 6372 6373 u8 packet_reformat_id[0x20]; 6374 6375 u8 reserved_at_60[0x20]; 6376 }; 6377 6378 enum { 6379 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6380 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6381 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6382 }; 6383 6384 enum mlx5_reformat_ctx_type { 6385 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6386 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6387 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6388 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6389 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6390 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6391 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6392 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6393 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6394 }; 6395 6396 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6397 u8 opcode[0x10]; 6398 u8 reserved_at_10[0x10]; 6399 6400 u8 reserved_at_20[0x10]; 6401 u8 op_mod[0x10]; 6402 6403 u8 reserved_at_40[0xa0]; 6404 6405 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6406 }; 6407 6408 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6409 u8 status[0x8]; 6410 u8 reserved_at_8[0x18]; 6411 6412 u8 syndrome[0x20]; 6413 6414 u8 reserved_at_40[0x40]; 6415 }; 6416 6417 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6418 u8 opcode[0x10]; 6419 u8 reserved_at_10[0x10]; 6420 6421 u8 reserved_20[0x10]; 6422 u8 op_mod[0x10]; 6423 6424 u8 packet_reformat_id[0x20]; 6425 6426 u8 reserved_60[0x20]; 6427 }; 6428 6429 struct mlx5_ifc_set_action_in_bits { 6430 u8 action_type[0x4]; 6431 u8 field[0xc]; 6432 u8 reserved_at_10[0x3]; 6433 u8 offset[0x5]; 6434 u8 reserved_at_18[0x3]; 6435 u8 length[0x5]; 6436 6437 u8 data[0x20]; 6438 }; 6439 6440 struct mlx5_ifc_add_action_in_bits { 6441 u8 action_type[0x4]; 6442 u8 field[0xc]; 6443 u8 reserved_at_10[0x10]; 6444 6445 u8 data[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_copy_action_in_bits { 6449 u8 action_type[0x4]; 6450 u8 src_field[0xc]; 6451 u8 reserved_at_10[0x3]; 6452 u8 src_offset[0x5]; 6453 u8 reserved_at_18[0x3]; 6454 u8 length[0x5]; 6455 6456 u8 reserved_at_20[0x4]; 6457 u8 dst_field[0xc]; 6458 u8 reserved_at_30[0x3]; 6459 u8 dst_offset[0x5]; 6460 u8 reserved_at_38[0x8]; 6461 }; 6462 6463 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6464 struct mlx5_ifc_set_action_in_bits set_action_in; 6465 struct mlx5_ifc_add_action_in_bits add_action_in; 6466 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6467 u8 reserved_at_0[0x40]; 6468 }; 6469 6470 enum { 6471 MLX5_ACTION_TYPE_SET = 0x1, 6472 MLX5_ACTION_TYPE_ADD = 0x2, 6473 MLX5_ACTION_TYPE_COPY = 0x3, 6474 }; 6475 6476 enum { 6477 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6478 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6479 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6480 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6481 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6482 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6483 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6484 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6485 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6486 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6487 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6488 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6489 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6490 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6491 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6492 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6493 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6494 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6495 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6496 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6497 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6498 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6499 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6500 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6501 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6502 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6503 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6504 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6505 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6506 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6509 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6511 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6512 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6513 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6514 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6515 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6516 }; 6517 6518 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6519 u8 status[0x8]; 6520 u8 reserved_at_8[0x18]; 6521 6522 u8 syndrome[0x20]; 6523 6524 u8 modify_header_id[0x20]; 6525 6526 u8 reserved_at_60[0x20]; 6527 }; 6528 6529 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6530 u8 opcode[0x10]; 6531 u8 reserved_at_10[0x10]; 6532 6533 u8 reserved_at_20[0x10]; 6534 u8 op_mod[0x10]; 6535 6536 u8 reserved_at_40[0x20]; 6537 6538 u8 table_type[0x8]; 6539 u8 reserved_at_68[0x10]; 6540 u8 num_of_actions[0x8]; 6541 6542 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6543 }; 6544 6545 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6546 u8 status[0x8]; 6547 u8 reserved_at_8[0x18]; 6548 6549 u8 syndrome[0x20]; 6550 6551 u8 reserved_at_40[0x40]; 6552 }; 6553 6554 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6555 u8 opcode[0x10]; 6556 u8 reserved_at_10[0x10]; 6557 6558 u8 reserved_at_20[0x10]; 6559 u8 op_mod[0x10]; 6560 6561 u8 modify_header_id[0x20]; 6562 6563 u8 reserved_at_60[0x20]; 6564 }; 6565 6566 struct mlx5_ifc_query_modify_header_context_in_bits { 6567 u8 opcode[0x10]; 6568 u8 uid[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 modify_header_id[0x20]; 6574 6575 u8 reserved_at_60[0xa0]; 6576 }; 6577 6578 struct mlx5_ifc_query_dct_out_bits { 6579 u8 status[0x8]; 6580 u8 reserved_at_8[0x18]; 6581 6582 u8 syndrome[0x20]; 6583 6584 u8 reserved_at_40[0x40]; 6585 6586 struct mlx5_ifc_dctc_bits dct_context_entry; 6587 6588 u8 reserved_at_280[0x180]; 6589 }; 6590 6591 struct mlx5_ifc_query_dct_in_bits { 6592 u8 opcode[0x10]; 6593 u8 reserved_at_10[0x10]; 6594 6595 u8 reserved_at_20[0x10]; 6596 u8 op_mod[0x10]; 6597 6598 u8 reserved_at_40[0x8]; 6599 u8 dctn[0x18]; 6600 6601 u8 reserved_at_60[0x20]; 6602 }; 6603 6604 struct mlx5_ifc_query_cq_out_bits { 6605 u8 status[0x8]; 6606 u8 reserved_at_8[0x18]; 6607 6608 u8 syndrome[0x20]; 6609 6610 u8 reserved_at_40[0x40]; 6611 6612 struct mlx5_ifc_cqc_bits cq_context; 6613 6614 u8 reserved_at_280[0x600]; 6615 6616 u8 pas[][0x40]; 6617 }; 6618 6619 struct mlx5_ifc_query_cq_in_bits { 6620 u8 opcode[0x10]; 6621 u8 reserved_at_10[0x10]; 6622 6623 u8 reserved_at_20[0x10]; 6624 u8 op_mod[0x10]; 6625 6626 u8 reserved_at_40[0x8]; 6627 u8 cqn[0x18]; 6628 6629 u8 reserved_at_60[0x20]; 6630 }; 6631 6632 struct mlx5_ifc_query_cong_status_out_bits { 6633 u8 status[0x8]; 6634 u8 reserved_at_8[0x18]; 6635 6636 u8 syndrome[0x20]; 6637 6638 u8 reserved_at_40[0x20]; 6639 6640 u8 enable[0x1]; 6641 u8 tag_enable[0x1]; 6642 u8 reserved_at_62[0x1e]; 6643 }; 6644 6645 struct mlx5_ifc_query_cong_status_in_bits { 6646 u8 opcode[0x10]; 6647 u8 reserved_at_10[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 reserved_at_40[0x18]; 6653 u8 priority[0x4]; 6654 u8 cong_protocol[0x4]; 6655 6656 u8 reserved_at_60[0x20]; 6657 }; 6658 6659 struct mlx5_ifc_query_cong_statistics_out_bits { 6660 u8 status[0x8]; 6661 u8 reserved_at_8[0x18]; 6662 6663 u8 syndrome[0x20]; 6664 6665 u8 reserved_at_40[0x40]; 6666 6667 u8 rp_cur_flows[0x20]; 6668 6669 u8 sum_flows[0x20]; 6670 6671 u8 rp_cnp_ignored_high[0x20]; 6672 6673 u8 rp_cnp_ignored_low[0x20]; 6674 6675 u8 rp_cnp_handled_high[0x20]; 6676 6677 u8 rp_cnp_handled_low[0x20]; 6678 6679 u8 reserved_at_140[0x100]; 6680 6681 u8 time_stamp_high[0x20]; 6682 6683 u8 time_stamp_low[0x20]; 6684 6685 u8 accumulators_period[0x20]; 6686 6687 u8 np_ecn_marked_roce_packets_high[0x20]; 6688 6689 u8 np_ecn_marked_roce_packets_low[0x20]; 6690 6691 u8 np_cnp_sent_high[0x20]; 6692 6693 u8 np_cnp_sent_low[0x20]; 6694 6695 u8 reserved_at_320[0x560]; 6696 }; 6697 6698 struct mlx5_ifc_query_cong_statistics_in_bits { 6699 u8 opcode[0x10]; 6700 u8 reserved_at_10[0x10]; 6701 6702 u8 reserved_at_20[0x10]; 6703 u8 op_mod[0x10]; 6704 6705 u8 clear[0x1]; 6706 u8 reserved_at_41[0x1f]; 6707 6708 u8 reserved_at_60[0x20]; 6709 }; 6710 6711 struct mlx5_ifc_query_cong_params_out_bits { 6712 u8 status[0x8]; 6713 u8 reserved_at_8[0x18]; 6714 6715 u8 syndrome[0x20]; 6716 6717 u8 reserved_at_40[0x40]; 6718 6719 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6720 }; 6721 6722 struct mlx5_ifc_query_cong_params_in_bits { 6723 u8 opcode[0x10]; 6724 u8 reserved_at_10[0x10]; 6725 6726 u8 reserved_at_20[0x10]; 6727 u8 op_mod[0x10]; 6728 6729 u8 reserved_at_40[0x1c]; 6730 u8 cong_protocol[0x4]; 6731 6732 u8 reserved_at_60[0x20]; 6733 }; 6734 6735 struct mlx5_ifc_query_adapter_out_bits { 6736 u8 status[0x8]; 6737 u8 reserved_at_8[0x18]; 6738 6739 u8 syndrome[0x20]; 6740 6741 u8 reserved_at_40[0x40]; 6742 6743 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6744 }; 6745 6746 struct mlx5_ifc_query_adapter_in_bits { 6747 u8 opcode[0x10]; 6748 u8 reserved_at_10[0x10]; 6749 6750 u8 reserved_at_20[0x10]; 6751 u8 op_mod[0x10]; 6752 6753 u8 reserved_at_40[0x40]; 6754 }; 6755 6756 struct mlx5_ifc_qp_2rst_out_bits { 6757 u8 status[0x8]; 6758 u8 reserved_at_8[0x18]; 6759 6760 u8 syndrome[0x20]; 6761 6762 u8 reserved_at_40[0x40]; 6763 }; 6764 6765 struct mlx5_ifc_qp_2rst_in_bits { 6766 u8 opcode[0x10]; 6767 u8 uid[0x10]; 6768 6769 u8 reserved_at_20[0x10]; 6770 u8 op_mod[0x10]; 6771 6772 u8 reserved_at_40[0x8]; 6773 u8 qpn[0x18]; 6774 6775 u8 reserved_at_60[0x20]; 6776 }; 6777 6778 struct mlx5_ifc_qp_2err_out_bits { 6779 u8 status[0x8]; 6780 u8 reserved_at_8[0x18]; 6781 6782 u8 syndrome[0x20]; 6783 6784 u8 reserved_at_40[0x40]; 6785 }; 6786 6787 struct mlx5_ifc_qp_2err_in_bits { 6788 u8 opcode[0x10]; 6789 u8 uid[0x10]; 6790 6791 u8 reserved_at_20[0x10]; 6792 u8 op_mod[0x10]; 6793 6794 u8 reserved_at_40[0x8]; 6795 u8 qpn[0x18]; 6796 6797 u8 reserved_at_60[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_page_fault_resume_out_bits { 6801 u8 status[0x8]; 6802 u8 reserved_at_8[0x18]; 6803 6804 u8 syndrome[0x20]; 6805 6806 u8 reserved_at_40[0x40]; 6807 }; 6808 6809 struct mlx5_ifc_page_fault_resume_in_bits { 6810 u8 opcode[0x10]; 6811 u8 reserved_at_10[0x10]; 6812 6813 u8 reserved_at_20[0x10]; 6814 u8 op_mod[0x10]; 6815 6816 u8 error[0x1]; 6817 u8 reserved_at_41[0x4]; 6818 u8 page_fault_type[0x3]; 6819 u8 wq_number[0x18]; 6820 6821 u8 reserved_at_60[0x8]; 6822 u8 token[0x18]; 6823 }; 6824 6825 struct mlx5_ifc_nop_out_bits { 6826 u8 status[0x8]; 6827 u8 reserved_at_8[0x18]; 6828 6829 u8 syndrome[0x20]; 6830 6831 u8 reserved_at_40[0x40]; 6832 }; 6833 6834 struct mlx5_ifc_nop_in_bits { 6835 u8 opcode[0x10]; 6836 u8 reserved_at_10[0x10]; 6837 6838 u8 reserved_at_20[0x10]; 6839 u8 op_mod[0x10]; 6840 6841 u8 reserved_at_40[0x40]; 6842 }; 6843 6844 struct mlx5_ifc_modify_vport_state_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x40]; 6851 }; 6852 6853 struct mlx5_ifc_modify_vport_state_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_at_10[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 other_vport[0x1]; 6861 u8 reserved_at_41[0xf]; 6862 u8 vport_number[0x10]; 6863 6864 u8 reserved_at_60[0x18]; 6865 u8 admin_state[0x4]; 6866 u8 reserved_at_7c[0x4]; 6867 }; 6868 6869 struct mlx5_ifc_modify_tis_out_bits { 6870 u8 status[0x8]; 6871 u8 reserved_at_8[0x18]; 6872 6873 u8 syndrome[0x20]; 6874 6875 u8 reserved_at_40[0x40]; 6876 }; 6877 6878 struct mlx5_ifc_modify_tis_bitmask_bits { 6879 u8 reserved_at_0[0x20]; 6880 6881 u8 reserved_at_20[0x1d]; 6882 u8 lag_tx_port_affinity[0x1]; 6883 u8 strict_lag_tx_port_affinity[0x1]; 6884 u8 prio[0x1]; 6885 }; 6886 6887 struct mlx5_ifc_modify_tis_in_bits { 6888 u8 opcode[0x10]; 6889 u8 uid[0x10]; 6890 6891 u8 reserved_at_20[0x10]; 6892 u8 op_mod[0x10]; 6893 6894 u8 reserved_at_40[0x8]; 6895 u8 tisn[0x18]; 6896 6897 u8 reserved_at_60[0x20]; 6898 6899 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6900 6901 u8 reserved_at_c0[0x40]; 6902 6903 struct mlx5_ifc_tisc_bits ctx; 6904 }; 6905 6906 struct mlx5_ifc_modify_tir_bitmask_bits { 6907 u8 reserved_at_0[0x20]; 6908 6909 u8 reserved_at_20[0x1b]; 6910 u8 self_lb_en[0x1]; 6911 u8 reserved_at_3c[0x1]; 6912 u8 hash[0x1]; 6913 u8 reserved_at_3e[0x1]; 6914 u8 packet_merge[0x1]; 6915 }; 6916 6917 struct mlx5_ifc_modify_tir_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x40]; 6924 }; 6925 6926 struct mlx5_ifc_modify_tir_in_bits { 6927 u8 opcode[0x10]; 6928 u8 uid[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 reserved_at_40[0x8]; 6934 u8 tirn[0x18]; 6935 6936 u8 reserved_at_60[0x20]; 6937 6938 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6939 6940 u8 reserved_at_c0[0x40]; 6941 6942 struct mlx5_ifc_tirc_bits ctx; 6943 }; 6944 6945 struct mlx5_ifc_modify_sq_out_bits { 6946 u8 status[0x8]; 6947 u8 reserved_at_8[0x18]; 6948 6949 u8 syndrome[0x20]; 6950 6951 u8 reserved_at_40[0x40]; 6952 }; 6953 6954 struct mlx5_ifc_modify_sq_in_bits { 6955 u8 opcode[0x10]; 6956 u8 uid[0x10]; 6957 6958 u8 reserved_at_20[0x10]; 6959 u8 op_mod[0x10]; 6960 6961 u8 sq_state[0x4]; 6962 u8 reserved_at_44[0x4]; 6963 u8 sqn[0x18]; 6964 6965 u8 reserved_at_60[0x20]; 6966 6967 u8 modify_bitmask[0x40]; 6968 6969 u8 reserved_at_c0[0x40]; 6970 6971 struct mlx5_ifc_sqc_bits ctx; 6972 }; 6973 6974 struct mlx5_ifc_modify_scheduling_element_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x1c0]; 6981 }; 6982 6983 enum { 6984 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6985 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6986 }; 6987 6988 struct mlx5_ifc_modify_scheduling_element_in_bits { 6989 u8 opcode[0x10]; 6990 u8 reserved_at_10[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 scheduling_hierarchy[0x8]; 6996 u8 reserved_at_48[0x18]; 6997 6998 u8 scheduling_element_id[0x20]; 6999 7000 u8 reserved_at_80[0x20]; 7001 7002 u8 modify_bitmask[0x20]; 7003 7004 u8 reserved_at_c0[0x40]; 7005 7006 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7007 7008 u8 reserved_at_300[0x100]; 7009 }; 7010 7011 struct mlx5_ifc_modify_rqt_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_at_8[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_at_40[0x40]; 7018 }; 7019 7020 struct mlx5_ifc_rqt_bitmask_bits { 7021 u8 reserved_at_0[0x20]; 7022 7023 u8 reserved_at_20[0x1f]; 7024 u8 rqn_list[0x1]; 7025 }; 7026 7027 struct mlx5_ifc_modify_rqt_in_bits { 7028 u8 opcode[0x10]; 7029 u8 uid[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 reserved_at_40[0x8]; 7035 u8 rqtn[0x18]; 7036 7037 u8 reserved_at_60[0x20]; 7038 7039 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7040 7041 u8 reserved_at_c0[0x40]; 7042 7043 struct mlx5_ifc_rqtc_bits ctx; 7044 }; 7045 7046 struct mlx5_ifc_modify_rq_out_bits { 7047 u8 status[0x8]; 7048 u8 reserved_at_8[0x18]; 7049 7050 u8 syndrome[0x20]; 7051 7052 u8 reserved_at_40[0x40]; 7053 }; 7054 7055 enum { 7056 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7057 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7058 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7059 }; 7060 7061 struct mlx5_ifc_modify_rq_in_bits { 7062 u8 opcode[0x10]; 7063 u8 uid[0x10]; 7064 7065 u8 reserved_at_20[0x10]; 7066 u8 op_mod[0x10]; 7067 7068 u8 rq_state[0x4]; 7069 u8 reserved_at_44[0x4]; 7070 u8 rqn[0x18]; 7071 7072 u8 reserved_at_60[0x20]; 7073 7074 u8 modify_bitmask[0x40]; 7075 7076 u8 reserved_at_c0[0x40]; 7077 7078 struct mlx5_ifc_rqc_bits ctx; 7079 }; 7080 7081 struct mlx5_ifc_modify_rmp_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_at_8[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_at_40[0x40]; 7088 }; 7089 7090 struct mlx5_ifc_rmp_bitmask_bits { 7091 u8 reserved_at_0[0x20]; 7092 7093 u8 reserved_at_20[0x1f]; 7094 u8 lwm[0x1]; 7095 }; 7096 7097 struct mlx5_ifc_modify_rmp_in_bits { 7098 u8 opcode[0x10]; 7099 u8 uid[0x10]; 7100 7101 u8 reserved_at_20[0x10]; 7102 u8 op_mod[0x10]; 7103 7104 u8 rmp_state[0x4]; 7105 u8 reserved_at_44[0x4]; 7106 u8 rmpn[0x18]; 7107 7108 u8 reserved_at_60[0x20]; 7109 7110 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7111 7112 u8 reserved_at_c0[0x40]; 7113 7114 struct mlx5_ifc_rmpc_bits ctx; 7115 }; 7116 7117 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7118 u8 status[0x8]; 7119 u8 reserved_at_8[0x18]; 7120 7121 u8 syndrome[0x20]; 7122 7123 u8 reserved_at_40[0x40]; 7124 }; 7125 7126 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7127 u8 reserved_at_0[0x12]; 7128 u8 affiliation[0x1]; 7129 u8 reserved_at_13[0x1]; 7130 u8 disable_uc_local_lb[0x1]; 7131 u8 disable_mc_local_lb[0x1]; 7132 u8 node_guid[0x1]; 7133 u8 port_guid[0x1]; 7134 u8 min_inline[0x1]; 7135 u8 mtu[0x1]; 7136 u8 change_event[0x1]; 7137 u8 promisc[0x1]; 7138 u8 permanent_address[0x1]; 7139 u8 addresses_list[0x1]; 7140 u8 roce_en[0x1]; 7141 u8 reserved_at_1f[0x1]; 7142 }; 7143 7144 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7145 u8 opcode[0x10]; 7146 u8 reserved_at_10[0x10]; 7147 7148 u8 reserved_at_20[0x10]; 7149 u8 op_mod[0x10]; 7150 7151 u8 other_vport[0x1]; 7152 u8 reserved_at_41[0xf]; 7153 u8 vport_number[0x10]; 7154 7155 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7156 7157 u8 reserved_at_80[0x780]; 7158 7159 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7160 }; 7161 7162 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7163 u8 status[0x8]; 7164 u8 reserved_at_8[0x18]; 7165 7166 u8 syndrome[0x20]; 7167 7168 u8 reserved_at_40[0x40]; 7169 }; 7170 7171 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7172 u8 opcode[0x10]; 7173 u8 reserved_at_10[0x10]; 7174 7175 u8 reserved_at_20[0x10]; 7176 u8 op_mod[0x10]; 7177 7178 u8 other_vport[0x1]; 7179 u8 reserved_at_41[0xb]; 7180 u8 port_num[0x4]; 7181 u8 vport_number[0x10]; 7182 7183 u8 reserved_at_60[0x20]; 7184 7185 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7186 }; 7187 7188 struct mlx5_ifc_modify_cq_out_bits { 7189 u8 status[0x8]; 7190 u8 reserved_at_8[0x18]; 7191 7192 u8 syndrome[0x20]; 7193 7194 u8 reserved_at_40[0x40]; 7195 }; 7196 7197 enum { 7198 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7199 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7200 }; 7201 7202 struct mlx5_ifc_modify_cq_in_bits { 7203 u8 opcode[0x10]; 7204 u8 uid[0x10]; 7205 7206 u8 reserved_at_20[0x10]; 7207 u8 op_mod[0x10]; 7208 7209 u8 reserved_at_40[0x8]; 7210 u8 cqn[0x18]; 7211 7212 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7213 7214 struct mlx5_ifc_cqc_bits cq_context; 7215 7216 u8 reserved_at_280[0x60]; 7217 7218 u8 cq_umem_valid[0x1]; 7219 u8 reserved_at_2e1[0x1f]; 7220 7221 u8 reserved_at_300[0x580]; 7222 7223 u8 pas[][0x40]; 7224 }; 7225 7226 struct mlx5_ifc_modify_cong_status_out_bits { 7227 u8 status[0x8]; 7228 u8 reserved_at_8[0x18]; 7229 7230 u8 syndrome[0x20]; 7231 7232 u8 reserved_at_40[0x40]; 7233 }; 7234 7235 struct mlx5_ifc_modify_cong_status_in_bits { 7236 u8 opcode[0x10]; 7237 u8 reserved_at_10[0x10]; 7238 7239 u8 reserved_at_20[0x10]; 7240 u8 op_mod[0x10]; 7241 7242 u8 reserved_at_40[0x18]; 7243 u8 priority[0x4]; 7244 u8 cong_protocol[0x4]; 7245 7246 u8 enable[0x1]; 7247 u8 tag_enable[0x1]; 7248 u8 reserved_at_62[0x1e]; 7249 }; 7250 7251 struct mlx5_ifc_modify_cong_params_out_bits { 7252 u8 status[0x8]; 7253 u8 reserved_at_8[0x18]; 7254 7255 u8 syndrome[0x20]; 7256 7257 u8 reserved_at_40[0x40]; 7258 }; 7259 7260 struct mlx5_ifc_modify_cong_params_in_bits { 7261 u8 opcode[0x10]; 7262 u8 reserved_at_10[0x10]; 7263 7264 u8 reserved_at_20[0x10]; 7265 u8 op_mod[0x10]; 7266 7267 u8 reserved_at_40[0x1c]; 7268 u8 cong_protocol[0x4]; 7269 7270 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7271 7272 u8 reserved_at_80[0x80]; 7273 7274 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7275 }; 7276 7277 struct mlx5_ifc_manage_pages_out_bits { 7278 u8 status[0x8]; 7279 u8 reserved_at_8[0x18]; 7280 7281 u8 syndrome[0x20]; 7282 7283 u8 output_num_entries[0x20]; 7284 7285 u8 reserved_at_60[0x20]; 7286 7287 u8 pas[][0x40]; 7288 }; 7289 7290 enum { 7291 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7292 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7293 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7294 }; 7295 7296 struct mlx5_ifc_manage_pages_in_bits { 7297 u8 opcode[0x10]; 7298 u8 reserved_at_10[0x10]; 7299 7300 u8 reserved_at_20[0x10]; 7301 u8 op_mod[0x10]; 7302 7303 u8 embedded_cpu_function[0x1]; 7304 u8 reserved_at_41[0xf]; 7305 u8 function_id[0x10]; 7306 7307 u8 input_num_entries[0x20]; 7308 7309 u8 pas[][0x40]; 7310 }; 7311 7312 struct mlx5_ifc_mad_ifc_out_bits { 7313 u8 status[0x8]; 7314 u8 reserved_at_8[0x18]; 7315 7316 u8 syndrome[0x20]; 7317 7318 u8 reserved_at_40[0x40]; 7319 7320 u8 response_mad_packet[256][0x8]; 7321 }; 7322 7323 struct mlx5_ifc_mad_ifc_in_bits { 7324 u8 opcode[0x10]; 7325 u8 reserved_at_10[0x10]; 7326 7327 u8 reserved_at_20[0x10]; 7328 u8 op_mod[0x10]; 7329 7330 u8 remote_lid[0x10]; 7331 u8 reserved_at_50[0x8]; 7332 u8 port[0x8]; 7333 7334 u8 reserved_at_60[0x20]; 7335 7336 u8 mad[256][0x8]; 7337 }; 7338 7339 struct mlx5_ifc_init_hca_out_bits { 7340 u8 status[0x8]; 7341 u8 reserved_at_8[0x18]; 7342 7343 u8 syndrome[0x20]; 7344 7345 u8 reserved_at_40[0x40]; 7346 }; 7347 7348 struct mlx5_ifc_init_hca_in_bits { 7349 u8 opcode[0x10]; 7350 u8 reserved_at_10[0x10]; 7351 7352 u8 reserved_at_20[0x10]; 7353 u8 op_mod[0x10]; 7354 7355 u8 reserved_at_40[0x20]; 7356 7357 u8 reserved_at_60[0x2]; 7358 u8 sw_vhca_id[0xe]; 7359 u8 reserved_at_70[0x10]; 7360 7361 u8 sw_owner_id[4][0x20]; 7362 }; 7363 7364 struct mlx5_ifc_init2rtr_qp_out_bits { 7365 u8 status[0x8]; 7366 u8 reserved_at_8[0x18]; 7367 7368 u8 syndrome[0x20]; 7369 7370 u8 reserved_at_40[0x20]; 7371 u8 ece[0x20]; 7372 }; 7373 7374 struct mlx5_ifc_init2rtr_qp_in_bits { 7375 u8 opcode[0x10]; 7376 u8 uid[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 reserved_at_40[0x8]; 7382 u8 qpn[0x18]; 7383 7384 u8 reserved_at_60[0x20]; 7385 7386 u8 opt_param_mask[0x20]; 7387 7388 u8 ece[0x20]; 7389 7390 struct mlx5_ifc_qpc_bits qpc; 7391 7392 u8 reserved_at_800[0x80]; 7393 }; 7394 7395 struct mlx5_ifc_init2init_qp_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_at_8[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_at_40[0x20]; 7402 u8 ece[0x20]; 7403 }; 7404 7405 struct mlx5_ifc_init2init_qp_in_bits { 7406 u8 opcode[0x10]; 7407 u8 uid[0x10]; 7408 7409 u8 reserved_at_20[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 reserved_at_40[0x8]; 7413 u8 qpn[0x18]; 7414 7415 u8 reserved_at_60[0x20]; 7416 7417 u8 opt_param_mask[0x20]; 7418 7419 u8 ece[0x20]; 7420 7421 struct mlx5_ifc_qpc_bits qpc; 7422 7423 u8 reserved_at_800[0x80]; 7424 }; 7425 7426 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7427 u8 status[0x8]; 7428 u8 reserved_at_8[0x18]; 7429 7430 u8 syndrome[0x20]; 7431 7432 u8 reserved_at_40[0x40]; 7433 7434 u8 packet_headers_log[128][0x8]; 7435 7436 u8 packet_syndrome[64][0x8]; 7437 }; 7438 7439 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7440 u8 opcode[0x10]; 7441 u8 reserved_at_10[0x10]; 7442 7443 u8 reserved_at_20[0x10]; 7444 u8 op_mod[0x10]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_gen_eqe_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_at_10[0x10]; 7452 7453 u8 reserved_at_20[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_at_40[0x18]; 7457 u8 eq_number[0x8]; 7458 7459 u8 reserved_at_60[0x20]; 7460 7461 u8 eqe[64][0x8]; 7462 }; 7463 7464 struct mlx5_ifc_gen_eq_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_at_8[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 reserved_at_40[0x40]; 7471 }; 7472 7473 struct mlx5_ifc_enable_hca_out_bits { 7474 u8 status[0x8]; 7475 u8 reserved_at_8[0x18]; 7476 7477 u8 syndrome[0x20]; 7478 7479 u8 reserved_at_40[0x20]; 7480 }; 7481 7482 struct mlx5_ifc_enable_hca_in_bits { 7483 u8 opcode[0x10]; 7484 u8 reserved_at_10[0x10]; 7485 7486 u8 reserved_at_20[0x10]; 7487 u8 op_mod[0x10]; 7488 7489 u8 embedded_cpu_function[0x1]; 7490 u8 reserved_at_41[0xf]; 7491 u8 function_id[0x10]; 7492 7493 u8 reserved_at_60[0x20]; 7494 }; 7495 7496 struct mlx5_ifc_drain_dct_out_bits { 7497 u8 status[0x8]; 7498 u8 reserved_at_8[0x18]; 7499 7500 u8 syndrome[0x20]; 7501 7502 u8 reserved_at_40[0x40]; 7503 }; 7504 7505 struct mlx5_ifc_drain_dct_in_bits { 7506 u8 opcode[0x10]; 7507 u8 uid[0x10]; 7508 7509 u8 reserved_at_20[0x10]; 7510 u8 op_mod[0x10]; 7511 7512 u8 reserved_at_40[0x8]; 7513 u8 dctn[0x18]; 7514 7515 u8 reserved_at_60[0x20]; 7516 }; 7517 7518 struct mlx5_ifc_disable_hca_out_bits { 7519 u8 status[0x8]; 7520 u8 reserved_at_8[0x18]; 7521 7522 u8 syndrome[0x20]; 7523 7524 u8 reserved_at_40[0x20]; 7525 }; 7526 7527 struct mlx5_ifc_disable_hca_in_bits { 7528 u8 opcode[0x10]; 7529 u8 reserved_at_10[0x10]; 7530 7531 u8 reserved_at_20[0x10]; 7532 u8 op_mod[0x10]; 7533 7534 u8 embedded_cpu_function[0x1]; 7535 u8 reserved_at_41[0xf]; 7536 u8 function_id[0x10]; 7537 7538 u8 reserved_at_60[0x20]; 7539 }; 7540 7541 struct mlx5_ifc_detach_from_mcg_out_bits { 7542 u8 status[0x8]; 7543 u8 reserved_at_8[0x18]; 7544 7545 u8 syndrome[0x20]; 7546 7547 u8 reserved_at_40[0x40]; 7548 }; 7549 7550 struct mlx5_ifc_detach_from_mcg_in_bits { 7551 u8 opcode[0x10]; 7552 u8 uid[0x10]; 7553 7554 u8 reserved_at_20[0x10]; 7555 u8 op_mod[0x10]; 7556 7557 u8 reserved_at_40[0x8]; 7558 u8 qpn[0x18]; 7559 7560 u8 reserved_at_60[0x20]; 7561 7562 u8 multicast_gid[16][0x8]; 7563 }; 7564 7565 struct mlx5_ifc_destroy_xrq_out_bits { 7566 u8 status[0x8]; 7567 u8 reserved_at_8[0x18]; 7568 7569 u8 syndrome[0x20]; 7570 7571 u8 reserved_at_40[0x40]; 7572 }; 7573 7574 struct mlx5_ifc_destroy_xrq_in_bits { 7575 u8 opcode[0x10]; 7576 u8 uid[0x10]; 7577 7578 u8 reserved_at_20[0x10]; 7579 u8 op_mod[0x10]; 7580 7581 u8 reserved_at_40[0x8]; 7582 u8 xrqn[0x18]; 7583 7584 u8 reserved_at_60[0x20]; 7585 }; 7586 7587 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7588 u8 status[0x8]; 7589 u8 reserved_at_8[0x18]; 7590 7591 u8 syndrome[0x20]; 7592 7593 u8 reserved_at_40[0x40]; 7594 }; 7595 7596 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7597 u8 opcode[0x10]; 7598 u8 uid[0x10]; 7599 7600 u8 reserved_at_20[0x10]; 7601 u8 op_mod[0x10]; 7602 7603 u8 reserved_at_40[0x8]; 7604 u8 xrc_srqn[0x18]; 7605 7606 u8 reserved_at_60[0x20]; 7607 }; 7608 7609 struct mlx5_ifc_destroy_tis_out_bits { 7610 u8 status[0x8]; 7611 u8 reserved_at_8[0x18]; 7612 7613 u8 syndrome[0x20]; 7614 7615 u8 reserved_at_40[0x40]; 7616 }; 7617 7618 struct mlx5_ifc_destroy_tis_in_bits { 7619 u8 opcode[0x10]; 7620 u8 uid[0x10]; 7621 7622 u8 reserved_at_20[0x10]; 7623 u8 op_mod[0x10]; 7624 7625 u8 reserved_at_40[0x8]; 7626 u8 tisn[0x18]; 7627 7628 u8 reserved_at_60[0x20]; 7629 }; 7630 7631 struct mlx5_ifc_destroy_tir_out_bits { 7632 u8 status[0x8]; 7633 u8 reserved_at_8[0x18]; 7634 7635 u8 syndrome[0x20]; 7636 7637 u8 reserved_at_40[0x40]; 7638 }; 7639 7640 struct mlx5_ifc_destroy_tir_in_bits { 7641 u8 opcode[0x10]; 7642 u8 uid[0x10]; 7643 7644 u8 reserved_at_20[0x10]; 7645 u8 op_mod[0x10]; 7646 7647 u8 reserved_at_40[0x8]; 7648 u8 tirn[0x18]; 7649 7650 u8 reserved_at_60[0x20]; 7651 }; 7652 7653 struct mlx5_ifc_destroy_srq_out_bits { 7654 u8 status[0x8]; 7655 u8 reserved_at_8[0x18]; 7656 7657 u8 syndrome[0x20]; 7658 7659 u8 reserved_at_40[0x40]; 7660 }; 7661 7662 struct mlx5_ifc_destroy_srq_in_bits { 7663 u8 opcode[0x10]; 7664 u8 uid[0x10]; 7665 7666 u8 reserved_at_20[0x10]; 7667 u8 op_mod[0x10]; 7668 7669 u8 reserved_at_40[0x8]; 7670 u8 srqn[0x18]; 7671 7672 u8 reserved_at_60[0x20]; 7673 }; 7674 7675 struct mlx5_ifc_destroy_sq_out_bits { 7676 u8 status[0x8]; 7677 u8 reserved_at_8[0x18]; 7678 7679 u8 syndrome[0x20]; 7680 7681 u8 reserved_at_40[0x40]; 7682 }; 7683 7684 struct mlx5_ifc_destroy_sq_in_bits { 7685 u8 opcode[0x10]; 7686 u8 uid[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 u8 reserved_at_40[0x8]; 7692 u8 sqn[0x18]; 7693 7694 u8 reserved_at_60[0x20]; 7695 }; 7696 7697 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x1c0]; 7704 }; 7705 7706 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 scheduling_hierarchy[0x8]; 7714 u8 reserved_at_48[0x18]; 7715 7716 u8 scheduling_element_id[0x20]; 7717 7718 u8 reserved_at_80[0x180]; 7719 }; 7720 7721 struct mlx5_ifc_destroy_rqt_out_bits { 7722 u8 status[0x8]; 7723 u8 reserved_at_8[0x18]; 7724 7725 u8 syndrome[0x20]; 7726 7727 u8 reserved_at_40[0x40]; 7728 }; 7729 7730 struct mlx5_ifc_destroy_rqt_in_bits { 7731 u8 opcode[0x10]; 7732 u8 uid[0x10]; 7733 7734 u8 reserved_at_20[0x10]; 7735 u8 op_mod[0x10]; 7736 7737 u8 reserved_at_40[0x8]; 7738 u8 rqtn[0x18]; 7739 7740 u8 reserved_at_60[0x20]; 7741 }; 7742 7743 struct mlx5_ifc_destroy_rq_out_bits { 7744 u8 status[0x8]; 7745 u8 reserved_at_8[0x18]; 7746 7747 u8 syndrome[0x20]; 7748 7749 u8 reserved_at_40[0x40]; 7750 }; 7751 7752 struct mlx5_ifc_destroy_rq_in_bits { 7753 u8 opcode[0x10]; 7754 u8 uid[0x10]; 7755 7756 u8 reserved_at_20[0x10]; 7757 u8 op_mod[0x10]; 7758 7759 u8 reserved_at_40[0x8]; 7760 u8 rqn[0x18]; 7761 7762 u8 reserved_at_60[0x20]; 7763 }; 7764 7765 struct mlx5_ifc_set_delay_drop_params_in_bits { 7766 u8 opcode[0x10]; 7767 u8 reserved_at_10[0x10]; 7768 7769 u8 reserved_at_20[0x10]; 7770 u8 op_mod[0x10]; 7771 7772 u8 reserved_at_40[0x20]; 7773 7774 u8 reserved_at_60[0x10]; 7775 u8 delay_drop_timeout[0x10]; 7776 }; 7777 7778 struct mlx5_ifc_set_delay_drop_params_out_bits { 7779 u8 status[0x8]; 7780 u8 reserved_at_8[0x18]; 7781 7782 u8 syndrome[0x20]; 7783 7784 u8 reserved_at_40[0x40]; 7785 }; 7786 7787 struct mlx5_ifc_destroy_rmp_out_bits { 7788 u8 status[0x8]; 7789 u8 reserved_at_8[0x18]; 7790 7791 u8 syndrome[0x20]; 7792 7793 u8 reserved_at_40[0x40]; 7794 }; 7795 7796 struct mlx5_ifc_destroy_rmp_in_bits { 7797 u8 opcode[0x10]; 7798 u8 uid[0x10]; 7799 7800 u8 reserved_at_20[0x10]; 7801 u8 op_mod[0x10]; 7802 7803 u8 reserved_at_40[0x8]; 7804 u8 rmpn[0x18]; 7805 7806 u8 reserved_at_60[0x20]; 7807 }; 7808 7809 struct mlx5_ifc_destroy_qp_out_bits { 7810 u8 status[0x8]; 7811 u8 reserved_at_8[0x18]; 7812 7813 u8 syndrome[0x20]; 7814 7815 u8 reserved_at_40[0x40]; 7816 }; 7817 7818 struct mlx5_ifc_destroy_qp_in_bits { 7819 u8 opcode[0x10]; 7820 u8 uid[0x10]; 7821 7822 u8 reserved_at_20[0x10]; 7823 u8 op_mod[0x10]; 7824 7825 u8 reserved_at_40[0x8]; 7826 u8 qpn[0x18]; 7827 7828 u8 reserved_at_60[0x20]; 7829 }; 7830 7831 struct mlx5_ifc_destroy_psv_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 struct mlx5_ifc_destroy_psv_in_bits { 7841 u8 opcode[0x10]; 7842 u8 reserved_at_10[0x10]; 7843 7844 u8 reserved_at_20[0x10]; 7845 u8 op_mod[0x10]; 7846 7847 u8 reserved_at_40[0x8]; 7848 u8 psvn[0x18]; 7849 7850 u8 reserved_at_60[0x20]; 7851 }; 7852 7853 struct mlx5_ifc_destroy_mkey_out_bits { 7854 u8 status[0x8]; 7855 u8 reserved_at_8[0x18]; 7856 7857 u8 syndrome[0x20]; 7858 7859 u8 reserved_at_40[0x40]; 7860 }; 7861 7862 struct mlx5_ifc_destroy_mkey_in_bits { 7863 u8 opcode[0x10]; 7864 u8 uid[0x10]; 7865 7866 u8 reserved_at_20[0x10]; 7867 u8 op_mod[0x10]; 7868 7869 u8 reserved_at_40[0x8]; 7870 u8 mkey_index[0x18]; 7871 7872 u8 reserved_at_60[0x20]; 7873 }; 7874 7875 struct mlx5_ifc_destroy_flow_table_out_bits { 7876 u8 status[0x8]; 7877 u8 reserved_at_8[0x18]; 7878 7879 u8 syndrome[0x20]; 7880 7881 u8 reserved_at_40[0x40]; 7882 }; 7883 7884 struct mlx5_ifc_destroy_flow_table_in_bits { 7885 u8 opcode[0x10]; 7886 u8 reserved_at_10[0x10]; 7887 7888 u8 reserved_at_20[0x10]; 7889 u8 op_mod[0x10]; 7890 7891 u8 other_vport[0x1]; 7892 u8 reserved_at_41[0xf]; 7893 u8 vport_number[0x10]; 7894 7895 u8 reserved_at_60[0x20]; 7896 7897 u8 table_type[0x8]; 7898 u8 reserved_at_88[0x18]; 7899 7900 u8 reserved_at_a0[0x8]; 7901 u8 table_id[0x18]; 7902 7903 u8 reserved_at_c0[0x140]; 7904 }; 7905 7906 struct mlx5_ifc_destroy_flow_group_out_bits { 7907 u8 status[0x8]; 7908 u8 reserved_at_8[0x18]; 7909 7910 u8 syndrome[0x20]; 7911 7912 u8 reserved_at_40[0x40]; 7913 }; 7914 7915 struct mlx5_ifc_destroy_flow_group_in_bits { 7916 u8 opcode[0x10]; 7917 u8 reserved_at_10[0x10]; 7918 7919 u8 reserved_at_20[0x10]; 7920 u8 op_mod[0x10]; 7921 7922 u8 other_vport[0x1]; 7923 u8 reserved_at_41[0xf]; 7924 u8 vport_number[0x10]; 7925 7926 u8 reserved_at_60[0x20]; 7927 7928 u8 table_type[0x8]; 7929 u8 reserved_at_88[0x18]; 7930 7931 u8 reserved_at_a0[0x8]; 7932 u8 table_id[0x18]; 7933 7934 u8 group_id[0x20]; 7935 7936 u8 reserved_at_e0[0x120]; 7937 }; 7938 7939 struct mlx5_ifc_destroy_eq_out_bits { 7940 u8 status[0x8]; 7941 u8 reserved_at_8[0x18]; 7942 7943 u8 syndrome[0x20]; 7944 7945 u8 reserved_at_40[0x40]; 7946 }; 7947 7948 struct mlx5_ifc_destroy_eq_in_bits { 7949 u8 opcode[0x10]; 7950 u8 reserved_at_10[0x10]; 7951 7952 u8 reserved_at_20[0x10]; 7953 u8 op_mod[0x10]; 7954 7955 u8 reserved_at_40[0x18]; 7956 u8 eq_number[0x8]; 7957 7958 u8 reserved_at_60[0x20]; 7959 }; 7960 7961 struct mlx5_ifc_destroy_dct_out_bits { 7962 u8 status[0x8]; 7963 u8 reserved_at_8[0x18]; 7964 7965 u8 syndrome[0x20]; 7966 7967 u8 reserved_at_40[0x40]; 7968 }; 7969 7970 struct mlx5_ifc_destroy_dct_in_bits { 7971 u8 opcode[0x10]; 7972 u8 uid[0x10]; 7973 7974 u8 reserved_at_20[0x10]; 7975 u8 op_mod[0x10]; 7976 7977 u8 reserved_at_40[0x8]; 7978 u8 dctn[0x18]; 7979 7980 u8 reserved_at_60[0x20]; 7981 }; 7982 7983 struct mlx5_ifc_destroy_cq_out_bits { 7984 u8 status[0x8]; 7985 u8 reserved_at_8[0x18]; 7986 7987 u8 syndrome[0x20]; 7988 7989 u8 reserved_at_40[0x40]; 7990 }; 7991 7992 struct mlx5_ifc_destroy_cq_in_bits { 7993 u8 opcode[0x10]; 7994 u8 uid[0x10]; 7995 7996 u8 reserved_at_20[0x10]; 7997 u8 op_mod[0x10]; 7998 7999 u8 reserved_at_40[0x8]; 8000 u8 cqn[0x18]; 8001 8002 u8 reserved_at_60[0x20]; 8003 }; 8004 8005 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8006 u8 status[0x8]; 8007 u8 reserved_at_8[0x18]; 8008 8009 u8 syndrome[0x20]; 8010 8011 u8 reserved_at_40[0x40]; 8012 }; 8013 8014 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8015 u8 opcode[0x10]; 8016 u8 reserved_at_10[0x10]; 8017 8018 u8 reserved_at_20[0x10]; 8019 u8 op_mod[0x10]; 8020 8021 u8 reserved_at_40[0x20]; 8022 8023 u8 reserved_at_60[0x10]; 8024 u8 vxlan_udp_port[0x10]; 8025 }; 8026 8027 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8028 u8 status[0x8]; 8029 u8 reserved_at_8[0x18]; 8030 8031 u8 syndrome[0x20]; 8032 8033 u8 reserved_at_40[0x40]; 8034 }; 8035 8036 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8037 u8 opcode[0x10]; 8038 u8 reserved_at_10[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 reserved_at_40[0x60]; 8044 8045 u8 reserved_at_a0[0x8]; 8046 u8 table_index[0x18]; 8047 8048 u8 reserved_at_c0[0x140]; 8049 }; 8050 8051 struct mlx5_ifc_delete_fte_out_bits { 8052 u8 status[0x8]; 8053 u8 reserved_at_8[0x18]; 8054 8055 u8 syndrome[0x20]; 8056 8057 u8 reserved_at_40[0x40]; 8058 }; 8059 8060 struct mlx5_ifc_delete_fte_in_bits { 8061 u8 opcode[0x10]; 8062 u8 reserved_at_10[0x10]; 8063 8064 u8 reserved_at_20[0x10]; 8065 u8 op_mod[0x10]; 8066 8067 u8 other_vport[0x1]; 8068 u8 reserved_at_41[0xf]; 8069 u8 vport_number[0x10]; 8070 8071 u8 reserved_at_60[0x20]; 8072 8073 u8 table_type[0x8]; 8074 u8 reserved_at_88[0x18]; 8075 8076 u8 reserved_at_a0[0x8]; 8077 u8 table_id[0x18]; 8078 8079 u8 reserved_at_c0[0x40]; 8080 8081 u8 flow_index[0x20]; 8082 8083 u8 reserved_at_120[0xe0]; 8084 }; 8085 8086 struct mlx5_ifc_dealloc_xrcd_out_bits { 8087 u8 status[0x8]; 8088 u8 reserved_at_8[0x18]; 8089 8090 u8 syndrome[0x20]; 8091 8092 u8 reserved_at_40[0x40]; 8093 }; 8094 8095 struct mlx5_ifc_dealloc_xrcd_in_bits { 8096 u8 opcode[0x10]; 8097 u8 uid[0x10]; 8098 8099 u8 reserved_at_20[0x10]; 8100 u8 op_mod[0x10]; 8101 8102 u8 reserved_at_40[0x8]; 8103 u8 xrcd[0x18]; 8104 8105 u8 reserved_at_60[0x20]; 8106 }; 8107 8108 struct mlx5_ifc_dealloc_uar_out_bits { 8109 u8 status[0x8]; 8110 u8 reserved_at_8[0x18]; 8111 8112 u8 syndrome[0x20]; 8113 8114 u8 reserved_at_40[0x40]; 8115 }; 8116 8117 struct mlx5_ifc_dealloc_uar_in_bits { 8118 u8 opcode[0x10]; 8119 u8 uid[0x10]; 8120 8121 u8 reserved_at_20[0x10]; 8122 u8 op_mod[0x10]; 8123 8124 u8 reserved_at_40[0x8]; 8125 u8 uar[0x18]; 8126 8127 u8 reserved_at_60[0x20]; 8128 }; 8129 8130 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8131 u8 status[0x8]; 8132 u8 reserved_at_8[0x18]; 8133 8134 u8 syndrome[0x20]; 8135 8136 u8 reserved_at_40[0x40]; 8137 }; 8138 8139 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8140 u8 opcode[0x10]; 8141 u8 uid[0x10]; 8142 8143 u8 reserved_at_20[0x10]; 8144 u8 op_mod[0x10]; 8145 8146 u8 reserved_at_40[0x8]; 8147 u8 transport_domain[0x18]; 8148 8149 u8 reserved_at_60[0x20]; 8150 }; 8151 8152 struct mlx5_ifc_dealloc_q_counter_out_bits { 8153 u8 status[0x8]; 8154 u8 reserved_at_8[0x18]; 8155 8156 u8 syndrome[0x20]; 8157 8158 u8 reserved_at_40[0x40]; 8159 }; 8160 8161 struct mlx5_ifc_dealloc_q_counter_in_bits { 8162 u8 opcode[0x10]; 8163 u8 reserved_at_10[0x10]; 8164 8165 u8 reserved_at_20[0x10]; 8166 u8 op_mod[0x10]; 8167 8168 u8 reserved_at_40[0x18]; 8169 u8 counter_set_id[0x8]; 8170 8171 u8 reserved_at_60[0x20]; 8172 }; 8173 8174 struct mlx5_ifc_dealloc_pd_out_bits { 8175 u8 status[0x8]; 8176 u8 reserved_at_8[0x18]; 8177 8178 u8 syndrome[0x20]; 8179 8180 u8 reserved_at_40[0x40]; 8181 }; 8182 8183 struct mlx5_ifc_dealloc_pd_in_bits { 8184 u8 opcode[0x10]; 8185 u8 uid[0x10]; 8186 8187 u8 reserved_at_20[0x10]; 8188 u8 op_mod[0x10]; 8189 8190 u8 reserved_at_40[0x8]; 8191 u8 pd[0x18]; 8192 8193 u8 reserved_at_60[0x20]; 8194 }; 8195 8196 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8197 u8 status[0x8]; 8198 u8 reserved_at_8[0x18]; 8199 8200 u8 syndrome[0x20]; 8201 8202 u8 reserved_at_40[0x40]; 8203 }; 8204 8205 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8206 u8 opcode[0x10]; 8207 u8 reserved_at_10[0x10]; 8208 8209 u8 reserved_at_20[0x10]; 8210 u8 op_mod[0x10]; 8211 8212 u8 flow_counter_id[0x20]; 8213 8214 u8 reserved_at_60[0x20]; 8215 }; 8216 8217 struct mlx5_ifc_create_xrq_out_bits { 8218 u8 status[0x8]; 8219 u8 reserved_at_8[0x18]; 8220 8221 u8 syndrome[0x20]; 8222 8223 u8 reserved_at_40[0x8]; 8224 u8 xrqn[0x18]; 8225 8226 u8 reserved_at_60[0x20]; 8227 }; 8228 8229 struct mlx5_ifc_create_xrq_in_bits { 8230 u8 opcode[0x10]; 8231 u8 uid[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x40]; 8237 8238 struct mlx5_ifc_xrqc_bits xrq_context; 8239 }; 8240 8241 struct mlx5_ifc_create_xrc_srq_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x8]; 8248 u8 xrc_srqn[0x18]; 8249 8250 u8 reserved_at_60[0x20]; 8251 }; 8252 8253 struct mlx5_ifc_create_xrc_srq_in_bits { 8254 u8 opcode[0x10]; 8255 u8 uid[0x10]; 8256 8257 u8 reserved_at_20[0x10]; 8258 u8 op_mod[0x10]; 8259 8260 u8 reserved_at_40[0x40]; 8261 8262 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8263 8264 u8 reserved_at_280[0x60]; 8265 8266 u8 xrc_srq_umem_valid[0x1]; 8267 u8 reserved_at_2e1[0x1f]; 8268 8269 u8 reserved_at_300[0x580]; 8270 8271 u8 pas[][0x40]; 8272 }; 8273 8274 struct mlx5_ifc_create_tis_out_bits { 8275 u8 status[0x8]; 8276 u8 reserved_at_8[0x18]; 8277 8278 u8 syndrome[0x20]; 8279 8280 u8 reserved_at_40[0x8]; 8281 u8 tisn[0x18]; 8282 8283 u8 reserved_at_60[0x20]; 8284 }; 8285 8286 struct mlx5_ifc_create_tis_in_bits { 8287 u8 opcode[0x10]; 8288 u8 uid[0x10]; 8289 8290 u8 reserved_at_20[0x10]; 8291 u8 op_mod[0x10]; 8292 8293 u8 reserved_at_40[0xc0]; 8294 8295 struct mlx5_ifc_tisc_bits ctx; 8296 }; 8297 8298 struct mlx5_ifc_create_tir_out_bits { 8299 u8 status[0x8]; 8300 u8 icm_address_63_40[0x18]; 8301 8302 u8 syndrome[0x20]; 8303 8304 u8 icm_address_39_32[0x8]; 8305 u8 tirn[0x18]; 8306 8307 u8 icm_address_31_0[0x20]; 8308 }; 8309 8310 struct mlx5_ifc_create_tir_in_bits { 8311 u8 opcode[0x10]; 8312 u8 uid[0x10]; 8313 8314 u8 reserved_at_20[0x10]; 8315 u8 op_mod[0x10]; 8316 8317 u8 reserved_at_40[0xc0]; 8318 8319 struct mlx5_ifc_tirc_bits ctx; 8320 }; 8321 8322 struct mlx5_ifc_create_srq_out_bits { 8323 u8 status[0x8]; 8324 u8 reserved_at_8[0x18]; 8325 8326 u8 syndrome[0x20]; 8327 8328 u8 reserved_at_40[0x8]; 8329 u8 srqn[0x18]; 8330 8331 u8 reserved_at_60[0x20]; 8332 }; 8333 8334 struct mlx5_ifc_create_srq_in_bits { 8335 u8 opcode[0x10]; 8336 u8 uid[0x10]; 8337 8338 u8 reserved_at_20[0x10]; 8339 u8 op_mod[0x10]; 8340 8341 u8 reserved_at_40[0x40]; 8342 8343 struct mlx5_ifc_srqc_bits srq_context_entry; 8344 8345 u8 reserved_at_280[0x600]; 8346 8347 u8 pas[][0x40]; 8348 }; 8349 8350 struct mlx5_ifc_create_sq_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 reserved_at_40[0x8]; 8357 u8 sqn[0x18]; 8358 8359 u8 reserved_at_60[0x20]; 8360 }; 8361 8362 struct mlx5_ifc_create_sq_in_bits { 8363 u8 opcode[0x10]; 8364 u8 uid[0x10]; 8365 8366 u8 reserved_at_20[0x10]; 8367 u8 op_mod[0x10]; 8368 8369 u8 reserved_at_40[0xc0]; 8370 8371 struct mlx5_ifc_sqc_bits ctx; 8372 }; 8373 8374 struct mlx5_ifc_create_scheduling_element_out_bits { 8375 u8 status[0x8]; 8376 u8 reserved_at_8[0x18]; 8377 8378 u8 syndrome[0x20]; 8379 8380 u8 reserved_at_40[0x40]; 8381 8382 u8 scheduling_element_id[0x20]; 8383 8384 u8 reserved_at_a0[0x160]; 8385 }; 8386 8387 struct mlx5_ifc_create_scheduling_element_in_bits { 8388 u8 opcode[0x10]; 8389 u8 reserved_at_10[0x10]; 8390 8391 u8 reserved_at_20[0x10]; 8392 u8 op_mod[0x10]; 8393 8394 u8 scheduling_hierarchy[0x8]; 8395 u8 reserved_at_48[0x18]; 8396 8397 u8 reserved_at_60[0xa0]; 8398 8399 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8400 8401 u8 reserved_at_300[0x100]; 8402 }; 8403 8404 struct mlx5_ifc_create_rqt_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x8]; 8411 u8 rqtn[0x18]; 8412 8413 u8 reserved_at_60[0x20]; 8414 }; 8415 8416 struct mlx5_ifc_create_rqt_in_bits { 8417 u8 opcode[0x10]; 8418 u8 uid[0x10]; 8419 8420 u8 reserved_at_20[0x10]; 8421 u8 op_mod[0x10]; 8422 8423 u8 reserved_at_40[0xc0]; 8424 8425 struct mlx5_ifc_rqtc_bits rqt_context; 8426 }; 8427 8428 struct mlx5_ifc_create_rq_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x8]; 8435 u8 rqn[0x18]; 8436 8437 u8 reserved_at_60[0x20]; 8438 }; 8439 8440 struct mlx5_ifc_create_rq_in_bits { 8441 u8 opcode[0x10]; 8442 u8 uid[0x10]; 8443 8444 u8 reserved_at_20[0x10]; 8445 u8 op_mod[0x10]; 8446 8447 u8 reserved_at_40[0xc0]; 8448 8449 struct mlx5_ifc_rqc_bits ctx; 8450 }; 8451 8452 struct mlx5_ifc_create_rmp_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x8]; 8459 u8 rmpn[0x18]; 8460 8461 u8 reserved_at_60[0x20]; 8462 }; 8463 8464 struct mlx5_ifc_create_rmp_in_bits { 8465 u8 opcode[0x10]; 8466 u8 uid[0x10]; 8467 8468 u8 reserved_at_20[0x10]; 8469 u8 op_mod[0x10]; 8470 8471 u8 reserved_at_40[0xc0]; 8472 8473 struct mlx5_ifc_rmpc_bits ctx; 8474 }; 8475 8476 struct mlx5_ifc_create_qp_out_bits { 8477 u8 status[0x8]; 8478 u8 reserved_at_8[0x18]; 8479 8480 u8 syndrome[0x20]; 8481 8482 u8 reserved_at_40[0x8]; 8483 u8 qpn[0x18]; 8484 8485 u8 ece[0x20]; 8486 }; 8487 8488 struct mlx5_ifc_create_qp_in_bits { 8489 u8 opcode[0x10]; 8490 u8 uid[0x10]; 8491 8492 u8 reserved_at_20[0x10]; 8493 u8 op_mod[0x10]; 8494 8495 u8 reserved_at_40[0x8]; 8496 u8 input_qpn[0x18]; 8497 8498 u8 reserved_at_60[0x20]; 8499 u8 opt_param_mask[0x20]; 8500 8501 u8 ece[0x20]; 8502 8503 struct mlx5_ifc_qpc_bits qpc; 8504 8505 u8 reserved_at_800[0x60]; 8506 8507 u8 wq_umem_valid[0x1]; 8508 u8 reserved_at_861[0x1f]; 8509 8510 u8 pas[][0x40]; 8511 }; 8512 8513 struct mlx5_ifc_create_psv_out_bits { 8514 u8 status[0x8]; 8515 u8 reserved_at_8[0x18]; 8516 8517 u8 syndrome[0x20]; 8518 8519 u8 reserved_at_40[0x40]; 8520 8521 u8 reserved_at_80[0x8]; 8522 u8 psv0_index[0x18]; 8523 8524 u8 reserved_at_a0[0x8]; 8525 u8 psv1_index[0x18]; 8526 8527 u8 reserved_at_c0[0x8]; 8528 u8 psv2_index[0x18]; 8529 8530 u8 reserved_at_e0[0x8]; 8531 u8 psv3_index[0x18]; 8532 }; 8533 8534 struct mlx5_ifc_create_psv_in_bits { 8535 u8 opcode[0x10]; 8536 u8 reserved_at_10[0x10]; 8537 8538 u8 reserved_at_20[0x10]; 8539 u8 op_mod[0x10]; 8540 8541 u8 num_psv[0x4]; 8542 u8 reserved_at_44[0x4]; 8543 u8 pd[0x18]; 8544 8545 u8 reserved_at_60[0x20]; 8546 }; 8547 8548 struct mlx5_ifc_create_mkey_out_bits { 8549 u8 status[0x8]; 8550 u8 reserved_at_8[0x18]; 8551 8552 u8 syndrome[0x20]; 8553 8554 u8 reserved_at_40[0x8]; 8555 u8 mkey_index[0x18]; 8556 8557 u8 reserved_at_60[0x20]; 8558 }; 8559 8560 struct mlx5_ifc_create_mkey_in_bits { 8561 u8 opcode[0x10]; 8562 u8 uid[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 reserved_at_40[0x20]; 8568 8569 u8 pg_access[0x1]; 8570 u8 mkey_umem_valid[0x1]; 8571 u8 reserved_at_62[0x1e]; 8572 8573 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8574 8575 u8 reserved_at_280[0x80]; 8576 8577 u8 translations_octword_actual_size[0x20]; 8578 8579 u8 reserved_at_320[0x560]; 8580 8581 u8 klm_pas_mtt[][0x20]; 8582 }; 8583 8584 enum { 8585 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8586 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8587 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8588 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8589 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8590 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8591 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8592 }; 8593 8594 struct mlx5_ifc_create_flow_table_out_bits { 8595 u8 status[0x8]; 8596 u8 icm_address_63_40[0x18]; 8597 8598 u8 syndrome[0x20]; 8599 8600 u8 icm_address_39_32[0x8]; 8601 u8 table_id[0x18]; 8602 8603 u8 icm_address_31_0[0x20]; 8604 }; 8605 8606 struct mlx5_ifc_create_flow_table_in_bits { 8607 u8 opcode[0x10]; 8608 u8 uid[0x10]; 8609 8610 u8 reserved_at_20[0x10]; 8611 u8 op_mod[0x10]; 8612 8613 u8 other_vport[0x1]; 8614 u8 reserved_at_41[0xf]; 8615 u8 vport_number[0x10]; 8616 8617 u8 reserved_at_60[0x20]; 8618 8619 u8 table_type[0x8]; 8620 u8 reserved_at_88[0x18]; 8621 8622 u8 reserved_at_a0[0x20]; 8623 8624 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8625 }; 8626 8627 struct mlx5_ifc_create_flow_group_out_bits { 8628 u8 status[0x8]; 8629 u8 reserved_at_8[0x18]; 8630 8631 u8 syndrome[0x20]; 8632 8633 u8 reserved_at_40[0x8]; 8634 u8 group_id[0x18]; 8635 8636 u8 reserved_at_60[0x20]; 8637 }; 8638 8639 enum { 8640 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8641 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8642 }; 8643 8644 enum { 8645 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8646 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8647 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8648 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8649 }; 8650 8651 struct mlx5_ifc_create_flow_group_in_bits { 8652 u8 opcode[0x10]; 8653 u8 reserved_at_10[0x10]; 8654 8655 u8 reserved_at_20[0x10]; 8656 u8 op_mod[0x10]; 8657 8658 u8 other_vport[0x1]; 8659 u8 reserved_at_41[0xf]; 8660 u8 vport_number[0x10]; 8661 8662 u8 reserved_at_60[0x20]; 8663 8664 u8 table_type[0x8]; 8665 u8 reserved_at_88[0x4]; 8666 u8 group_type[0x4]; 8667 u8 reserved_at_90[0x10]; 8668 8669 u8 reserved_at_a0[0x8]; 8670 u8 table_id[0x18]; 8671 8672 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8673 8674 u8 reserved_at_c1[0x1f]; 8675 8676 u8 start_flow_index[0x20]; 8677 8678 u8 reserved_at_100[0x20]; 8679 8680 u8 end_flow_index[0x20]; 8681 8682 u8 reserved_at_140[0x10]; 8683 u8 match_definer_id[0x10]; 8684 8685 u8 reserved_at_160[0x80]; 8686 8687 u8 reserved_at_1e0[0x18]; 8688 u8 match_criteria_enable[0x8]; 8689 8690 struct mlx5_ifc_fte_match_param_bits match_criteria; 8691 8692 u8 reserved_at_1200[0xe00]; 8693 }; 8694 8695 struct mlx5_ifc_create_eq_out_bits { 8696 u8 status[0x8]; 8697 u8 reserved_at_8[0x18]; 8698 8699 u8 syndrome[0x20]; 8700 8701 u8 reserved_at_40[0x18]; 8702 u8 eq_number[0x8]; 8703 8704 u8 reserved_at_60[0x20]; 8705 }; 8706 8707 struct mlx5_ifc_create_eq_in_bits { 8708 u8 opcode[0x10]; 8709 u8 uid[0x10]; 8710 8711 u8 reserved_at_20[0x10]; 8712 u8 op_mod[0x10]; 8713 8714 u8 reserved_at_40[0x40]; 8715 8716 struct mlx5_ifc_eqc_bits eq_context_entry; 8717 8718 u8 reserved_at_280[0x40]; 8719 8720 u8 event_bitmask[4][0x40]; 8721 8722 u8 reserved_at_3c0[0x4c0]; 8723 8724 u8 pas[][0x40]; 8725 }; 8726 8727 struct mlx5_ifc_create_dct_out_bits { 8728 u8 status[0x8]; 8729 u8 reserved_at_8[0x18]; 8730 8731 u8 syndrome[0x20]; 8732 8733 u8 reserved_at_40[0x8]; 8734 u8 dctn[0x18]; 8735 8736 u8 ece[0x20]; 8737 }; 8738 8739 struct mlx5_ifc_create_dct_in_bits { 8740 u8 opcode[0x10]; 8741 u8 uid[0x10]; 8742 8743 u8 reserved_at_20[0x10]; 8744 u8 op_mod[0x10]; 8745 8746 u8 reserved_at_40[0x40]; 8747 8748 struct mlx5_ifc_dctc_bits dct_context_entry; 8749 8750 u8 reserved_at_280[0x180]; 8751 }; 8752 8753 struct mlx5_ifc_create_cq_out_bits { 8754 u8 status[0x8]; 8755 u8 reserved_at_8[0x18]; 8756 8757 u8 syndrome[0x20]; 8758 8759 u8 reserved_at_40[0x8]; 8760 u8 cqn[0x18]; 8761 8762 u8 reserved_at_60[0x20]; 8763 }; 8764 8765 struct mlx5_ifc_create_cq_in_bits { 8766 u8 opcode[0x10]; 8767 u8 uid[0x10]; 8768 8769 u8 reserved_at_20[0x10]; 8770 u8 op_mod[0x10]; 8771 8772 u8 reserved_at_40[0x40]; 8773 8774 struct mlx5_ifc_cqc_bits cq_context; 8775 8776 u8 reserved_at_280[0x60]; 8777 8778 u8 cq_umem_valid[0x1]; 8779 u8 reserved_at_2e1[0x59f]; 8780 8781 u8 pas[][0x40]; 8782 }; 8783 8784 struct mlx5_ifc_config_int_moderation_out_bits { 8785 u8 status[0x8]; 8786 u8 reserved_at_8[0x18]; 8787 8788 u8 syndrome[0x20]; 8789 8790 u8 reserved_at_40[0x4]; 8791 u8 min_delay[0xc]; 8792 u8 int_vector[0x10]; 8793 8794 u8 reserved_at_60[0x20]; 8795 }; 8796 8797 enum { 8798 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8799 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8800 }; 8801 8802 struct mlx5_ifc_config_int_moderation_in_bits { 8803 u8 opcode[0x10]; 8804 u8 reserved_at_10[0x10]; 8805 8806 u8 reserved_at_20[0x10]; 8807 u8 op_mod[0x10]; 8808 8809 u8 reserved_at_40[0x4]; 8810 u8 min_delay[0xc]; 8811 u8 int_vector[0x10]; 8812 8813 u8 reserved_at_60[0x20]; 8814 }; 8815 8816 struct mlx5_ifc_attach_to_mcg_out_bits { 8817 u8 status[0x8]; 8818 u8 reserved_at_8[0x18]; 8819 8820 u8 syndrome[0x20]; 8821 8822 u8 reserved_at_40[0x40]; 8823 }; 8824 8825 struct mlx5_ifc_attach_to_mcg_in_bits { 8826 u8 opcode[0x10]; 8827 u8 uid[0x10]; 8828 8829 u8 reserved_at_20[0x10]; 8830 u8 op_mod[0x10]; 8831 8832 u8 reserved_at_40[0x8]; 8833 u8 qpn[0x18]; 8834 8835 u8 reserved_at_60[0x20]; 8836 8837 u8 multicast_gid[16][0x8]; 8838 }; 8839 8840 struct mlx5_ifc_arm_xrq_out_bits { 8841 u8 status[0x8]; 8842 u8 reserved_at_8[0x18]; 8843 8844 u8 syndrome[0x20]; 8845 8846 u8 reserved_at_40[0x40]; 8847 }; 8848 8849 struct mlx5_ifc_arm_xrq_in_bits { 8850 u8 opcode[0x10]; 8851 u8 reserved_at_10[0x10]; 8852 8853 u8 reserved_at_20[0x10]; 8854 u8 op_mod[0x10]; 8855 8856 u8 reserved_at_40[0x8]; 8857 u8 xrqn[0x18]; 8858 8859 u8 reserved_at_60[0x10]; 8860 u8 lwm[0x10]; 8861 }; 8862 8863 struct mlx5_ifc_arm_xrc_srq_out_bits { 8864 u8 status[0x8]; 8865 u8 reserved_at_8[0x18]; 8866 8867 u8 syndrome[0x20]; 8868 8869 u8 reserved_at_40[0x40]; 8870 }; 8871 8872 enum { 8873 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8874 }; 8875 8876 struct mlx5_ifc_arm_xrc_srq_in_bits { 8877 u8 opcode[0x10]; 8878 u8 uid[0x10]; 8879 8880 u8 reserved_at_20[0x10]; 8881 u8 op_mod[0x10]; 8882 8883 u8 reserved_at_40[0x8]; 8884 u8 xrc_srqn[0x18]; 8885 8886 u8 reserved_at_60[0x10]; 8887 u8 lwm[0x10]; 8888 }; 8889 8890 struct mlx5_ifc_arm_rq_out_bits { 8891 u8 status[0x8]; 8892 u8 reserved_at_8[0x18]; 8893 8894 u8 syndrome[0x20]; 8895 8896 u8 reserved_at_40[0x40]; 8897 }; 8898 8899 enum { 8900 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8901 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8902 }; 8903 8904 struct mlx5_ifc_arm_rq_in_bits { 8905 u8 opcode[0x10]; 8906 u8 uid[0x10]; 8907 8908 u8 reserved_at_20[0x10]; 8909 u8 op_mod[0x10]; 8910 8911 u8 reserved_at_40[0x8]; 8912 u8 srq_number[0x18]; 8913 8914 u8 reserved_at_60[0x10]; 8915 u8 lwm[0x10]; 8916 }; 8917 8918 struct mlx5_ifc_arm_dct_out_bits { 8919 u8 status[0x8]; 8920 u8 reserved_at_8[0x18]; 8921 8922 u8 syndrome[0x20]; 8923 8924 u8 reserved_at_40[0x40]; 8925 }; 8926 8927 struct mlx5_ifc_arm_dct_in_bits { 8928 u8 opcode[0x10]; 8929 u8 reserved_at_10[0x10]; 8930 8931 u8 reserved_at_20[0x10]; 8932 u8 op_mod[0x10]; 8933 8934 u8 reserved_at_40[0x8]; 8935 u8 dct_number[0x18]; 8936 8937 u8 reserved_at_60[0x20]; 8938 }; 8939 8940 struct mlx5_ifc_alloc_xrcd_out_bits { 8941 u8 status[0x8]; 8942 u8 reserved_at_8[0x18]; 8943 8944 u8 syndrome[0x20]; 8945 8946 u8 reserved_at_40[0x8]; 8947 u8 xrcd[0x18]; 8948 8949 u8 reserved_at_60[0x20]; 8950 }; 8951 8952 struct mlx5_ifc_alloc_xrcd_in_bits { 8953 u8 opcode[0x10]; 8954 u8 uid[0x10]; 8955 8956 u8 reserved_at_20[0x10]; 8957 u8 op_mod[0x10]; 8958 8959 u8 reserved_at_40[0x40]; 8960 }; 8961 8962 struct mlx5_ifc_alloc_uar_out_bits { 8963 u8 status[0x8]; 8964 u8 reserved_at_8[0x18]; 8965 8966 u8 syndrome[0x20]; 8967 8968 u8 reserved_at_40[0x8]; 8969 u8 uar[0x18]; 8970 8971 u8 reserved_at_60[0x20]; 8972 }; 8973 8974 struct mlx5_ifc_alloc_uar_in_bits { 8975 u8 opcode[0x10]; 8976 u8 uid[0x10]; 8977 8978 u8 reserved_at_20[0x10]; 8979 u8 op_mod[0x10]; 8980 8981 u8 reserved_at_40[0x40]; 8982 }; 8983 8984 struct mlx5_ifc_alloc_transport_domain_out_bits { 8985 u8 status[0x8]; 8986 u8 reserved_at_8[0x18]; 8987 8988 u8 syndrome[0x20]; 8989 8990 u8 reserved_at_40[0x8]; 8991 u8 transport_domain[0x18]; 8992 8993 u8 reserved_at_60[0x20]; 8994 }; 8995 8996 struct mlx5_ifc_alloc_transport_domain_in_bits { 8997 u8 opcode[0x10]; 8998 u8 uid[0x10]; 8999 9000 u8 reserved_at_20[0x10]; 9001 u8 op_mod[0x10]; 9002 9003 u8 reserved_at_40[0x40]; 9004 }; 9005 9006 struct mlx5_ifc_alloc_q_counter_out_bits { 9007 u8 status[0x8]; 9008 u8 reserved_at_8[0x18]; 9009 9010 u8 syndrome[0x20]; 9011 9012 u8 reserved_at_40[0x18]; 9013 u8 counter_set_id[0x8]; 9014 9015 u8 reserved_at_60[0x20]; 9016 }; 9017 9018 struct mlx5_ifc_alloc_q_counter_in_bits { 9019 u8 opcode[0x10]; 9020 u8 uid[0x10]; 9021 9022 u8 reserved_at_20[0x10]; 9023 u8 op_mod[0x10]; 9024 9025 u8 reserved_at_40[0x40]; 9026 }; 9027 9028 struct mlx5_ifc_alloc_pd_out_bits { 9029 u8 status[0x8]; 9030 u8 reserved_at_8[0x18]; 9031 9032 u8 syndrome[0x20]; 9033 9034 u8 reserved_at_40[0x8]; 9035 u8 pd[0x18]; 9036 9037 u8 reserved_at_60[0x20]; 9038 }; 9039 9040 struct mlx5_ifc_alloc_pd_in_bits { 9041 u8 opcode[0x10]; 9042 u8 uid[0x10]; 9043 9044 u8 reserved_at_20[0x10]; 9045 u8 op_mod[0x10]; 9046 9047 u8 reserved_at_40[0x40]; 9048 }; 9049 9050 struct mlx5_ifc_alloc_flow_counter_out_bits { 9051 u8 status[0x8]; 9052 u8 reserved_at_8[0x18]; 9053 9054 u8 syndrome[0x20]; 9055 9056 u8 flow_counter_id[0x20]; 9057 9058 u8 reserved_at_60[0x20]; 9059 }; 9060 9061 struct mlx5_ifc_alloc_flow_counter_in_bits { 9062 u8 opcode[0x10]; 9063 u8 reserved_at_10[0x10]; 9064 9065 u8 reserved_at_20[0x10]; 9066 u8 op_mod[0x10]; 9067 9068 u8 reserved_at_40[0x33]; 9069 u8 flow_counter_bulk_log_size[0x5]; 9070 u8 flow_counter_bulk[0x8]; 9071 }; 9072 9073 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9074 u8 status[0x8]; 9075 u8 reserved_at_8[0x18]; 9076 9077 u8 syndrome[0x20]; 9078 9079 u8 reserved_at_40[0x40]; 9080 }; 9081 9082 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9083 u8 opcode[0x10]; 9084 u8 reserved_at_10[0x10]; 9085 9086 u8 reserved_at_20[0x10]; 9087 u8 op_mod[0x10]; 9088 9089 u8 reserved_at_40[0x20]; 9090 9091 u8 reserved_at_60[0x10]; 9092 u8 vxlan_udp_port[0x10]; 9093 }; 9094 9095 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9096 u8 status[0x8]; 9097 u8 reserved_at_8[0x18]; 9098 9099 u8 syndrome[0x20]; 9100 9101 u8 reserved_at_40[0x40]; 9102 }; 9103 9104 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9105 u8 rate_limit[0x20]; 9106 9107 u8 burst_upper_bound[0x20]; 9108 9109 u8 reserved_at_40[0x10]; 9110 u8 typical_packet_size[0x10]; 9111 9112 u8 reserved_at_60[0x120]; 9113 }; 9114 9115 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9116 u8 opcode[0x10]; 9117 u8 uid[0x10]; 9118 9119 u8 reserved_at_20[0x10]; 9120 u8 op_mod[0x10]; 9121 9122 u8 reserved_at_40[0x10]; 9123 u8 rate_limit_index[0x10]; 9124 9125 u8 reserved_at_60[0x20]; 9126 9127 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9128 }; 9129 9130 struct mlx5_ifc_access_register_out_bits { 9131 u8 status[0x8]; 9132 u8 reserved_at_8[0x18]; 9133 9134 u8 syndrome[0x20]; 9135 9136 u8 reserved_at_40[0x40]; 9137 9138 u8 register_data[][0x20]; 9139 }; 9140 9141 enum { 9142 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9143 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9144 }; 9145 9146 struct mlx5_ifc_access_register_in_bits { 9147 u8 opcode[0x10]; 9148 u8 reserved_at_10[0x10]; 9149 9150 u8 reserved_at_20[0x10]; 9151 u8 op_mod[0x10]; 9152 9153 u8 reserved_at_40[0x10]; 9154 u8 register_id[0x10]; 9155 9156 u8 argument[0x20]; 9157 9158 u8 register_data[][0x20]; 9159 }; 9160 9161 struct mlx5_ifc_sltp_reg_bits { 9162 u8 status[0x4]; 9163 u8 version[0x4]; 9164 u8 local_port[0x8]; 9165 u8 pnat[0x2]; 9166 u8 reserved_at_12[0x2]; 9167 u8 lane[0x4]; 9168 u8 reserved_at_18[0x8]; 9169 9170 u8 reserved_at_20[0x20]; 9171 9172 u8 reserved_at_40[0x7]; 9173 u8 polarity[0x1]; 9174 u8 ob_tap0[0x8]; 9175 u8 ob_tap1[0x8]; 9176 u8 ob_tap2[0x8]; 9177 9178 u8 reserved_at_60[0xc]; 9179 u8 ob_preemp_mode[0x4]; 9180 u8 ob_reg[0x8]; 9181 u8 ob_bias[0x8]; 9182 9183 u8 reserved_at_80[0x20]; 9184 }; 9185 9186 struct mlx5_ifc_slrg_reg_bits { 9187 u8 status[0x4]; 9188 u8 version[0x4]; 9189 u8 local_port[0x8]; 9190 u8 pnat[0x2]; 9191 u8 reserved_at_12[0x2]; 9192 u8 lane[0x4]; 9193 u8 reserved_at_18[0x8]; 9194 9195 u8 time_to_link_up[0x10]; 9196 u8 reserved_at_30[0xc]; 9197 u8 grade_lane_speed[0x4]; 9198 9199 u8 grade_version[0x8]; 9200 u8 grade[0x18]; 9201 9202 u8 reserved_at_60[0x4]; 9203 u8 height_grade_type[0x4]; 9204 u8 height_grade[0x18]; 9205 9206 u8 height_dz[0x10]; 9207 u8 height_dv[0x10]; 9208 9209 u8 reserved_at_a0[0x10]; 9210 u8 height_sigma[0x10]; 9211 9212 u8 reserved_at_c0[0x20]; 9213 9214 u8 reserved_at_e0[0x4]; 9215 u8 phase_grade_type[0x4]; 9216 u8 phase_grade[0x18]; 9217 9218 u8 reserved_at_100[0x8]; 9219 u8 phase_eo_pos[0x8]; 9220 u8 reserved_at_110[0x8]; 9221 u8 phase_eo_neg[0x8]; 9222 9223 u8 ffe_set_tested[0x10]; 9224 u8 test_errors_per_lane[0x10]; 9225 }; 9226 9227 struct mlx5_ifc_pvlc_reg_bits { 9228 u8 reserved_at_0[0x8]; 9229 u8 local_port[0x8]; 9230 u8 reserved_at_10[0x10]; 9231 9232 u8 reserved_at_20[0x1c]; 9233 u8 vl_hw_cap[0x4]; 9234 9235 u8 reserved_at_40[0x1c]; 9236 u8 vl_admin[0x4]; 9237 9238 u8 reserved_at_60[0x1c]; 9239 u8 vl_operational[0x4]; 9240 }; 9241 9242 struct mlx5_ifc_pude_reg_bits { 9243 u8 swid[0x8]; 9244 u8 local_port[0x8]; 9245 u8 reserved_at_10[0x4]; 9246 u8 admin_status[0x4]; 9247 u8 reserved_at_18[0x4]; 9248 u8 oper_status[0x4]; 9249 9250 u8 reserved_at_20[0x60]; 9251 }; 9252 9253 struct mlx5_ifc_ptys_reg_bits { 9254 u8 reserved_at_0[0x1]; 9255 u8 an_disable_admin[0x1]; 9256 u8 an_disable_cap[0x1]; 9257 u8 reserved_at_3[0x5]; 9258 u8 local_port[0x8]; 9259 u8 reserved_at_10[0xd]; 9260 u8 proto_mask[0x3]; 9261 9262 u8 an_status[0x4]; 9263 u8 reserved_at_24[0xc]; 9264 u8 data_rate_oper[0x10]; 9265 9266 u8 ext_eth_proto_capability[0x20]; 9267 9268 u8 eth_proto_capability[0x20]; 9269 9270 u8 ib_link_width_capability[0x10]; 9271 u8 ib_proto_capability[0x10]; 9272 9273 u8 ext_eth_proto_admin[0x20]; 9274 9275 u8 eth_proto_admin[0x20]; 9276 9277 u8 ib_link_width_admin[0x10]; 9278 u8 ib_proto_admin[0x10]; 9279 9280 u8 ext_eth_proto_oper[0x20]; 9281 9282 u8 eth_proto_oper[0x20]; 9283 9284 u8 ib_link_width_oper[0x10]; 9285 u8 ib_proto_oper[0x10]; 9286 9287 u8 reserved_at_160[0x1c]; 9288 u8 connector_type[0x4]; 9289 9290 u8 eth_proto_lp_advertise[0x20]; 9291 9292 u8 reserved_at_1a0[0x60]; 9293 }; 9294 9295 struct mlx5_ifc_mlcr_reg_bits { 9296 u8 reserved_at_0[0x8]; 9297 u8 local_port[0x8]; 9298 u8 reserved_at_10[0x20]; 9299 9300 u8 beacon_duration[0x10]; 9301 u8 reserved_at_40[0x10]; 9302 9303 u8 beacon_remain[0x10]; 9304 }; 9305 9306 struct mlx5_ifc_ptas_reg_bits { 9307 u8 reserved_at_0[0x20]; 9308 9309 u8 algorithm_options[0x10]; 9310 u8 reserved_at_30[0x4]; 9311 u8 repetitions_mode[0x4]; 9312 u8 num_of_repetitions[0x8]; 9313 9314 u8 grade_version[0x8]; 9315 u8 height_grade_type[0x4]; 9316 u8 phase_grade_type[0x4]; 9317 u8 height_grade_weight[0x8]; 9318 u8 phase_grade_weight[0x8]; 9319 9320 u8 gisim_measure_bits[0x10]; 9321 u8 adaptive_tap_measure_bits[0x10]; 9322 9323 u8 ber_bath_high_error_threshold[0x10]; 9324 u8 ber_bath_mid_error_threshold[0x10]; 9325 9326 u8 ber_bath_low_error_threshold[0x10]; 9327 u8 one_ratio_high_threshold[0x10]; 9328 9329 u8 one_ratio_high_mid_threshold[0x10]; 9330 u8 one_ratio_low_mid_threshold[0x10]; 9331 9332 u8 one_ratio_low_threshold[0x10]; 9333 u8 ndeo_error_threshold[0x10]; 9334 9335 u8 mixer_offset_step_size[0x10]; 9336 u8 reserved_at_110[0x8]; 9337 u8 mix90_phase_for_voltage_bath[0x8]; 9338 9339 u8 mixer_offset_start[0x10]; 9340 u8 mixer_offset_end[0x10]; 9341 9342 u8 reserved_at_140[0x15]; 9343 u8 ber_test_time[0xb]; 9344 }; 9345 9346 struct mlx5_ifc_pspa_reg_bits { 9347 u8 swid[0x8]; 9348 u8 local_port[0x8]; 9349 u8 sub_port[0x8]; 9350 u8 reserved_at_18[0x8]; 9351 9352 u8 reserved_at_20[0x20]; 9353 }; 9354 9355 struct mlx5_ifc_pqdr_reg_bits { 9356 u8 reserved_at_0[0x8]; 9357 u8 local_port[0x8]; 9358 u8 reserved_at_10[0x5]; 9359 u8 prio[0x3]; 9360 u8 reserved_at_18[0x6]; 9361 u8 mode[0x2]; 9362 9363 u8 reserved_at_20[0x20]; 9364 9365 u8 reserved_at_40[0x10]; 9366 u8 min_threshold[0x10]; 9367 9368 u8 reserved_at_60[0x10]; 9369 u8 max_threshold[0x10]; 9370 9371 u8 reserved_at_80[0x10]; 9372 u8 mark_probability_denominator[0x10]; 9373 9374 u8 reserved_at_a0[0x60]; 9375 }; 9376 9377 struct mlx5_ifc_ppsc_reg_bits { 9378 u8 reserved_at_0[0x8]; 9379 u8 local_port[0x8]; 9380 u8 reserved_at_10[0x10]; 9381 9382 u8 reserved_at_20[0x60]; 9383 9384 u8 reserved_at_80[0x1c]; 9385 u8 wrps_admin[0x4]; 9386 9387 u8 reserved_at_a0[0x1c]; 9388 u8 wrps_status[0x4]; 9389 9390 u8 reserved_at_c0[0x8]; 9391 u8 up_threshold[0x8]; 9392 u8 reserved_at_d0[0x8]; 9393 u8 down_threshold[0x8]; 9394 9395 u8 reserved_at_e0[0x20]; 9396 9397 u8 reserved_at_100[0x1c]; 9398 u8 srps_admin[0x4]; 9399 9400 u8 reserved_at_120[0x1c]; 9401 u8 srps_status[0x4]; 9402 9403 u8 reserved_at_140[0x40]; 9404 }; 9405 9406 struct mlx5_ifc_pplr_reg_bits { 9407 u8 reserved_at_0[0x8]; 9408 u8 local_port[0x8]; 9409 u8 reserved_at_10[0x10]; 9410 9411 u8 reserved_at_20[0x8]; 9412 u8 lb_cap[0x8]; 9413 u8 reserved_at_30[0x8]; 9414 u8 lb_en[0x8]; 9415 }; 9416 9417 struct mlx5_ifc_pplm_reg_bits { 9418 u8 reserved_at_0[0x8]; 9419 u8 local_port[0x8]; 9420 u8 reserved_at_10[0x10]; 9421 9422 u8 reserved_at_20[0x20]; 9423 9424 u8 port_profile_mode[0x8]; 9425 u8 static_port_profile[0x8]; 9426 u8 active_port_profile[0x8]; 9427 u8 reserved_at_58[0x8]; 9428 9429 u8 retransmission_active[0x8]; 9430 u8 fec_mode_active[0x18]; 9431 9432 u8 rs_fec_correction_bypass_cap[0x4]; 9433 u8 reserved_at_84[0x8]; 9434 u8 fec_override_cap_56g[0x4]; 9435 u8 fec_override_cap_100g[0x4]; 9436 u8 fec_override_cap_50g[0x4]; 9437 u8 fec_override_cap_25g[0x4]; 9438 u8 fec_override_cap_10g_40g[0x4]; 9439 9440 u8 rs_fec_correction_bypass_admin[0x4]; 9441 u8 reserved_at_a4[0x8]; 9442 u8 fec_override_admin_56g[0x4]; 9443 u8 fec_override_admin_100g[0x4]; 9444 u8 fec_override_admin_50g[0x4]; 9445 u8 fec_override_admin_25g[0x4]; 9446 u8 fec_override_admin_10g_40g[0x4]; 9447 9448 u8 fec_override_cap_400g_8x[0x10]; 9449 u8 fec_override_cap_200g_4x[0x10]; 9450 9451 u8 fec_override_cap_100g_2x[0x10]; 9452 u8 fec_override_cap_50g_1x[0x10]; 9453 9454 u8 fec_override_admin_400g_8x[0x10]; 9455 u8 fec_override_admin_200g_4x[0x10]; 9456 9457 u8 fec_override_admin_100g_2x[0x10]; 9458 u8 fec_override_admin_50g_1x[0x10]; 9459 9460 u8 reserved_at_140[0x140]; 9461 }; 9462 9463 struct mlx5_ifc_ppcnt_reg_bits { 9464 u8 swid[0x8]; 9465 u8 local_port[0x8]; 9466 u8 pnat[0x2]; 9467 u8 reserved_at_12[0x8]; 9468 u8 grp[0x6]; 9469 9470 u8 clr[0x1]; 9471 u8 reserved_at_21[0x1c]; 9472 u8 prio_tc[0x3]; 9473 9474 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9475 }; 9476 9477 struct mlx5_ifc_mpein_reg_bits { 9478 u8 reserved_at_0[0x2]; 9479 u8 depth[0x6]; 9480 u8 pcie_index[0x8]; 9481 u8 node[0x8]; 9482 u8 reserved_at_18[0x8]; 9483 9484 u8 capability_mask[0x20]; 9485 9486 u8 reserved_at_40[0x8]; 9487 u8 link_width_enabled[0x8]; 9488 u8 link_speed_enabled[0x10]; 9489 9490 u8 lane0_physical_position[0x8]; 9491 u8 link_width_active[0x8]; 9492 u8 link_speed_active[0x10]; 9493 9494 u8 num_of_pfs[0x10]; 9495 u8 num_of_vfs[0x10]; 9496 9497 u8 bdf0[0x10]; 9498 u8 reserved_at_b0[0x10]; 9499 9500 u8 max_read_request_size[0x4]; 9501 u8 max_payload_size[0x4]; 9502 u8 reserved_at_c8[0x5]; 9503 u8 pwr_status[0x3]; 9504 u8 port_type[0x4]; 9505 u8 reserved_at_d4[0xb]; 9506 u8 lane_reversal[0x1]; 9507 9508 u8 reserved_at_e0[0x14]; 9509 u8 pci_power[0xc]; 9510 9511 u8 reserved_at_100[0x20]; 9512 9513 u8 device_status[0x10]; 9514 u8 port_state[0x8]; 9515 u8 reserved_at_138[0x8]; 9516 9517 u8 reserved_at_140[0x10]; 9518 u8 receiver_detect_result[0x10]; 9519 9520 u8 reserved_at_160[0x20]; 9521 }; 9522 9523 struct mlx5_ifc_mpcnt_reg_bits { 9524 u8 reserved_at_0[0x8]; 9525 u8 pcie_index[0x8]; 9526 u8 reserved_at_10[0xa]; 9527 u8 grp[0x6]; 9528 9529 u8 clr[0x1]; 9530 u8 reserved_at_21[0x1f]; 9531 9532 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9533 }; 9534 9535 struct mlx5_ifc_ppad_reg_bits { 9536 u8 reserved_at_0[0x3]; 9537 u8 single_mac[0x1]; 9538 u8 reserved_at_4[0x4]; 9539 u8 local_port[0x8]; 9540 u8 mac_47_32[0x10]; 9541 9542 u8 mac_31_0[0x20]; 9543 9544 u8 reserved_at_40[0x40]; 9545 }; 9546 9547 struct mlx5_ifc_pmtu_reg_bits { 9548 u8 reserved_at_0[0x8]; 9549 u8 local_port[0x8]; 9550 u8 reserved_at_10[0x10]; 9551 9552 u8 max_mtu[0x10]; 9553 u8 reserved_at_30[0x10]; 9554 9555 u8 admin_mtu[0x10]; 9556 u8 reserved_at_50[0x10]; 9557 9558 u8 oper_mtu[0x10]; 9559 u8 reserved_at_70[0x10]; 9560 }; 9561 9562 struct mlx5_ifc_pmpr_reg_bits { 9563 u8 reserved_at_0[0x8]; 9564 u8 module[0x8]; 9565 u8 reserved_at_10[0x10]; 9566 9567 u8 reserved_at_20[0x18]; 9568 u8 attenuation_5g[0x8]; 9569 9570 u8 reserved_at_40[0x18]; 9571 u8 attenuation_7g[0x8]; 9572 9573 u8 reserved_at_60[0x18]; 9574 u8 attenuation_12g[0x8]; 9575 }; 9576 9577 struct mlx5_ifc_pmpe_reg_bits { 9578 u8 reserved_at_0[0x8]; 9579 u8 module[0x8]; 9580 u8 reserved_at_10[0xc]; 9581 u8 module_status[0x4]; 9582 9583 u8 reserved_at_20[0x60]; 9584 }; 9585 9586 struct mlx5_ifc_pmpc_reg_bits { 9587 u8 module_state_updated[32][0x8]; 9588 }; 9589 9590 struct mlx5_ifc_pmlpn_reg_bits { 9591 u8 reserved_at_0[0x4]; 9592 u8 mlpn_status[0x4]; 9593 u8 local_port[0x8]; 9594 u8 reserved_at_10[0x10]; 9595 9596 u8 e[0x1]; 9597 u8 reserved_at_21[0x1f]; 9598 }; 9599 9600 struct mlx5_ifc_pmlp_reg_bits { 9601 u8 rxtx[0x1]; 9602 u8 reserved_at_1[0x7]; 9603 u8 local_port[0x8]; 9604 u8 reserved_at_10[0x8]; 9605 u8 width[0x8]; 9606 9607 u8 lane0_module_mapping[0x20]; 9608 9609 u8 lane1_module_mapping[0x20]; 9610 9611 u8 lane2_module_mapping[0x20]; 9612 9613 u8 lane3_module_mapping[0x20]; 9614 9615 u8 reserved_at_a0[0x160]; 9616 }; 9617 9618 struct mlx5_ifc_pmaos_reg_bits { 9619 u8 reserved_at_0[0x8]; 9620 u8 module[0x8]; 9621 u8 reserved_at_10[0x4]; 9622 u8 admin_status[0x4]; 9623 u8 reserved_at_18[0x4]; 9624 u8 oper_status[0x4]; 9625 9626 u8 ase[0x1]; 9627 u8 ee[0x1]; 9628 u8 reserved_at_22[0x1c]; 9629 u8 e[0x2]; 9630 9631 u8 reserved_at_40[0x40]; 9632 }; 9633 9634 struct mlx5_ifc_plpc_reg_bits { 9635 u8 reserved_at_0[0x4]; 9636 u8 profile_id[0xc]; 9637 u8 reserved_at_10[0x4]; 9638 u8 proto_mask[0x4]; 9639 u8 reserved_at_18[0x8]; 9640 9641 u8 reserved_at_20[0x10]; 9642 u8 lane_speed[0x10]; 9643 9644 u8 reserved_at_40[0x17]; 9645 u8 lpbf[0x1]; 9646 u8 fec_mode_policy[0x8]; 9647 9648 u8 retransmission_capability[0x8]; 9649 u8 fec_mode_capability[0x18]; 9650 9651 u8 retransmission_support_admin[0x8]; 9652 u8 fec_mode_support_admin[0x18]; 9653 9654 u8 retransmission_request_admin[0x8]; 9655 u8 fec_mode_request_admin[0x18]; 9656 9657 u8 reserved_at_c0[0x80]; 9658 }; 9659 9660 struct mlx5_ifc_plib_reg_bits { 9661 u8 reserved_at_0[0x8]; 9662 u8 local_port[0x8]; 9663 u8 reserved_at_10[0x8]; 9664 u8 ib_port[0x8]; 9665 9666 u8 reserved_at_20[0x60]; 9667 }; 9668 9669 struct mlx5_ifc_plbf_reg_bits { 9670 u8 reserved_at_0[0x8]; 9671 u8 local_port[0x8]; 9672 u8 reserved_at_10[0xd]; 9673 u8 lbf_mode[0x3]; 9674 9675 u8 reserved_at_20[0x20]; 9676 }; 9677 9678 struct mlx5_ifc_pipg_reg_bits { 9679 u8 reserved_at_0[0x8]; 9680 u8 local_port[0x8]; 9681 u8 reserved_at_10[0x10]; 9682 9683 u8 dic[0x1]; 9684 u8 reserved_at_21[0x19]; 9685 u8 ipg[0x4]; 9686 u8 reserved_at_3e[0x2]; 9687 }; 9688 9689 struct mlx5_ifc_pifr_reg_bits { 9690 u8 reserved_at_0[0x8]; 9691 u8 local_port[0x8]; 9692 u8 reserved_at_10[0x10]; 9693 9694 u8 reserved_at_20[0xe0]; 9695 9696 u8 port_filter[8][0x20]; 9697 9698 u8 port_filter_update_en[8][0x20]; 9699 }; 9700 9701 struct mlx5_ifc_pfcc_reg_bits { 9702 u8 reserved_at_0[0x8]; 9703 u8 local_port[0x8]; 9704 u8 reserved_at_10[0xb]; 9705 u8 ppan_mask_n[0x1]; 9706 u8 minor_stall_mask[0x1]; 9707 u8 critical_stall_mask[0x1]; 9708 u8 reserved_at_1e[0x2]; 9709 9710 u8 ppan[0x4]; 9711 u8 reserved_at_24[0x4]; 9712 u8 prio_mask_tx[0x8]; 9713 u8 reserved_at_30[0x8]; 9714 u8 prio_mask_rx[0x8]; 9715 9716 u8 pptx[0x1]; 9717 u8 aptx[0x1]; 9718 u8 pptx_mask_n[0x1]; 9719 u8 reserved_at_43[0x5]; 9720 u8 pfctx[0x8]; 9721 u8 reserved_at_50[0x10]; 9722 9723 u8 pprx[0x1]; 9724 u8 aprx[0x1]; 9725 u8 pprx_mask_n[0x1]; 9726 u8 reserved_at_63[0x5]; 9727 u8 pfcrx[0x8]; 9728 u8 reserved_at_70[0x10]; 9729 9730 u8 device_stall_minor_watermark[0x10]; 9731 u8 device_stall_critical_watermark[0x10]; 9732 9733 u8 reserved_at_a0[0x60]; 9734 }; 9735 9736 struct mlx5_ifc_pelc_reg_bits { 9737 u8 op[0x4]; 9738 u8 reserved_at_4[0x4]; 9739 u8 local_port[0x8]; 9740 u8 reserved_at_10[0x10]; 9741 9742 u8 op_admin[0x8]; 9743 u8 op_capability[0x8]; 9744 u8 op_request[0x8]; 9745 u8 op_active[0x8]; 9746 9747 u8 admin[0x40]; 9748 9749 u8 capability[0x40]; 9750 9751 u8 request[0x40]; 9752 9753 u8 active[0x40]; 9754 9755 u8 reserved_at_140[0x80]; 9756 }; 9757 9758 struct mlx5_ifc_peir_reg_bits { 9759 u8 reserved_at_0[0x8]; 9760 u8 local_port[0x8]; 9761 u8 reserved_at_10[0x10]; 9762 9763 u8 reserved_at_20[0xc]; 9764 u8 error_count[0x4]; 9765 u8 reserved_at_30[0x10]; 9766 9767 u8 reserved_at_40[0xc]; 9768 u8 lane[0x4]; 9769 u8 reserved_at_50[0x8]; 9770 u8 error_type[0x8]; 9771 }; 9772 9773 struct mlx5_ifc_mpegc_reg_bits { 9774 u8 reserved_at_0[0x30]; 9775 u8 field_select[0x10]; 9776 9777 u8 tx_overflow_sense[0x1]; 9778 u8 mark_cqe[0x1]; 9779 u8 mark_cnp[0x1]; 9780 u8 reserved_at_43[0x1b]; 9781 u8 tx_lossy_overflow_oper[0x2]; 9782 9783 u8 reserved_at_60[0x100]; 9784 }; 9785 9786 enum { 9787 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9788 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9789 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9790 }; 9791 9792 struct mlx5_ifc_mtutc_reg_bits { 9793 u8 reserved_at_0[0x1c]; 9794 u8 operation[0x4]; 9795 9796 u8 freq_adjustment[0x20]; 9797 9798 u8 reserved_at_40[0x40]; 9799 9800 u8 utc_sec[0x20]; 9801 9802 u8 reserved_at_a0[0x2]; 9803 u8 utc_nsec[0x1e]; 9804 9805 u8 time_adjustment[0x20]; 9806 }; 9807 9808 struct mlx5_ifc_pcam_enhanced_features_bits { 9809 u8 reserved_at_0[0x68]; 9810 u8 fec_50G_per_lane_in_pplm[0x1]; 9811 u8 reserved_at_69[0x4]; 9812 u8 rx_icrc_encapsulated_counter[0x1]; 9813 u8 reserved_at_6e[0x4]; 9814 u8 ptys_extended_ethernet[0x1]; 9815 u8 reserved_at_73[0x3]; 9816 u8 pfcc_mask[0x1]; 9817 u8 reserved_at_77[0x3]; 9818 u8 per_lane_error_counters[0x1]; 9819 u8 rx_buffer_fullness_counters[0x1]; 9820 u8 ptys_connector_type[0x1]; 9821 u8 reserved_at_7d[0x1]; 9822 u8 ppcnt_discard_group[0x1]; 9823 u8 ppcnt_statistical_group[0x1]; 9824 }; 9825 9826 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9827 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9828 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9829 9830 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9831 u8 pplm[0x1]; 9832 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9833 9834 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9835 u8 pbmc[0x1]; 9836 u8 pptb[0x1]; 9837 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9838 u8 ppcnt[0x1]; 9839 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9840 }; 9841 9842 struct mlx5_ifc_pcam_reg_bits { 9843 u8 reserved_at_0[0x8]; 9844 u8 feature_group[0x8]; 9845 u8 reserved_at_10[0x8]; 9846 u8 access_reg_group[0x8]; 9847 9848 u8 reserved_at_20[0x20]; 9849 9850 union { 9851 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9852 u8 reserved_at_0[0x80]; 9853 } port_access_reg_cap_mask; 9854 9855 u8 reserved_at_c0[0x80]; 9856 9857 union { 9858 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9859 u8 reserved_at_0[0x80]; 9860 } feature_cap_mask; 9861 9862 u8 reserved_at_1c0[0xc0]; 9863 }; 9864 9865 struct mlx5_ifc_mcam_enhanced_features_bits { 9866 u8 reserved_at_0[0x5d]; 9867 u8 mcia_32dwords[0x1]; 9868 u8 out_pulse_duration_ns[0x1]; 9869 u8 npps_period[0x1]; 9870 u8 reserved_at_60[0xa]; 9871 u8 reset_state[0x1]; 9872 u8 ptpcyc2realtime_modify[0x1]; 9873 u8 reserved_at_6c[0x2]; 9874 u8 pci_status_and_power[0x1]; 9875 u8 reserved_at_6f[0x5]; 9876 u8 mark_tx_action_cnp[0x1]; 9877 u8 mark_tx_action_cqe[0x1]; 9878 u8 dynamic_tx_overflow[0x1]; 9879 u8 reserved_at_77[0x4]; 9880 u8 pcie_outbound_stalled[0x1]; 9881 u8 tx_overflow_buffer_pkt[0x1]; 9882 u8 mtpps_enh_out_per_adj[0x1]; 9883 u8 mtpps_fs[0x1]; 9884 u8 pcie_performance_group[0x1]; 9885 }; 9886 9887 struct mlx5_ifc_mcam_access_reg_bits { 9888 u8 reserved_at_0[0x1c]; 9889 u8 mcda[0x1]; 9890 u8 mcc[0x1]; 9891 u8 mcqi[0x1]; 9892 u8 mcqs[0x1]; 9893 9894 u8 regs_95_to_87[0x9]; 9895 u8 mpegc[0x1]; 9896 u8 mtutc[0x1]; 9897 u8 regs_84_to_68[0x11]; 9898 u8 tracer_registers[0x4]; 9899 9900 u8 regs_63_to_46[0x12]; 9901 u8 mrtc[0x1]; 9902 u8 regs_44_to_32[0xd]; 9903 9904 u8 regs_31_to_0[0x20]; 9905 }; 9906 9907 struct mlx5_ifc_mcam_access_reg_bits1 { 9908 u8 regs_127_to_96[0x20]; 9909 9910 u8 regs_95_to_64[0x20]; 9911 9912 u8 regs_63_to_32[0x20]; 9913 9914 u8 regs_31_to_0[0x20]; 9915 }; 9916 9917 struct mlx5_ifc_mcam_access_reg_bits2 { 9918 u8 regs_127_to_99[0x1d]; 9919 u8 mirc[0x1]; 9920 u8 regs_97_to_96[0x2]; 9921 9922 u8 regs_95_to_64[0x20]; 9923 9924 u8 regs_63_to_32[0x20]; 9925 9926 u8 regs_31_to_0[0x20]; 9927 }; 9928 9929 struct mlx5_ifc_mcam_reg_bits { 9930 u8 reserved_at_0[0x8]; 9931 u8 feature_group[0x8]; 9932 u8 reserved_at_10[0x8]; 9933 u8 access_reg_group[0x8]; 9934 9935 u8 reserved_at_20[0x20]; 9936 9937 union { 9938 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9939 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9940 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9941 u8 reserved_at_0[0x80]; 9942 } mng_access_reg_cap_mask; 9943 9944 u8 reserved_at_c0[0x80]; 9945 9946 union { 9947 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9948 u8 reserved_at_0[0x80]; 9949 } mng_feature_cap_mask; 9950 9951 u8 reserved_at_1c0[0x80]; 9952 }; 9953 9954 struct mlx5_ifc_qcam_access_reg_cap_mask { 9955 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9956 u8 qpdpm[0x1]; 9957 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9958 u8 qdpm[0x1]; 9959 u8 qpts[0x1]; 9960 u8 qcap[0x1]; 9961 u8 qcam_access_reg_cap_mask_0[0x1]; 9962 }; 9963 9964 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9965 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9966 u8 qpts_trust_both[0x1]; 9967 }; 9968 9969 struct mlx5_ifc_qcam_reg_bits { 9970 u8 reserved_at_0[0x8]; 9971 u8 feature_group[0x8]; 9972 u8 reserved_at_10[0x8]; 9973 u8 access_reg_group[0x8]; 9974 u8 reserved_at_20[0x20]; 9975 9976 union { 9977 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9978 u8 reserved_at_0[0x80]; 9979 } qos_access_reg_cap_mask; 9980 9981 u8 reserved_at_c0[0x80]; 9982 9983 union { 9984 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9985 u8 reserved_at_0[0x80]; 9986 } qos_feature_cap_mask; 9987 9988 u8 reserved_at_1c0[0x80]; 9989 }; 9990 9991 struct mlx5_ifc_core_dump_reg_bits { 9992 u8 reserved_at_0[0x18]; 9993 u8 core_dump_type[0x8]; 9994 9995 u8 reserved_at_20[0x30]; 9996 u8 vhca_id[0x10]; 9997 9998 u8 reserved_at_60[0x8]; 9999 u8 qpn[0x18]; 10000 u8 reserved_at_80[0x180]; 10001 }; 10002 10003 struct mlx5_ifc_pcap_reg_bits { 10004 u8 reserved_at_0[0x8]; 10005 u8 local_port[0x8]; 10006 u8 reserved_at_10[0x10]; 10007 10008 u8 port_capability_mask[4][0x20]; 10009 }; 10010 10011 struct mlx5_ifc_paos_reg_bits { 10012 u8 swid[0x8]; 10013 u8 local_port[0x8]; 10014 u8 reserved_at_10[0x4]; 10015 u8 admin_status[0x4]; 10016 u8 reserved_at_18[0x4]; 10017 u8 oper_status[0x4]; 10018 10019 u8 ase[0x1]; 10020 u8 ee[0x1]; 10021 u8 reserved_at_22[0x1c]; 10022 u8 e[0x2]; 10023 10024 u8 reserved_at_40[0x40]; 10025 }; 10026 10027 struct mlx5_ifc_pamp_reg_bits { 10028 u8 reserved_at_0[0x8]; 10029 u8 opamp_group[0x8]; 10030 u8 reserved_at_10[0xc]; 10031 u8 opamp_group_type[0x4]; 10032 10033 u8 start_index[0x10]; 10034 u8 reserved_at_30[0x4]; 10035 u8 num_of_indices[0xc]; 10036 10037 u8 index_data[18][0x10]; 10038 }; 10039 10040 struct mlx5_ifc_pcmr_reg_bits { 10041 u8 reserved_at_0[0x8]; 10042 u8 local_port[0x8]; 10043 u8 reserved_at_10[0x10]; 10044 10045 u8 entropy_force_cap[0x1]; 10046 u8 entropy_calc_cap[0x1]; 10047 u8 entropy_gre_calc_cap[0x1]; 10048 u8 reserved_at_23[0xf]; 10049 u8 rx_ts_over_crc_cap[0x1]; 10050 u8 reserved_at_33[0xb]; 10051 u8 fcs_cap[0x1]; 10052 u8 reserved_at_3f[0x1]; 10053 10054 u8 entropy_force[0x1]; 10055 u8 entropy_calc[0x1]; 10056 u8 entropy_gre_calc[0x1]; 10057 u8 reserved_at_43[0xf]; 10058 u8 rx_ts_over_crc[0x1]; 10059 u8 reserved_at_53[0xb]; 10060 u8 fcs_chk[0x1]; 10061 u8 reserved_at_5f[0x1]; 10062 }; 10063 10064 struct mlx5_ifc_lane_2_module_mapping_bits { 10065 u8 reserved_at_0[0x4]; 10066 u8 rx_lane[0x4]; 10067 u8 reserved_at_8[0x4]; 10068 u8 tx_lane[0x4]; 10069 u8 reserved_at_10[0x8]; 10070 u8 module[0x8]; 10071 }; 10072 10073 struct mlx5_ifc_bufferx_reg_bits { 10074 u8 reserved_at_0[0x6]; 10075 u8 lossy[0x1]; 10076 u8 epsb[0x1]; 10077 u8 reserved_at_8[0x8]; 10078 u8 size[0x10]; 10079 10080 u8 xoff_threshold[0x10]; 10081 u8 xon_threshold[0x10]; 10082 }; 10083 10084 struct mlx5_ifc_set_node_in_bits { 10085 u8 node_description[64][0x8]; 10086 }; 10087 10088 struct mlx5_ifc_register_power_settings_bits { 10089 u8 reserved_at_0[0x18]; 10090 u8 power_settings_level[0x8]; 10091 10092 u8 reserved_at_20[0x60]; 10093 }; 10094 10095 struct mlx5_ifc_register_host_endianness_bits { 10096 u8 he[0x1]; 10097 u8 reserved_at_1[0x1f]; 10098 10099 u8 reserved_at_20[0x60]; 10100 }; 10101 10102 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10103 u8 reserved_at_0[0x20]; 10104 10105 u8 mkey[0x20]; 10106 10107 u8 addressh_63_32[0x20]; 10108 10109 u8 addressl_31_0[0x20]; 10110 }; 10111 10112 struct mlx5_ifc_ud_adrs_vector_bits { 10113 u8 dc_key[0x40]; 10114 10115 u8 ext[0x1]; 10116 u8 reserved_at_41[0x7]; 10117 u8 destination_qp_dct[0x18]; 10118 10119 u8 static_rate[0x4]; 10120 u8 sl_eth_prio[0x4]; 10121 u8 fl[0x1]; 10122 u8 mlid[0x7]; 10123 u8 rlid_udp_sport[0x10]; 10124 10125 u8 reserved_at_80[0x20]; 10126 10127 u8 rmac_47_16[0x20]; 10128 10129 u8 rmac_15_0[0x10]; 10130 u8 tclass[0x8]; 10131 u8 hop_limit[0x8]; 10132 10133 u8 reserved_at_e0[0x1]; 10134 u8 grh[0x1]; 10135 u8 reserved_at_e2[0x2]; 10136 u8 src_addr_index[0x8]; 10137 u8 flow_label[0x14]; 10138 10139 u8 rgid_rip[16][0x8]; 10140 }; 10141 10142 struct mlx5_ifc_pages_req_event_bits { 10143 u8 reserved_at_0[0x10]; 10144 u8 function_id[0x10]; 10145 10146 u8 num_pages[0x20]; 10147 10148 u8 reserved_at_40[0xa0]; 10149 }; 10150 10151 struct mlx5_ifc_eqe_bits { 10152 u8 reserved_at_0[0x8]; 10153 u8 event_type[0x8]; 10154 u8 reserved_at_10[0x8]; 10155 u8 event_sub_type[0x8]; 10156 10157 u8 reserved_at_20[0xe0]; 10158 10159 union mlx5_ifc_event_auto_bits event_data; 10160 10161 u8 reserved_at_1e0[0x10]; 10162 u8 signature[0x8]; 10163 u8 reserved_at_1f8[0x7]; 10164 u8 owner[0x1]; 10165 }; 10166 10167 enum { 10168 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10169 }; 10170 10171 struct mlx5_ifc_cmd_queue_entry_bits { 10172 u8 type[0x8]; 10173 u8 reserved_at_8[0x18]; 10174 10175 u8 input_length[0x20]; 10176 10177 u8 input_mailbox_pointer_63_32[0x20]; 10178 10179 u8 input_mailbox_pointer_31_9[0x17]; 10180 u8 reserved_at_77[0x9]; 10181 10182 u8 command_input_inline_data[16][0x8]; 10183 10184 u8 command_output_inline_data[16][0x8]; 10185 10186 u8 output_mailbox_pointer_63_32[0x20]; 10187 10188 u8 output_mailbox_pointer_31_9[0x17]; 10189 u8 reserved_at_1b7[0x9]; 10190 10191 u8 output_length[0x20]; 10192 10193 u8 token[0x8]; 10194 u8 signature[0x8]; 10195 u8 reserved_at_1f0[0x8]; 10196 u8 status[0x7]; 10197 u8 ownership[0x1]; 10198 }; 10199 10200 struct mlx5_ifc_cmd_out_bits { 10201 u8 status[0x8]; 10202 u8 reserved_at_8[0x18]; 10203 10204 u8 syndrome[0x20]; 10205 10206 u8 command_output[0x20]; 10207 }; 10208 10209 struct mlx5_ifc_cmd_in_bits { 10210 u8 opcode[0x10]; 10211 u8 reserved_at_10[0x10]; 10212 10213 u8 reserved_at_20[0x10]; 10214 u8 op_mod[0x10]; 10215 10216 u8 command[][0x20]; 10217 }; 10218 10219 struct mlx5_ifc_cmd_if_box_bits { 10220 u8 mailbox_data[512][0x8]; 10221 10222 u8 reserved_at_1000[0x180]; 10223 10224 u8 next_pointer_63_32[0x20]; 10225 10226 u8 next_pointer_31_10[0x16]; 10227 u8 reserved_at_11b6[0xa]; 10228 10229 u8 block_number[0x20]; 10230 10231 u8 reserved_at_11e0[0x8]; 10232 u8 token[0x8]; 10233 u8 ctrl_signature[0x8]; 10234 u8 signature[0x8]; 10235 }; 10236 10237 struct mlx5_ifc_mtt_bits { 10238 u8 ptag_63_32[0x20]; 10239 10240 u8 ptag_31_8[0x18]; 10241 u8 reserved_at_38[0x6]; 10242 u8 wr_en[0x1]; 10243 u8 rd_en[0x1]; 10244 }; 10245 10246 struct mlx5_ifc_query_wol_rol_out_bits { 10247 u8 status[0x8]; 10248 u8 reserved_at_8[0x18]; 10249 10250 u8 syndrome[0x20]; 10251 10252 u8 reserved_at_40[0x10]; 10253 u8 rol_mode[0x8]; 10254 u8 wol_mode[0x8]; 10255 10256 u8 reserved_at_60[0x20]; 10257 }; 10258 10259 struct mlx5_ifc_query_wol_rol_in_bits { 10260 u8 opcode[0x10]; 10261 u8 reserved_at_10[0x10]; 10262 10263 u8 reserved_at_20[0x10]; 10264 u8 op_mod[0x10]; 10265 10266 u8 reserved_at_40[0x40]; 10267 }; 10268 10269 struct mlx5_ifc_set_wol_rol_out_bits { 10270 u8 status[0x8]; 10271 u8 reserved_at_8[0x18]; 10272 10273 u8 syndrome[0x20]; 10274 10275 u8 reserved_at_40[0x40]; 10276 }; 10277 10278 struct mlx5_ifc_set_wol_rol_in_bits { 10279 u8 opcode[0x10]; 10280 u8 reserved_at_10[0x10]; 10281 10282 u8 reserved_at_20[0x10]; 10283 u8 op_mod[0x10]; 10284 10285 u8 rol_mode_valid[0x1]; 10286 u8 wol_mode_valid[0x1]; 10287 u8 reserved_at_42[0xe]; 10288 u8 rol_mode[0x8]; 10289 u8 wol_mode[0x8]; 10290 10291 u8 reserved_at_60[0x20]; 10292 }; 10293 10294 enum { 10295 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10296 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10297 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10298 }; 10299 10300 enum { 10301 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10302 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10303 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10304 }; 10305 10306 enum { 10307 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10308 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10309 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10310 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10311 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10312 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10313 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10314 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10315 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10316 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10317 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10318 }; 10319 10320 struct mlx5_ifc_initial_seg_bits { 10321 u8 fw_rev_minor[0x10]; 10322 u8 fw_rev_major[0x10]; 10323 10324 u8 cmd_interface_rev[0x10]; 10325 u8 fw_rev_subminor[0x10]; 10326 10327 u8 reserved_at_40[0x40]; 10328 10329 u8 cmdq_phy_addr_63_32[0x20]; 10330 10331 u8 cmdq_phy_addr_31_12[0x14]; 10332 u8 reserved_at_b4[0x2]; 10333 u8 nic_interface[0x2]; 10334 u8 log_cmdq_size[0x4]; 10335 u8 log_cmdq_stride[0x4]; 10336 10337 u8 command_doorbell_vector[0x20]; 10338 10339 u8 reserved_at_e0[0xf00]; 10340 10341 u8 initializing[0x1]; 10342 u8 reserved_at_fe1[0x4]; 10343 u8 nic_interface_supported[0x3]; 10344 u8 embedded_cpu[0x1]; 10345 u8 reserved_at_fe9[0x17]; 10346 10347 struct mlx5_ifc_health_buffer_bits health_buffer; 10348 10349 u8 no_dram_nic_offset[0x20]; 10350 10351 u8 reserved_at_1220[0x6e40]; 10352 10353 u8 reserved_at_8060[0x1f]; 10354 u8 clear_int[0x1]; 10355 10356 u8 health_syndrome[0x8]; 10357 u8 health_counter[0x18]; 10358 10359 u8 reserved_at_80a0[0x17fc0]; 10360 }; 10361 10362 struct mlx5_ifc_mtpps_reg_bits { 10363 u8 reserved_at_0[0xc]; 10364 u8 cap_number_of_pps_pins[0x4]; 10365 u8 reserved_at_10[0x4]; 10366 u8 cap_max_num_of_pps_in_pins[0x4]; 10367 u8 reserved_at_18[0x4]; 10368 u8 cap_max_num_of_pps_out_pins[0x4]; 10369 10370 u8 reserved_at_20[0x13]; 10371 u8 cap_log_min_npps_period[0x5]; 10372 u8 reserved_at_38[0x3]; 10373 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10374 10375 u8 reserved_at_40[0x4]; 10376 u8 cap_pin_3_mode[0x4]; 10377 u8 reserved_at_48[0x4]; 10378 u8 cap_pin_2_mode[0x4]; 10379 u8 reserved_at_50[0x4]; 10380 u8 cap_pin_1_mode[0x4]; 10381 u8 reserved_at_58[0x4]; 10382 u8 cap_pin_0_mode[0x4]; 10383 10384 u8 reserved_at_60[0x4]; 10385 u8 cap_pin_7_mode[0x4]; 10386 u8 reserved_at_68[0x4]; 10387 u8 cap_pin_6_mode[0x4]; 10388 u8 reserved_at_70[0x4]; 10389 u8 cap_pin_5_mode[0x4]; 10390 u8 reserved_at_78[0x4]; 10391 u8 cap_pin_4_mode[0x4]; 10392 10393 u8 field_select[0x20]; 10394 u8 reserved_at_a0[0x20]; 10395 10396 u8 npps_period[0x40]; 10397 10398 u8 enable[0x1]; 10399 u8 reserved_at_101[0xb]; 10400 u8 pattern[0x4]; 10401 u8 reserved_at_110[0x4]; 10402 u8 pin_mode[0x4]; 10403 u8 pin[0x8]; 10404 10405 u8 reserved_at_120[0x2]; 10406 u8 out_pulse_duration_ns[0x1e]; 10407 10408 u8 time_stamp[0x40]; 10409 10410 u8 out_pulse_duration[0x10]; 10411 u8 out_periodic_adjustment[0x10]; 10412 u8 enhanced_out_periodic_adjustment[0x20]; 10413 10414 u8 reserved_at_1c0[0x20]; 10415 }; 10416 10417 struct mlx5_ifc_mtppse_reg_bits { 10418 u8 reserved_at_0[0x18]; 10419 u8 pin[0x8]; 10420 u8 event_arm[0x1]; 10421 u8 reserved_at_21[0x1b]; 10422 u8 event_generation_mode[0x4]; 10423 u8 reserved_at_40[0x40]; 10424 }; 10425 10426 struct mlx5_ifc_mcqs_reg_bits { 10427 u8 last_index_flag[0x1]; 10428 u8 reserved_at_1[0x7]; 10429 u8 fw_device[0x8]; 10430 u8 component_index[0x10]; 10431 10432 u8 reserved_at_20[0x10]; 10433 u8 identifier[0x10]; 10434 10435 u8 reserved_at_40[0x17]; 10436 u8 component_status[0x5]; 10437 u8 component_update_state[0x4]; 10438 10439 u8 last_update_state_changer_type[0x4]; 10440 u8 last_update_state_changer_host_id[0x4]; 10441 u8 reserved_at_68[0x18]; 10442 }; 10443 10444 struct mlx5_ifc_mcqi_cap_bits { 10445 u8 supported_info_bitmask[0x20]; 10446 10447 u8 component_size[0x20]; 10448 10449 u8 max_component_size[0x20]; 10450 10451 u8 log_mcda_word_size[0x4]; 10452 u8 reserved_at_64[0xc]; 10453 u8 mcda_max_write_size[0x10]; 10454 10455 u8 rd_en[0x1]; 10456 u8 reserved_at_81[0x1]; 10457 u8 match_chip_id[0x1]; 10458 u8 match_psid[0x1]; 10459 u8 check_user_timestamp[0x1]; 10460 u8 match_base_guid_mac[0x1]; 10461 u8 reserved_at_86[0x1a]; 10462 }; 10463 10464 struct mlx5_ifc_mcqi_version_bits { 10465 u8 reserved_at_0[0x2]; 10466 u8 build_time_valid[0x1]; 10467 u8 user_defined_time_valid[0x1]; 10468 u8 reserved_at_4[0x14]; 10469 u8 version_string_length[0x8]; 10470 10471 u8 version[0x20]; 10472 10473 u8 build_time[0x40]; 10474 10475 u8 user_defined_time[0x40]; 10476 10477 u8 build_tool_version[0x20]; 10478 10479 u8 reserved_at_e0[0x20]; 10480 10481 u8 version_string[92][0x8]; 10482 }; 10483 10484 struct mlx5_ifc_mcqi_activation_method_bits { 10485 u8 pending_server_ac_power_cycle[0x1]; 10486 u8 pending_server_dc_power_cycle[0x1]; 10487 u8 pending_server_reboot[0x1]; 10488 u8 pending_fw_reset[0x1]; 10489 u8 auto_activate[0x1]; 10490 u8 all_hosts_sync[0x1]; 10491 u8 device_hw_reset[0x1]; 10492 u8 reserved_at_7[0x19]; 10493 }; 10494 10495 union mlx5_ifc_mcqi_reg_data_bits { 10496 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10497 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10498 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10499 }; 10500 10501 struct mlx5_ifc_mcqi_reg_bits { 10502 u8 read_pending_component[0x1]; 10503 u8 reserved_at_1[0xf]; 10504 u8 component_index[0x10]; 10505 10506 u8 reserved_at_20[0x20]; 10507 10508 u8 reserved_at_40[0x1b]; 10509 u8 info_type[0x5]; 10510 10511 u8 info_size[0x20]; 10512 10513 u8 offset[0x20]; 10514 10515 u8 reserved_at_a0[0x10]; 10516 u8 data_size[0x10]; 10517 10518 union mlx5_ifc_mcqi_reg_data_bits data[]; 10519 }; 10520 10521 struct mlx5_ifc_mcc_reg_bits { 10522 u8 reserved_at_0[0x4]; 10523 u8 time_elapsed_since_last_cmd[0xc]; 10524 u8 reserved_at_10[0x8]; 10525 u8 instruction[0x8]; 10526 10527 u8 reserved_at_20[0x10]; 10528 u8 component_index[0x10]; 10529 10530 u8 reserved_at_40[0x8]; 10531 u8 update_handle[0x18]; 10532 10533 u8 handle_owner_type[0x4]; 10534 u8 handle_owner_host_id[0x4]; 10535 u8 reserved_at_68[0x1]; 10536 u8 control_progress[0x7]; 10537 u8 error_code[0x8]; 10538 u8 reserved_at_78[0x4]; 10539 u8 control_state[0x4]; 10540 10541 u8 component_size[0x20]; 10542 10543 u8 reserved_at_a0[0x60]; 10544 }; 10545 10546 struct mlx5_ifc_mcda_reg_bits { 10547 u8 reserved_at_0[0x8]; 10548 u8 update_handle[0x18]; 10549 10550 u8 offset[0x20]; 10551 10552 u8 reserved_at_40[0x10]; 10553 u8 size[0x10]; 10554 10555 u8 reserved_at_60[0x20]; 10556 10557 u8 data[][0x20]; 10558 }; 10559 10560 enum { 10561 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10562 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10563 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10564 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10565 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10566 }; 10567 10568 enum { 10569 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10570 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10571 }; 10572 10573 enum { 10574 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10575 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10576 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10577 }; 10578 10579 struct mlx5_ifc_mfrl_reg_bits { 10580 u8 reserved_at_0[0x20]; 10581 10582 u8 reserved_at_20[0x2]; 10583 u8 pci_sync_for_fw_update_start[0x1]; 10584 u8 pci_sync_for_fw_update_resp[0x2]; 10585 u8 rst_type_sel[0x3]; 10586 u8 reserved_at_28[0x4]; 10587 u8 reset_state[0x4]; 10588 u8 reset_type[0x8]; 10589 u8 reset_level[0x8]; 10590 }; 10591 10592 struct mlx5_ifc_mirc_reg_bits { 10593 u8 reserved_at_0[0x18]; 10594 u8 status_code[0x8]; 10595 10596 u8 reserved_at_20[0x20]; 10597 }; 10598 10599 struct mlx5_ifc_pddr_monitor_opcode_bits { 10600 u8 reserved_at_0[0x10]; 10601 u8 monitor_opcode[0x10]; 10602 }; 10603 10604 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10605 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10606 u8 reserved_at_0[0x20]; 10607 }; 10608 10609 enum { 10610 /* Monitor opcodes */ 10611 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10612 }; 10613 10614 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10615 u8 reserved_at_0[0x10]; 10616 u8 group_opcode[0x10]; 10617 10618 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10619 10620 u8 reserved_at_40[0x20]; 10621 10622 u8 status_message[59][0x20]; 10623 }; 10624 10625 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10626 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10627 u8 reserved_at_0[0x7c0]; 10628 }; 10629 10630 enum { 10631 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10632 }; 10633 10634 struct mlx5_ifc_pddr_reg_bits { 10635 u8 reserved_at_0[0x8]; 10636 u8 local_port[0x8]; 10637 u8 pnat[0x2]; 10638 u8 reserved_at_12[0xe]; 10639 10640 u8 reserved_at_20[0x18]; 10641 u8 page_select[0x8]; 10642 10643 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10644 }; 10645 10646 struct mlx5_ifc_mrtc_reg_bits { 10647 u8 time_synced[0x1]; 10648 u8 reserved_at_1[0x1f]; 10649 10650 u8 reserved_at_20[0x20]; 10651 10652 u8 time_h[0x20]; 10653 10654 u8 time_l[0x20]; 10655 }; 10656 10657 union mlx5_ifc_ports_control_registers_document_bits { 10658 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10659 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10660 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10661 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10662 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10663 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10664 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10665 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10666 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10667 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10668 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10669 struct mlx5_ifc_paos_reg_bits paos_reg; 10670 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10671 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10672 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10673 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10674 struct mlx5_ifc_peir_reg_bits peir_reg; 10675 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10676 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10677 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10678 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10679 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10680 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10681 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10682 struct mlx5_ifc_plib_reg_bits plib_reg; 10683 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10684 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10685 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10686 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10687 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10688 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10689 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10690 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10691 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10692 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10693 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10694 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10695 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10696 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10697 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10698 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10699 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10700 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10701 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10702 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10703 struct mlx5_ifc_pude_reg_bits pude_reg; 10704 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10705 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10706 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10707 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10708 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10709 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10710 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10711 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10712 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10713 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10714 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10715 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10716 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10717 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10718 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10719 u8 reserved_at_0[0x60e0]; 10720 }; 10721 10722 union mlx5_ifc_debug_enhancements_document_bits { 10723 struct mlx5_ifc_health_buffer_bits health_buffer; 10724 u8 reserved_at_0[0x200]; 10725 }; 10726 10727 union mlx5_ifc_uplink_pci_interface_document_bits { 10728 struct mlx5_ifc_initial_seg_bits initial_seg; 10729 u8 reserved_at_0[0x20060]; 10730 }; 10731 10732 struct mlx5_ifc_set_flow_table_root_out_bits { 10733 u8 status[0x8]; 10734 u8 reserved_at_8[0x18]; 10735 10736 u8 syndrome[0x20]; 10737 10738 u8 reserved_at_40[0x40]; 10739 }; 10740 10741 struct mlx5_ifc_set_flow_table_root_in_bits { 10742 u8 opcode[0x10]; 10743 u8 reserved_at_10[0x10]; 10744 10745 u8 reserved_at_20[0x10]; 10746 u8 op_mod[0x10]; 10747 10748 u8 other_vport[0x1]; 10749 u8 reserved_at_41[0xf]; 10750 u8 vport_number[0x10]; 10751 10752 u8 reserved_at_60[0x20]; 10753 10754 u8 table_type[0x8]; 10755 u8 reserved_at_88[0x7]; 10756 u8 table_of_other_vport[0x1]; 10757 u8 table_vport_number[0x10]; 10758 10759 u8 reserved_at_a0[0x8]; 10760 u8 table_id[0x18]; 10761 10762 u8 reserved_at_c0[0x8]; 10763 u8 underlay_qpn[0x18]; 10764 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10765 u8 reserved_at_e1[0xf]; 10766 u8 table_eswitch_owner_vhca_id[0x10]; 10767 u8 reserved_at_100[0x100]; 10768 }; 10769 10770 enum { 10771 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10772 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10773 }; 10774 10775 struct mlx5_ifc_modify_flow_table_out_bits { 10776 u8 status[0x8]; 10777 u8 reserved_at_8[0x18]; 10778 10779 u8 syndrome[0x20]; 10780 10781 u8 reserved_at_40[0x40]; 10782 }; 10783 10784 struct mlx5_ifc_modify_flow_table_in_bits { 10785 u8 opcode[0x10]; 10786 u8 reserved_at_10[0x10]; 10787 10788 u8 reserved_at_20[0x10]; 10789 u8 op_mod[0x10]; 10790 10791 u8 other_vport[0x1]; 10792 u8 reserved_at_41[0xf]; 10793 u8 vport_number[0x10]; 10794 10795 u8 reserved_at_60[0x10]; 10796 u8 modify_field_select[0x10]; 10797 10798 u8 table_type[0x8]; 10799 u8 reserved_at_88[0x18]; 10800 10801 u8 reserved_at_a0[0x8]; 10802 u8 table_id[0x18]; 10803 10804 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10805 }; 10806 10807 struct mlx5_ifc_ets_tcn_config_reg_bits { 10808 u8 g[0x1]; 10809 u8 b[0x1]; 10810 u8 r[0x1]; 10811 u8 reserved_at_3[0x9]; 10812 u8 group[0x4]; 10813 u8 reserved_at_10[0x9]; 10814 u8 bw_allocation[0x7]; 10815 10816 u8 reserved_at_20[0xc]; 10817 u8 max_bw_units[0x4]; 10818 u8 reserved_at_30[0x8]; 10819 u8 max_bw_value[0x8]; 10820 }; 10821 10822 struct mlx5_ifc_ets_global_config_reg_bits { 10823 u8 reserved_at_0[0x2]; 10824 u8 r[0x1]; 10825 u8 reserved_at_3[0x1d]; 10826 10827 u8 reserved_at_20[0xc]; 10828 u8 max_bw_units[0x4]; 10829 u8 reserved_at_30[0x8]; 10830 u8 max_bw_value[0x8]; 10831 }; 10832 10833 struct mlx5_ifc_qetc_reg_bits { 10834 u8 reserved_at_0[0x8]; 10835 u8 port_number[0x8]; 10836 u8 reserved_at_10[0x30]; 10837 10838 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10839 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10840 }; 10841 10842 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10843 u8 e[0x1]; 10844 u8 reserved_at_01[0x0b]; 10845 u8 prio[0x04]; 10846 }; 10847 10848 struct mlx5_ifc_qpdpm_reg_bits { 10849 u8 reserved_at_0[0x8]; 10850 u8 local_port[0x8]; 10851 u8 reserved_at_10[0x10]; 10852 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10853 }; 10854 10855 struct mlx5_ifc_qpts_reg_bits { 10856 u8 reserved_at_0[0x8]; 10857 u8 local_port[0x8]; 10858 u8 reserved_at_10[0x2d]; 10859 u8 trust_state[0x3]; 10860 }; 10861 10862 struct mlx5_ifc_pptb_reg_bits { 10863 u8 reserved_at_0[0x2]; 10864 u8 mm[0x2]; 10865 u8 reserved_at_4[0x4]; 10866 u8 local_port[0x8]; 10867 u8 reserved_at_10[0x6]; 10868 u8 cm[0x1]; 10869 u8 um[0x1]; 10870 u8 pm[0x8]; 10871 10872 u8 prio_x_buff[0x20]; 10873 10874 u8 pm_msb[0x8]; 10875 u8 reserved_at_48[0x10]; 10876 u8 ctrl_buff[0x4]; 10877 u8 untagged_buff[0x4]; 10878 }; 10879 10880 struct mlx5_ifc_sbcam_reg_bits { 10881 u8 reserved_at_0[0x8]; 10882 u8 feature_group[0x8]; 10883 u8 reserved_at_10[0x8]; 10884 u8 access_reg_group[0x8]; 10885 10886 u8 reserved_at_20[0x20]; 10887 10888 u8 sb_access_reg_cap_mask[4][0x20]; 10889 10890 u8 reserved_at_c0[0x80]; 10891 10892 u8 sb_feature_cap_mask[4][0x20]; 10893 10894 u8 reserved_at_1c0[0x40]; 10895 10896 u8 cap_total_buffer_size[0x20]; 10897 10898 u8 cap_cell_size[0x10]; 10899 u8 cap_max_pg_buffers[0x8]; 10900 u8 cap_num_pool_supported[0x8]; 10901 10902 u8 reserved_at_240[0x8]; 10903 u8 cap_sbsr_stat_size[0x8]; 10904 u8 cap_max_tclass_data[0x8]; 10905 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10906 }; 10907 10908 struct mlx5_ifc_pbmc_reg_bits { 10909 u8 reserved_at_0[0x8]; 10910 u8 local_port[0x8]; 10911 u8 reserved_at_10[0x10]; 10912 10913 u8 xoff_timer_value[0x10]; 10914 u8 xoff_refresh[0x10]; 10915 10916 u8 reserved_at_40[0x9]; 10917 u8 fullness_threshold[0x7]; 10918 u8 port_buffer_size[0x10]; 10919 10920 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10921 10922 u8 reserved_at_2e0[0x80]; 10923 }; 10924 10925 struct mlx5_ifc_qtct_reg_bits { 10926 u8 reserved_at_0[0x8]; 10927 u8 port_number[0x8]; 10928 u8 reserved_at_10[0xd]; 10929 u8 prio[0x3]; 10930 10931 u8 reserved_at_20[0x1d]; 10932 u8 tclass[0x3]; 10933 }; 10934 10935 struct mlx5_ifc_mcia_reg_bits { 10936 u8 l[0x1]; 10937 u8 reserved_at_1[0x7]; 10938 u8 module[0x8]; 10939 u8 reserved_at_10[0x8]; 10940 u8 status[0x8]; 10941 10942 u8 i2c_device_address[0x8]; 10943 u8 page_number[0x8]; 10944 u8 device_address[0x10]; 10945 10946 u8 reserved_at_40[0x10]; 10947 u8 size[0x10]; 10948 10949 u8 reserved_at_60[0x20]; 10950 10951 u8 dword_0[0x20]; 10952 u8 dword_1[0x20]; 10953 u8 dword_2[0x20]; 10954 u8 dword_3[0x20]; 10955 u8 dword_4[0x20]; 10956 u8 dword_5[0x20]; 10957 u8 dword_6[0x20]; 10958 u8 dword_7[0x20]; 10959 u8 dword_8[0x20]; 10960 u8 dword_9[0x20]; 10961 u8 dword_10[0x20]; 10962 u8 dword_11[0x20]; 10963 }; 10964 10965 struct mlx5_ifc_dcbx_param_bits { 10966 u8 dcbx_cee_cap[0x1]; 10967 u8 dcbx_ieee_cap[0x1]; 10968 u8 dcbx_standby_cap[0x1]; 10969 u8 reserved_at_3[0x5]; 10970 u8 port_number[0x8]; 10971 u8 reserved_at_10[0xa]; 10972 u8 max_application_table_size[6]; 10973 u8 reserved_at_20[0x15]; 10974 u8 version_oper[0x3]; 10975 u8 reserved_at_38[5]; 10976 u8 version_admin[0x3]; 10977 u8 willing_admin[0x1]; 10978 u8 reserved_at_41[0x3]; 10979 u8 pfc_cap_oper[0x4]; 10980 u8 reserved_at_48[0x4]; 10981 u8 pfc_cap_admin[0x4]; 10982 u8 reserved_at_50[0x4]; 10983 u8 num_of_tc_oper[0x4]; 10984 u8 reserved_at_58[0x4]; 10985 u8 num_of_tc_admin[0x4]; 10986 u8 remote_willing[0x1]; 10987 u8 reserved_at_61[3]; 10988 u8 remote_pfc_cap[4]; 10989 u8 reserved_at_68[0x14]; 10990 u8 remote_num_of_tc[0x4]; 10991 u8 reserved_at_80[0x18]; 10992 u8 error[0x8]; 10993 u8 reserved_at_a0[0x160]; 10994 }; 10995 10996 enum { 10997 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10998 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10999 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11000 }; 11001 11002 struct mlx5_ifc_lagc_bits { 11003 u8 fdb_selection_mode[0x1]; 11004 u8 reserved_at_1[0x14]; 11005 u8 port_select_mode[0x3]; 11006 u8 reserved_at_18[0x5]; 11007 u8 lag_state[0x3]; 11008 11009 u8 reserved_at_20[0xc]; 11010 u8 active_port[0x4]; 11011 u8 reserved_at_30[0x4]; 11012 u8 tx_remap_affinity_2[0x4]; 11013 u8 reserved_at_38[0x4]; 11014 u8 tx_remap_affinity_1[0x4]; 11015 }; 11016 11017 struct mlx5_ifc_create_lag_out_bits { 11018 u8 status[0x8]; 11019 u8 reserved_at_8[0x18]; 11020 11021 u8 syndrome[0x20]; 11022 11023 u8 reserved_at_40[0x40]; 11024 }; 11025 11026 struct mlx5_ifc_create_lag_in_bits { 11027 u8 opcode[0x10]; 11028 u8 reserved_at_10[0x10]; 11029 11030 u8 reserved_at_20[0x10]; 11031 u8 op_mod[0x10]; 11032 11033 struct mlx5_ifc_lagc_bits ctx; 11034 }; 11035 11036 struct mlx5_ifc_modify_lag_out_bits { 11037 u8 status[0x8]; 11038 u8 reserved_at_8[0x18]; 11039 11040 u8 syndrome[0x20]; 11041 11042 u8 reserved_at_40[0x40]; 11043 }; 11044 11045 struct mlx5_ifc_modify_lag_in_bits { 11046 u8 opcode[0x10]; 11047 u8 reserved_at_10[0x10]; 11048 11049 u8 reserved_at_20[0x10]; 11050 u8 op_mod[0x10]; 11051 11052 u8 reserved_at_40[0x20]; 11053 u8 field_select[0x20]; 11054 11055 struct mlx5_ifc_lagc_bits ctx; 11056 }; 11057 11058 struct mlx5_ifc_query_lag_out_bits { 11059 u8 status[0x8]; 11060 u8 reserved_at_8[0x18]; 11061 11062 u8 syndrome[0x20]; 11063 11064 struct mlx5_ifc_lagc_bits ctx; 11065 }; 11066 11067 struct mlx5_ifc_query_lag_in_bits { 11068 u8 opcode[0x10]; 11069 u8 reserved_at_10[0x10]; 11070 11071 u8 reserved_at_20[0x10]; 11072 u8 op_mod[0x10]; 11073 11074 u8 reserved_at_40[0x40]; 11075 }; 11076 11077 struct mlx5_ifc_destroy_lag_out_bits { 11078 u8 status[0x8]; 11079 u8 reserved_at_8[0x18]; 11080 11081 u8 syndrome[0x20]; 11082 11083 u8 reserved_at_40[0x40]; 11084 }; 11085 11086 struct mlx5_ifc_destroy_lag_in_bits { 11087 u8 opcode[0x10]; 11088 u8 reserved_at_10[0x10]; 11089 11090 u8 reserved_at_20[0x10]; 11091 u8 op_mod[0x10]; 11092 11093 u8 reserved_at_40[0x40]; 11094 }; 11095 11096 struct mlx5_ifc_create_vport_lag_out_bits { 11097 u8 status[0x8]; 11098 u8 reserved_at_8[0x18]; 11099 11100 u8 syndrome[0x20]; 11101 11102 u8 reserved_at_40[0x40]; 11103 }; 11104 11105 struct mlx5_ifc_create_vport_lag_in_bits { 11106 u8 opcode[0x10]; 11107 u8 reserved_at_10[0x10]; 11108 11109 u8 reserved_at_20[0x10]; 11110 u8 op_mod[0x10]; 11111 11112 u8 reserved_at_40[0x40]; 11113 }; 11114 11115 struct mlx5_ifc_destroy_vport_lag_out_bits { 11116 u8 status[0x8]; 11117 u8 reserved_at_8[0x18]; 11118 11119 u8 syndrome[0x20]; 11120 11121 u8 reserved_at_40[0x40]; 11122 }; 11123 11124 struct mlx5_ifc_destroy_vport_lag_in_bits { 11125 u8 opcode[0x10]; 11126 u8 reserved_at_10[0x10]; 11127 11128 u8 reserved_at_20[0x10]; 11129 u8 op_mod[0x10]; 11130 11131 u8 reserved_at_40[0x40]; 11132 }; 11133 11134 enum { 11135 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11136 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11137 }; 11138 11139 struct mlx5_ifc_modify_memic_in_bits { 11140 u8 opcode[0x10]; 11141 u8 uid[0x10]; 11142 11143 u8 reserved_at_20[0x10]; 11144 u8 op_mod[0x10]; 11145 11146 u8 reserved_at_40[0x20]; 11147 11148 u8 reserved_at_60[0x18]; 11149 u8 memic_operation_type[0x8]; 11150 11151 u8 memic_start_addr[0x40]; 11152 11153 u8 reserved_at_c0[0x140]; 11154 }; 11155 11156 struct mlx5_ifc_modify_memic_out_bits { 11157 u8 status[0x8]; 11158 u8 reserved_at_8[0x18]; 11159 11160 u8 syndrome[0x20]; 11161 11162 u8 reserved_at_40[0x40]; 11163 11164 u8 memic_operation_addr[0x40]; 11165 11166 u8 reserved_at_c0[0x140]; 11167 }; 11168 11169 struct mlx5_ifc_alloc_memic_in_bits { 11170 u8 opcode[0x10]; 11171 u8 reserved_at_10[0x10]; 11172 11173 u8 reserved_at_20[0x10]; 11174 u8 op_mod[0x10]; 11175 11176 u8 reserved_at_30[0x20]; 11177 11178 u8 reserved_at_40[0x18]; 11179 u8 log_memic_addr_alignment[0x8]; 11180 11181 u8 range_start_addr[0x40]; 11182 11183 u8 range_size[0x20]; 11184 11185 u8 memic_size[0x20]; 11186 }; 11187 11188 struct mlx5_ifc_alloc_memic_out_bits { 11189 u8 status[0x8]; 11190 u8 reserved_at_8[0x18]; 11191 11192 u8 syndrome[0x20]; 11193 11194 u8 memic_start_addr[0x40]; 11195 }; 11196 11197 struct mlx5_ifc_dealloc_memic_in_bits { 11198 u8 opcode[0x10]; 11199 u8 reserved_at_10[0x10]; 11200 11201 u8 reserved_at_20[0x10]; 11202 u8 op_mod[0x10]; 11203 11204 u8 reserved_at_40[0x40]; 11205 11206 u8 memic_start_addr[0x40]; 11207 11208 u8 memic_size[0x20]; 11209 11210 u8 reserved_at_e0[0x20]; 11211 }; 11212 11213 struct mlx5_ifc_dealloc_memic_out_bits { 11214 u8 status[0x8]; 11215 u8 reserved_at_8[0x18]; 11216 11217 u8 syndrome[0x20]; 11218 11219 u8 reserved_at_40[0x40]; 11220 }; 11221 11222 struct mlx5_ifc_umem_bits { 11223 u8 reserved_at_0[0x80]; 11224 11225 u8 ats[0x1]; 11226 u8 reserved_at_81[0x1a]; 11227 u8 log_page_size[0x5]; 11228 11229 u8 page_offset[0x20]; 11230 11231 u8 num_of_mtt[0x40]; 11232 11233 struct mlx5_ifc_mtt_bits mtt[]; 11234 }; 11235 11236 struct mlx5_ifc_uctx_bits { 11237 u8 cap[0x20]; 11238 11239 u8 reserved_at_20[0x160]; 11240 }; 11241 11242 struct mlx5_ifc_sw_icm_bits { 11243 u8 modify_field_select[0x40]; 11244 11245 u8 reserved_at_40[0x18]; 11246 u8 log_sw_icm_size[0x8]; 11247 11248 u8 reserved_at_60[0x20]; 11249 11250 u8 sw_icm_start_addr[0x40]; 11251 11252 u8 reserved_at_c0[0x140]; 11253 }; 11254 11255 struct mlx5_ifc_geneve_tlv_option_bits { 11256 u8 modify_field_select[0x40]; 11257 11258 u8 reserved_at_40[0x18]; 11259 u8 geneve_option_fte_index[0x8]; 11260 11261 u8 option_class[0x10]; 11262 u8 option_type[0x8]; 11263 u8 reserved_at_78[0x3]; 11264 u8 option_data_length[0x5]; 11265 11266 u8 reserved_at_80[0x180]; 11267 }; 11268 11269 struct mlx5_ifc_create_umem_in_bits { 11270 u8 opcode[0x10]; 11271 u8 uid[0x10]; 11272 11273 u8 reserved_at_20[0x10]; 11274 u8 op_mod[0x10]; 11275 11276 u8 reserved_at_40[0x40]; 11277 11278 struct mlx5_ifc_umem_bits umem; 11279 }; 11280 11281 struct mlx5_ifc_create_umem_out_bits { 11282 u8 status[0x8]; 11283 u8 reserved_at_8[0x18]; 11284 11285 u8 syndrome[0x20]; 11286 11287 u8 reserved_at_40[0x8]; 11288 u8 umem_id[0x18]; 11289 11290 u8 reserved_at_60[0x20]; 11291 }; 11292 11293 struct mlx5_ifc_destroy_umem_in_bits { 11294 u8 opcode[0x10]; 11295 u8 uid[0x10]; 11296 11297 u8 reserved_at_20[0x10]; 11298 u8 op_mod[0x10]; 11299 11300 u8 reserved_at_40[0x8]; 11301 u8 umem_id[0x18]; 11302 11303 u8 reserved_at_60[0x20]; 11304 }; 11305 11306 struct mlx5_ifc_destroy_umem_out_bits { 11307 u8 status[0x8]; 11308 u8 reserved_at_8[0x18]; 11309 11310 u8 syndrome[0x20]; 11311 11312 u8 reserved_at_40[0x40]; 11313 }; 11314 11315 struct mlx5_ifc_create_uctx_in_bits { 11316 u8 opcode[0x10]; 11317 u8 reserved_at_10[0x10]; 11318 11319 u8 reserved_at_20[0x10]; 11320 u8 op_mod[0x10]; 11321 11322 u8 reserved_at_40[0x40]; 11323 11324 struct mlx5_ifc_uctx_bits uctx; 11325 }; 11326 11327 struct mlx5_ifc_create_uctx_out_bits { 11328 u8 status[0x8]; 11329 u8 reserved_at_8[0x18]; 11330 11331 u8 syndrome[0x20]; 11332 11333 u8 reserved_at_40[0x10]; 11334 u8 uid[0x10]; 11335 11336 u8 reserved_at_60[0x20]; 11337 }; 11338 11339 struct mlx5_ifc_destroy_uctx_in_bits { 11340 u8 opcode[0x10]; 11341 u8 reserved_at_10[0x10]; 11342 11343 u8 reserved_at_20[0x10]; 11344 u8 op_mod[0x10]; 11345 11346 u8 reserved_at_40[0x10]; 11347 u8 uid[0x10]; 11348 11349 u8 reserved_at_60[0x20]; 11350 }; 11351 11352 struct mlx5_ifc_destroy_uctx_out_bits { 11353 u8 status[0x8]; 11354 u8 reserved_at_8[0x18]; 11355 11356 u8 syndrome[0x20]; 11357 11358 u8 reserved_at_40[0x40]; 11359 }; 11360 11361 struct mlx5_ifc_create_sw_icm_in_bits { 11362 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11363 struct mlx5_ifc_sw_icm_bits sw_icm; 11364 }; 11365 11366 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11367 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11368 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11369 }; 11370 11371 struct mlx5_ifc_mtrc_string_db_param_bits { 11372 u8 string_db_base_address[0x20]; 11373 11374 u8 reserved_at_20[0x8]; 11375 u8 string_db_size[0x18]; 11376 }; 11377 11378 struct mlx5_ifc_mtrc_cap_bits { 11379 u8 trace_owner[0x1]; 11380 u8 trace_to_memory[0x1]; 11381 u8 reserved_at_2[0x4]; 11382 u8 trc_ver[0x2]; 11383 u8 reserved_at_8[0x14]; 11384 u8 num_string_db[0x4]; 11385 11386 u8 first_string_trace[0x8]; 11387 u8 num_string_trace[0x8]; 11388 u8 reserved_at_30[0x28]; 11389 11390 u8 log_max_trace_buffer_size[0x8]; 11391 11392 u8 reserved_at_60[0x20]; 11393 11394 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11395 11396 u8 reserved_at_280[0x180]; 11397 }; 11398 11399 struct mlx5_ifc_mtrc_conf_bits { 11400 u8 reserved_at_0[0x1c]; 11401 u8 trace_mode[0x4]; 11402 u8 reserved_at_20[0x18]; 11403 u8 log_trace_buffer_size[0x8]; 11404 u8 trace_mkey[0x20]; 11405 u8 reserved_at_60[0x3a0]; 11406 }; 11407 11408 struct mlx5_ifc_mtrc_stdb_bits { 11409 u8 string_db_index[0x4]; 11410 u8 reserved_at_4[0x4]; 11411 u8 read_size[0x18]; 11412 u8 start_offset[0x20]; 11413 u8 string_db_data[]; 11414 }; 11415 11416 struct mlx5_ifc_mtrc_ctrl_bits { 11417 u8 trace_status[0x2]; 11418 u8 reserved_at_2[0x2]; 11419 u8 arm_event[0x1]; 11420 u8 reserved_at_5[0xb]; 11421 u8 modify_field_select[0x10]; 11422 u8 reserved_at_20[0x2b]; 11423 u8 current_timestamp52_32[0x15]; 11424 u8 current_timestamp31_0[0x20]; 11425 u8 reserved_at_80[0x180]; 11426 }; 11427 11428 struct mlx5_ifc_host_params_context_bits { 11429 u8 host_number[0x8]; 11430 u8 reserved_at_8[0x7]; 11431 u8 host_pf_disabled[0x1]; 11432 u8 host_num_of_vfs[0x10]; 11433 11434 u8 host_total_vfs[0x10]; 11435 u8 host_pci_bus[0x10]; 11436 11437 u8 reserved_at_40[0x10]; 11438 u8 host_pci_device[0x10]; 11439 11440 u8 reserved_at_60[0x10]; 11441 u8 host_pci_function[0x10]; 11442 11443 u8 reserved_at_80[0x180]; 11444 }; 11445 11446 struct mlx5_ifc_query_esw_functions_in_bits { 11447 u8 opcode[0x10]; 11448 u8 reserved_at_10[0x10]; 11449 11450 u8 reserved_at_20[0x10]; 11451 u8 op_mod[0x10]; 11452 11453 u8 reserved_at_40[0x40]; 11454 }; 11455 11456 struct mlx5_ifc_query_esw_functions_out_bits { 11457 u8 status[0x8]; 11458 u8 reserved_at_8[0x18]; 11459 11460 u8 syndrome[0x20]; 11461 11462 u8 reserved_at_40[0x40]; 11463 11464 struct mlx5_ifc_host_params_context_bits host_params_context; 11465 11466 u8 reserved_at_280[0x180]; 11467 u8 host_sf_enable[][0x40]; 11468 }; 11469 11470 struct mlx5_ifc_sf_partition_bits { 11471 u8 reserved_at_0[0x10]; 11472 u8 log_num_sf[0x8]; 11473 u8 log_sf_bar_size[0x8]; 11474 }; 11475 11476 struct mlx5_ifc_query_sf_partitions_out_bits { 11477 u8 status[0x8]; 11478 u8 reserved_at_8[0x18]; 11479 11480 u8 syndrome[0x20]; 11481 11482 u8 reserved_at_40[0x18]; 11483 u8 num_sf_partitions[0x8]; 11484 11485 u8 reserved_at_60[0x20]; 11486 11487 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11488 }; 11489 11490 struct mlx5_ifc_query_sf_partitions_in_bits { 11491 u8 opcode[0x10]; 11492 u8 reserved_at_10[0x10]; 11493 11494 u8 reserved_at_20[0x10]; 11495 u8 op_mod[0x10]; 11496 11497 u8 reserved_at_40[0x40]; 11498 }; 11499 11500 struct mlx5_ifc_dealloc_sf_out_bits { 11501 u8 status[0x8]; 11502 u8 reserved_at_8[0x18]; 11503 11504 u8 syndrome[0x20]; 11505 11506 u8 reserved_at_40[0x40]; 11507 }; 11508 11509 struct mlx5_ifc_dealloc_sf_in_bits { 11510 u8 opcode[0x10]; 11511 u8 reserved_at_10[0x10]; 11512 11513 u8 reserved_at_20[0x10]; 11514 u8 op_mod[0x10]; 11515 11516 u8 reserved_at_40[0x10]; 11517 u8 function_id[0x10]; 11518 11519 u8 reserved_at_60[0x20]; 11520 }; 11521 11522 struct mlx5_ifc_alloc_sf_out_bits { 11523 u8 status[0x8]; 11524 u8 reserved_at_8[0x18]; 11525 11526 u8 syndrome[0x20]; 11527 11528 u8 reserved_at_40[0x40]; 11529 }; 11530 11531 struct mlx5_ifc_alloc_sf_in_bits { 11532 u8 opcode[0x10]; 11533 u8 reserved_at_10[0x10]; 11534 11535 u8 reserved_at_20[0x10]; 11536 u8 op_mod[0x10]; 11537 11538 u8 reserved_at_40[0x10]; 11539 u8 function_id[0x10]; 11540 11541 u8 reserved_at_60[0x20]; 11542 }; 11543 11544 struct mlx5_ifc_affiliated_event_header_bits { 11545 u8 reserved_at_0[0x10]; 11546 u8 obj_type[0x10]; 11547 11548 u8 obj_id[0x20]; 11549 }; 11550 11551 enum { 11552 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11553 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11554 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11555 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11556 }; 11557 11558 enum { 11559 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11560 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11561 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11562 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11563 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11564 }; 11565 11566 enum { 11567 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11568 }; 11569 11570 struct mlx5_ifc_ipsec_obj_bits { 11571 u8 modify_field_select[0x40]; 11572 u8 full_offload[0x1]; 11573 u8 reserved_at_41[0x1]; 11574 u8 esn_en[0x1]; 11575 u8 esn_overlap[0x1]; 11576 u8 reserved_at_44[0x2]; 11577 u8 icv_length[0x2]; 11578 u8 reserved_at_48[0x4]; 11579 u8 aso_return_reg[0x4]; 11580 u8 reserved_at_50[0x10]; 11581 11582 u8 esn_msb[0x20]; 11583 11584 u8 reserved_at_80[0x8]; 11585 u8 dekn[0x18]; 11586 11587 u8 salt[0x20]; 11588 11589 u8 implicit_iv[0x40]; 11590 11591 u8 reserved_at_100[0x700]; 11592 }; 11593 11594 struct mlx5_ifc_create_ipsec_obj_in_bits { 11595 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11596 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11597 }; 11598 11599 enum { 11600 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11601 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11602 }; 11603 11604 struct mlx5_ifc_query_ipsec_obj_out_bits { 11605 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11606 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11607 }; 11608 11609 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11610 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11611 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11612 }; 11613 11614 enum { 11615 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11616 }; 11617 11618 enum { 11619 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11620 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11621 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11622 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11623 }; 11624 11625 #define MLX5_MACSEC_ASO_INC_SN 0x2 11626 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11627 11628 struct mlx5_ifc_macsec_aso_bits { 11629 u8 valid[0x1]; 11630 u8 reserved_at_1[0x1]; 11631 u8 mode[0x2]; 11632 u8 window_size[0x2]; 11633 u8 soft_lifetime_arm[0x1]; 11634 u8 hard_lifetime_arm[0x1]; 11635 u8 remove_flow_enable[0x1]; 11636 u8 epn_event_arm[0x1]; 11637 u8 reserved_at_a[0x16]; 11638 11639 u8 remove_flow_packet_count[0x20]; 11640 11641 u8 remove_flow_soft_lifetime[0x20]; 11642 11643 u8 reserved_at_60[0x80]; 11644 11645 u8 mode_parameter[0x20]; 11646 11647 u8 replay_protection_window[8][0x20]; 11648 }; 11649 11650 struct mlx5_ifc_macsec_offload_obj_bits { 11651 u8 modify_field_select[0x40]; 11652 11653 u8 confidentiality_en[0x1]; 11654 u8 reserved_at_41[0x1]; 11655 u8 epn_en[0x1]; 11656 u8 epn_overlap[0x1]; 11657 u8 reserved_at_44[0x2]; 11658 u8 confidentiality_offset[0x2]; 11659 u8 reserved_at_48[0x4]; 11660 u8 aso_return_reg[0x4]; 11661 u8 reserved_at_50[0x10]; 11662 11663 u8 epn_msb[0x20]; 11664 11665 u8 reserved_at_80[0x8]; 11666 u8 dekn[0x18]; 11667 11668 u8 reserved_at_a0[0x20]; 11669 11670 u8 sci[0x40]; 11671 11672 u8 reserved_at_100[0x8]; 11673 u8 macsec_aso_access_pd[0x18]; 11674 11675 u8 reserved_at_120[0x60]; 11676 11677 u8 salt[3][0x20]; 11678 11679 u8 reserved_at_1e0[0x20]; 11680 11681 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11682 }; 11683 11684 struct mlx5_ifc_create_macsec_obj_in_bits { 11685 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11686 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11687 }; 11688 11689 struct mlx5_ifc_modify_macsec_obj_in_bits { 11690 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11691 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11692 }; 11693 11694 enum { 11695 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11696 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11697 }; 11698 11699 struct mlx5_ifc_query_macsec_obj_out_bits { 11700 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11701 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11702 }; 11703 11704 struct mlx5_ifc_encryption_key_obj_bits { 11705 u8 modify_field_select[0x40]; 11706 11707 u8 reserved_at_40[0x14]; 11708 u8 key_size[0x4]; 11709 u8 reserved_at_58[0x4]; 11710 u8 key_type[0x4]; 11711 11712 u8 reserved_at_60[0x8]; 11713 u8 pd[0x18]; 11714 11715 u8 reserved_at_80[0x180]; 11716 u8 key[8][0x20]; 11717 11718 u8 reserved_at_300[0x500]; 11719 }; 11720 11721 struct mlx5_ifc_create_encryption_key_in_bits { 11722 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11723 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11724 }; 11725 11726 enum { 11727 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11728 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11729 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11730 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11731 }; 11732 11733 struct mlx5_ifc_flow_meter_parameters_bits { 11734 u8 valid[0x1]; 11735 u8 bucket_overflow[0x1]; 11736 u8 start_color[0x2]; 11737 u8 both_buckets_on_green[0x1]; 11738 u8 reserved_at_5[0x1]; 11739 u8 meter_mode[0x2]; 11740 u8 reserved_at_8[0x18]; 11741 11742 u8 reserved_at_20[0x20]; 11743 11744 u8 reserved_at_40[0x3]; 11745 u8 cbs_exponent[0x5]; 11746 u8 cbs_mantissa[0x8]; 11747 u8 reserved_at_50[0x3]; 11748 u8 cir_exponent[0x5]; 11749 u8 cir_mantissa[0x8]; 11750 11751 u8 reserved_at_60[0x20]; 11752 11753 u8 reserved_at_80[0x3]; 11754 u8 ebs_exponent[0x5]; 11755 u8 ebs_mantissa[0x8]; 11756 u8 reserved_at_90[0x3]; 11757 u8 eir_exponent[0x5]; 11758 u8 eir_mantissa[0x8]; 11759 11760 u8 reserved_at_a0[0x60]; 11761 }; 11762 11763 struct mlx5_ifc_flow_meter_aso_obj_bits { 11764 u8 modify_field_select[0x40]; 11765 11766 u8 reserved_at_40[0x40]; 11767 11768 u8 reserved_at_80[0x8]; 11769 u8 meter_aso_access_pd[0x18]; 11770 11771 u8 reserved_at_a0[0x160]; 11772 11773 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11774 }; 11775 11776 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11777 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11778 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11779 }; 11780 11781 struct mlx5_ifc_sampler_obj_bits { 11782 u8 modify_field_select[0x40]; 11783 11784 u8 table_type[0x8]; 11785 u8 level[0x8]; 11786 u8 reserved_at_50[0xf]; 11787 u8 ignore_flow_level[0x1]; 11788 11789 u8 sample_ratio[0x20]; 11790 11791 u8 reserved_at_80[0x8]; 11792 u8 sample_table_id[0x18]; 11793 11794 u8 reserved_at_a0[0x8]; 11795 u8 default_table_id[0x18]; 11796 11797 u8 sw_steering_icm_address_rx[0x40]; 11798 u8 sw_steering_icm_address_tx[0x40]; 11799 11800 u8 reserved_at_140[0xa0]; 11801 }; 11802 11803 struct mlx5_ifc_create_sampler_obj_in_bits { 11804 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11805 struct mlx5_ifc_sampler_obj_bits sampler_object; 11806 }; 11807 11808 struct mlx5_ifc_query_sampler_obj_out_bits { 11809 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11810 struct mlx5_ifc_sampler_obj_bits sampler_object; 11811 }; 11812 11813 enum { 11814 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11815 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11816 }; 11817 11818 enum { 11819 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11820 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11821 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11822 }; 11823 11824 struct mlx5_ifc_tls_static_params_bits { 11825 u8 const_2[0x2]; 11826 u8 tls_version[0x4]; 11827 u8 const_1[0x2]; 11828 u8 reserved_at_8[0x14]; 11829 u8 encryption_standard[0x4]; 11830 11831 u8 reserved_at_20[0x20]; 11832 11833 u8 initial_record_number[0x40]; 11834 11835 u8 resync_tcp_sn[0x20]; 11836 11837 u8 gcm_iv[0x20]; 11838 11839 u8 implicit_iv[0x40]; 11840 11841 u8 reserved_at_100[0x8]; 11842 u8 dek_index[0x18]; 11843 11844 u8 reserved_at_120[0xe0]; 11845 }; 11846 11847 struct mlx5_ifc_tls_progress_params_bits { 11848 u8 next_record_tcp_sn[0x20]; 11849 11850 u8 hw_resync_tcp_sn[0x20]; 11851 11852 u8 record_tracker_state[0x2]; 11853 u8 auth_state[0x2]; 11854 u8 reserved_at_44[0x4]; 11855 u8 hw_offset_record_number[0x18]; 11856 }; 11857 11858 enum { 11859 MLX5_MTT_PERM_READ = 1 << 0, 11860 MLX5_MTT_PERM_WRITE = 1 << 1, 11861 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11862 }; 11863 11864 enum { 11865 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11866 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11867 }; 11868 11869 struct mlx5_ifc_suspend_vhca_in_bits { 11870 u8 opcode[0x10]; 11871 u8 uid[0x10]; 11872 11873 u8 reserved_at_20[0x10]; 11874 u8 op_mod[0x10]; 11875 11876 u8 reserved_at_40[0x10]; 11877 u8 vhca_id[0x10]; 11878 11879 u8 reserved_at_60[0x20]; 11880 }; 11881 11882 struct mlx5_ifc_suspend_vhca_out_bits { 11883 u8 status[0x8]; 11884 u8 reserved_at_8[0x18]; 11885 11886 u8 syndrome[0x20]; 11887 11888 u8 reserved_at_40[0x40]; 11889 }; 11890 11891 enum { 11892 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11893 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11894 }; 11895 11896 struct mlx5_ifc_resume_vhca_in_bits { 11897 u8 opcode[0x10]; 11898 u8 uid[0x10]; 11899 11900 u8 reserved_at_20[0x10]; 11901 u8 op_mod[0x10]; 11902 11903 u8 reserved_at_40[0x10]; 11904 u8 vhca_id[0x10]; 11905 11906 u8 reserved_at_60[0x20]; 11907 }; 11908 11909 struct mlx5_ifc_resume_vhca_out_bits { 11910 u8 status[0x8]; 11911 u8 reserved_at_8[0x18]; 11912 11913 u8 syndrome[0x20]; 11914 11915 u8 reserved_at_40[0x40]; 11916 }; 11917 11918 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11919 u8 opcode[0x10]; 11920 u8 uid[0x10]; 11921 11922 u8 reserved_at_20[0x10]; 11923 u8 op_mod[0x10]; 11924 11925 u8 reserved_at_40[0x10]; 11926 u8 vhca_id[0x10]; 11927 11928 u8 reserved_at_60[0x20]; 11929 }; 11930 11931 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11932 u8 status[0x8]; 11933 u8 reserved_at_8[0x18]; 11934 11935 u8 syndrome[0x20]; 11936 11937 u8 reserved_at_40[0x40]; 11938 11939 u8 required_umem_size[0x20]; 11940 11941 u8 reserved_at_a0[0x160]; 11942 }; 11943 11944 struct mlx5_ifc_save_vhca_state_in_bits { 11945 u8 opcode[0x10]; 11946 u8 uid[0x10]; 11947 11948 u8 reserved_at_20[0x10]; 11949 u8 op_mod[0x10]; 11950 11951 u8 reserved_at_40[0x10]; 11952 u8 vhca_id[0x10]; 11953 11954 u8 reserved_at_60[0x20]; 11955 11956 u8 va[0x40]; 11957 11958 u8 mkey[0x20]; 11959 11960 u8 size[0x20]; 11961 }; 11962 11963 struct mlx5_ifc_save_vhca_state_out_bits { 11964 u8 status[0x8]; 11965 u8 reserved_at_8[0x18]; 11966 11967 u8 syndrome[0x20]; 11968 11969 u8 actual_image_size[0x20]; 11970 11971 u8 reserved_at_60[0x20]; 11972 }; 11973 11974 struct mlx5_ifc_load_vhca_state_in_bits { 11975 u8 opcode[0x10]; 11976 u8 uid[0x10]; 11977 11978 u8 reserved_at_20[0x10]; 11979 u8 op_mod[0x10]; 11980 11981 u8 reserved_at_40[0x10]; 11982 u8 vhca_id[0x10]; 11983 11984 u8 reserved_at_60[0x20]; 11985 11986 u8 va[0x40]; 11987 11988 u8 mkey[0x20]; 11989 11990 u8 size[0x20]; 11991 }; 11992 11993 struct mlx5_ifc_load_vhca_state_out_bits { 11994 u8 status[0x8]; 11995 u8 reserved_at_8[0x18]; 11996 11997 u8 syndrome[0x20]; 11998 11999 u8 reserved_at_40[0x40]; 12000 }; 12001 12002 struct mlx5_ifc_adv_virtualization_cap_bits { 12003 u8 reserved_at_0[0x3]; 12004 u8 pg_track_log_max_num[0x5]; 12005 u8 pg_track_max_num_range[0x8]; 12006 u8 pg_track_log_min_addr_space[0x8]; 12007 u8 pg_track_log_max_addr_space[0x8]; 12008 12009 u8 reserved_at_20[0x3]; 12010 u8 pg_track_log_min_msg_size[0x5]; 12011 u8 reserved_at_28[0x3]; 12012 u8 pg_track_log_max_msg_size[0x5]; 12013 u8 reserved_at_30[0x3]; 12014 u8 pg_track_log_min_page_size[0x5]; 12015 u8 reserved_at_38[0x3]; 12016 u8 pg_track_log_max_page_size[0x5]; 12017 12018 u8 reserved_at_40[0x7c0]; 12019 }; 12020 12021 struct mlx5_ifc_page_track_report_entry_bits { 12022 u8 dirty_address_high[0x20]; 12023 12024 u8 dirty_address_low[0x20]; 12025 }; 12026 12027 enum { 12028 MLX5_PAGE_TRACK_STATE_TRACKING, 12029 MLX5_PAGE_TRACK_STATE_REPORTING, 12030 MLX5_PAGE_TRACK_STATE_ERROR, 12031 }; 12032 12033 struct mlx5_ifc_page_track_range_bits { 12034 u8 start_address[0x40]; 12035 12036 u8 length[0x40]; 12037 }; 12038 12039 struct mlx5_ifc_page_track_bits { 12040 u8 modify_field_select[0x40]; 12041 12042 u8 reserved_at_40[0x10]; 12043 u8 vhca_id[0x10]; 12044 12045 u8 reserved_at_60[0x20]; 12046 12047 u8 state[0x4]; 12048 u8 track_type[0x4]; 12049 u8 log_addr_space_size[0x8]; 12050 u8 reserved_at_90[0x3]; 12051 u8 log_page_size[0x5]; 12052 u8 reserved_at_98[0x3]; 12053 u8 log_msg_size[0x5]; 12054 12055 u8 reserved_at_a0[0x8]; 12056 u8 reporting_qpn[0x18]; 12057 12058 u8 reserved_at_c0[0x18]; 12059 u8 num_ranges[0x8]; 12060 12061 u8 reserved_at_e0[0x20]; 12062 12063 u8 range_start_address[0x40]; 12064 12065 u8 length[0x40]; 12066 12067 struct mlx5_ifc_page_track_range_bits track_range[0]; 12068 }; 12069 12070 struct mlx5_ifc_create_page_track_obj_in_bits { 12071 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12072 struct mlx5_ifc_page_track_bits obj_context; 12073 }; 12074 12075 struct mlx5_ifc_modify_page_track_obj_in_bits { 12076 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12077 struct mlx5_ifc_page_track_bits obj_context; 12078 }; 12079 12080 #endif /* MLX5_IFC_H */ 12081