1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
41
42 #include "amdgpu_ras.h"
43 #include "amdgpu_securedisplay.h"
44 #include "amdgpu_atomfirmware.h"
45
46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
47
48 static int psp_sysfs_init(struct amdgpu_device *adev);
49 static void psp_sysfs_fini(struct amdgpu_device *adev);
50
51 static int psp_load_smu_fw(struct psp_context *psp);
52 static int psp_rap_terminate(struct psp_context *psp);
53 static int psp_securedisplay_terminate(struct psp_context *psp);
54
55 /*
56 * Due to DF Cstate management centralized to PMFW, the firmware
57 * loading sequence will be updated as below:
58 * - Load KDB
59 * - Load SYS_DRV
60 * - Load tOS
61 * - Load PMFW
62 * - Setup TMR
63 * - Load other non-psp fw
64 * - Load ASD
65 * - Load XGMI/RAS/HDCP/DTM TA if any
66 *
67 * This new sequence is required for
68 * - Arcturus and onwards
69 */
psp_check_pmfw_centralized_cstate_management(struct psp_context * psp)70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
71 {
72 struct amdgpu_device *adev = psp->adev;
73
74 if (amdgpu_sriov_vf(adev)) {
75 psp->pmfw_centralized_cstate_management = false;
76 return;
77 }
78
79 switch (adev->ip_versions[MP0_HWIP][0]) {
80 case IP_VERSION(11, 0, 0):
81 case IP_VERSION(11, 0, 4):
82 case IP_VERSION(11, 0, 5):
83 case IP_VERSION(11, 0, 7):
84 case IP_VERSION(11, 0, 9):
85 case IP_VERSION(11, 0, 11):
86 case IP_VERSION(11, 0, 12):
87 case IP_VERSION(11, 0, 13):
88 case IP_VERSION(13, 0, 0):
89 case IP_VERSION(13, 0, 2):
90 case IP_VERSION(13, 0, 7):
91 psp->pmfw_centralized_cstate_management = true;
92 break;
93 default:
94 psp->pmfw_centralized_cstate_management = false;
95 break;
96 }
97 }
98
psp_early_init(void * handle)99 static int psp_early_init(void *handle)
100 {
101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
102 struct psp_context *psp = &adev->psp;
103
104 switch (adev->ip_versions[MP0_HWIP][0]) {
105 case IP_VERSION(9, 0, 0):
106 psp_v3_1_set_psp_funcs(psp);
107 psp->autoload_supported = false;
108 break;
109 case IP_VERSION(10, 0, 0):
110 case IP_VERSION(10, 0, 1):
111 psp_v10_0_set_psp_funcs(psp);
112 psp->autoload_supported = false;
113 break;
114 case IP_VERSION(11, 0, 2):
115 case IP_VERSION(11, 0, 4):
116 psp_v11_0_set_psp_funcs(psp);
117 psp->autoload_supported = false;
118 break;
119 case IP_VERSION(11, 0, 0):
120 case IP_VERSION(11, 0, 5):
121 case IP_VERSION(11, 0, 9):
122 case IP_VERSION(11, 0, 7):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 5, 0):
125 case IP_VERSION(11, 0, 12):
126 case IP_VERSION(11, 0, 13):
127 psp_v11_0_set_psp_funcs(psp);
128 psp->autoload_supported = true;
129 break;
130 case IP_VERSION(11, 0, 3):
131 case IP_VERSION(12, 0, 1):
132 psp_v12_0_set_psp_funcs(psp);
133 break;
134 case IP_VERSION(13, 0, 2):
135 psp_v13_0_set_psp_funcs(psp);
136 break;
137 case IP_VERSION(13, 0, 1):
138 case IP_VERSION(13, 0, 3):
139 case IP_VERSION(13, 0, 5):
140 case IP_VERSION(13, 0, 8):
141 case IP_VERSION(13, 0, 10):
142 case IP_VERSION(13, 0, 11):
143 psp_v13_0_set_psp_funcs(psp);
144 psp->autoload_supported = true;
145 break;
146 case IP_VERSION(11, 0, 8):
147 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
148 psp_v11_0_8_set_psp_funcs(psp);
149 psp->autoload_supported = false;
150 }
151 break;
152 case IP_VERSION(13, 0, 0):
153 case IP_VERSION(13, 0, 7):
154 psp_v13_0_set_psp_funcs(psp);
155 psp->autoload_supported = true;
156 break;
157 case IP_VERSION(13, 0, 4):
158 psp_v13_0_4_set_psp_funcs(psp);
159 psp->autoload_supported = true;
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 psp->adev = adev;
166
167 psp_check_pmfw_centralized_cstate_management(psp);
168
169 return 0;
170 }
171
psp_ta_free_shared_buf(struct ta_mem_context * mem_ctx)172 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
173 {
174 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
175 &mem_ctx->shared_buf);
176 mem_ctx->shared_bo = NULL;
177 }
178
psp_free_shared_bufs(struct psp_context * psp)179 static void psp_free_shared_bufs(struct psp_context *psp)
180 {
181 void *tmr_buf;
182 void **pptr;
183
184 /* free TMR memory buffer */
185 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
186 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
187 psp->tmr_bo = NULL;
188
189 /* free xgmi shared memory */
190 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
191
192 /* free ras shared memory */
193 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
194
195 /* free hdcp shared memory */
196 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
197
198 /* free dtm shared memory */
199 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
200
201 /* free rap shared memory */
202 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
203
204 /* free securedisplay shared memory */
205 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
206
207
208 }
209
psp_memory_training_fini(struct psp_context * psp)210 static void psp_memory_training_fini(struct psp_context *psp)
211 {
212 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
213
214 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
215 kfree(ctx->sys_cache);
216 ctx->sys_cache = NULL;
217 }
218
psp_memory_training_init(struct psp_context * psp)219 static int psp_memory_training_init(struct psp_context *psp)
220 {
221 int ret;
222 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
223
224 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
225 DRM_DEBUG("memory training is not supported!\n");
226 return 0;
227 }
228
229 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
230 if (ctx->sys_cache == NULL) {
231 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
232 ret = -ENOMEM;
233 goto Err_out;
234 }
235
236 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
237 ctx->train_data_size,
238 ctx->p2c_train_data_offset,
239 ctx->c2p_train_data_offset);
240 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
241 return 0;
242
243 Err_out:
244 psp_memory_training_fini(psp);
245 return ret;
246 }
247
248 /*
249 * Helper funciton to query psp runtime database entry
250 *
251 * @adev: amdgpu_device pointer
252 * @entry_type: the type of psp runtime database entry
253 * @db_entry: runtime database entry pointer
254 *
255 * Return false if runtime database doesn't exit or entry is invalid
256 * or true if the specific database entry is found, and copy to @db_entry
257 */
psp_get_runtime_db_entry(struct amdgpu_device * adev,enum psp_runtime_entry_type entry_type,void * db_entry)258 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
259 enum psp_runtime_entry_type entry_type,
260 void *db_entry)
261 {
262 uint64_t db_header_pos, db_dir_pos;
263 struct psp_runtime_data_header db_header = {0};
264 struct psp_runtime_data_directory db_dir = {0};
265 bool ret = false;
266 int i;
267
268 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
269 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
270
271 /* read runtime db header from vram */
272 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
273 sizeof(struct psp_runtime_data_header), false);
274
275 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
276 /* runtime db doesn't exist, exit */
277 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
278 return false;
279 }
280
281 /* read runtime database entry from vram */
282 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
283 sizeof(struct psp_runtime_data_directory), false);
284
285 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
286 /* invalid db entry count, exit */
287 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
288 return false;
289 }
290
291 /* look up for requested entry type */
292 for (i = 0; i < db_dir.entry_count && !ret; i++) {
293 if (db_dir.entry_list[i].entry_type == entry_type) {
294 switch (entry_type) {
295 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
296 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
297 /* invalid db entry size */
298 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
299 return false;
300 }
301 /* read runtime database entry */
302 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
303 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
304 ret = true;
305 break;
306 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
307 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
308 /* invalid db entry size */
309 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
310 return false;
311 }
312 /* read runtime database entry */
313 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
314 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
315 ret = true;
316 break;
317 default:
318 ret = false;
319 break;
320 }
321 }
322 }
323
324 return ret;
325 }
326
psp_init_sriov_microcode(struct psp_context * psp)327 static int psp_init_sriov_microcode(struct psp_context *psp)
328 {
329 struct amdgpu_device *adev = psp->adev;
330 int ret = 0;
331
332 switch (adev->ip_versions[MP0_HWIP][0]) {
333 case IP_VERSION(9, 0, 0):
334 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
335 ret = psp_init_cap_microcode(psp, "vega10");
336 break;
337 case IP_VERSION(11, 0, 9):
338 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
339 ret = psp_init_cap_microcode(psp, "navi12");
340 break;
341 case IP_VERSION(11, 0, 7):
342 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
343 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
344 break;
345 case IP_VERSION(13, 0, 2):
346 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
347 ret = psp_init_cap_microcode(psp, "aldebaran");
348 ret &= psp_init_ta_microcode(psp, "aldebaran");
349 break;
350 case IP_VERSION(13, 0, 0):
351 adev->virt.autoload_ucode_id = 0;
352 break;
353 case IP_VERSION(13, 0, 10):
354 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
355 break;
356 default:
357 ret = -EINVAL;
358 break;
359 }
360 return ret;
361 }
362
psp_sw_init(void * handle)363 static int psp_sw_init(void *handle)
364 {
365 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
366 struct psp_context *psp = &adev->psp;
367 int ret;
368 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
369 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
370 struct psp_runtime_scpm_entry scpm_entry;
371
372 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
373 if (!psp->cmd) {
374 DRM_ERROR("Failed to allocate memory to command buffer!\n");
375 ret = -ENOMEM;
376 }
377
378 if (amdgpu_sriov_vf(adev))
379 ret = psp_init_sriov_microcode(psp);
380 else
381 ret = psp_init_microcode(psp);
382 if (ret) {
383 DRM_ERROR("Failed to load psp firmware!\n");
384 return ret;
385 }
386
387 adev->psp.xgmi_context.supports_extended_data =
388 !adev->gmc.xgmi.connected_to_cpu &&
389 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
390
391 memset(&scpm_entry, 0, sizeof(scpm_entry));
392 if ((psp_get_runtime_db_entry(adev,
393 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
394 &scpm_entry)) &&
395 (SCPM_DISABLE != scpm_entry.scpm_status)) {
396 adev->scpm_enabled = true;
397 adev->scpm_status = scpm_entry.scpm_status;
398 } else {
399 adev->scpm_enabled = false;
400 adev->scpm_status = SCPM_DISABLE;
401 }
402
403 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
404
405 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
406 if (psp_get_runtime_db_entry(adev,
407 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
408 &boot_cfg_entry)) {
409 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
410 if ((psp->boot_cfg_bitmask) &
411 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
412 /* If psp runtime database exists, then
413 * only enable two stage memory training
414 * when TWO_STAGE_DRAM_TRAINING bit is set
415 * in runtime database */
416 mem_training_ctx->enable_mem_training = true;
417 }
418
419 } else {
420 /* If psp runtime database doesn't exist or
421 * is invalid, force enable two stage memory
422 * training */
423 mem_training_ctx->enable_mem_training = true;
424 }
425
426 if (mem_training_ctx->enable_mem_training) {
427 ret = psp_memory_training_init(psp);
428 if (ret) {
429 DRM_ERROR("Failed to initialize memory training!\n");
430 return ret;
431 }
432
433 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
434 if (ret) {
435 DRM_ERROR("Failed to process memory training!\n");
436 return ret;
437 }
438 }
439
440 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
441 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
442 ret= psp_sysfs_init(adev);
443 if (ret) {
444 return ret;
445 }
446 }
447
448 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
449 amdgpu_sriov_vf(adev) ?
450 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
451 &psp->fw_pri_bo,
452 &psp->fw_pri_mc_addr,
453 &psp->fw_pri_buf);
454 if (ret)
455 return ret;
456
457 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
458 AMDGPU_GEM_DOMAIN_VRAM,
459 &psp->fence_buf_bo,
460 &psp->fence_buf_mc_addr,
461 &psp->fence_buf);
462 if (ret)
463 goto failed1;
464
465 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
466 AMDGPU_GEM_DOMAIN_VRAM,
467 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
468 (void **)&psp->cmd_buf_mem);
469 if (ret)
470 goto failed2;
471
472 return 0;
473
474 failed2:
475 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
476 &psp->fence_buf_mc_addr, &psp->fence_buf);
477 failed1:
478 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
479 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
480 return ret;
481 }
482
psp_sw_fini(void * handle)483 static int psp_sw_fini(void *handle)
484 {
485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
486 struct psp_context *psp = &adev->psp;
487 struct psp_gfx_cmd_resp *cmd = psp->cmd;
488
489 psp_memory_training_fini(psp);
490 if (psp->sos_fw) {
491 release_firmware(psp->sos_fw);
492 psp->sos_fw = NULL;
493 }
494 if (psp->asd_fw) {
495 release_firmware(psp->asd_fw);
496 psp->asd_fw = NULL;
497 }
498 if (psp->ta_fw) {
499 release_firmware(psp->ta_fw);
500 psp->ta_fw = NULL;
501 }
502 if (psp->cap_fw) {
503 release_firmware(psp->cap_fw);
504 psp->cap_fw = NULL;
505 }
506 if (psp->toc_fw) {
507 release_firmware(psp->toc_fw);
508 psp->toc_fw = NULL;
509 }
510 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
511 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
512 psp_sysfs_fini(adev);
513
514 kfree(cmd);
515 cmd = NULL;
516
517 psp_free_shared_bufs(psp);
518
519 if (psp->km_ring.ring_mem)
520 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
521 &psp->km_ring.ring_mem_mc_addr,
522 (void **)&psp->km_ring.ring_mem);
523
524 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
525 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
526 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
527 &psp->fence_buf_mc_addr, &psp->fence_buf);
528 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
529 (void **)&psp->cmd_buf_mem);
530
531 return 0;
532 }
533
psp_wait_for(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,bool check_changed)534 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
535 uint32_t reg_val, uint32_t mask, bool check_changed)
536 {
537 uint32_t val;
538 int i;
539 struct amdgpu_device *adev = psp->adev;
540
541 if (psp->adev->no_hw_access)
542 return 0;
543
544 for (i = 0; i < adev->usec_timeout; i++) {
545 val = RREG32(reg_index);
546 if (check_changed) {
547 if (val != reg_val)
548 return 0;
549 } else {
550 if ((val & mask) == reg_val)
551 return 0;
552 }
553 udelay(1);
554 }
555
556 return -ETIME;
557 }
558
psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)559 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
560 {
561 switch (cmd_id) {
562 case GFX_CMD_ID_LOAD_TA:
563 return "LOAD_TA";
564 case GFX_CMD_ID_UNLOAD_TA:
565 return "UNLOAD_TA";
566 case GFX_CMD_ID_INVOKE_CMD:
567 return "INVOKE_CMD";
568 case GFX_CMD_ID_LOAD_ASD:
569 return "LOAD_ASD";
570 case GFX_CMD_ID_SETUP_TMR:
571 return "SETUP_TMR";
572 case GFX_CMD_ID_LOAD_IP_FW:
573 return "LOAD_IP_FW";
574 case GFX_CMD_ID_DESTROY_TMR:
575 return "DESTROY_TMR";
576 case GFX_CMD_ID_SAVE_RESTORE:
577 return "SAVE_RESTORE_IP_FW";
578 case GFX_CMD_ID_SETUP_VMR:
579 return "SETUP_VMR";
580 case GFX_CMD_ID_DESTROY_VMR:
581 return "DESTROY_VMR";
582 case GFX_CMD_ID_PROG_REG:
583 return "PROG_REG";
584 case GFX_CMD_ID_GET_FW_ATTESTATION:
585 return "GET_FW_ATTESTATION";
586 case GFX_CMD_ID_LOAD_TOC:
587 return "ID_LOAD_TOC";
588 case GFX_CMD_ID_AUTOLOAD_RLC:
589 return "AUTOLOAD_RLC";
590 case GFX_CMD_ID_BOOT_CFG:
591 return "BOOT_CFG";
592 default:
593 return "UNKNOWN CMD";
594 }
595 }
596
597 static int
psp_cmd_submit_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd,uint64_t fence_mc_addr)598 psp_cmd_submit_buf(struct psp_context *psp,
599 struct amdgpu_firmware_info *ucode,
600 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
601 {
602 int ret;
603 int index, idx;
604 int timeout = 20000;
605 bool ras_intr = false;
606 bool skip_unsupport = false;
607
608 if (psp->adev->no_hw_access)
609 return 0;
610
611 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
612 return 0;
613
614 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
615
616 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
617
618 index = atomic_inc_return(&psp->fence_value);
619 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
620 if (ret) {
621 atomic_dec(&psp->fence_value);
622 goto exit;
623 }
624
625 amdgpu_device_invalidate_hdp(psp->adev, NULL);
626 while (*((unsigned int *)psp->fence_buf) != index) {
627 if (--timeout == 0)
628 break;
629 /*
630 * Shouldn't wait for timeout when err_event_athub occurs,
631 * because gpu reset thread triggered and lock resource should
632 * be released for psp resume sequence.
633 */
634 ras_intr = amdgpu_ras_intr_triggered();
635 if (ras_intr)
636 break;
637 usleep_range(10, 100);
638 amdgpu_device_invalidate_hdp(psp->adev, NULL);
639 }
640
641 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
642 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
643 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
644
645 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
646
647 /* In some cases, psp response status is not 0 even there is no
648 * problem while the command is submitted. Some version of PSP FW
649 * doesn't write 0 to that field.
650 * So here we would like to only print a warning instead of an error
651 * during psp initialization to avoid breaking hw_init and it doesn't
652 * return -EINVAL.
653 */
654 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
655 if (ucode)
656 DRM_WARN("failed to load ucode %s(0x%X) ",
657 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
658 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
659 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
660 psp->cmd_buf_mem->resp.status);
661 /* If any firmware (including CAP) load fails under SRIOV, it should
662 * return failure to stop the VF from initializing.
663 * Also return failure in case of timeout
664 */
665 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
666 ret = -EINVAL;
667 goto exit;
668 }
669 }
670
671 if (ucode) {
672 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
673 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
674 }
675
676 exit:
677 drm_dev_exit(idx);
678 return ret;
679 }
680
acquire_psp_cmd_buf(struct psp_context * psp)681 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
682 {
683 struct psp_gfx_cmd_resp *cmd = psp->cmd;
684
685 mutex_lock(&psp->mutex);
686
687 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
688
689 return cmd;
690 }
691
release_psp_cmd_buf(struct psp_context * psp)692 static void release_psp_cmd_buf(struct psp_context *psp)
693 {
694 mutex_unlock(&psp->mutex);
695 }
696
psp_prep_tmr_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd,uint64_t tmr_mc,struct amdgpu_bo * tmr_bo)697 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
698 struct psp_gfx_cmd_resp *cmd,
699 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
700 {
701 struct amdgpu_device *adev = psp->adev;
702 uint32_t size = amdgpu_bo_size(tmr_bo);
703 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
704
705 if (amdgpu_sriov_vf(psp->adev))
706 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
707 else
708 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
709 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
710 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
711 cmd->cmd.cmd_setup_tmr.buf_size = size;
712 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
713 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
714 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
715 }
716
psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t pri_buf_mc,uint32_t size)717 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
718 uint64_t pri_buf_mc, uint32_t size)
719 {
720 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
721 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
722 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
723 cmd->cmd.cmd_load_toc.toc_size = size;
724 }
725
726 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
psp_load_toc(struct psp_context * psp,uint32_t * tmr_size)727 static int psp_load_toc(struct psp_context *psp,
728 uint32_t *tmr_size)
729 {
730 int ret;
731 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
732
733 /* Copy toc to psp firmware private buffer */
734 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
735
736 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
737
738 ret = psp_cmd_submit_buf(psp, NULL, cmd,
739 psp->fence_buf_mc_addr);
740 if (!ret)
741 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
742
743 release_psp_cmd_buf(psp);
744
745 return ret;
746 }
747
748 /* Set up Trusted Memory Region */
psp_tmr_init(struct psp_context * psp)749 static int psp_tmr_init(struct psp_context *psp)
750 {
751 int ret = 0;
752 int tmr_size;
753 void *tmr_buf;
754 void **pptr;
755
756 /*
757 * According to HW engineer, they prefer the TMR address be "naturally
758 * aligned" , e.g. the start address be an integer divide of TMR size.
759 *
760 * Note: this memory need be reserved till the driver
761 * uninitializes.
762 */
763 tmr_size = PSP_TMR_SIZE(psp->adev);
764
765 /* For ASICs support RLC autoload, psp will parse the toc
766 * and calculate the total size of TMR needed */
767 if (!amdgpu_sriov_vf(psp->adev) &&
768 psp->toc.start_addr &&
769 psp->toc.size_bytes &&
770 psp->fw_pri_buf) {
771 ret = psp_load_toc(psp, &tmr_size);
772 if (ret) {
773 DRM_ERROR("Failed to load toc\n");
774 return ret;
775 }
776 }
777
778 if (!psp->tmr_bo) {
779 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
780 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
781 AMDGPU_GEM_DOMAIN_VRAM,
782 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
783 }
784
785 return ret;
786 }
787
psp_skip_tmr(struct psp_context * psp)788 static bool psp_skip_tmr(struct psp_context *psp)
789 {
790 switch (psp->adev->ip_versions[MP0_HWIP][0]) {
791 case IP_VERSION(11, 0, 9):
792 case IP_VERSION(11, 0, 7):
793 case IP_VERSION(13, 0, 2):
794 case IP_VERSION(13, 0, 10):
795 return true;
796 default:
797 return false;
798 }
799 }
800
psp_tmr_load(struct psp_context * psp)801 static int psp_tmr_load(struct psp_context *psp)
802 {
803 int ret;
804 struct psp_gfx_cmd_resp *cmd;
805
806 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
807 * Already set up by host driver.
808 */
809 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
810 return 0;
811
812 cmd = acquire_psp_cmd_buf(psp);
813
814 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
815 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
816 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
817
818 ret = psp_cmd_submit_buf(psp, NULL, cmd,
819 psp->fence_buf_mc_addr);
820
821 release_psp_cmd_buf(psp);
822
823 return ret;
824 }
825
psp_prep_tmr_unload_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd)826 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
827 struct psp_gfx_cmd_resp *cmd)
828 {
829 if (amdgpu_sriov_vf(psp->adev))
830 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
831 else
832 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
833 }
834
psp_tmr_unload(struct psp_context * psp)835 static int psp_tmr_unload(struct psp_context *psp)
836 {
837 int ret;
838 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
839
840 psp_prep_tmr_unload_cmd_buf(psp, cmd);
841 dev_info(psp->adev->dev, "free PSP TMR buffer\n");
842
843 ret = psp_cmd_submit_buf(psp, NULL, cmd,
844 psp->fence_buf_mc_addr);
845
846 release_psp_cmd_buf(psp);
847
848 return ret;
849 }
850
psp_tmr_terminate(struct psp_context * psp)851 static int psp_tmr_terminate(struct psp_context *psp)
852 {
853 return psp_tmr_unload(psp);
854 }
855
psp_get_fw_attestation_records_addr(struct psp_context * psp,uint64_t * output_ptr)856 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
857 uint64_t *output_ptr)
858 {
859 int ret;
860 struct psp_gfx_cmd_resp *cmd;
861
862 if (!output_ptr)
863 return -EINVAL;
864
865 if (amdgpu_sriov_vf(psp->adev))
866 return 0;
867
868 cmd = acquire_psp_cmd_buf(psp);
869
870 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
871
872 ret = psp_cmd_submit_buf(psp, NULL, cmd,
873 psp->fence_buf_mc_addr);
874
875 if (!ret) {
876 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
877 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
878 }
879
880 release_psp_cmd_buf(psp);
881
882 return ret;
883 }
884
psp_boot_config_get(struct amdgpu_device * adev,uint32_t * boot_cfg)885 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
886 {
887 struct psp_context *psp = &adev->psp;
888 struct psp_gfx_cmd_resp *cmd;
889 int ret;
890
891 if (amdgpu_sriov_vf(adev))
892 return 0;
893
894 cmd = acquire_psp_cmd_buf(psp);
895
896 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
897 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
898
899 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
900 if (!ret) {
901 *boot_cfg =
902 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
903 }
904
905 release_psp_cmd_buf(psp);
906
907 return ret;
908 }
909
psp_boot_config_set(struct amdgpu_device * adev,uint32_t boot_cfg)910 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
911 {
912 int ret;
913 struct psp_context *psp = &adev->psp;
914 struct psp_gfx_cmd_resp *cmd;
915
916 if (amdgpu_sriov_vf(adev))
917 return 0;
918
919 cmd = acquire_psp_cmd_buf(psp);
920
921 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
922 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
923 cmd->cmd.boot_cfg.boot_config = boot_cfg;
924 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
925
926 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
927
928 release_psp_cmd_buf(psp);
929
930 return ret;
931 }
932
psp_rl_load(struct amdgpu_device * adev)933 static int psp_rl_load(struct amdgpu_device *adev)
934 {
935 int ret;
936 struct psp_context *psp = &adev->psp;
937 struct psp_gfx_cmd_resp *cmd;
938
939 if (!is_psp_fw_valid(psp->rl))
940 return 0;
941
942 cmd = acquire_psp_cmd_buf(psp);
943
944 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
945 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
946
947 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
948 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
949 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
950 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
951 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
952
953 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
954
955 release_psp_cmd_buf(psp);
956
957 return ret;
958 }
959
psp_asd_initialize(struct psp_context * psp)960 static int psp_asd_initialize(struct psp_context *psp)
961 {
962 int ret;
963
964 /* If PSP version doesn't match ASD version, asd loading will be failed.
965 * add workaround to bypass it for sriov now.
966 * TODO: add version check to make it common
967 */
968 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
969 return 0;
970
971 psp->asd_context.mem_context.shared_mc_addr = 0;
972 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
973 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
974
975 ret = psp_ta_load(psp, &psp->asd_context);
976 if (!ret)
977 psp->asd_context.initialized = true;
978
979 return ret;
980 }
981
psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t session_id)982 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
983 uint32_t session_id)
984 {
985 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
986 cmd->cmd.cmd_unload_ta.session_id = session_id;
987 }
988
psp_ta_unload(struct psp_context * psp,struct ta_context * context)989 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
990 {
991 int ret;
992 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
993
994 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
995
996 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
997
998 release_psp_cmd_buf(psp);
999
1000 return ret;
1001 }
1002
psp_asd_terminate(struct psp_context * psp)1003 static int psp_asd_terminate(struct psp_context *psp)
1004 {
1005 int ret;
1006
1007 if (amdgpu_sriov_vf(psp->adev))
1008 return 0;
1009
1010 if (!psp->asd_context.initialized)
1011 return 0;
1012
1013 ret = psp_ta_unload(psp, &psp->asd_context);
1014 if (!ret)
1015 psp->asd_context.initialized = false;
1016
1017 return ret;
1018 }
1019
psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t id,uint32_t value)1020 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1021 uint32_t id, uint32_t value)
1022 {
1023 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1024 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1025 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1026 }
1027
psp_reg_program(struct psp_context * psp,enum psp_reg_prog_id reg,uint32_t value)1028 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1029 uint32_t value)
1030 {
1031 struct psp_gfx_cmd_resp *cmd;
1032 int ret = 0;
1033
1034 if (reg >= PSP_REG_LAST)
1035 return -EINVAL;
1036
1037 cmd = acquire_psp_cmd_buf(psp);
1038
1039 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1040 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1041 if (ret)
1042 DRM_ERROR("PSP failed to program reg id %d", reg);
1043
1044 release_psp_cmd_buf(psp);
1045
1046 return ret;
1047 }
1048
psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t ta_bin_mc,struct ta_context * context)1049 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1050 uint64_t ta_bin_mc,
1051 struct ta_context *context)
1052 {
1053 cmd->cmd_id = context->ta_load_type;
1054 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1055 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1056 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1057
1058 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1059 lower_32_bits(context->mem_context.shared_mc_addr);
1060 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1061 upper_32_bits(context->mem_context.shared_mc_addr);
1062 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1063 }
1064
psp_ta_init_shared_buf(struct psp_context * psp,struct ta_mem_context * mem_ctx)1065 int psp_ta_init_shared_buf(struct psp_context *psp,
1066 struct ta_mem_context *mem_ctx)
1067 {
1068 /*
1069 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1070 * physical) for ta to host memory
1071 */
1072 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1073 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1074 &mem_ctx->shared_bo,
1075 &mem_ctx->shared_mc_addr,
1076 &mem_ctx->shared_buf);
1077 }
1078
psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,struct ta_context * context)1079 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1080 uint32_t ta_cmd_id,
1081 struct ta_context *context)
1082 {
1083 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1084 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id;
1085 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1086
1087 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1;
1088 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
1089 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
1090 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
1091 lower_32_bits(context->mem_context.shared_mc_addr);
1092 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
1093 upper_32_bits(context->mem_context.shared_mc_addr);
1094 }
1095
psp_ta_invoke_indirect(struct psp_context * psp,uint32_t ta_cmd_id,struct ta_context * context)1096 int psp_ta_invoke_indirect(struct psp_context *psp,
1097 uint32_t ta_cmd_id,
1098 struct ta_context *context)
1099 {
1100 int ret;
1101 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1102
1103 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
1104
1105 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1106 psp->fence_buf_mc_addr);
1107
1108 context->resp_status = cmd->resp.status;
1109
1110 release_psp_cmd_buf(psp);
1111
1112 return ret;
1113 }
1114
psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,uint32_t session_id)1115 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1116 uint32_t ta_cmd_id,
1117 uint32_t session_id)
1118 {
1119 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1120 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1121 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1122 }
1123
psp_ta_invoke(struct psp_context * psp,uint32_t ta_cmd_id,struct ta_context * context)1124 int psp_ta_invoke(struct psp_context *psp,
1125 uint32_t ta_cmd_id,
1126 struct ta_context *context)
1127 {
1128 int ret;
1129 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1130
1131 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1132
1133 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1134 psp->fence_buf_mc_addr);
1135
1136 context->resp_status = cmd->resp.status;
1137
1138 release_psp_cmd_buf(psp);
1139
1140 return ret;
1141 }
1142
psp_ta_load(struct psp_context * psp,struct ta_context * context)1143 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1144 {
1145 int ret;
1146 struct psp_gfx_cmd_resp *cmd;
1147
1148 cmd = acquire_psp_cmd_buf(psp);
1149
1150 psp_copy_fw(psp, context->bin_desc.start_addr,
1151 context->bin_desc.size_bytes);
1152
1153 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1154
1155 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1156 psp->fence_buf_mc_addr);
1157
1158 context->resp_status = cmd->resp.status;
1159
1160 if (!ret) {
1161 context->session_id = cmd->resp.session_id;
1162 }
1163
1164 release_psp_cmd_buf(psp);
1165
1166 return ret;
1167 }
1168
psp_xgmi_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1169 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1170 {
1171 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1172 }
1173
psp_xgmi_terminate(struct psp_context * psp)1174 int psp_xgmi_terminate(struct psp_context *psp)
1175 {
1176 int ret;
1177 struct amdgpu_device *adev = psp->adev;
1178
1179 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1180 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1181 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1182 adev->gmc.xgmi.connected_to_cpu))
1183 return 0;
1184
1185 if (!psp->xgmi_context.context.initialized)
1186 return 0;
1187
1188 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1189
1190 psp->xgmi_context.context.initialized = false;
1191
1192 return ret;
1193 }
1194
psp_xgmi_initialize(struct psp_context * psp,bool set_extended_data,bool load_ta)1195 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1196 {
1197 struct ta_xgmi_shared_memory *xgmi_cmd;
1198 int ret;
1199
1200 if (!psp->ta_fw ||
1201 !psp->xgmi_context.context.bin_desc.size_bytes ||
1202 !psp->xgmi_context.context.bin_desc.start_addr)
1203 return -ENOENT;
1204
1205 if (!load_ta)
1206 goto invoke;
1207
1208 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1209 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1210
1211 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1212 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 /* Load XGMI TA */
1218 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1219 if (!ret)
1220 psp->xgmi_context.context.initialized = true;
1221 else
1222 return ret;
1223
1224 invoke:
1225 /* Initialize XGMI session */
1226 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1227 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1228 xgmi_cmd->flag_extend_link_record = set_extended_data;
1229 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1230
1231 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1232
1233 return ret;
1234 }
1235
psp_xgmi_get_hive_id(struct psp_context * psp,uint64_t * hive_id)1236 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1237 {
1238 struct ta_xgmi_shared_memory *xgmi_cmd;
1239 int ret;
1240
1241 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1242 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1243
1244 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1245
1246 /* Invoke xgmi ta to get hive id */
1247 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1248 if (ret)
1249 return ret;
1250
1251 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1252
1253 return 0;
1254 }
1255
psp_xgmi_get_node_id(struct psp_context * psp,uint64_t * node_id)1256 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1257 {
1258 struct ta_xgmi_shared_memory *xgmi_cmd;
1259 int ret;
1260
1261 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1262 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1263
1264 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1265
1266 /* Invoke xgmi ta to get the node id */
1267 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1268 if (ret)
1269 return ret;
1270
1271 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1272
1273 return 0;
1274 }
1275
psp_xgmi_peer_link_info_supported(struct psp_context * psp)1276 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1277 {
1278 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1279 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1280 }
1281
1282 /*
1283 * Chips that support extended topology information require the driver to
1284 * reflect topology information in the opposite direction. This is
1285 * because the TA has already exceeded its link record limit and if the
1286 * TA holds bi-directional information, the driver would have to do
1287 * multiple fetches instead of just two.
1288 */
psp_xgmi_reflect_topology_info(struct psp_context * psp,struct psp_xgmi_node_info node_info)1289 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1290 struct psp_xgmi_node_info node_info)
1291 {
1292 struct amdgpu_device *mirror_adev;
1293 struct amdgpu_hive_info *hive;
1294 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1295 uint64_t dst_node_id = node_info.node_id;
1296 uint8_t dst_num_hops = node_info.num_hops;
1297 uint8_t dst_num_links = node_info.num_links;
1298
1299 hive = amdgpu_get_xgmi_hive(psp->adev);
1300 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1301 struct psp_xgmi_topology_info *mirror_top_info;
1302 int j;
1303
1304 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1305 continue;
1306
1307 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1308 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1309 if (mirror_top_info->nodes[j].node_id != src_node_id)
1310 continue;
1311
1312 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1313 /*
1314 * prevent 0 num_links value re-reflection since reflection
1315 * criteria is based on num_hops (direct or indirect).
1316 *
1317 */
1318 if (dst_num_links)
1319 mirror_top_info->nodes[j].num_links = dst_num_links;
1320
1321 break;
1322 }
1323
1324 break;
1325 }
1326
1327 amdgpu_put_xgmi_hive(hive);
1328 }
1329
psp_xgmi_get_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology,bool get_extended_data)1330 int psp_xgmi_get_topology_info(struct psp_context *psp,
1331 int number_devices,
1332 struct psp_xgmi_topology_info *topology,
1333 bool get_extended_data)
1334 {
1335 struct ta_xgmi_shared_memory *xgmi_cmd;
1336 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1337 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1338 int i;
1339 int ret;
1340
1341 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1342 return -EINVAL;
1343
1344 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1345 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1346 xgmi_cmd->flag_extend_link_record = get_extended_data;
1347
1348 /* Fill in the shared memory with topology information as input */
1349 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1350 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1351 topology_info_input->num_nodes = number_devices;
1352
1353 for (i = 0; i < topology_info_input->num_nodes; i++) {
1354 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1355 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1356 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1357 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1358 }
1359
1360 /* Invoke xgmi ta to get the topology information */
1361 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1362 if (ret)
1363 return ret;
1364
1365 /* Read the output topology information from the shared memory */
1366 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1367 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1368 for (i = 0; i < topology->num_nodes; i++) {
1369 /* extended data will either be 0 or equal to non-extended data */
1370 if (topology_info_output->nodes[i].num_hops)
1371 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1372
1373 /* non-extended data gets everything here so no need to update */
1374 if (!get_extended_data) {
1375 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1376 topology->nodes[i].is_sharing_enabled =
1377 topology_info_output->nodes[i].is_sharing_enabled;
1378 topology->nodes[i].sdma_engine =
1379 topology_info_output->nodes[i].sdma_engine;
1380 }
1381
1382 }
1383
1384 /* Invoke xgmi ta again to get the link information */
1385 if (psp_xgmi_peer_link_info_supported(psp)) {
1386 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1387
1388 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1389
1390 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1391
1392 if (ret)
1393 return ret;
1394
1395 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1396 for (i = 0; i < topology->num_nodes; i++) {
1397 /* accumulate num_links on extended data */
1398 topology->nodes[i].num_links = get_extended_data ?
1399 topology->nodes[i].num_links +
1400 link_info_output->nodes[i].num_links :
1401 link_info_output->nodes[i].num_links;
1402
1403 /* reflect the topology information for bi-directionality */
1404 if (psp->xgmi_context.supports_extended_data &&
1405 get_extended_data && topology->nodes[i].num_hops)
1406 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1407 }
1408 }
1409
1410 return 0;
1411 }
1412
psp_xgmi_set_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)1413 int psp_xgmi_set_topology_info(struct psp_context *psp,
1414 int number_devices,
1415 struct psp_xgmi_topology_info *topology)
1416 {
1417 struct ta_xgmi_shared_memory *xgmi_cmd;
1418 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1419 int i;
1420
1421 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1422 return -EINVAL;
1423
1424 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1425 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1426
1427 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1428 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1429 topology_info_input->num_nodes = number_devices;
1430
1431 for (i = 0; i < topology_info_input->num_nodes; i++) {
1432 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1433 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1434 topology_info_input->nodes[i].is_sharing_enabled = 1;
1435 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1436 }
1437
1438 /* Invoke xgmi ta to set topology information */
1439 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1440 }
1441
1442 // ras begin
psp_ras_ta_check_status(struct psp_context * psp)1443 static void psp_ras_ta_check_status(struct psp_context *psp)
1444 {
1445 struct ta_ras_shared_memory *ras_cmd =
1446 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1447
1448 switch (ras_cmd->ras_status) {
1449 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1450 dev_warn(psp->adev->dev,
1451 "RAS WARNING: cmd failed due to unsupported ip\n");
1452 break;
1453 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1454 dev_warn(psp->adev->dev,
1455 "RAS WARNING: cmd failed due to unsupported error injection\n");
1456 break;
1457 case TA_RAS_STATUS__SUCCESS:
1458 break;
1459 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1460 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1461 dev_warn(psp->adev->dev,
1462 "RAS WARNING: Inject error to critical region is not allowed\n");
1463 break;
1464 default:
1465 dev_warn(psp->adev->dev,
1466 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1467 break;
1468 }
1469 }
1470
psp_ras_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1471 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1472 {
1473 struct ta_ras_shared_memory *ras_cmd;
1474 int ret;
1475
1476 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1477
1478 /*
1479 * TODO: bypass the loading in sriov for now
1480 */
1481 if (amdgpu_sriov_vf(psp->adev))
1482 return 0;
1483
1484 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1485
1486 if (amdgpu_ras_intr_triggered())
1487 return ret;
1488
1489 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1490 {
1491 DRM_WARN("RAS: Unsupported Interface");
1492 return -EINVAL;
1493 }
1494
1495 if (!ret) {
1496 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1497 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1498
1499 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1500 }
1501 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1502 dev_warn(psp->adev->dev,
1503 "RAS internal register access blocked\n");
1504
1505 psp_ras_ta_check_status(psp);
1506 }
1507
1508 return ret;
1509 }
1510
psp_ras_enable_features(struct psp_context * psp,union ta_ras_cmd_input * info,bool enable)1511 int psp_ras_enable_features(struct psp_context *psp,
1512 union ta_ras_cmd_input *info, bool enable)
1513 {
1514 struct ta_ras_shared_memory *ras_cmd;
1515 int ret;
1516
1517 if (!psp->ras_context.context.initialized)
1518 return -EINVAL;
1519
1520 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1521 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1522
1523 if (enable)
1524 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1525 else
1526 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1527
1528 ras_cmd->ras_in_message = *info;
1529
1530 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1531 if (ret)
1532 return -EINVAL;
1533
1534 return 0;
1535 }
1536
psp_ras_terminate(struct psp_context * psp)1537 int psp_ras_terminate(struct psp_context *psp)
1538 {
1539 int ret;
1540
1541 /*
1542 * TODO: bypass the terminate in sriov for now
1543 */
1544 if (amdgpu_sriov_vf(psp->adev))
1545 return 0;
1546
1547 if (!psp->ras_context.context.initialized)
1548 return 0;
1549
1550 ret = psp_ta_unload(psp, &psp->ras_context.context);
1551
1552 psp->ras_context.context.initialized = false;
1553
1554 return ret;
1555 }
1556
psp_ras_initialize(struct psp_context * psp)1557 static int psp_ras_initialize(struct psp_context *psp)
1558 {
1559 int ret;
1560 uint32_t boot_cfg = 0xFF;
1561 struct amdgpu_device *adev = psp->adev;
1562 struct ta_ras_shared_memory *ras_cmd;
1563
1564 /*
1565 * TODO: bypass the initialize in sriov for now
1566 */
1567 if (amdgpu_sriov_vf(adev))
1568 return 0;
1569
1570 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1571 !adev->psp.ras_context.context.bin_desc.start_addr) {
1572 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1573 return 0;
1574 }
1575
1576 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1577 /* query GECC enablement status from boot config
1578 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1579 */
1580 ret = psp_boot_config_get(adev, &boot_cfg);
1581 if (ret)
1582 dev_warn(adev->dev, "PSP get boot config failed\n");
1583
1584 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1585 if (!boot_cfg) {
1586 dev_info(adev->dev, "GECC is disabled\n");
1587 } else {
1588 /* disable GECC in next boot cycle if ras is
1589 * disabled by module parameter amdgpu_ras_enable
1590 * and/or amdgpu_ras_mask, or boot_config_get call
1591 * is failed
1592 */
1593 ret = psp_boot_config_set(adev, 0);
1594 if (ret)
1595 dev_warn(adev->dev, "PSP set boot config failed\n");
1596 else
1597 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1598 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1599 }
1600 } else {
1601 if (1 == boot_cfg) {
1602 dev_info(adev->dev, "GECC is enabled\n");
1603 } else {
1604 /* enable GECC in next boot cycle if it is disabled
1605 * in boot config, or force enable GECC if failed to
1606 * get boot configuration
1607 */
1608 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1609 if (ret)
1610 dev_warn(adev->dev, "PSP set boot config failed\n");
1611 else
1612 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1613 }
1614 }
1615 }
1616
1617 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1618 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1619
1620 if (!psp->ras_context.context.initialized) {
1621 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1622 if (ret)
1623 return ret;
1624 }
1625
1626 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1627 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1628
1629 if (amdgpu_ras_is_poison_mode_supported(adev))
1630 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1631 if (!adev->gmc.xgmi.connected_to_cpu)
1632 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1633
1634 ret = psp_ta_load(psp, &psp->ras_context.context);
1635
1636 if (!ret && !ras_cmd->ras_status)
1637 psp->ras_context.context.initialized = true;
1638 else {
1639 if (ras_cmd->ras_status)
1640 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1641 amdgpu_ras_fini(psp->adev);
1642 }
1643
1644 return ret;
1645 }
1646
psp_ras_trigger_error(struct psp_context * psp,struct ta_ras_trigger_error_input * info)1647 int psp_ras_trigger_error(struct psp_context *psp,
1648 struct ta_ras_trigger_error_input *info)
1649 {
1650 struct ta_ras_shared_memory *ras_cmd;
1651 int ret;
1652
1653 if (!psp->ras_context.context.initialized)
1654 return -EINVAL;
1655
1656 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1657 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1658
1659 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1660 ras_cmd->ras_in_message.trigger_error = *info;
1661
1662 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1663 if (ret)
1664 return -EINVAL;
1665
1666 /* If err_event_athub occurs error inject was successful, however
1667 return status from TA is no long reliable */
1668 if (amdgpu_ras_intr_triggered())
1669 return 0;
1670
1671 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1672 return -EACCES;
1673 else if (ras_cmd->ras_status)
1674 return -EINVAL;
1675
1676 return 0;
1677 }
1678 // ras end
1679
1680 // HDCP start
psp_hdcp_initialize(struct psp_context * psp)1681 static int psp_hdcp_initialize(struct psp_context *psp)
1682 {
1683 int ret;
1684
1685 /*
1686 * TODO: bypass the initialize in sriov for now
1687 */
1688 if (amdgpu_sriov_vf(psp->adev))
1689 return 0;
1690
1691 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1692 !psp->hdcp_context.context.bin_desc.start_addr) {
1693 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1694 return 0;
1695 }
1696
1697 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1698 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1699
1700 if (!psp->hdcp_context.context.mem_context.shared_buf) {
1701 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1702 if (ret)
1703 return ret;
1704 }
1705
1706 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1707 if (!ret) {
1708 psp->hdcp_context.context.initialized = true;
1709 mutex_init(&psp->hdcp_context.mutex);
1710 }
1711
1712 return ret;
1713 }
1714
psp_hdcp_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1715 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1716 {
1717 /*
1718 * TODO: bypass the loading in sriov for now
1719 */
1720 if (amdgpu_sriov_vf(psp->adev))
1721 return 0;
1722
1723 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1724 }
1725
psp_hdcp_terminate(struct psp_context * psp)1726 static int psp_hdcp_terminate(struct psp_context *psp)
1727 {
1728 int ret;
1729
1730 /*
1731 * TODO: bypass the terminate in sriov for now
1732 */
1733 if (amdgpu_sriov_vf(psp->adev))
1734 return 0;
1735
1736 if (!psp->hdcp_context.context.initialized)
1737 return 0;
1738
1739 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1740
1741 psp->hdcp_context.context.initialized = false;
1742
1743 return ret;
1744 }
1745 // HDCP end
1746
1747 // DTM start
psp_dtm_initialize(struct psp_context * psp)1748 static int psp_dtm_initialize(struct psp_context *psp)
1749 {
1750 int ret;
1751
1752 /*
1753 * TODO: bypass the initialize in sriov for now
1754 */
1755 if (amdgpu_sriov_vf(psp->adev))
1756 return 0;
1757
1758 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1759 !psp->dtm_context.context.bin_desc.start_addr) {
1760 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1761 return 0;
1762 }
1763
1764 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1765 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1766
1767 if (!psp->dtm_context.context.mem_context.shared_buf) {
1768 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1769 if (ret)
1770 return ret;
1771 }
1772
1773 ret = psp_ta_load(psp, &psp->dtm_context.context);
1774 if (!ret) {
1775 psp->dtm_context.context.initialized = true;
1776 mutex_init(&psp->dtm_context.mutex);
1777 }
1778
1779 return ret;
1780 }
1781
psp_dtm_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1782 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1783 {
1784 /*
1785 * TODO: bypass the loading in sriov for now
1786 */
1787 if (amdgpu_sriov_vf(psp->adev))
1788 return 0;
1789
1790 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1791 }
1792
psp_dtm_terminate(struct psp_context * psp)1793 static int psp_dtm_terminate(struct psp_context *psp)
1794 {
1795 int ret;
1796
1797 /*
1798 * TODO: bypass the terminate in sriov for now
1799 */
1800 if (amdgpu_sriov_vf(psp->adev))
1801 return 0;
1802
1803 if (!psp->dtm_context.context.initialized)
1804 return 0;
1805
1806 ret = psp_ta_unload(psp, &psp->dtm_context.context);
1807
1808 psp->dtm_context.context.initialized = false;
1809
1810 return ret;
1811 }
1812 // DTM end
1813
1814 // RAP start
psp_rap_initialize(struct psp_context * psp)1815 static int psp_rap_initialize(struct psp_context *psp)
1816 {
1817 int ret;
1818 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1819
1820 /*
1821 * TODO: bypass the initialize in sriov for now
1822 */
1823 if (amdgpu_sriov_vf(psp->adev))
1824 return 0;
1825
1826 if (!psp->rap_context.context.bin_desc.size_bytes ||
1827 !psp->rap_context.context.bin_desc.start_addr) {
1828 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1829 return 0;
1830 }
1831
1832 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1833 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1834
1835 if (!psp->rap_context.context.mem_context.shared_buf) {
1836 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1837 if (ret)
1838 return ret;
1839 }
1840
1841 ret = psp_ta_load(psp, &psp->rap_context.context);
1842 if (!ret) {
1843 psp->rap_context.context.initialized = true;
1844 mutex_init(&psp->rap_context.mutex);
1845 } else
1846 return ret;
1847
1848 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1849 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1850 psp_rap_terminate(psp);
1851 /* free rap shared memory */
1852 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1853
1854 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1855 ret, status);
1856
1857 return ret;
1858 }
1859
1860 return 0;
1861 }
1862
psp_rap_terminate(struct psp_context * psp)1863 static int psp_rap_terminate(struct psp_context *psp)
1864 {
1865 int ret;
1866
1867 if (!psp->rap_context.context.initialized)
1868 return 0;
1869
1870 ret = psp_ta_unload(psp, &psp->rap_context.context);
1871
1872 psp->rap_context.context.initialized = false;
1873
1874 return ret;
1875 }
1876
psp_rap_invoke(struct psp_context * psp,uint32_t ta_cmd_id,enum ta_rap_status * status)1877 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1878 {
1879 struct ta_rap_shared_memory *rap_cmd;
1880 int ret = 0;
1881
1882 if (!psp->rap_context.context.initialized)
1883 return 0;
1884
1885 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1886 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1887 return -EINVAL;
1888
1889 mutex_lock(&psp->rap_context.mutex);
1890
1891 rap_cmd = (struct ta_rap_shared_memory *)
1892 psp->rap_context.context.mem_context.shared_buf;
1893 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1894
1895 rap_cmd->cmd_id = ta_cmd_id;
1896 rap_cmd->validation_method_id = METHOD_A;
1897
1898 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1899 if (ret)
1900 goto out_unlock;
1901
1902 if (status)
1903 *status = rap_cmd->rap_status;
1904
1905 out_unlock:
1906 mutex_unlock(&psp->rap_context.mutex);
1907
1908 return ret;
1909 }
1910 // RAP end
1911
1912 /* securedisplay start */
psp_securedisplay_initialize(struct psp_context * psp)1913 static int psp_securedisplay_initialize(struct psp_context *psp)
1914 {
1915 int ret;
1916 struct securedisplay_cmd *securedisplay_cmd;
1917
1918 /*
1919 * TODO: bypass the initialize in sriov for now
1920 */
1921 if (amdgpu_sriov_vf(psp->adev))
1922 return 0;
1923
1924 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1925 !psp->securedisplay_context.context.bin_desc.start_addr) {
1926 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1927 return 0;
1928 }
1929
1930 psp->securedisplay_context.context.mem_context.shared_mem_size =
1931 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1932 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1933
1934 if (!psp->securedisplay_context.context.initialized) {
1935 ret = psp_ta_init_shared_buf(psp,
1936 &psp->securedisplay_context.context.mem_context);
1937 if (ret)
1938 return ret;
1939 }
1940
1941 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1942 if (!ret) {
1943 psp->securedisplay_context.context.initialized = true;
1944 mutex_init(&psp->securedisplay_context.mutex);
1945 } else
1946 return ret;
1947
1948 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1949 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1950
1951 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1952 if (ret) {
1953 psp_securedisplay_terminate(psp);
1954 /* free securedisplay shared memory */
1955 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1956 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1957 return -EINVAL;
1958 }
1959
1960 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1961 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1962 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1963 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1964 /* don't try again */
1965 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
1966 }
1967
1968 return 0;
1969 }
1970
psp_securedisplay_terminate(struct psp_context * psp)1971 static int psp_securedisplay_terminate(struct psp_context *psp)
1972 {
1973 int ret;
1974
1975 /*
1976 * TODO:bypass the terminate in sriov for now
1977 */
1978 if (amdgpu_sriov_vf(psp->adev))
1979 return 0;
1980
1981 if (!psp->securedisplay_context.context.initialized)
1982 return 0;
1983
1984 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1985
1986 psp->securedisplay_context.context.initialized = false;
1987
1988 return ret;
1989 }
1990
psp_securedisplay_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1991 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1992 {
1993 int ret;
1994
1995 if (!psp->securedisplay_context.context.initialized)
1996 return -EINVAL;
1997
1998 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1999 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2000 return -EINVAL;
2001
2002 mutex_lock(&psp->securedisplay_context.mutex);
2003
2004 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2005
2006 mutex_unlock(&psp->securedisplay_context.mutex);
2007
2008 return ret;
2009 }
2010 /* SECUREDISPLAY end */
2011
psp_hw_start(struct psp_context * psp)2012 static int psp_hw_start(struct psp_context *psp)
2013 {
2014 struct amdgpu_device *adev = psp->adev;
2015 int ret;
2016
2017 if (!amdgpu_sriov_vf(adev)) {
2018 if ((is_psp_fw_valid(psp->kdb)) &&
2019 (psp->funcs->bootloader_load_kdb != NULL)) {
2020 ret = psp_bootloader_load_kdb(psp);
2021 if (ret) {
2022 DRM_ERROR("PSP load kdb failed!\n");
2023 return ret;
2024 }
2025 }
2026
2027 if ((is_psp_fw_valid(psp->spl)) &&
2028 (psp->funcs->bootloader_load_spl != NULL)) {
2029 ret = psp_bootloader_load_spl(psp);
2030 if (ret) {
2031 DRM_ERROR("PSP load spl failed!\n");
2032 return ret;
2033 }
2034 }
2035
2036 if ((is_psp_fw_valid(psp->sys)) &&
2037 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2038 ret = psp_bootloader_load_sysdrv(psp);
2039 if (ret) {
2040 DRM_ERROR("PSP load sys drv failed!\n");
2041 return ret;
2042 }
2043 }
2044
2045 if ((is_psp_fw_valid(psp->soc_drv)) &&
2046 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2047 ret = psp_bootloader_load_soc_drv(psp);
2048 if (ret) {
2049 DRM_ERROR("PSP load soc drv failed!\n");
2050 return ret;
2051 }
2052 }
2053
2054 if ((is_psp_fw_valid(psp->intf_drv)) &&
2055 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2056 ret = psp_bootloader_load_intf_drv(psp);
2057 if (ret) {
2058 DRM_ERROR("PSP load intf drv failed!\n");
2059 return ret;
2060 }
2061 }
2062
2063 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2064 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2065 ret = psp_bootloader_load_dbg_drv(psp);
2066 if (ret) {
2067 DRM_ERROR("PSP load dbg drv failed!\n");
2068 return ret;
2069 }
2070 }
2071
2072 if ((is_psp_fw_valid(psp->ras_drv)) &&
2073 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2074 ret = psp_bootloader_load_ras_drv(psp);
2075 if (ret) {
2076 DRM_ERROR("PSP load ras_drv failed!\n");
2077 return ret;
2078 }
2079 }
2080
2081 if ((is_psp_fw_valid(psp->sos)) &&
2082 (psp->funcs->bootloader_load_sos != NULL)) {
2083 ret = psp_bootloader_load_sos(psp);
2084 if (ret) {
2085 DRM_ERROR("PSP load sos failed!\n");
2086 return ret;
2087 }
2088 }
2089 }
2090
2091 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2092 if (ret) {
2093 DRM_ERROR("PSP create ring failed!\n");
2094 return ret;
2095 }
2096
2097 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2098 goto skip_pin_bo;
2099
2100 ret = psp_tmr_init(psp);
2101 if (ret) {
2102 DRM_ERROR("PSP tmr init failed!\n");
2103 return ret;
2104 }
2105
2106 skip_pin_bo:
2107 /*
2108 * For ASICs with DF Cstate management centralized
2109 * to PMFW, TMR setup should be performed after PMFW
2110 * loaded and before other non-psp firmware loaded.
2111 */
2112 if (psp->pmfw_centralized_cstate_management) {
2113 ret = psp_load_smu_fw(psp);
2114 if (ret)
2115 return ret;
2116 }
2117
2118 ret = psp_tmr_load(psp);
2119 if (ret) {
2120 DRM_ERROR("PSP load tmr failed!\n");
2121 return ret;
2122 }
2123
2124 return 0;
2125 }
2126
psp_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)2127 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2128 enum psp_gfx_fw_type *type)
2129 {
2130 switch (ucode->ucode_id) {
2131 case AMDGPU_UCODE_ID_CAP:
2132 *type = GFX_FW_TYPE_CAP;
2133 break;
2134 case AMDGPU_UCODE_ID_SDMA0:
2135 *type = GFX_FW_TYPE_SDMA0;
2136 break;
2137 case AMDGPU_UCODE_ID_SDMA1:
2138 *type = GFX_FW_TYPE_SDMA1;
2139 break;
2140 case AMDGPU_UCODE_ID_SDMA2:
2141 *type = GFX_FW_TYPE_SDMA2;
2142 break;
2143 case AMDGPU_UCODE_ID_SDMA3:
2144 *type = GFX_FW_TYPE_SDMA3;
2145 break;
2146 case AMDGPU_UCODE_ID_SDMA4:
2147 *type = GFX_FW_TYPE_SDMA4;
2148 break;
2149 case AMDGPU_UCODE_ID_SDMA5:
2150 *type = GFX_FW_TYPE_SDMA5;
2151 break;
2152 case AMDGPU_UCODE_ID_SDMA6:
2153 *type = GFX_FW_TYPE_SDMA6;
2154 break;
2155 case AMDGPU_UCODE_ID_SDMA7:
2156 *type = GFX_FW_TYPE_SDMA7;
2157 break;
2158 case AMDGPU_UCODE_ID_CP_MES:
2159 *type = GFX_FW_TYPE_CP_MES;
2160 break;
2161 case AMDGPU_UCODE_ID_CP_MES_DATA:
2162 *type = GFX_FW_TYPE_MES_STACK;
2163 break;
2164 case AMDGPU_UCODE_ID_CP_MES1:
2165 *type = GFX_FW_TYPE_CP_MES_KIQ;
2166 break;
2167 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2168 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2169 break;
2170 case AMDGPU_UCODE_ID_CP_CE:
2171 *type = GFX_FW_TYPE_CP_CE;
2172 break;
2173 case AMDGPU_UCODE_ID_CP_PFP:
2174 *type = GFX_FW_TYPE_CP_PFP;
2175 break;
2176 case AMDGPU_UCODE_ID_CP_ME:
2177 *type = GFX_FW_TYPE_CP_ME;
2178 break;
2179 case AMDGPU_UCODE_ID_CP_MEC1:
2180 *type = GFX_FW_TYPE_CP_MEC;
2181 break;
2182 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2183 *type = GFX_FW_TYPE_CP_MEC_ME1;
2184 break;
2185 case AMDGPU_UCODE_ID_CP_MEC2:
2186 *type = GFX_FW_TYPE_CP_MEC;
2187 break;
2188 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2189 *type = GFX_FW_TYPE_CP_MEC_ME2;
2190 break;
2191 case AMDGPU_UCODE_ID_RLC_P:
2192 *type = GFX_FW_TYPE_RLC_P;
2193 break;
2194 case AMDGPU_UCODE_ID_RLC_V:
2195 *type = GFX_FW_TYPE_RLC_V;
2196 break;
2197 case AMDGPU_UCODE_ID_RLC_G:
2198 *type = GFX_FW_TYPE_RLC_G;
2199 break;
2200 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2201 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2202 break;
2203 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2204 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2205 break;
2206 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2207 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2208 break;
2209 case AMDGPU_UCODE_ID_RLC_IRAM:
2210 *type = GFX_FW_TYPE_RLC_IRAM;
2211 break;
2212 case AMDGPU_UCODE_ID_RLC_DRAM:
2213 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2214 break;
2215 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2216 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2217 break;
2218 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2219 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2220 break;
2221 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2222 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2223 break;
2224 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2225 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2226 break;
2227 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2228 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2229 break;
2230 case AMDGPU_UCODE_ID_SMC:
2231 *type = GFX_FW_TYPE_SMU;
2232 break;
2233 case AMDGPU_UCODE_ID_PPTABLE:
2234 *type = GFX_FW_TYPE_PPTABLE;
2235 break;
2236 case AMDGPU_UCODE_ID_UVD:
2237 *type = GFX_FW_TYPE_UVD;
2238 break;
2239 case AMDGPU_UCODE_ID_UVD1:
2240 *type = GFX_FW_TYPE_UVD1;
2241 break;
2242 case AMDGPU_UCODE_ID_VCE:
2243 *type = GFX_FW_TYPE_VCE;
2244 break;
2245 case AMDGPU_UCODE_ID_VCN:
2246 *type = GFX_FW_TYPE_VCN;
2247 break;
2248 case AMDGPU_UCODE_ID_VCN1:
2249 *type = GFX_FW_TYPE_VCN1;
2250 break;
2251 case AMDGPU_UCODE_ID_DMCU_ERAM:
2252 *type = GFX_FW_TYPE_DMCU_ERAM;
2253 break;
2254 case AMDGPU_UCODE_ID_DMCU_INTV:
2255 *type = GFX_FW_TYPE_DMCU_ISR;
2256 break;
2257 case AMDGPU_UCODE_ID_VCN0_RAM:
2258 *type = GFX_FW_TYPE_VCN0_RAM;
2259 break;
2260 case AMDGPU_UCODE_ID_VCN1_RAM:
2261 *type = GFX_FW_TYPE_VCN1_RAM;
2262 break;
2263 case AMDGPU_UCODE_ID_DMCUB:
2264 *type = GFX_FW_TYPE_DMUB;
2265 break;
2266 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2267 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2268 break;
2269 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2270 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2271 break;
2272 case AMDGPU_UCODE_ID_IMU_I:
2273 *type = GFX_FW_TYPE_IMU_I;
2274 break;
2275 case AMDGPU_UCODE_ID_IMU_D:
2276 *type = GFX_FW_TYPE_IMU_D;
2277 break;
2278 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2279 *type = GFX_FW_TYPE_RS64_PFP;
2280 break;
2281 case AMDGPU_UCODE_ID_CP_RS64_ME:
2282 *type = GFX_FW_TYPE_RS64_ME;
2283 break;
2284 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2285 *type = GFX_FW_TYPE_RS64_MEC;
2286 break;
2287 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2288 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2289 break;
2290 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2291 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2292 break;
2293 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2294 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2295 break;
2296 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2297 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2298 break;
2299 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2300 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2301 break;
2302 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2303 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2304 break;
2305 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2306 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2307 break;
2308 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2309 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2310 break;
2311 case AMDGPU_UCODE_ID_MAXIMUM:
2312 default:
2313 return -EINVAL;
2314 }
2315
2316 return 0;
2317 }
2318
psp_print_fw_hdr(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2319 static void psp_print_fw_hdr(struct psp_context *psp,
2320 struct amdgpu_firmware_info *ucode)
2321 {
2322 struct amdgpu_device *adev = psp->adev;
2323 struct common_firmware_header *hdr;
2324
2325 switch (ucode->ucode_id) {
2326 case AMDGPU_UCODE_ID_SDMA0:
2327 case AMDGPU_UCODE_ID_SDMA1:
2328 case AMDGPU_UCODE_ID_SDMA2:
2329 case AMDGPU_UCODE_ID_SDMA3:
2330 case AMDGPU_UCODE_ID_SDMA4:
2331 case AMDGPU_UCODE_ID_SDMA5:
2332 case AMDGPU_UCODE_ID_SDMA6:
2333 case AMDGPU_UCODE_ID_SDMA7:
2334 hdr = (struct common_firmware_header *)
2335 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2336 amdgpu_ucode_print_sdma_hdr(hdr);
2337 break;
2338 case AMDGPU_UCODE_ID_CP_CE:
2339 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2340 amdgpu_ucode_print_gfx_hdr(hdr);
2341 break;
2342 case AMDGPU_UCODE_ID_CP_PFP:
2343 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2344 amdgpu_ucode_print_gfx_hdr(hdr);
2345 break;
2346 case AMDGPU_UCODE_ID_CP_ME:
2347 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2348 amdgpu_ucode_print_gfx_hdr(hdr);
2349 break;
2350 case AMDGPU_UCODE_ID_CP_MEC1:
2351 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2352 amdgpu_ucode_print_gfx_hdr(hdr);
2353 break;
2354 case AMDGPU_UCODE_ID_RLC_G:
2355 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2356 amdgpu_ucode_print_rlc_hdr(hdr);
2357 break;
2358 case AMDGPU_UCODE_ID_SMC:
2359 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2360 amdgpu_ucode_print_smc_hdr(hdr);
2361 break;
2362 default:
2363 break;
2364 }
2365 }
2366
psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)2367 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2368 struct psp_gfx_cmd_resp *cmd)
2369 {
2370 int ret;
2371 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2372
2373 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2374 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2375 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2376 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2377
2378 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2379 if (ret)
2380 DRM_ERROR("Unknown firmware type\n");
2381
2382 return ret;
2383 }
2384
psp_execute_non_psp_fw_load(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2385 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2386 struct amdgpu_firmware_info *ucode)
2387 {
2388 int ret = 0;
2389 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2390
2391 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2392 if (!ret) {
2393 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2394 psp->fence_buf_mc_addr);
2395 }
2396
2397 release_psp_cmd_buf(psp);
2398
2399 return ret;
2400 }
2401
psp_load_smu_fw(struct psp_context * psp)2402 static int psp_load_smu_fw(struct psp_context *psp)
2403 {
2404 int ret;
2405 struct amdgpu_device *adev = psp->adev;
2406 struct amdgpu_firmware_info *ucode =
2407 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2408 struct amdgpu_ras *ras = psp->ras_context.ras;
2409
2410 /*
2411 * Skip SMU FW reloading in case of using BACO for runpm only,
2412 * as SMU is always alive.
2413 */
2414 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2415 return 0;
2416
2417 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2418 return 0;
2419
2420 if ((amdgpu_in_reset(adev) &&
2421 ras && adev->ras_enabled &&
2422 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2423 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2424 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2425 if (ret) {
2426 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2427 }
2428 }
2429
2430 ret = psp_execute_non_psp_fw_load(psp, ucode);
2431
2432 if (ret)
2433 DRM_ERROR("PSP load smu failed!\n");
2434
2435 return ret;
2436 }
2437
fw_load_skip_check(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2438 static bool fw_load_skip_check(struct psp_context *psp,
2439 struct amdgpu_firmware_info *ucode)
2440 {
2441 if (!ucode->fw || !ucode->ucode_size)
2442 return true;
2443
2444 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2445 (psp_smu_reload_quirk(psp) ||
2446 psp->autoload_supported ||
2447 psp->pmfw_centralized_cstate_management))
2448 return true;
2449
2450 if (amdgpu_sriov_vf(psp->adev) &&
2451 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2452 return true;
2453
2454 if (psp->autoload_supported &&
2455 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2456 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2457 /* skip mec JT when autoload is enabled */
2458 return true;
2459
2460 return false;
2461 }
2462
psp_load_fw_list(struct psp_context * psp,struct amdgpu_firmware_info ** ucode_list,int ucode_count)2463 int psp_load_fw_list(struct psp_context *psp,
2464 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2465 {
2466 int ret = 0, i;
2467 struct amdgpu_firmware_info *ucode;
2468
2469 for (i = 0; i < ucode_count; ++i) {
2470 ucode = ucode_list[i];
2471 psp_print_fw_hdr(psp, ucode);
2472 ret = psp_execute_non_psp_fw_load(psp, ucode);
2473 if (ret)
2474 return ret;
2475 }
2476 return ret;
2477 }
2478
psp_load_non_psp_fw(struct psp_context * psp)2479 static int psp_load_non_psp_fw(struct psp_context *psp)
2480 {
2481 int i, ret;
2482 struct amdgpu_firmware_info *ucode;
2483 struct amdgpu_device *adev = psp->adev;
2484
2485 if (psp->autoload_supported &&
2486 !psp->pmfw_centralized_cstate_management) {
2487 ret = psp_load_smu_fw(psp);
2488 if (ret)
2489 return ret;
2490 }
2491
2492 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2493 ucode = &adev->firmware.ucode[i];
2494
2495 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2496 !fw_load_skip_check(psp, ucode)) {
2497 ret = psp_load_smu_fw(psp);
2498 if (ret)
2499 return ret;
2500 continue;
2501 }
2502
2503 if (fw_load_skip_check(psp, ucode))
2504 continue;
2505
2506 if (psp->autoload_supported &&
2507 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2508 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2509 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2510 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2511 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2512 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2513 /* PSP only receive one SDMA fw for sienna_cichlid,
2514 * as all four sdma fw are same */
2515 continue;
2516
2517 psp_print_fw_hdr(psp, ucode);
2518
2519 ret = psp_execute_non_psp_fw_load(psp, ucode);
2520 if (ret)
2521 return ret;
2522
2523 /* Start rlc autoload after psp recieved all the gfx firmware */
2524 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2525 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2526 ret = psp_rlc_autoload_start(psp);
2527 if (ret) {
2528 DRM_ERROR("Failed to start rlc autoload\n");
2529 return ret;
2530 }
2531 }
2532 }
2533
2534 return 0;
2535 }
2536
psp_load_fw(struct amdgpu_device * adev)2537 static int psp_load_fw(struct amdgpu_device *adev)
2538 {
2539 int ret;
2540 struct psp_context *psp = &adev->psp;
2541
2542 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2543 /* should not destroy ring, only stop */
2544 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2545 } else {
2546 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2547
2548 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2549 if (ret) {
2550 DRM_ERROR("PSP ring init failed!\n");
2551 goto failed;
2552 }
2553 }
2554
2555 ret = psp_hw_start(psp);
2556 if (ret)
2557 goto failed;
2558
2559 ret = psp_load_non_psp_fw(psp);
2560 if (ret)
2561 goto failed1;
2562
2563 ret = psp_asd_initialize(psp);
2564 if (ret) {
2565 DRM_ERROR("PSP load asd failed!\n");
2566 goto failed1;
2567 }
2568
2569 ret = psp_rl_load(adev);
2570 if (ret) {
2571 DRM_ERROR("PSP load RL failed!\n");
2572 goto failed1;
2573 }
2574
2575 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2576 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2577 ret = psp_xgmi_initialize(psp, false, true);
2578 /* Warning the XGMI seesion initialize failure
2579 * Instead of stop driver initialization
2580 */
2581 if (ret)
2582 dev_err(psp->adev->dev,
2583 "XGMI: Failed to initialize XGMI session\n");
2584 }
2585 }
2586
2587 if (psp->ta_fw) {
2588 ret = psp_ras_initialize(psp);
2589 if (ret)
2590 dev_err(psp->adev->dev,
2591 "RAS: Failed to initialize RAS\n");
2592
2593 ret = psp_hdcp_initialize(psp);
2594 if (ret)
2595 dev_err(psp->adev->dev,
2596 "HDCP: Failed to initialize HDCP\n");
2597
2598 ret = psp_dtm_initialize(psp);
2599 if (ret)
2600 dev_err(psp->adev->dev,
2601 "DTM: Failed to initialize DTM\n");
2602
2603 ret = psp_rap_initialize(psp);
2604 if (ret)
2605 dev_err(psp->adev->dev,
2606 "RAP: Failed to initialize RAP\n");
2607
2608 ret = psp_securedisplay_initialize(psp);
2609 if (ret)
2610 dev_err(psp->adev->dev,
2611 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2612 }
2613
2614 return 0;
2615
2616 failed1:
2617 psp_free_shared_bufs(psp);
2618 failed:
2619 /*
2620 * all cleanup jobs (xgmi terminate, ras terminate,
2621 * ring destroy, cmd/fence/fw buffers destory,
2622 * psp->cmd destory) are delayed to psp_hw_fini
2623 */
2624 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2625 return ret;
2626 }
2627
psp_hw_init(void * handle)2628 static int psp_hw_init(void *handle)
2629 {
2630 int ret;
2631 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2632
2633 mutex_lock(&adev->firmware.mutex);
2634 /*
2635 * This sequence is just used on hw_init only once, no need on
2636 * resume.
2637 */
2638 ret = amdgpu_ucode_init_bo(adev);
2639 if (ret)
2640 goto failed;
2641
2642 ret = psp_load_fw(adev);
2643 if (ret) {
2644 DRM_ERROR("PSP firmware loading failed\n");
2645 goto failed;
2646 }
2647
2648 mutex_unlock(&adev->firmware.mutex);
2649 return 0;
2650
2651 failed:
2652 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2653 mutex_unlock(&adev->firmware.mutex);
2654 return -EINVAL;
2655 }
2656
psp_hw_fini(void * handle)2657 static int psp_hw_fini(void *handle)
2658 {
2659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2660 struct psp_context *psp = &adev->psp;
2661
2662 if (psp->ta_fw) {
2663 psp_ras_terminate(psp);
2664 psp_securedisplay_terminate(psp);
2665 psp_rap_terminate(psp);
2666 psp_dtm_terminate(psp);
2667 psp_hdcp_terminate(psp);
2668
2669 if (adev->gmc.xgmi.num_physical_nodes > 1)
2670 psp_xgmi_terminate(psp);
2671 }
2672
2673 psp_asd_terminate(psp);
2674 psp_tmr_terminate(psp);
2675
2676 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2677
2678 return 0;
2679 }
2680
psp_suspend(void * handle)2681 static int psp_suspend(void *handle)
2682 {
2683 int ret = 0;
2684 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2685 struct psp_context *psp = &adev->psp;
2686
2687 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2688 psp->xgmi_context.context.initialized) {
2689 ret = psp_xgmi_terminate(psp);
2690 if (ret) {
2691 DRM_ERROR("Failed to terminate xgmi ta\n");
2692 goto out;
2693 }
2694 }
2695
2696 if (psp->ta_fw) {
2697 ret = psp_ras_terminate(psp);
2698 if (ret) {
2699 DRM_ERROR("Failed to terminate ras ta\n");
2700 goto out;
2701 }
2702 ret = psp_hdcp_terminate(psp);
2703 if (ret) {
2704 DRM_ERROR("Failed to terminate hdcp ta\n");
2705 goto out;
2706 }
2707 ret = psp_dtm_terminate(psp);
2708 if (ret) {
2709 DRM_ERROR("Failed to terminate dtm ta\n");
2710 goto out;
2711 }
2712 ret = psp_rap_terminate(psp);
2713 if (ret) {
2714 DRM_ERROR("Failed to terminate rap ta\n");
2715 goto out;
2716 }
2717 ret = psp_securedisplay_terminate(psp);
2718 if (ret) {
2719 DRM_ERROR("Failed to terminate securedisplay ta\n");
2720 goto out;
2721 }
2722 }
2723
2724 ret = psp_asd_terminate(psp);
2725 if (ret) {
2726 DRM_ERROR("Failed to terminate asd\n");
2727 goto out;
2728 }
2729
2730 ret = psp_tmr_terminate(psp);
2731 if (ret) {
2732 DRM_ERROR("Failed to terminate tmr\n");
2733 goto out;
2734 }
2735
2736 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2737 if (ret) {
2738 DRM_ERROR("PSP ring stop failed\n");
2739 }
2740
2741 out:
2742 return ret;
2743 }
2744
psp_resume(void * handle)2745 static int psp_resume(void *handle)
2746 {
2747 int ret;
2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2749 struct psp_context *psp = &adev->psp;
2750
2751 DRM_INFO("PSP is resuming...\n");
2752
2753 if (psp->mem_train_ctx.enable_mem_training) {
2754 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2755 if (ret) {
2756 DRM_ERROR("Failed to process memory training!\n");
2757 return ret;
2758 }
2759 }
2760
2761 mutex_lock(&adev->firmware.mutex);
2762
2763 ret = psp_hw_start(psp);
2764 if (ret)
2765 goto failed;
2766
2767 ret = psp_load_non_psp_fw(psp);
2768 if (ret)
2769 goto failed;
2770
2771 ret = psp_asd_initialize(psp);
2772 if (ret) {
2773 DRM_ERROR("PSP load asd failed!\n");
2774 goto failed;
2775 }
2776
2777 ret = psp_rl_load(adev);
2778 if (ret) {
2779 dev_err(adev->dev, "PSP load RL failed!\n");
2780 goto failed;
2781 }
2782
2783 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2784 ret = psp_xgmi_initialize(psp, false, true);
2785 /* Warning the XGMI seesion initialize failure
2786 * Instead of stop driver initialization
2787 */
2788 if (ret)
2789 dev_err(psp->adev->dev,
2790 "XGMI: Failed to initialize XGMI session\n");
2791 }
2792
2793 if (psp->ta_fw) {
2794 ret = psp_ras_initialize(psp);
2795 if (ret)
2796 dev_err(psp->adev->dev,
2797 "RAS: Failed to initialize RAS\n");
2798
2799 ret = psp_hdcp_initialize(psp);
2800 if (ret)
2801 dev_err(psp->adev->dev,
2802 "HDCP: Failed to initialize HDCP\n");
2803
2804 ret = psp_dtm_initialize(psp);
2805 if (ret)
2806 dev_err(psp->adev->dev,
2807 "DTM: Failed to initialize DTM\n");
2808
2809 ret = psp_rap_initialize(psp);
2810 if (ret)
2811 dev_err(psp->adev->dev,
2812 "RAP: Failed to initialize RAP\n");
2813
2814 ret = psp_securedisplay_initialize(psp);
2815 if (ret)
2816 dev_err(psp->adev->dev,
2817 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2818 }
2819
2820 mutex_unlock(&adev->firmware.mutex);
2821
2822 return 0;
2823
2824 failed:
2825 DRM_ERROR("PSP resume failed\n");
2826 mutex_unlock(&adev->firmware.mutex);
2827 return ret;
2828 }
2829
psp_gpu_reset(struct amdgpu_device * adev)2830 int psp_gpu_reset(struct amdgpu_device *adev)
2831 {
2832 int ret;
2833
2834 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2835 return 0;
2836
2837 mutex_lock(&adev->psp.mutex);
2838 ret = psp_mode1_reset(&adev->psp);
2839 mutex_unlock(&adev->psp.mutex);
2840
2841 return ret;
2842 }
2843
psp_rlc_autoload_start(struct psp_context * psp)2844 int psp_rlc_autoload_start(struct psp_context *psp)
2845 {
2846 int ret;
2847 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2848
2849 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2850
2851 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2852 psp->fence_buf_mc_addr);
2853
2854 release_psp_cmd_buf(psp);
2855
2856 return ret;
2857 }
2858
psp_update_vcn_sram(struct amdgpu_device * adev,int inst_idx,uint64_t cmd_gpu_addr,int cmd_size)2859 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2860 uint64_t cmd_gpu_addr, int cmd_size)
2861 {
2862 struct amdgpu_firmware_info ucode = {0};
2863
2864 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2865 AMDGPU_UCODE_ID_VCN0_RAM;
2866 ucode.mc_addr = cmd_gpu_addr;
2867 ucode.ucode_size = cmd_size;
2868
2869 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2870 }
2871
psp_ring_cmd_submit(struct psp_context * psp,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)2872 int psp_ring_cmd_submit(struct psp_context *psp,
2873 uint64_t cmd_buf_mc_addr,
2874 uint64_t fence_mc_addr,
2875 int index)
2876 {
2877 unsigned int psp_write_ptr_reg = 0;
2878 struct psp_gfx_rb_frame *write_frame;
2879 struct psp_ring *ring = &psp->km_ring;
2880 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2881 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2882 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2883 struct amdgpu_device *adev = psp->adev;
2884 uint32_t ring_size_dw = ring->ring_size / 4;
2885 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2886
2887 /* KM (GPCOM) prepare write pointer */
2888 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2889
2890 /* Update KM RB frame pointer to new frame */
2891 /* write_frame ptr increments by size of rb_frame in bytes */
2892 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2893 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2894 write_frame = ring_buffer_start;
2895 else
2896 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2897 /* Check invalid write_frame ptr address */
2898 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2899 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2900 ring_buffer_start, ring_buffer_end, write_frame);
2901 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2902 return -EINVAL;
2903 }
2904
2905 /* Initialize KM RB frame */
2906 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2907
2908 /* Update KM RB frame */
2909 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2910 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2911 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2912 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2913 write_frame->fence_value = index;
2914 amdgpu_device_flush_hdp(adev, NULL);
2915
2916 /* Update the write Pointer in DWORDs */
2917 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2918 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2919 return 0;
2920 }
2921
psp_init_asd_microcode(struct psp_context * psp,const char * chip_name)2922 int psp_init_asd_microcode(struct psp_context *psp,
2923 const char *chip_name)
2924 {
2925 struct amdgpu_device *adev = psp->adev;
2926 char fw_name[PSP_FW_NAME_LEN];
2927 const struct psp_firmware_header_v1_0 *asd_hdr;
2928 int err = 0;
2929
2930 if (!chip_name) {
2931 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2932 return -EINVAL;
2933 }
2934
2935 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2936 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2937 if (err)
2938 goto out;
2939
2940 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2941 if (err)
2942 goto out;
2943
2944 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2945 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2946 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2947 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2948 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2949 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2950 return 0;
2951 out:
2952 dev_err(adev->dev, "fail to initialize asd microcode\n");
2953 release_firmware(adev->psp.asd_fw);
2954 adev->psp.asd_fw = NULL;
2955 return err;
2956 }
2957
psp_init_toc_microcode(struct psp_context * psp,const char * chip_name)2958 int psp_init_toc_microcode(struct psp_context *psp,
2959 const char *chip_name)
2960 {
2961 struct amdgpu_device *adev = psp->adev;
2962 char fw_name[PSP_FW_NAME_LEN];
2963 const struct psp_firmware_header_v1_0 *toc_hdr;
2964 int err = 0;
2965
2966 if (!chip_name) {
2967 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2968 return -EINVAL;
2969 }
2970
2971 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2972 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2973 if (err)
2974 goto out;
2975
2976 err = amdgpu_ucode_validate(adev->psp.toc_fw);
2977 if (err)
2978 goto out;
2979
2980 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2981 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2982 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2983 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2984 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2985 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2986 return 0;
2987 out:
2988 dev_err(adev->dev, "fail to request/validate toc microcode\n");
2989 release_firmware(adev->psp.toc_fw);
2990 adev->psp.toc_fw = NULL;
2991 return err;
2992 }
2993
parse_sos_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct psp_firmware_header_v2_0 * sos_hdr)2994 static int parse_sos_bin_descriptor(struct psp_context *psp,
2995 const struct psp_fw_bin_desc *desc,
2996 const struct psp_firmware_header_v2_0 *sos_hdr)
2997 {
2998 uint8_t *ucode_start_addr = NULL;
2999
3000 if (!psp || !desc || !sos_hdr)
3001 return -EINVAL;
3002
3003 ucode_start_addr = (uint8_t *)sos_hdr +
3004 le32_to_cpu(desc->offset_bytes) +
3005 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3006
3007 switch (desc->fw_type) {
3008 case PSP_FW_TYPE_PSP_SOS:
3009 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3010 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3011 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3012 psp->sos.start_addr = ucode_start_addr;
3013 break;
3014 case PSP_FW_TYPE_PSP_SYS_DRV:
3015 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3016 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3017 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3018 psp->sys.start_addr = ucode_start_addr;
3019 break;
3020 case PSP_FW_TYPE_PSP_KDB:
3021 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3022 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3023 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3024 psp->kdb.start_addr = ucode_start_addr;
3025 break;
3026 case PSP_FW_TYPE_PSP_TOC:
3027 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3028 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3029 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3030 psp->toc.start_addr = ucode_start_addr;
3031 break;
3032 case PSP_FW_TYPE_PSP_SPL:
3033 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3034 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3035 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3036 psp->spl.start_addr = ucode_start_addr;
3037 break;
3038 case PSP_FW_TYPE_PSP_RL:
3039 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3040 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3041 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3042 psp->rl.start_addr = ucode_start_addr;
3043 break;
3044 case PSP_FW_TYPE_PSP_SOC_DRV:
3045 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3046 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3047 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3048 psp->soc_drv.start_addr = ucode_start_addr;
3049 break;
3050 case PSP_FW_TYPE_PSP_INTF_DRV:
3051 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3052 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3053 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3054 psp->intf_drv.start_addr = ucode_start_addr;
3055 break;
3056 case PSP_FW_TYPE_PSP_DBG_DRV:
3057 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3058 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3059 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3060 psp->dbg_drv.start_addr = ucode_start_addr;
3061 break;
3062 case PSP_FW_TYPE_PSP_RAS_DRV:
3063 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3064 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3065 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3066 psp->ras_drv.start_addr = ucode_start_addr;
3067 break;
3068 default:
3069 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3070 break;
3071 }
3072
3073 return 0;
3074 }
3075
psp_init_sos_base_fw(struct amdgpu_device * adev)3076 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3077 {
3078 const struct psp_firmware_header_v1_0 *sos_hdr;
3079 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3080 uint8_t *ucode_array_start_addr;
3081
3082 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3083 ucode_array_start_addr = (uint8_t *)sos_hdr +
3084 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3085
3086 if (adev->gmc.xgmi.connected_to_cpu ||
3087 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3088 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3089 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3090
3091 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3092 adev->psp.sys.start_addr = ucode_array_start_addr;
3093
3094 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3095 adev->psp.sos.start_addr = ucode_array_start_addr +
3096 le32_to_cpu(sos_hdr->sos.offset_bytes);
3097 } else {
3098 /* Load alternate PSP SOS FW */
3099 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3100
3101 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3102 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3103
3104 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3105 adev->psp.sys.start_addr = ucode_array_start_addr +
3106 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3107
3108 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3109 adev->psp.sos.start_addr = ucode_array_start_addr +
3110 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3111 }
3112
3113 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3114 dev_warn(adev->dev, "PSP SOS FW not available");
3115 return -EINVAL;
3116 }
3117
3118 return 0;
3119 }
3120
psp_init_sos_microcode(struct psp_context * psp,const char * chip_name)3121 int psp_init_sos_microcode(struct psp_context *psp,
3122 const char *chip_name)
3123 {
3124 struct amdgpu_device *adev = psp->adev;
3125 char fw_name[PSP_FW_NAME_LEN];
3126 const struct psp_firmware_header_v1_0 *sos_hdr;
3127 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3128 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3129 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3130 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3131 int err = 0;
3132 uint8_t *ucode_array_start_addr;
3133 int fw_index = 0;
3134
3135 if (!chip_name) {
3136 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3137 return -EINVAL;
3138 }
3139
3140 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3141 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3142 if (err)
3143 goto out;
3144
3145 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3146 if (err)
3147 goto out;
3148
3149 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3150 ucode_array_start_addr = (uint8_t *)sos_hdr +
3151 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3152 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3153
3154 switch (sos_hdr->header.header_version_major) {
3155 case 1:
3156 err = psp_init_sos_base_fw(adev);
3157 if (err)
3158 goto out;
3159
3160 if (sos_hdr->header.header_version_minor == 1) {
3161 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3162 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3163 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3164 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3165 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3166 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3167 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3168 }
3169 if (sos_hdr->header.header_version_minor == 2) {
3170 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3171 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3172 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3173 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3174 }
3175 if (sos_hdr->header.header_version_minor == 3) {
3176 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3177 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3178 adev->psp.toc.start_addr = ucode_array_start_addr +
3179 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3180 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3181 adev->psp.kdb.start_addr = ucode_array_start_addr +
3182 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3183 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3184 adev->psp.spl.start_addr = ucode_array_start_addr +
3185 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3186 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3187 adev->psp.rl.start_addr = ucode_array_start_addr +
3188 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3189 }
3190 break;
3191 case 2:
3192 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3193
3194 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3195 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3196 err = -EINVAL;
3197 goto out;
3198 }
3199
3200 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3201 err = parse_sos_bin_descriptor(psp,
3202 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3203 sos_hdr_v2_0);
3204 if (err)
3205 goto out;
3206 }
3207 break;
3208 default:
3209 dev_err(adev->dev,
3210 "unsupported psp sos firmware\n");
3211 err = -EINVAL;
3212 goto out;
3213 }
3214
3215 return 0;
3216 out:
3217 dev_err(adev->dev,
3218 "failed to init sos firmware\n");
3219 release_firmware(adev->psp.sos_fw);
3220 adev->psp.sos_fw = NULL;
3221
3222 return err;
3223 }
3224
parse_ta_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct ta_firmware_header_v2_0 * ta_hdr)3225 static int parse_ta_bin_descriptor(struct psp_context *psp,
3226 const struct psp_fw_bin_desc *desc,
3227 const struct ta_firmware_header_v2_0 *ta_hdr)
3228 {
3229 uint8_t *ucode_start_addr = NULL;
3230
3231 if (!psp || !desc || !ta_hdr)
3232 return -EINVAL;
3233
3234 ucode_start_addr = (uint8_t *)ta_hdr +
3235 le32_to_cpu(desc->offset_bytes) +
3236 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3237
3238 switch (desc->fw_type) {
3239 case TA_FW_TYPE_PSP_ASD:
3240 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3241 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3242 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3243 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3244 break;
3245 case TA_FW_TYPE_PSP_XGMI:
3246 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3247 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3248 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3249 break;
3250 case TA_FW_TYPE_PSP_RAS:
3251 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3252 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3253 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3254 break;
3255 case TA_FW_TYPE_PSP_HDCP:
3256 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3257 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3258 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3259 break;
3260 case TA_FW_TYPE_PSP_DTM:
3261 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3262 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3263 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3264 break;
3265 case TA_FW_TYPE_PSP_RAP:
3266 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3267 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3268 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3269 break;
3270 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3271 psp->securedisplay_context.context.bin_desc.fw_version =
3272 le32_to_cpu(desc->fw_version);
3273 psp->securedisplay_context.context.bin_desc.size_bytes =
3274 le32_to_cpu(desc->size_bytes);
3275 psp->securedisplay_context.context.bin_desc.start_addr =
3276 ucode_start_addr;
3277 break;
3278 default:
3279 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3280 break;
3281 }
3282
3283 return 0;
3284 }
3285
psp_init_ta_microcode(struct psp_context * psp,const char * chip_name)3286 int psp_init_ta_microcode(struct psp_context *psp,
3287 const char *chip_name)
3288 {
3289 struct amdgpu_device *adev = psp->adev;
3290 char fw_name[PSP_FW_NAME_LEN];
3291 const struct ta_firmware_header_v2_0 *ta_hdr;
3292 int err = 0;
3293 int ta_index = 0;
3294
3295 if (!chip_name) {
3296 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3297 return -EINVAL;
3298 }
3299
3300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3301 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3302 if (err)
3303 goto out;
3304
3305 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3306 if (err)
3307 goto out;
3308
3309 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3310
3311 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3312 dev_err(adev->dev, "unsupported TA header version\n");
3313 err = -EINVAL;
3314 goto out;
3315 }
3316
3317 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3318 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3319 err = -EINVAL;
3320 goto out;
3321 }
3322
3323 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3324 err = parse_ta_bin_descriptor(psp,
3325 &ta_hdr->ta_fw_bin[ta_index],
3326 ta_hdr);
3327 if (err)
3328 goto out;
3329 }
3330
3331 return 0;
3332 out:
3333 dev_err(adev->dev, "fail to initialize ta microcode\n");
3334 release_firmware(adev->psp.ta_fw);
3335 adev->psp.ta_fw = NULL;
3336 return err;
3337 }
3338
psp_init_cap_microcode(struct psp_context * psp,const char * chip_name)3339 int psp_init_cap_microcode(struct psp_context *psp,
3340 const char *chip_name)
3341 {
3342 struct amdgpu_device *adev = psp->adev;
3343 char fw_name[PSP_FW_NAME_LEN];
3344 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3345 struct amdgpu_firmware_info *info = NULL;
3346 int err = 0;
3347
3348 if (!chip_name) {
3349 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3350 return -EINVAL;
3351 }
3352
3353 if (!amdgpu_sriov_vf(adev)) {
3354 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3355 return -EINVAL;
3356 }
3357
3358 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3359 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3360 if (err) {
3361 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3362 err = 0;
3363 goto out;
3364 }
3365
3366 err = amdgpu_ucode_validate(adev->psp.cap_fw);
3367 if (err) {
3368 dev_err(adev->dev, "fail to initialize cap microcode\n");
3369 goto out;
3370 }
3371
3372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3373 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3374 info->fw = adev->psp.cap_fw;
3375 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3376 adev->psp.cap_fw->data;
3377 adev->firmware.fw_size += ALIGN(
3378 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3379 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3380 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3381 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3382
3383 return 0;
3384
3385 out:
3386 release_firmware(adev->psp.cap_fw);
3387 adev->psp.cap_fw = NULL;
3388 return err;
3389 }
3390
psp_set_clockgating_state(void * handle,enum amd_clockgating_state state)3391 static int psp_set_clockgating_state(void *handle,
3392 enum amd_clockgating_state state)
3393 {
3394 return 0;
3395 }
3396
psp_set_powergating_state(void * handle,enum amd_powergating_state state)3397 static int psp_set_powergating_state(void *handle,
3398 enum amd_powergating_state state)
3399 {
3400 return 0;
3401 }
3402
psp_usbc_pd_fw_sysfs_read(struct device * dev,struct device_attribute * attr,char * buf)3403 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3404 struct device_attribute *attr,
3405 char *buf)
3406 {
3407 struct drm_device *ddev = dev_get_drvdata(dev);
3408 struct amdgpu_device *adev = drm_to_adev(ddev);
3409 uint32_t fw_ver;
3410 int ret;
3411
3412 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3413 DRM_INFO("PSP block is not ready yet.");
3414 return -EBUSY;
3415 }
3416
3417 mutex_lock(&adev->psp.mutex);
3418 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3419 mutex_unlock(&adev->psp.mutex);
3420
3421 if (ret) {
3422 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3423 return ret;
3424 }
3425
3426 return sysfs_emit(buf, "%x\n", fw_ver);
3427 }
3428
psp_usbc_pd_fw_sysfs_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3429 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3430 struct device_attribute *attr,
3431 const char *buf,
3432 size_t count)
3433 {
3434 struct drm_device *ddev = dev_get_drvdata(dev);
3435 struct amdgpu_device *adev = drm_to_adev(ddev);
3436 int ret, idx;
3437 char fw_name[100];
3438 const struct firmware *usbc_pd_fw;
3439 struct amdgpu_bo *fw_buf_bo = NULL;
3440 uint64_t fw_pri_mc_addr;
3441 void *fw_pri_cpu_addr;
3442
3443 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3444 DRM_INFO("PSP block is not ready yet.");
3445 return -EBUSY;
3446 }
3447
3448 if (!drm_dev_enter(ddev, &idx))
3449 return -ENODEV;
3450
3451 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3452 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3453 if (ret)
3454 goto fail;
3455
3456 /* LFB address which is aligned to 1MB boundary per PSP request */
3457 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3458 AMDGPU_GEM_DOMAIN_VRAM,
3459 &fw_buf_bo,
3460 &fw_pri_mc_addr,
3461 &fw_pri_cpu_addr);
3462 if (ret)
3463 goto rel_buf;
3464
3465 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3466
3467 mutex_lock(&adev->psp.mutex);
3468 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3469 mutex_unlock(&adev->psp.mutex);
3470
3471 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3472
3473 rel_buf:
3474 release_firmware(usbc_pd_fw);
3475 fail:
3476 if (ret) {
3477 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3478 count = ret;
3479 }
3480
3481 drm_dev_exit(idx);
3482 return count;
3483 }
3484
psp_copy_fw(struct psp_context * psp,uint8_t * start_addr,uint32_t bin_size)3485 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3486 {
3487 int idx;
3488
3489 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3490 return;
3491
3492 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3493 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3494
3495 drm_dev_exit(idx);
3496 }
3497
3498 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3499 psp_usbc_pd_fw_sysfs_read,
3500 psp_usbc_pd_fw_sysfs_write);
3501
is_psp_fw_valid(struct psp_bin_desc bin)3502 int is_psp_fw_valid(struct psp_bin_desc bin)
3503 {
3504 return bin.size_bytes;
3505 }
3506
amdgpu_psp_vbflash_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)3507 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3508 struct bin_attribute *bin_attr,
3509 char *buffer, loff_t pos, size_t count)
3510 {
3511 struct device *dev = kobj_to_dev(kobj);
3512 struct drm_device *ddev = dev_get_drvdata(dev);
3513 struct amdgpu_device *adev = drm_to_adev(ddev);
3514
3515 adev->psp.vbflash_done = false;
3516
3517 /* Safeguard against memory drain */
3518 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3519 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3520 kvfree(adev->psp.vbflash_tmp_buf);
3521 adev->psp.vbflash_tmp_buf = NULL;
3522 adev->psp.vbflash_image_size = 0;
3523 return -ENOMEM;
3524 }
3525
3526 /* TODO Just allocate max for now and optimize to realloc later if needed */
3527 if (!adev->psp.vbflash_tmp_buf) {
3528 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3529 if (!adev->psp.vbflash_tmp_buf)
3530 return -ENOMEM;
3531 }
3532
3533 mutex_lock(&adev->psp.mutex);
3534 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3535 adev->psp.vbflash_image_size += count;
3536 mutex_unlock(&adev->psp.mutex);
3537
3538 dev_info(adev->dev, "VBIOS flash write PSP done");
3539
3540 return count;
3541 }
3542
amdgpu_psp_vbflash_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)3543 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3544 struct bin_attribute *bin_attr, char *buffer,
3545 loff_t pos, size_t count)
3546 {
3547 struct device *dev = kobj_to_dev(kobj);
3548 struct drm_device *ddev = dev_get_drvdata(dev);
3549 struct amdgpu_device *adev = drm_to_adev(ddev);
3550 struct amdgpu_bo *fw_buf_bo = NULL;
3551 uint64_t fw_pri_mc_addr;
3552 void *fw_pri_cpu_addr;
3553 int ret;
3554
3555 if (adev->psp.vbflash_image_size == 0)
3556 return -EINVAL;
3557
3558 dev_info(adev->dev, "VBIOS flash to PSP started");
3559
3560 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3561 AMDGPU_GPU_PAGE_SIZE,
3562 AMDGPU_GEM_DOMAIN_VRAM,
3563 &fw_buf_bo,
3564 &fw_pri_mc_addr,
3565 &fw_pri_cpu_addr);
3566 if (ret)
3567 goto rel_buf;
3568
3569 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3570
3571 mutex_lock(&adev->psp.mutex);
3572 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3573 mutex_unlock(&adev->psp.mutex);
3574
3575 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3576
3577 rel_buf:
3578 kvfree(adev->psp.vbflash_tmp_buf);
3579 adev->psp.vbflash_tmp_buf = NULL;
3580 adev->psp.vbflash_image_size = 0;
3581
3582 if (ret) {
3583 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3584 return ret;
3585 }
3586
3587 dev_info(adev->dev, "VBIOS flash to PSP done");
3588 return 0;
3589 }
3590
amdgpu_psp_vbflash_status(struct device * dev,struct device_attribute * attr,char * buf)3591 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3592 struct device_attribute *attr,
3593 char *buf)
3594 {
3595 struct drm_device *ddev = dev_get_drvdata(dev);
3596 struct amdgpu_device *adev = drm_to_adev(ddev);
3597 uint32_t vbflash_status;
3598
3599 vbflash_status = psp_vbflash_status(&adev->psp);
3600 if (!adev->psp.vbflash_done)
3601 vbflash_status = 0;
3602 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3603 vbflash_status = 1;
3604
3605 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3606 }
3607
3608 static const struct bin_attribute psp_vbflash_bin_attr = {
3609 .attr = {.name = "psp_vbflash", .mode = 0660},
3610 .size = 0,
3611 .write = amdgpu_psp_vbflash_write,
3612 .read = amdgpu_psp_vbflash_read,
3613 };
3614
3615 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3616
amdgpu_psp_sysfs_init(struct amdgpu_device * adev)3617 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3618 {
3619 int ret = 0;
3620 struct psp_context *psp = &adev->psp;
3621
3622 if (amdgpu_sriov_vf(adev))
3623 return -EINVAL;
3624
3625 switch (adev->ip_versions[MP0_HWIP][0]) {
3626 case IP_VERSION(13, 0, 0):
3627 case IP_VERSION(13, 0, 7):
3628 if (!psp->adev) {
3629 psp->adev = adev;
3630 psp_v13_0_set_psp_funcs(psp);
3631 }
3632 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3633 if (ret)
3634 dev_err(adev->dev, "Failed to create device file psp_vbflash");
3635 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3636 if (ret)
3637 dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3638 return ret;
3639 default:
3640 return 0;
3641 }
3642 }
3643
3644 const struct amd_ip_funcs psp_ip_funcs = {
3645 .name = "psp",
3646 .early_init = psp_early_init,
3647 .late_init = NULL,
3648 .sw_init = psp_sw_init,
3649 .sw_fini = psp_sw_fini,
3650 .hw_init = psp_hw_init,
3651 .hw_fini = psp_hw_fini,
3652 .suspend = psp_suspend,
3653 .resume = psp_resume,
3654 .is_idle = NULL,
3655 .check_soft_reset = NULL,
3656 .wait_for_idle = NULL,
3657 .soft_reset = NULL,
3658 .set_clockgating_state = psp_set_clockgating_state,
3659 .set_powergating_state = psp_set_powergating_state,
3660 };
3661
psp_sysfs_init(struct amdgpu_device * adev)3662 static int psp_sysfs_init(struct amdgpu_device *adev)
3663 {
3664 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3665
3666 if (ret)
3667 DRM_ERROR("Failed to create USBC PD FW control file!");
3668
3669 return ret;
3670 }
3671
amdgpu_psp_sysfs_fini(struct amdgpu_device * adev)3672 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3673 {
3674 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3675 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3676 }
3677
psp_sysfs_fini(struct amdgpu_device * adev)3678 static void psp_sysfs_fini(struct amdgpu_device *adev)
3679 {
3680 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3681 }
3682
3683 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3684 {
3685 .type = AMD_IP_BLOCK_TYPE_PSP,
3686 .major = 3,
3687 .minor = 1,
3688 .rev = 0,
3689 .funcs = &psp_ip_funcs,
3690 };
3691
3692 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3693 {
3694 .type = AMD_IP_BLOCK_TYPE_PSP,
3695 .major = 10,
3696 .minor = 0,
3697 .rev = 0,
3698 .funcs = &psp_ip_funcs,
3699 };
3700
3701 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3702 {
3703 .type = AMD_IP_BLOCK_TYPE_PSP,
3704 .major = 11,
3705 .minor = 0,
3706 .rev = 0,
3707 .funcs = &psp_ip_funcs,
3708 };
3709
3710 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3711 .type = AMD_IP_BLOCK_TYPE_PSP,
3712 .major = 11,
3713 .minor = 0,
3714 .rev = 8,
3715 .funcs = &psp_ip_funcs,
3716 };
3717
3718 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3719 {
3720 .type = AMD_IP_BLOCK_TYPE_PSP,
3721 .major = 12,
3722 .minor = 0,
3723 .rev = 0,
3724 .funcs = &psp_ip_funcs,
3725 };
3726
3727 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3728 .type = AMD_IP_BLOCK_TYPE_PSP,
3729 .major = 13,
3730 .minor = 0,
3731 .rev = 0,
3732 .funcs = &psp_ip_funcs,
3733 };
3734
3735 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3736 .type = AMD_IP_BLOCK_TYPE_PSP,
3737 .major = 13,
3738 .minor = 0,
3739 .rev = 4,
3740 .funcs = &psp_ip_funcs,
3741 };
3742