1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * QUICC Engine GPIOs
4 *
5 * Copyright (c) MontaVista Software, Inc. 2008.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/spinlock.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/gpio/driver.h>
18 /* FIXME: needed for gpio_to_chip() get rid of this */
19 #include <linux/gpio.h>
20 #include <linux/slab.h>
21 #include <linux/export.h>
22 #include <soc/fsl/qe/qe.h>
23
24 struct qe_gpio_chip {
25 struct of_mm_gpio_chip mm_gc;
26 spinlock_t lock;
27
28 unsigned long pin_flags[QE_PIO_PINS];
29 #define QE_PIN_REQUESTED 0
30
31 /* shadowed data register to clear/set bits safely */
32 u32 cpdata;
33
34 /* saved_regs used to restore dedicated functions */
35 struct qe_pio_regs saved_regs;
36 };
37
qe_gpio_save_regs(struct of_mm_gpio_chip * mm_gc)38 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
39 {
40 struct qe_gpio_chip *qe_gc =
41 container_of(mm_gc, struct qe_gpio_chip, mm_gc);
42 struct qe_pio_regs __iomem *regs = mm_gc->regs;
43
44 qe_gc->cpdata = ioread32be(®s->cpdata);
45 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
46 qe_gc->saved_regs.cpdir1 = ioread32be(®s->cpdir1);
47 qe_gc->saved_regs.cpdir2 = ioread32be(®s->cpdir2);
48 qe_gc->saved_regs.cppar1 = ioread32be(®s->cppar1);
49 qe_gc->saved_regs.cppar2 = ioread32be(®s->cppar2);
50 qe_gc->saved_regs.cpodr = ioread32be(®s->cpodr);
51 }
52
qe_gpio_get(struct gpio_chip * gc,unsigned int gpio)53 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
54 {
55 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
56 struct qe_pio_regs __iomem *regs = mm_gc->regs;
57 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
58
59 return !!(ioread32be(®s->cpdata) & pin_mask);
60 }
61
qe_gpio_set(struct gpio_chip * gc,unsigned int gpio,int val)62 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
63 {
64 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
65 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
66 struct qe_pio_regs __iomem *regs = mm_gc->regs;
67 unsigned long flags;
68 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
69
70 spin_lock_irqsave(&qe_gc->lock, flags);
71
72 if (val)
73 qe_gc->cpdata |= pin_mask;
74 else
75 qe_gc->cpdata &= ~pin_mask;
76
77 iowrite32be(qe_gc->cpdata, ®s->cpdata);
78
79 spin_unlock_irqrestore(&qe_gc->lock, flags);
80 }
81
qe_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)82 static void qe_gpio_set_multiple(struct gpio_chip *gc,
83 unsigned long *mask, unsigned long *bits)
84 {
85 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
86 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
87 struct qe_pio_regs __iomem *regs = mm_gc->regs;
88 unsigned long flags;
89 int i;
90
91 spin_lock_irqsave(&qe_gc->lock, flags);
92
93 for (i = 0; i < gc->ngpio; i++) {
94 if (*mask == 0)
95 break;
96 if (__test_and_clear_bit(i, mask)) {
97 if (test_bit(i, bits))
98 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
99 else
100 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
101 }
102 }
103
104 iowrite32be(qe_gc->cpdata, ®s->cpdata);
105
106 spin_unlock_irqrestore(&qe_gc->lock, flags);
107 }
108
qe_gpio_dir_in(struct gpio_chip * gc,unsigned int gpio)109 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
110 {
111 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
112 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
113 unsigned long flags;
114
115 spin_lock_irqsave(&qe_gc->lock, flags);
116
117 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
118
119 spin_unlock_irqrestore(&qe_gc->lock, flags);
120
121 return 0;
122 }
123
qe_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)124 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
125 {
126 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
127 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
128 unsigned long flags;
129
130 qe_gpio_set(gc, gpio, val);
131
132 spin_lock_irqsave(&qe_gc->lock, flags);
133
134 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
135
136 spin_unlock_irqrestore(&qe_gc->lock, flags);
137
138 return 0;
139 }
140
141 struct qe_pin {
142 /*
143 * The qe_gpio_chip name is unfortunate, we should change that to
144 * something like qe_pio_controller. Someday.
145 */
146 struct qe_gpio_chip *controller;
147 int num;
148 };
149
150 /**
151 * qe_pin_request - Request a QE pin
152 * @np: device node to get a pin from
153 * @index: index of a pin in the device tree
154 * Context: non-atomic
155 *
156 * This function return qe_pin so that you could use it with the rest of
157 * the QE Pin Multiplexing API.
158 */
qe_pin_request(struct device_node * np,int index)159 struct qe_pin *qe_pin_request(struct device_node *np, int index)
160 {
161 struct qe_pin *qe_pin;
162 struct gpio_chip *gc;
163 struct qe_gpio_chip *qe_gc;
164 int err;
165 unsigned long flags;
166
167 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
168 if (!qe_pin) {
169 pr_debug("%s: can't allocate memory\n", __func__);
170 return ERR_PTR(-ENOMEM);
171 }
172
173 err = of_get_gpio(np, index);
174 if (err < 0)
175 goto err0;
176 gc = gpio_to_chip(err);
177 if (WARN_ON(!gc)) {
178 err = -ENODEV;
179 goto err0;
180 }
181
182 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
183 pr_debug("%s: tried to get a non-qe pin\n", __func__);
184 err = -EINVAL;
185 goto err0;
186 }
187
188 qe_gc = gpiochip_get_data(gc);
189
190 spin_lock_irqsave(&qe_gc->lock, flags);
191
192 err -= gc->base;
193 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
194 qe_pin->controller = qe_gc;
195 qe_pin->num = err;
196 err = 0;
197 } else {
198 err = -EBUSY;
199 }
200
201 spin_unlock_irqrestore(&qe_gc->lock, flags);
202
203 if (!err)
204 return qe_pin;
205 err0:
206 kfree(qe_pin);
207 pr_debug("%s failed with status %d\n", __func__, err);
208 return ERR_PTR(err);
209 }
210 EXPORT_SYMBOL(qe_pin_request);
211
212 /**
213 * qe_pin_free - Free a pin
214 * @qe_pin: pointer to the qe_pin structure
215 * Context: any
216 *
217 * This function frees the qe_pin structure and makes a pin available
218 * for further qe_pin_request() calls.
219 */
qe_pin_free(struct qe_pin * qe_pin)220 void qe_pin_free(struct qe_pin *qe_pin)
221 {
222 struct qe_gpio_chip *qe_gc = qe_pin->controller;
223 unsigned long flags;
224 const int pin = qe_pin->num;
225
226 spin_lock_irqsave(&qe_gc->lock, flags);
227 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
228 spin_unlock_irqrestore(&qe_gc->lock, flags);
229
230 kfree(qe_pin);
231 }
232 EXPORT_SYMBOL(qe_pin_free);
233
234 /**
235 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
236 * @qe_pin: pointer to the qe_pin structure
237 * Context: any
238 *
239 * This function resets a pin to a dedicated peripheral function that
240 * has been set up by the firmware.
241 */
qe_pin_set_dedicated(struct qe_pin * qe_pin)242 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
243 {
244 struct qe_gpio_chip *qe_gc = qe_pin->controller;
245 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
246 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
247 int pin = qe_pin->num;
248 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
249 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
250 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
251 unsigned long flags;
252
253 spin_lock_irqsave(&qe_gc->lock, flags);
254
255 if (second_reg) {
256 qe_clrsetbits_be32(®s->cpdir2, mask2,
257 sregs->cpdir2 & mask2);
258 qe_clrsetbits_be32(®s->cppar2, mask2,
259 sregs->cppar2 & mask2);
260 } else {
261 qe_clrsetbits_be32(®s->cpdir1, mask2,
262 sregs->cpdir1 & mask2);
263 qe_clrsetbits_be32(®s->cppar1, mask2,
264 sregs->cppar1 & mask2);
265 }
266
267 if (sregs->cpdata & mask1)
268 qe_gc->cpdata |= mask1;
269 else
270 qe_gc->cpdata &= ~mask1;
271
272 iowrite32be(qe_gc->cpdata, ®s->cpdata);
273 qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
274
275 spin_unlock_irqrestore(&qe_gc->lock, flags);
276 }
277 EXPORT_SYMBOL(qe_pin_set_dedicated);
278
279 /**
280 * qe_pin_set_gpio - Set a pin to the GPIO mode
281 * @qe_pin: pointer to the qe_pin structure
282 * Context: any
283 *
284 * This function sets a pin to the GPIO mode.
285 */
qe_pin_set_gpio(struct qe_pin * qe_pin)286 void qe_pin_set_gpio(struct qe_pin *qe_pin)
287 {
288 struct qe_gpio_chip *qe_gc = qe_pin->controller;
289 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
290 unsigned long flags;
291
292 spin_lock_irqsave(&qe_gc->lock, flags);
293
294 /* Let's make it input by default, GPIO API is able to change that. */
295 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
296
297 spin_unlock_irqrestore(&qe_gc->lock, flags);
298 }
299 EXPORT_SYMBOL(qe_pin_set_gpio);
300
qe_add_gpiochips(void)301 static int __init qe_add_gpiochips(void)
302 {
303 struct device_node *np;
304
305 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
306 int ret;
307 struct qe_gpio_chip *qe_gc;
308 struct of_mm_gpio_chip *mm_gc;
309 struct gpio_chip *gc;
310
311 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
312 if (!qe_gc) {
313 ret = -ENOMEM;
314 goto err;
315 }
316
317 spin_lock_init(&qe_gc->lock);
318
319 mm_gc = &qe_gc->mm_gc;
320 gc = &mm_gc->gc;
321
322 mm_gc->save_regs = qe_gpio_save_regs;
323 gc->ngpio = QE_PIO_PINS;
324 gc->direction_input = qe_gpio_dir_in;
325 gc->direction_output = qe_gpio_dir_out;
326 gc->get = qe_gpio_get;
327 gc->set = qe_gpio_set;
328 gc->set_multiple = qe_gpio_set_multiple;
329
330 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
331 if (ret)
332 goto err;
333 continue;
334 err:
335 pr_err("%pOF: registration failed with status %d\n",
336 np, ret);
337 kfree(qe_gc);
338 /* try others anyway */
339 }
340 return 0;
341 }
342 arch_initcall(qe_add_gpiochips);
343