1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_device.h>
30 #include <drm/radeon_drm.h>
31
32 #include "radeon.h"
33
34 #include "atom.h"
35 #include "atom-bits.h"
36 #include "radeon_asic.h"
37 #include "radeon_atombios.h"
38 #include "radeon_legacy_encoders.h"
39
40 union atom_supported_devices {
41 struct _ATOM_SUPPORTED_DEVICES_INFO info;
42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
44 };
45
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
47 ATOM_GPIO_I2C_ASSIGMENT *gpio,
48 u8 index)
49 {
50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
51 if ((rdev->family == CHIP_R420) ||
52 (rdev->family == CHIP_R423) ||
53 (rdev->family == CHIP_RV410)) {
54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
57 gpio->ucClkMaskShift = 0x19;
58 gpio->ucDataMaskShift = 0x18;
59 }
60 }
61
62 /* some evergreen boards have bad data for this entry */
63 if (ASIC_IS_DCE4(rdev)) {
64 if ((index == 7) &&
65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
66 (gpio->sucI2cId.ucAccess == 0)) {
67 gpio->sucI2cId.ucAccess = 0x97;
68 gpio->ucDataMaskShift = 8;
69 gpio->ucDataEnShift = 8;
70 gpio->ucDataY_Shift = 8;
71 gpio->ucDataA_Shift = 8;
72 }
73 }
74
75 /* some DCE3 boards have bad data for this entry */
76 if (ASIC_IS_DCE3(rdev)) {
77 if ((index == 4) &&
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
79 (gpio->sucI2cId.ucAccess == 0x94))
80 gpio->sucI2cId.ucAccess = 0x14;
81 }
82 }
83
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
85 {
86 struct radeon_i2c_bus_rec i2c;
87
88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
89
90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
101 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
106
107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
108 i2c.hw_capable = true;
109 else
110 i2c.hw_capable = false;
111
112 if (gpio->sucI2cId.ucAccess == 0xa0)
113 i2c.mm_i2c = true;
114 else
115 i2c.mm_i2c = false;
116
117 i2c.i2c_id = gpio->sucI2cId.ucAccess;
118
119 if (i2c.mask_clk_reg)
120 i2c.valid = true;
121 else
122 i2c.valid = false;
123
124 return i2c;
125 }
126
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
128 uint8_t id)
129 {
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137
138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
139 i2c.valid = false;
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 gpio = &i2c_info->asGPIO_Info[0];
148 for (i = 0; i < num_indices; i++) {
149
150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
151
152 if (gpio->sucI2cId.ucAccess == id) {
153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
154 break;
155 }
156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
158 }
159 }
160
161 return i2c;
162 }
163
radeon_atombios_i2c_init(struct radeon_device * rdev)164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
165 {
166 struct atom_context *ctx = rdev->mode_info.atom_context;
167 ATOM_GPIO_I2C_ASSIGMENT *gpio;
168 struct radeon_i2c_bus_rec i2c;
169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
170 struct _ATOM_GPIO_I2C_INFO *i2c_info;
171 uint16_t data_offset, size;
172 int i, num_indices;
173 char stmp[32];
174
175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
177
178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
179 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
180
181 gpio = &i2c_info->asGPIO_Info[0];
182 for (i = 0; i < num_indices; i++) {
183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
184
185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
186
187 if (i2c.valid) {
188 sprintf(stmp, "0x%x", i2c.i2c_id);
189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
190 }
191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
193 }
194 }
195 }
196
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
198 u8 id)
199 {
200 struct atom_context *ctx = rdev->mode_info.atom_context;
201 struct radeon_gpio_rec gpio;
202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
203 struct _ATOM_GPIO_PIN_LUT *gpio_info;
204 ATOM_GPIO_PIN_ASSIGNMENT *pin;
205 u16 data_offset, size;
206 int i, num_indices;
207
208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
209 gpio.valid = false;
210
211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
213
214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
216
217 pin = gpio_info->asGPIO_Pin;
218 for (i = 0; i < num_indices; i++) {
219 if (id == pin->ucGPIO_ID) {
220 gpio.id = pin->ucGPIO_ID;
221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
222 gpio.shift = pin->ucGpioPinBitShift;
223 gpio.mask = (1 << pin->ucGpioPinBitShift);
224 gpio.valid = true;
225 break;
226 }
227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
229 }
230 }
231
232 return gpio;
233 }
234
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
236 struct radeon_gpio_rec *gpio)
237 {
238 struct radeon_hpd hpd;
239 u32 reg;
240
241 memset(&hpd, 0, sizeof(struct radeon_hpd));
242
243 if (ASIC_IS_DCE6(rdev))
244 reg = SI_DC_GPIO_HPD_A;
245 else if (ASIC_IS_DCE4(rdev))
246 reg = EVERGREEN_DC_GPIO_HPD_A;
247 else
248 reg = AVIVO_DC_GPIO_HPD_A;
249
250 hpd.gpio = *gpio;
251 if (gpio->reg == reg) {
252 switch(gpio->mask) {
253 case (1 << 0):
254 hpd.hpd = RADEON_HPD_1;
255 break;
256 case (1 << 8):
257 hpd.hpd = RADEON_HPD_2;
258 break;
259 case (1 << 16):
260 hpd.hpd = RADEON_HPD_3;
261 break;
262 case (1 << 24):
263 hpd.hpd = RADEON_HPD_4;
264 break;
265 case (1 << 26):
266 hpd.hpd = RADEON_HPD_5;
267 break;
268 case (1 << 28):
269 hpd.hpd = RADEON_HPD_6;
270 break;
271 default:
272 hpd.hpd = RADEON_HPD_NONE;
273 break;
274 }
275 } else
276 hpd.hpd = RADEON_HPD_NONE;
277 return hpd;
278 }
279
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
281 uint32_t supported_device,
282 int *connector_type,
283 struct radeon_i2c_bus_rec *i2c_bus,
284 uint16_t *line_mux,
285 struct radeon_hpd *hpd)
286 {
287 struct pci_dev *pdev = to_pci_dev(dev->dev);
288
289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
290 if ((pdev->device == 0x791e) &&
291 (pdev->subsystem_vendor == 0x1043) &&
292 (pdev->subsystem_device == 0x826d)) {
293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
295 *connector_type = DRM_MODE_CONNECTOR_DVID;
296 }
297
298 /* Asrock RS600 board lists the DVI port as HDMI */
299 if ((pdev->device == 0x7941) &&
300 (pdev->subsystem_vendor == 0x1849) &&
301 (pdev->subsystem_device == 0x7941)) {
302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
304 *connector_type = DRM_MODE_CONNECTOR_DVID;
305 }
306
307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
308 if ((pdev->device == 0x796e) &&
309 (pdev->subsystem_vendor == 0x1462) &&
310 (pdev->subsystem_device == 0x7302)) {
311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
313 return false;
314 }
315
316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
317 if ((pdev->device == 0x7941) &&
318 (pdev->subsystem_vendor == 0x147b) &&
319 (pdev->subsystem_device == 0x2412)) {
320 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
321 return false;
322 }
323
324 /* Falcon NW laptop lists vga ddc line for LVDS */
325 if ((pdev->device == 0x5653) &&
326 (pdev->subsystem_vendor == 0x1462) &&
327 (pdev->subsystem_device == 0x0291)) {
328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
329 i2c_bus->valid = false;
330 *line_mux = 53;
331 }
332 }
333
334 /* HIS X1300 is DVI+VGA, not DVI+DVI */
335 if ((pdev->device == 0x7146) &&
336 (pdev->subsystem_vendor == 0x17af) &&
337 (pdev->subsystem_device == 0x2058)) {
338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
339 return false;
340 }
341
342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
343 if ((pdev->device == 0x7142) &&
344 (pdev->subsystem_vendor == 0x1458) &&
345 (pdev->subsystem_device == 0x2134)) {
346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
347 return false;
348 }
349
350
351 /* Funky macbooks */
352 if ((pdev->device == 0x71C5) &&
353 (pdev->subsystem_vendor == 0x106b) &&
354 (pdev->subsystem_device == 0x0080)) {
355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
357 return false;
358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
359 *line_mux = 0x90;
360 }
361
362 /* mac rv630, rv730, others */
363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
367 }
368
369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
370 if ((pdev->device == 0x9598) &&
371 (pdev->subsystem_vendor == 0x1043) &&
372 (pdev->subsystem_device == 0x01da)) {
373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
374 *connector_type = DRM_MODE_CONNECTOR_DVII;
375 }
376 }
377
378 /* ASUS HD 3600 board lists the DVI port as HDMI */
379 if ((pdev->device == 0x9598) &&
380 (pdev->subsystem_vendor == 0x1043) &&
381 (pdev->subsystem_device == 0x01e4)) {
382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
383 *connector_type = DRM_MODE_CONNECTOR_DVII;
384 }
385 }
386
387 /* ASUS HD 3450 board lists the DVI port as HDMI */
388 if ((pdev->device == 0x95C5) &&
389 (pdev->subsystem_vendor == 0x1043) &&
390 (pdev->subsystem_device == 0x01e2)) {
391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
392 *connector_type = DRM_MODE_CONNECTOR_DVII;
393 }
394 }
395
396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
397 * HDMI + VGA reporting as HDMI
398 */
399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
401 *connector_type = DRM_MODE_CONNECTOR_VGA;
402 *line_mux = 0;
403 }
404 }
405
406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
407 * on the laptop and a DVI port on the docking station and
408 * both share the same encoder, hpd pin, and ddc line.
409 * So while the bios table is technically correct,
410 * we drop the DVI port here since xrandr has no concept of
411 * encoders and will try and drive both connectors
412 * with different crtcs which isn't possible on the hardware
413 * side and leaves no crtcs for LVDS or VGA.
414 */
415 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
416 (pdev->subsystem_vendor == 0x1025) &&
417 (pdev->subsystem_device == 0x013c)) {
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 /* actually it's a DVI-D port not DVI-I */
421 *connector_type = DRM_MODE_CONNECTOR_DVID;
422 return false;
423 }
424 }
425
426 /* XFX Pine Group device rv730 reports no VGA DDC lines
427 * even though they are wired up to record 0x93
428 */
429 if ((pdev->device == 0x9498) &&
430 (pdev->subsystem_vendor == 0x1682) &&
431 (pdev->subsystem_device == 0x2452) &&
432 (i2c_bus->valid == false) &&
433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
436 }
437
438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
439 if (((pdev->device == 0x9802) ||
440 (pdev->device == 0x9805) ||
441 (pdev->device == 0x9806)) &&
442 (pdev->subsystem_vendor == 0x1734) &&
443 (pdev->subsystem_device == 0x11bd)) {
444 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
445 *connector_type = DRM_MODE_CONNECTOR_DVII;
446 *line_mux = 0x3103;
447 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
448 *connector_type = DRM_MODE_CONNECTOR_DVII;
449 }
450 }
451
452 return true;
453 }
454
455 static const int supported_devices_connector_convert[] = {
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_VGA,
458 DRM_MODE_CONNECTOR_DVII,
459 DRM_MODE_CONNECTOR_DVID,
460 DRM_MODE_CONNECTOR_DVIA,
461 DRM_MODE_CONNECTOR_SVIDEO,
462 DRM_MODE_CONNECTOR_Composite,
463 DRM_MODE_CONNECTOR_LVDS,
464 DRM_MODE_CONNECTOR_Unknown,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_HDMIA,
467 DRM_MODE_CONNECTOR_HDMIB,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_9PinDIN,
471 DRM_MODE_CONNECTOR_DisplayPort
472 };
473
474 static const uint16_t supported_devices_connector_object_id_convert[] = {
475 CONNECTOR_OBJECT_ID_NONE,
476 CONNECTOR_OBJECT_ID_VGA,
477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
480 CONNECTOR_OBJECT_ID_COMPOSITE,
481 CONNECTOR_OBJECT_ID_SVIDEO,
482 CONNECTOR_OBJECT_ID_LVDS,
483 CONNECTOR_OBJECT_ID_9PIN_DIN,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_DISPLAYPORT,
486 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
488 CONNECTOR_OBJECT_ID_SVIDEO
489 };
490
491 static const int object_connector_convert[] = {
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_DVII,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVID,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_VGA,
498 DRM_MODE_CONNECTOR_Composite,
499 DRM_MODE_CONNECTOR_SVIDEO,
500 DRM_MODE_CONNECTOR_Unknown,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_9PinDIN,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_HDMIA,
505 DRM_MODE_CONNECTOR_HDMIB,
506 DRM_MODE_CONNECTOR_LVDS,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_DisplayPort,
512 DRM_MODE_CONNECTOR_eDP,
513 DRM_MODE_CONNECTOR_Unknown
514 };
515
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
517 {
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_mode_info *mode_info = &rdev->mode_info;
520 struct atom_context *ctx = mode_info->atom_context;
521 int index = GetIndexIntoMasterTable(DATA, Object_Header);
522 u16 size, data_offset;
523 u8 frev, crev;
524 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
525 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
526 ATOM_OBJECT_TABLE *router_obj;
527 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
528 ATOM_OBJECT_HEADER *obj_header;
529 int i, j, k, path_size, device_support;
530 int connector_type;
531 u16 igp_lane_info, conn_id, connector_object_id;
532 struct radeon_i2c_bus_rec ddc_bus;
533 struct radeon_router router;
534 struct radeon_gpio_rec gpio;
535 struct radeon_hpd hpd;
536
537 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
538 return false;
539
540 if (crev < 2)
541 return false;
542
543 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
544 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
545 (ctx->bios + data_offset +
546 le16_to_cpu(obj_header->usDisplayPathTableOffset));
547 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
548 (ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
550 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
551 (ctx->bios + data_offset +
552 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
553 router_obj = (ATOM_OBJECT_TABLE *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(obj_header->usRouterObjectTableOffset));
556 device_support = le16_to_cpu(obj_header->usDeviceSupport);
557
558 path_size = 0;
559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
560 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
561 ATOM_DISPLAY_OBJECT_PATH *path;
562 addr += path_size;
563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
564 path_size += le16_to_cpu(path->usSize);
565
566 if (device_support & le16_to_cpu(path->usDeviceTag)) {
567 uint8_t con_obj_id, con_obj_num;
568
569 con_obj_id =
570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
571 >> OBJECT_ID_SHIFT;
572 con_obj_num =
573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
574 >> ENUM_ID_SHIFT;
575
576 /* TODO CV support */
577 if (le16_to_cpu(path->usDeviceTag) ==
578 ATOM_DEVICE_CV_SUPPORT)
579 continue;
580
581 /* IGP chips */
582 if ((rdev->flags & RADEON_IS_IGP) &&
583 (con_obj_id ==
584 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
585 uint16_t igp_offset = 0;
586 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
587
588 index =
589 GetIndexIntoMasterTable(DATA,
590 IntegratedSystemInfo);
591
592 if (atom_parse_data_header(ctx, index, &size, &frev,
593 &crev, &igp_offset)) {
594
595 if (crev >= 2) {
596 igp_obj =
597 (ATOM_INTEGRATED_SYSTEM_INFO_V2
598 *) (ctx->bios + igp_offset);
599
600 if (igp_obj) {
601 uint32_t slot_config, ct;
602
603 if (con_obj_num == 1)
604 slot_config =
605 igp_obj->
606 ulDDISlot1Config;
607 else
608 slot_config =
609 igp_obj->
610 ulDDISlot2Config;
611
612 ct = (slot_config >> 16) & 0xff;
613 connector_type =
614 object_connector_convert
615 [ct];
616 connector_object_id = ct;
617 igp_lane_info =
618 slot_config & 0xffff;
619 } else
620 continue;
621 } else
622 continue;
623 } else {
624 igp_lane_info = 0;
625 connector_type =
626 object_connector_convert[con_obj_id];
627 connector_object_id = con_obj_id;
628 }
629 } else {
630 igp_lane_info = 0;
631 connector_type =
632 object_connector_convert[con_obj_id];
633 connector_object_id = con_obj_id;
634 }
635
636 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
637 continue;
638
639 router.ddc_valid = false;
640 router.cd_valid = false;
641 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
642 uint8_t grph_obj_type =
643 (le16_to_cpu(path->usGraphicObjIds[j]) &
644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
645
646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
651 (ctx->bios + data_offset +
652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
653 ATOM_ENCODER_CAP_RECORD *cap_record;
654 u16 caps = 0;
655
656 while (record->ucRecordSize > 0 &&
657 record->ucRecordType > 0 &&
658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
659 switch (record->ucRecordType) {
660 case ATOM_ENCODER_CAP_RECORD_TYPE:
661 cap_record =(ATOM_ENCODER_CAP_RECORD *)
662 record;
663 caps = le16_to_cpu(cap_record->usEncoderCap);
664 break;
665 }
666 record = (ATOM_COMMON_RECORD_HEADER *)
667 ((char *)record + record->ucRecordSize);
668 }
669 radeon_add_atom_encoder(dev,
670 encoder_obj,
671 le16_to_cpu
672 (path->
673 usDeviceTag),
674 caps);
675 }
676 }
677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
682 (ctx->bios + data_offset +
683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
684 ATOM_I2C_RECORD *i2c_record;
685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
690 (ctx->bios + data_offset +
691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
692 u8 *num_dst_objs = (u8 *)
693 ((u8 *)router_src_dst_table + 1 +
694 (router_src_dst_table->ucNumberOfSrc * 2));
695 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
696 int enum_id;
697
698 router.router_id = router_obj_id;
699 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
700 if (le16_to_cpu(path->usConnObjectId) ==
701 le16_to_cpu(dst_objs[enum_id]))
702 break;
703 }
704
705 while (record->ucRecordSize > 0 &&
706 record->ucRecordType > 0 &&
707 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
708 switch (record->ucRecordType) {
709 case ATOM_I2C_RECORD_TYPE:
710 i2c_record =
711 (ATOM_I2C_RECORD *)
712 record;
713 i2c_config =
714 (ATOM_I2C_ID_CONFIG_ACCESS *)
715 &i2c_record->sucI2cId;
716 router.i2c_info =
717 radeon_lookup_i2c_gpio(rdev,
718 i2c_config->
719 ucAccess);
720 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
721 break;
722 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
723 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
724 record;
725 router.ddc_valid = true;
726 router.ddc_mux_type = ddc_path->ucMuxType;
727 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
728 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
729 break;
730 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
731 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
732 record;
733 router.cd_valid = true;
734 router.cd_mux_type = cd_path->ucMuxType;
735 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
736 router.cd_mux_state = cd_path->ucMuxState[enum_id];
737 break;
738 }
739 record = (ATOM_COMMON_RECORD_HEADER *)
740 ((char *)record + record->ucRecordSize);
741 }
742 }
743 }
744 }
745 }
746
747 /* look up gpio for ddc, hpd */
748 ddc_bus.valid = false;
749 hpd.hpd = RADEON_HPD_NONE;
750 if ((le16_to_cpu(path->usDeviceTag) &
751 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
752 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
753 if (le16_to_cpu(path->usConnObjectId) ==
754 le16_to_cpu(con_obj->asObjects[j].
755 usObjectID)) {
756 ATOM_COMMON_RECORD_HEADER
757 *record =
758 (ATOM_COMMON_RECORD_HEADER
759 *)
760 (ctx->bios + data_offset +
761 le16_to_cpu(con_obj->
762 asObjects[j].
763 usRecordOffset));
764 ATOM_I2C_RECORD *i2c_record;
765 ATOM_HPD_INT_RECORD *hpd_record;
766 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
767
768 while (record->ucRecordSize > 0 &&
769 record->ucRecordType > 0 &&
770 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
771 switch (record->ucRecordType) {
772 case ATOM_I2C_RECORD_TYPE:
773 i2c_record =
774 (ATOM_I2C_RECORD *)
775 record;
776 i2c_config =
777 (ATOM_I2C_ID_CONFIG_ACCESS *)
778 &i2c_record->sucI2cId;
779 ddc_bus = radeon_lookup_i2c_gpio(rdev,
780 i2c_config->
781 ucAccess);
782 break;
783 case ATOM_HPD_INT_RECORD_TYPE:
784 hpd_record =
785 (ATOM_HPD_INT_RECORD *)
786 record;
787 gpio = radeon_atombios_lookup_gpio(rdev,
788 hpd_record->ucHPDIntGPIOID);
789 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
790 hpd.plugged_state = hpd_record->ucPlugged_PinState;
791 break;
792 }
793 record =
794 (ATOM_COMMON_RECORD_HEADER
795 *) ((char *)record
796 +
797 record->
798 ucRecordSize);
799 }
800 break;
801 }
802 }
803 }
804
805 /* needed for aux chan transactions */
806 ddc_bus.hpd = hpd.hpd;
807
808 conn_id = le16_to_cpu(path->usConnObjectId);
809
810 if (!radeon_atom_apply_quirks
811 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
812 &ddc_bus, &conn_id, &hpd))
813 continue;
814
815 radeon_add_atom_connector(dev,
816 conn_id,
817 le16_to_cpu(path->
818 usDeviceTag),
819 connector_type, &ddc_bus,
820 igp_lane_info,
821 connector_object_id,
822 &hpd,
823 &router);
824
825 }
826 }
827
828 radeon_link_encoder_connector(dev);
829 return true;
830 }
831
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)832 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
833 int connector_type,
834 uint16_t devices)
835 {
836 struct radeon_device *rdev = dev->dev_private;
837
838 if (rdev->flags & RADEON_IS_IGP) {
839 return supported_devices_connector_object_id_convert
840 [connector_type];
841 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
842 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
843 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
844 struct radeon_mode_info *mode_info = &rdev->mode_info;
845 struct atom_context *ctx = mode_info->atom_context;
846 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
847 uint16_t size, data_offset;
848 uint8_t frev, crev;
849 ATOM_XTMDS_INFO *xtmds;
850
851 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
852 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
853
854 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
855 if (connector_type == DRM_MODE_CONNECTOR_DVII)
856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
857 else
858 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
859 } else {
860 if (connector_type == DRM_MODE_CONNECTOR_DVII)
861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
862 else
863 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
864 }
865 } else
866 return supported_devices_connector_object_id_convert
867 [connector_type];
868 } else {
869 return supported_devices_connector_object_id_convert
870 [connector_type];
871 }
872 }
873
874 struct bios_connector {
875 bool valid;
876 uint16_t line_mux;
877 uint16_t devices;
878 int connector_type;
879 struct radeon_i2c_bus_rec ddc_bus;
880 struct radeon_hpd hpd;
881 };
882
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)883 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
884 drm_device
885 *dev)
886 {
887 struct radeon_device *rdev = dev->dev_private;
888 struct radeon_mode_info *mode_info = &rdev->mode_info;
889 struct atom_context *ctx = mode_info->atom_context;
890 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
891 uint16_t size, data_offset;
892 uint8_t frev, crev;
893 uint16_t device_support;
894 uint8_t dac;
895 union atom_supported_devices *supported_devices;
896 int i, j, max_device;
897 struct bios_connector *bios_connectors;
898 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
899 struct radeon_router router;
900
901 router.ddc_valid = false;
902 router.cd_valid = false;
903
904 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
905 if (!bios_connectors)
906 return false;
907
908 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
909 &data_offset)) {
910 kfree(bios_connectors);
911 return false;
912 }
913
914 supported_devices =
915 (union atom_supported_devices *)(ctx->bios + data_offset);
916
917 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
918
919 if (frev > 1)
920 max_device = ATOM_MAX_SUPPORTED_DEVICE;
921 else
922 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
923
924 for (i = 0; i < max_device; i++) {
925 ATOM_CONNECTOR_INFO_I2C ci =
926 supported_devices->info.asConnInfo[i];
927
928 bios_connectors[i].valid = false;
929
930 if (!(device_support & (1 << i))) {
931 continue;
932 }
933
934 if (i == ATOM_DEVICE_CV_INDEX) {
935 DRM_DEBUG_KMS("Skipping Component Video\n");
936 continue;
937 }
938
939 bios_connectors[i].connector_type =
940 supported_devices_connector_convert[ci.sucConnectorInfo.
941 sbfAccess.
942 bfConnectorType];
943
944 if (bios_connectors[i].connector_type ==
945 DRM_MODE_CONNECTOR_Unknown)
946 continue;
947
948 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
949
950 bios_connectors[i].line_mux =
951 ci.sucI2cId.ucAccess;
952
953 /* give tv unique connector ids */
954 if (i == ATOM_DEVICE_TV1_INDEX) {
955 bios_connectors[i].ddc_bus.valid = false;
956 bios_connectors[i].line_mux = 50;
957 } else if (i == ATOM_DEVICE_TV2_INDEX) {
958 bios_connectors[i].ddc_bus.valid = false;
959 bios_connectors[i].line_mux = 51;
960 } else if (i == ATOM_DEVICE_CV_INDEX) {
961 bios_connectors[i].ddc_bus.valid = false;
962 bios_connectors[i].line_mux = 52;
963 } else
964 bios_connectors[i].ddc_bus =
965 radeon_lookup_i2c_gpio(rdev,
966 bios_connectors[i].line_mux);
967
968 if ((crev > 1) && (frev > 1)) {
969 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
970 switch (isb) {
971 case 0x4:
972 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
973 break;
974 case 0xa:
975 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
976 break;
977 default:
978 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
979 break;
980 }
981 } else {
982 if (i == ATOM_DEVICE_DFP1_INDEX)
983 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
984 else if (i == ATOM_DEVICE_DFP2_INDEX)
985 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
986 else
987 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
988 }
989
990 /* Always set the connector type to VGA for CRT1/CRT2. if they are
991 * shared with a DVI port, we'll pick up the DVI connector when we
992 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
993 */
994 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
995 bios_connectors[i].connector_type =
996 DRM_MODE_CONNECTOR_VGA;
997
998 if (!radeon_atom_apply_quirks
999 (dev, (1 << i), &bios_connectors[i].connector_type,
1000 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1001 &bios_connectors[i].hpd))
1002 continue;
1003
1004 bios_connectors[i].valid = true;
1005 bios_connectors[i].devices = (1 << i);
1006
1007 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1008 radeon_add_atom_encoder(dev,
1009 radeon_get_encoder_enum(dev,
1010 (1 << i),
1011 dac),
1012 (1 << i),
1013 0);
1014 else
1015 radeon_add_legacy_encoder(dev,
1016 radeon_get_encoder_enum(dev,
1017 (1 << i),
1018 dac),
1019 (1 << i));
1020 }
1021
1022 /* combine shared connectors */
1023 for (i = 0; i < max_device; i++) {
1024 if (bios_connectors[i].valid) {
1025 for (j = 0; j < max_device; j++) {
1026 if (bios_connectors[j].valid && (i != j)) {
1027 if (bios_connectors[i].line_mux ==
1028 bios_connectors[j].line_mux) {
1029 /* make sure not to combine LVDS */
1030 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1031 bios_connectors[i].line_mux = 53;
1032 bios_connectors[i].ddc_bus.valid = false;
1033 continue;
1034 }
1035 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1036 bios_connectors[j].line_mux = 53;
1037 bios_connectors[j].ddc_bus.valid = false;
1038 continue;
1039 }
1040 /* combine analog and digital for DVI-I */
1041 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1042 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1043 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1045 bios_connectors[i].devices |=
1046 bios_connectors[j].devices;
1047 bios_connectors[i].connector_type =
1048 DRM_MODE_CONNECTOR_DVII;
1049 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1050 bios_connectors[i].hpd =
1051 bios_connectors[j].hpd;
1052 bios_connectors[j].valid = false;
1053 }
1054 }
1055 }
1056 }
1057 }
1058 }
1059
1060 /* add the connectors */
1061 for (i = 0; i < max_device; i++) {
1062 if (bios_connectors[i].valid) {
1063 uint16_t connector_object_id =
1064 atombios_get_connector_object_id(dev,
1065 bios_connectors[i].connector_type,
1066 bios_connectors[i].devices);
1067 radeon_add_atom_connector(dev,
1068 bios_connectors[i].line_mux,
1069 bios_connectors[i].devices,
1070 bios_connectors[i].
1071 connector_type,
1072 &bios_connectors[i].ddc_bus,
1073 0,
1074 connector_object_id,
1075 &bios_connectors[i].hpd,
1076 &router);
1077 }
1078 }
1079
1080 radeon_link_encoder_connector(dev);
1081
1082 kfree(bios_connectors);
1083 return true;
1084 }
1085
1086 union firmware_info {
1087 ATOM_FIRMWARE_INFO info;
1088 ATOM_FIRMWARE_INFO_V1_2 info_12;
1089 ATOM_FIRMWARE_INFO_V1_3 info_13;
1090 ATOM_FIRMWARE_INFO_V1_4 info_14;
1091 ATOM_FIRMWARE_INFO_V2_1 info_21;
1092 ATOM_FIRMWARE_INFO_V2_2 info_22;
1093 };
1094
1095 union igp_info {
1096 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1097 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1098 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1099 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1100 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1101 };
1102
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1103 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1104 {
1105 struct radeon_mode_info *mode_info = &rdev->mode_info;
1106 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1107 union igp_info *igp_info;
1108 u8 frev, crev;
1109 u16 data_offset;
1110
1111 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1112 &frev, &crev, &data_offset)) {
1113 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1114 data_offset);
1115 rdev->clock.vco_freq =
1116 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1117 }
1118 }
1119
radeon_atom_get_clock_info(struct drm_device * dev)1120 bool radeon_atom_get_clock_info(struct drm_device *dev)
1121 {
1122 struct radeon_device *rdev = dev->dev_private;
1123 struct radeon_mode_info *mode_info = &rdev->mode_info;
1124 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1125 union firmware_info *firmware_info;
1126 uint8_t frev, crev;
1127 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1128 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1129 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1130 struct radeon_pll *spll = &rdev->clock.spll;
1131 struct radeon_pll *mpll = &rdev->clock.mpll;
1132 uint16_t data_offset;
1133
1134 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1135 &frev, &crev, &data_offset)) {
1136 firmware_info =
1137 (union firmware_info *)(mode_info->atom_context->bios +
1138 data_offset);
1139 /* pixel clocks */
1140 p1pll->reference_freq =
1141 le16_to_cpu(firmware_info->info.usReferenceClock);
1142 p1pll->reference_div = 0;
1143
1144 if ((frev < 2) && (crev < 2))
1145 p1pll->pll_out_min =
1146 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1147 else
1148 p1pll->pll_out_min =
1149 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1150 p1pll->pll_out_max =
1151 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1152
1153 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1154 p1pll->lcd_pll_out_min =
1155 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1156 if (p1pll->lcd_pll_out_min == 0)
1157 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1158 p1pll->lcd_pll_out_max =
1159 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1160 if (p1pll->lcd_pll_out_max == 0)
1161 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1162 } else {
1163 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1164 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1165 }
1166
1167 if (p1pll->pll_out_min == 0) {
1168 if (ASIC_IS_AVIVO(rdev))
1169 p1pll->pll_out_min = 64800;
1170 else
1171 p1pll->pll_out_min = 20000;
1172 }
1173
1174 p1pll->pll_in_min =
1175 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1176 p1pll->pll_in_max =
1177 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1178
1179 *p2pll = *p1pll;
1180
1181 /* system clock */
1182 if (ASIC_IS_DCE4(rdev))
1183 spll->reference_freq =
1184 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1185 else
1186 spll->reference_freq =
1187 le16_to_cpu(firmware_info->info.usReferenceClock);
1188 spll->reference_div = 0;
1189
1190 spll->pll_out_min =
1191 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1192 spll->pll_out_max =
1193 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1194
1195 /* ??? */
1196 if (spll->pll_out_min == 0) {
1197 if (ASIC_IS_AVIVO(rdev))
1198 spll->pll_out_min = 64800;
1199 else
1200 spll->pll_out_min = 20000;
1201 }
1202
1203 spll->pll_in_min =
1204 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1205 spll->pll_in_max =
1206 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1207
1208 /* memory clock */
1209 if (ASIC_IS_DCE4(rdev))
1210 mpll->reference_freq =
1211 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1212 else
1213 mpll->reference_freq =
1214 le16_to_cpu(firmware_info->info.usReferenceClock);
1215 mpll->reference_div = 0;
1216
1217 mpll->pll_out_min =
1218 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1219 mpll->pll_out_max =
1220 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1221
1222 /* ??? */
1223 if (mpll->pll_out_min == 0) {
1224 if (ASIC_IS_AVIVO(rdev))
1225 mpll->pll_out_min = 64800;
1226 else
1227 mpll->pll_out_min = 20000;
1228 }
1229
1230 mpll->pll_in_min =
1231 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1232 mpll->pll_in_max =
1233 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1234
1235 rdev->clock.default_sclk =
1236 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1237 rdev->clock.default_mclk =
1238 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1239
1240 if (ASIC_IS_DCE4(rdev)) {
1241 rdev->clock.default_dispclk =
1242 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1243 if (rdev->clock.default_dispclk == 0) {
1244 if (ASIC_IS_DCE6(rdev))
1245 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1246 else if (ASIC_IS_DCE5(rdev))
1247 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1248 else
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1250 }
1251 /* set a reasonable default for DP */
1252 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1253 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1254 rdev->clock.default_dispclk / 100);
1255 rdev->clock.default_dispclk = 60000;
1256 }
1257 rdev->clock.dp_extclk =
1258 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1259 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1260 }
1261 *dcpll = *p1pll;
1262
1263 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1264 if (rdev->clock.max_pixel_clock == 0)
1265 rdev->clock.max_pixel_clock = 40000;
1266
1267 /* not technically a clock, but... */
1268 rdev->mode_info.firmware_flags =
1269 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1270
1271 if (ASIC_IS_DCE8(rdev))
1272 rdev->clock.vco_freq =
1273 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1274 else if (ASIC_IS_DCE5(rdev))
1275 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1276 else if (ASIC_IS_DCE41(rdev))
1277 radeon_atombios_get_dentist_vco_freq(rdev);
1278 else
1279 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1280
1281 if (rdev->clock.vco_freq == 0)
1282 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1283
1284 return true;
1285 }
1286
1287 return false;
1288 }
1289
radeon_atombios_sideport_present(struct radeon_device * rdev)1290 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1291 {
1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1294 union igp_info *igp_info;
1295 u8 frev, crev;
1296 u16 data_offset;
1297
1298 /* sideport is AMD only */
1299 if (rdev->family == CHIP_RS600)
1300 return false;
1301
1302 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1303 &frev, &crev, &data_offset)) {
1304 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1305 data_offset);
1306 switch (crev) {
1307 case 1:
1308 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1309 return true;
1310 break;
1311 case 2:
1312 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1313 return true;
1314 break;
1315 default:
1316 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1317 break;
1318 }
1319 }
1320 return false;
1321 }
1322
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1323 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1324 struct radeon_encoder_int_tmds *tmds)
1325 {
1326 struct drm_device *dev = encoder->base.dev;
1327 struct radeon_device *rdev = dev->dev_private;
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1329 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1330 uint16_t data_offset;
1331 struct _ATOM_TMDS_INFO *tmds_info;
1332 uint8_t frev, crev;
1333 uint16_t maxfreq;
1334 int i;
1335
1336 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1337 &frev, &crev, &data_offset)) {
1338 tmds_info =
1339 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1340 data_offset);
1341
1342 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1343 for (i = 0; i < 4; i++) {
1344 tmds->tmds_pll[i].freq =
1345 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1346 tmds->tmds_pll[i].value =
1347 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1348 tmds->tmds_pll[i].value |=
1349 (tmds_info->asMiscInfo[i].
1350 ucPLL_VCO_Gain & 0x3f) << 6;
1351 tmds->tmds_pll[i].value |=
1352 (tmds_info->asMiscInfo[i].
1353 ucPLL_DutyCycle & 0xf) << 12;
1354 tmds->tmds_pll[i].value |=
1355 (tmds_info->asMiscInfo[i].
1356 ucPLL_VoltageSwing & 0xf) << 16;
1357
1358 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1359 tmds->tmds_pll[i].freq,
1360 tmds->tmds_pll[i].value);
1361
1362 if (maxfreq == tmds->tmds_pll[i].freq) {
1363 tmds->tmds_pll[i].freq = 0xffffffff;
1364 break;
1365 }
1366 }
1367 return true;
1368 }
1369 return false;
1370 }
1371
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1372 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1373 struct radeon_atom_ss *ss,
1374 int id)
1375 {
1376 struct radeon_mode_info *mode_info = &rdev->mode_info;
1377 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1378 uint16_t data_offset, size;
1379 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1380 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1381 uint8_t frev, crev;
1382 int i, num_indices;
1383
1384 memset(ss, 0, sizeof(struct radeon_atom_ss));
1385 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1386 &frev, &crev, &data_offset)) {
1387 ss_info =
1388 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1389
1390 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1391 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1392 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1393 ((u8 *)&ss_info->asSS_Info[0]);
1394 for (i = 0; i < num_indices; i++) {
1395 if (ss_assign->ucSS_Id == id) {
1396 ss->percentage =
1397 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1398 ss->type = ss_assign->ucSpreadSpectrumType;
1399 ss->step = ss_assign->ucSS_Step;
1400 ss->delay = ss_assign->ucSS_Delay;
1401 ss->range = ss_assign->ucSS_Range;
1402 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1403 return true;
1404 }
1405 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1406 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1407 }
1408 }
1409 return false;
1410 }
1411
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1412 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1413 struct radeon_atom_ss *ss,
1414 int id)
1415 {
1416 struct radeon_mode_info *mode_info = &rdev->mode_info;
1417 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1418 u16 data_offset, size;
1419 union igp_info *igp_info;
1420 u8 frev, crev;
1421 u16 percentage = 0, rate = 0;
1422
1423 /* get any igp specific overrides */
1424 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1425 &frev, &crev, &data_offset)) {
1426 igp_info = (union igp_info *)
1427 (mode_info->atom_context->bios + data_offset);
1428 switch (crev) {
1429 case 6:
1430 switch (id) {
1431 case ASIC_INTERNAL_SS_ON_TMDS:
1432 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1433 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1434 break;
1435 case ASIC_INTERNAL_SS_ON_HDMI:
1436 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1437 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1438 break;
1439 case ASIC_INTERNAL_SS_ON_LVDS:
1440 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1441 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1442 break;
1443 }
1444 break;
1445 case 7:
1446 switch (id) {
1447 case ASIC_INTERNAL_SS_ON_TMDS:
1448 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1449 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1450 break;
1451 case ASIC_INTERNAL_SS_ON_HDMI:
1452 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1453 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1454 break;
1455 case ASIC_INTERNAL_SS_ON_LVDS:
1456 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1457 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1458 break;
1459 }
1460 break;
1461 case 8:
1462 switch (id) {
1463 case ASIC_INTERNAL_SS_ON_TMDS:
1464 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1465 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1466 break;
1467 case ASIC_INTERNAL_SS_ON_HDMI:
1468 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1469 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1470 break;
1471 case ASIC_INTERNAL_SS_ON_LVDS:
1472 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1473 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1474 break;
1475 }
1476 break;
1477 default:
1478 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1479 break;
1480 }
1481 if (percentage)
1482 ss->percentage = percentage;
1483 if (rate)
1484 ss->rate = rate;
1485 }
1486 }
1487
1488 union asic_ss_info {
1489 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1490 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1491 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1492 };
1493
1494 union asic_ss_assignment {
1495 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1496 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1497 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1498 };
1499
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1500 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1501 struct radeon_atom_ss *ss,
1502 int id, u32 clock)
1503 {
1504 struct radeon_mode_info *mode_info = &rdev->mode_info;
1505 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1506 uint16_t data_offset, size;
1507 union asic_ss_info *ss_info;
1508 union asic_ss_assignment *ss_assign;
1509 uint8_t frev, crev;
1510 int i, num_indices;
1511
1512 if (id == ASIC_INTERNAL_MEMORY_SS) {
1513 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1514 return false;
1515 }
1516 if (id == ASIC_INTERNAL_ENGINE_SS) {
1517 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1518 return false;
1519 }
1520
1521 memset(ss, 0, sizeof(struct radeon_atom_ss));
1522 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1523 &frev, &crev, &data_offset)) {
1524
1525 ss_info =
1526 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1527
1528 switch (frev) {
1529 case 1:
1530 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1531 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1532
1533 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1534 for (i = 0; i < num_indices; i++) {
1535 if ((ss_assign->v1.ucClockIndication == id) &&
1536 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1537 ss->percentage =
1538 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1539 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1540 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1541 ss->percentage_divider = 100;
1542 return true;
1543 }
1544 ss_assign = (union asic_ss_assignment *)
1545 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1546 }
1547 break;
1548 case 2:
1549 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1550 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1551 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1552 for (i = 0; i < num_indices; i++) {
1553 if ((ss_assign->v2.ucClockIndication == id) &&
1554 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1555 ss->percentage =
1556 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1557 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1558 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1559 ss->percentage_divider = 100;
1560 if ((crev == 2) &&
1561 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1562 (id == ASIC_INTERNAL_MEMORY_SS)))
1563 ss->rate /= 100;
1564 return true;
1565 }
1566 ss_assign = (union asic_ss_assignment *)
1567 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1568 }
1569 break;
1570 case 3:
1571 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1572 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1573 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1574 for (i = 0; i < num_indices; i++) {
1575 if ((ss_assign->v3.ucClockIndication == id) &&
1576 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1577 ss->percentage =
1578 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1579 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1580 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1581 if (ss_assign->v3.ucSpreadSpectrumMode &
1582 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1583 ss->percentage_divider = 1000;
1584 else
1585 ss->percentage_divider = 100;
1586 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1587 (id == ASIC_INTERNAL_MEMORY_SS))
1588 ss->rate /= 100;
1589 if (rdev->flags & RADEON_IS_IGP)
1590 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1591 return true;
1592 }
1593 ss_assign = (union asic_ss_assignment *)
1594 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1595 }
1596 break;
1597 default:
1598 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1599 break;
1600 }
1601
1602 }
1603 return false;
1604 }
1605
1606 union lvds_info {
1607 struct _ATOM_LVDS_INFO info;
1608 struct _ATOM_LVDS_INFO_V12 info_12;
1609 };
1610
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1611 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1612 radeon_encoder
1613 *encoder)
1614 {
1615 struct drm_device *dev = encoder->base.dev;
1616 struct radeon_device *rdev = dev->dev_private;
1617 struct radeon_mode_info *mode_info = &rdev->mode_info;
1618 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1619 uint16_t data_offset, misc;
1620 union lvds_info *lvds_info;
1621 uint8_t frev, crev;
1622 struct radeon_encoder_atom_dig *lvds = NULL;
1623 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1624
1625 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1626 &frev, &crev, &data_offset)) {
1627 lvds_info =
1628 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1629 lvds =
1630 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1631
1632 if (!lvds)
1633 return NULL;
1634
1635 lvds->native_mode.clock =
1636 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1637 lvds->native_mode.hdisplay =
1638 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1639 lvds->native_mode.vdisplay =
1640 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1641 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1642 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1643 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1644 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1645 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1647 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1648 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1649 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1651 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1653 lvds->panel_pwr_delay =
1654 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1655 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1656
1657 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1658 if (misc & ATOM_VSYNC_POLARITY)
1659 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1660 if (misc & ATOM_HSYNC_POLARITY)
1661 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1662 if (misc & ATOM_COMPOSITESYNC)
1663 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1664 if (misc & ATOM_INTERLACE)
1665 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1666 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1668
1669 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1670 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1671
1672 /* set crtc values */
1673 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1674
1675 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1676
1677 encoder->native_mode = lvds->native_mode;
1678
1679 if (encoder_enum == 2)
1680 lvds->linkb = true;
1681 else
1682 lvds->linkb = false;
1683
1684 /* parse the lcd record table */
1685 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1686 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1687 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1688 bool bad_record = false;
1689 u8 *record;
1690
1691 if ((frev == 1) && (crev < 2))
1692 /* absolute */
1693 record = (u8 *)(mode_info->atom_context->bios +
1694 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1695 else
1696 /* relative */
1697 record = (u8 *)(mode_info->atom_context->bios +
1698 data_offset +
1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1700 while (*record != ATOM_RECORD_END_TYPE) {
1701 switch (*record) {
1702 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1703 record += sizeof(ATOM_PATCH_RECORD_MODE);
1704 break;
1705 case LCD_RTS_RECORD_TYPE:
1706 record += sizeof(ATOM_LCD_RTS_RECORD);
1707 break;
1708 case LCD_CAP_RECORD_TYPE:
1709 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1710 break;
1711 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1712 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1713 if (fake_edid_record->ucFakeEDIDLength) {
1714 struct edid *edid;
1715 int edid_size =
1716 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1717 edid = kmalloc(edid_size, GFP_KERNEL);
1718 if (edid) {
1719 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1720 fake_edid_record->ucFakeEDIDLength);
1721
1722 if (drm_edid_is_valid(edid)) {
1723 rdev->mode_info.bios_hardcoded_edid = edid;
1724 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1725 } else
1726 kfree(edid);
1727 }
1728 }
1729 record += fake_edid_record->ucFakeEDIDLength ?
1730 fake_edid_record->ucFakeEDIDLength + 2 :
1731 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1732 break;
1733 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1734 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1735 lvds->native_mode.width_mm = panel_res_record->usHSize;
1736 lvds->native_mode.height_mm = panel_res_record->usVSize;
1737 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1738 break;
1739 default:
1740 DRM_ERROR("Bad LCD record %d\n", *record);
1741 bad_record = true;
1742 break;
1743 }
1744 if (bad_record)
1745 break;
1746 }
1747 }
1748 }
1749 return lvds;
1750 }
1751
1752 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1753 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1754 {
1755 struct drm_device *dev = encoder->base.dev;
1756 struct radeon_device *rdev = dev->dev_private;
1757 struct radeon_mode_info *mode_info = &rdev->mode_info;
1758 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1759 uint16_t data_offset;
1760 struct _COMPASSIONATE_DATA *dac_info;
1761 uint8_t frev, crev;
1762 uint8_t bg, dac;
1763 struct radeon_encoder_primary_dac *p_dac = NULL;
1764
1765 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1766 &frev, &crev, &data_offset)) {
1767 dac_info = (struct _COMPASSIONATE_DATA *)
1768 (mode_info->atom_context->bios + data_offset);
1769
1770 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1771
1772 if (!p_dac)
1773 return NULL;
1774
1775 bg = dac_info->ucDAC1_BG_Adjustment;
1776 dac = dac_info->ucDAC1_DAC_Adjustment;
1777 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1778
1779 }
1780 return p_dac;
1781 }
1782
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1783 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1784 struct drm_display_mode *mode)
1785 {
1786 struct radeon_mode_info *mode_info = &rdev->mode_info;
1787 ATOM_ANALOG_TV_INFO *tv_info;
1788 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1789 ATOM_DTD_FORMAT *dtd_timings;
1790 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1791 u8 frev, crev;
1792 u16 data_offset, misc;
1793
1794 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1795 &frev, &crev, &data_offset))
1796 return false;
1797
1798 switch (crev) {
1799 case 1:
1800 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1801 if (index >= MAX_SUPPORTED_TV_TIMING)
1802 return false;
1803
1804 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1805 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1806 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1807 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1808 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1809
1810 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1811 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1812 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1813 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1814 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1815
1816 mode->flags = 0;
1817 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1818 if (misc & ATOM_VSYNC_POLARITY)
1819 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1820 if (misc & ATOM_HSYNC_POLARITY)
1821 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1822 if (misc & ATOM_COMPOSITESYNC)
1823 mode->flags |= DRM_MODE_FLAG_CSYNC;
1824 if (misc & ATOM_INTERLACE)
1825 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1826 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1827 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1828
1829 mode->crtc_clock = mode->clock =
1830 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1831
1832 if (index == 1) {
1833 /* PAL timings appear to have wrong values for totals */
1834 mode->crtc_htotal -= 1;
1835 mode->crtc_vtotal -= 1;
1836 }
1837 break;
1838 case 2:
1839 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1840 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1841 return false;
1842
1843 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1844 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1845 le16_to_cpu(dtd_timings->usHBlanking_Time);
1846 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1847 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1848 le16_to_cpu(dtd_timings->usHSyncOffset);
1849 mode->crtc_hsync_end = mode->crtc_hsync_start +
1850 le16_to_cpu(dtd_timings->usHSyncWidth);
1851
1852 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1853 le16_to_cpu(dtd_timings->usVBlanking_Time);
1854 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1855 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1856 le16_to_cpu(dtd_timings->usVSyncOffset);
1857 mode->crtc_vsync_end = mode->crtc_vsync_start +
1858 le16_to_cpu(dtd_timings->usVSyncWidth);
1859
1860 mode->flags = 0;
1861 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1862 if (misc & ATOM_VSYNC_POLARITY)
1863 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1864 if (misc & ATOM_HSYNC_POLARITY)
1865 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1866 if (misc & ATOM_COMPOSITESYNC)
1867 mode->flags |= DRM_MODE_FLAG_CSYNC;
1868 if (misc & ATOM_INTERLACE)
1869 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1870 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1871 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1872
1873 mode->crtc_clock = mode->clock =
1874 le16_to_cpu(dtd_timings->usPixClk) * 10;
1875 break;
1876 }
1877 return true;
1878 }
1879
1880 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1881 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1882 {
1883 struct radeon_mode_info *mode_info = &rdev->mode_info;
1884 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1885 uint16_t data_offset;
1886 uint8_t frev, crev;
1887 struct _ATOM_ANALOG_TV_INFO *tv_info;
1888 enum radeon_tv_std tv_std = TV_STD_NTSC;
1889
1890 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1891 &frev, &crev, &data_offset)) {
1892
1893 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1894 (mode_info->atom_context->bios + data_offset);
1895
1896 switch (tv_info->ucTV_BootUpDefaultStandard) {
1897 case ATOM_TV_NTSC:
1898 tv_std = TV_STD_NTSC;
1899 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1900 break;
1901 case ATOM_TV_NTSCJ:
1902 tv_std = TV_STD_NTSC_J;
1903 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1904 break;
1905 case ATOM_TV_PAL:
1906 tv_std = TV_STD_PAL;
1907 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1908 break;
1909 case ATOM_TV_PALM:
1910 tv_std = TV_STD_PAL_M;
1911 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1912 break;
1913 case ATOM_TV_PALN:
1914 tv_std = TV_STD_PAL_N;
1915 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1916 break;
1917 case ATOM_TV_PALCN:
1918 tv_std = TV_STD_PAL_CN;
1919 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1920 break;
1921 case ATOM_TV_PAL60:
1922 tv_std = TV_STD_PAL_60;
1923 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1924 break;
1925 case ATOM_TV_SECAM:
1926 tv_std = TV_STD_SECAM;
1927 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1928 break;
1929 default:
1930 tv_std = TV_STD_NTSC;
1931 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1932 break;
1933 }
1934 }
1935 return tv_std;
1936 }
1937
1938 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1939 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1940 {
1941 struct drm_device *dev = encoder->base.dev;
1942 struct radeon_device *rdev = dev->dev_private;
1943 struct radeon_mode_info *mode_info = &rdev->mode_info;
1944 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1945 uint16_t data_offset;
1946 struct _COMPASSIONATE_DATA *dac_info;
1947 uint8_t frev, crev;
1948 uint8_t bg, dac;
1949 struct radeon_encoder_tv_dac *tv_dac = NULL;
1950
1951 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1952 &frev, &crev, &data_offset)) {
1953
1954 dac_info = (struct _COMPASSIONATE_DATA *)
1955 (mode_info->atom_context->bios + data_offset);
1956
1957 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1958
1959 if (!tv_dac)
1960 return NULL;
1961
1962 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1963 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1964 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1965
1966 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1967 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1968 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1969
1970 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1971 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1972 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1973
1974 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1975 }
1976 return tv_dac;
1977 }
1978
1979 static const char *thermal_controller_names[] = {
1980 "NONE",
1981 "lm63",
1982 "adm1032",
1983 "adm1030",
1984 "max6649",
1985 "lm63", /* lm64 */
1986 "f75375",
1987 "asc7xxx",
1988 };
1989
1990 static const char *pp_lib_thermal_controller_names[] = {
1991 "NONE",
1992 "lm63",
1993 "adm1032",
1994 "adm1030",
1995 "max6649",
1996 "lm63", /* lm64 */
1997 "f75375",
1998 "RV6xx",
1999 "RV770",
2000 "adt7473",
2001 "NONE",
2002 "External GPIO",
2003 "Evergreen",
2004 "emc2103",
2005 "Sumo",
2006 "Northern Islands",
2007 "Southern Islands",
2008 "lm96163",
2009 "Sea Islands",
2010 };
2011
2012 union power_info {
2013 struct _ATOM_POWERPLAY_INFO info;
2014 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2015 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2016 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2017 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2018 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2019 };
2020
2021 union pplib_clock_info {
2022 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2023 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2024 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2025 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2026 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2027 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2028 };
2029
2030 union pplib_power_state {
2031 struct _ATOM_PPLIB_STATE v1;
2032 struct _ATOM_PPLIB_STATE_V2 v2;
2033 };
2034
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2035 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2036 int state_index,
2037 u32 misc, u32 misc2)
2038 {
2039 rdev->pm.power_state[state_index].misc = misc;
2040 rdev->pm.power_state[state_index].misc2 = misc2;
2041 /* order matters! */
2042 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2043 rdev->pm.power_state[state_index].type =
2044 POWER_STATE_TYPE_POWERSAVE;
2045 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2046 rdev->pm.power_state[state_index].type =
2047 POWER_STATE_TYPE_BATTERY;
2048 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_BATTERY;
2051 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BALANCED;
2054 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_PERFORMANCE;
2057 rdev->pm.power_state[state_index].flags &=
2058 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2059 }
2060 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_BALANCED;
2063 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_DEFAULT;
2066 rdev->pm.default_power_state_index = state_index;
2067 rdev->pm.power_state[state_index].default_clock_mode =
2068 &rdev->pm.power_state[state_index].clock_info[0];
2069 } else if (state_index == 0) {
2070 rdev->pm.power_state[state_index].clock_info[0].flags |=
2071 RADEON_PM_MODE_NO_DISPLAY;
2072 }
2073 }
2074
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2075 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2076 {
2077 struct radeon_mode_info *mode_info = &rdev->mode_info;
2078 u32 misc, misc2 = 0;
2079 int num_modes = 0, i;
2080 int state_index = 0;
2081 struct radeon_i2c_bus_rec i2c_bus;
2082 union power_info *power_info;
2083 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2084 u16 data_offset;
2085 u8 frev, crev;
2086
2087 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2088 &frev, &crev, &data_offset))
2089 return state_index;
2090 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2091
2092 /* add the i2c bus for thermal/fan chip */
2093 if ((power_info->info.ucOverdriveThermalController > 0) &&
2094 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2095 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2096 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2097 power_info->info.ucOverdriveControllerAddress >> 1);
2098 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2099 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2100 if (rdev->pm.i2c_bus) {
2101 struct i2c_board_info info = { };
2102 const char *name = thermal_controller_names[power_info->info.
2103 ucOverdriveThermalController];
2104 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2105 strlcpy(info.type, name, sizeof(info.type));
2106 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2107 }
2108 }
2109 num_modes = power_info->info.ucNumOfPowerModeEntries;
2110 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2111 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2112 if (num_modes == 0)
2113 return state_index;
2114 rdev->pm.power_state = kcalloc(num_modes,
2115 sizeof(struct radeon_power_state),
2116 GFP_KERNEL);
2117 if (!rdev->pm.power_state)
2118 return state_index;
2119 /* last mode is usually default, array is low to high */
2120 for (i = 0; i < num_modes; i++) {
2121 /* avoid memory leaks from invalid modes or unknown frev. */
2122 if (!rdev->pm.power_state[state_index].clock_info) {
2123 rdev->pm.power_state[state_index].clock_info =
2124 kzalloc(sizeof(struct radeon_pm_clock_info),
2125 GFP_KERNEL);
2126 }
2127 if (!rdev->pm.power_state[state_index].clock_info)
2128 goto out;
2129 rdev->pm.power_state[state_index].num_clock_modes = 1;
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2131 switch (frev) {
2132 case 1:
2133 rdev->pm.power_state[state_index].clock_info[0].mclk =
2134 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2135 rdev->pm.power_state[state_index].clock_info[0].sclk =
2136 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2137 /* skip invalid modes */
2138 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2139 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2140 continue;
2141 rdev->pm.power_state[state_index].pcie_lanes =
2142 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2143 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2144 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2145 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2146 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2147 VOLTAGE_GPIO;
2148 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2149 radeon_atombios_lookup_gpio(rdev,
2150 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2151 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2153 true;
2154 else
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2156 false;
2157 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2159 VOLTAGE_VDDC;
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2161 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2162 }
2163 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2164 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2165 state_index++;
2166 break;
2167 case 2:
2168 rdev->pm.power_state[state_index].clock_info[0].mclk =
2169 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2170 rdev->pm.power_state[state_index].clock_info[0].sclk =
2171 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2172 /* skip invalid modes */
2173 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2174 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2175 continue;
2176 rdev->pm.power_state[state_index].pcie_lanes =
2177 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2178 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2179 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2180 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2181 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2182 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2183 VOLTAGE_GPIO;
2184 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2185 radeon_atombios_lookup_gpio(rdev,
2186 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2187 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2188 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2189 true;
2190 else
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2192 false;
2193 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2195 VOLTAGE_VDDC;
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2197 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2198 }
2199 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2200 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2201 state_index++;
2202 break;
2203 case 3:
2204 rdev->pm.power_state[state_index].clock_info[0].mclk =
2205 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2206 rdev->pm.power_state[state_index].clock_info[0].sclk =
2207 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2208 /* skip invalid modes */
2209 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2210 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2211 continue;
2212 rdev->pm.power_state[state_index].pcie_lanes =
2213 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2214 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2215 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2216 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2217 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2218 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2219 VOLTAGE_GPIO;
2220 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2221 radeon_atombios_lookup_gpio(rdev,
2222 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2223 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2224 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2225 true;
2226 else
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2228 false;
2229 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2231 VOLTAGE_VDDC;
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2233 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2234 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2236 true;
2237 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2238 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2239 }
2240 }
2241 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2242 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2243 state_index++;
2244 break;
2245 }
2246 }
2247 out:
2248 /* free any unused clock_info allocation. */
2249 if (state_index && state_index < num_modes) {
2250 kfree(rdev->pm.power_state[state_index].clock_info);
2251 rdev->pm.power_state[state_index].clock_info = NULL;
2252 }
2253
2254 /* last mode is usually default */
2255 if (state_index && rdev->pm.default_power_state_index == -1) {
2256 rdev->pm.power_state[state_index - 1].type =
2257 POWER_STATE_TYPE_DEFAULT;
2258 rdev->pm.default_power_state_index = state_index - 1;
2259 rdev->pm.power_state[state_index - 1].default_clock_mode =
2260 &rdev->pm.power_state[state_index - 1].clock_info[0];
2261 rdev->pm.power_state[state_index - 1].flags &=
2262 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2263 rdev->pm.power_state[state_index - 1].misc = 0;
2264 rdev->pm.power_state[state_index - 1].misc2 = 0;
2265 }
2266 return state_index;
2267 }
2268
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2269 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2270 ATOM_PPLIB_THERMALCONTROLLER *controller)
2271 {
2272 struct radeon_i2c_bus_rec i2c_bus;
2273
2274 /* add the i2c bus for thermal/fan chip */
2275 if (controller->ucType > 0) {
2276 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2277 rdev->pm.no_fan = true;
2278 rdev->pm.fan_pulses_per_revolution =
2279 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2280 if (rdev->pm.fan_pulses_per_revolution) {
2281 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2282 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2283 }
2284 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2285 DRM_INFO("Internal thermal controller %s fan control\n",
2286 (controller->ucFanParameters &
2287 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2288 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2289 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2290 DRM_INFO("Internal thermal controller %s fan control\n",
2291 (controller->ucFanParameters &
2292 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2293 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2294 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2295 DRM_INFO("Internal thermal controller %s fan control\n",
2296 (controller->ucFanParameters &
2297 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2298 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2299 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2300 DRM_INFO("Internal thermal controller %s fan control\n",
2301 (controller->ucFanParameters &
2302 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2303 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2304 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2305 DRM_INFO("Internal thermal controller %s fan control\n",
2306 (controller->ucFanParameters &
2307 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2308 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2309 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2310 DRM_INFO("Internal thermal controller %s fan control\n",
2311 (controller->ucFanParameters &
2312 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2313 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2314 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2315 DRM_INFO("Internal thermal controller %s fan control\n",
2316 (controller->ucFanParameters &
2317 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2318 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2319 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2320 DRM_INFO("Internal thermal controller %s fan control\n",
2321 (controller->ucFanParameters &
2322 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2323 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2324 } else if (controller->ucType ==
2325 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2326 DRM_INFO("External GPIO thermal controller %s fan control\n",
2327 (controller->ucFanParameters &
2328 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2329 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2330 } else if (controller->ucType ==
2331 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2332 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2333 (controller->ucFanParameters &
2334 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2335 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2336 } else if (controller->ucType ==
2337 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2338 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2342 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2343 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2344 pp_lib_thermal_controller_names[controller->ucType],
2345 controller->ucI2cAddress >> 1,
2346 (controller->ucFanParameters &
2347 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2348 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2349 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2350 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2351 if (rdev->pm.i2c_bus) {
2352 struct i2c_board_info info = { };
2353 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2354 info.addr = controller->ucI2cAddress >> 1;
2355 strlcpy(info.type, name, sizeof(info.type));
2356 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2357 }
2358 } else {
2359 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2360 controller->ucType,
2361 controller->ucI2cAddress >> 1,
2362 (controller->ucFanParameters &
2363 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2364 }
2365 }
2366 }
2367
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2368 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2369 u16 *vddc, u16 *vddci, u16 *mvdd)
2370 {
2371 struct radeon_mode_info *mode_info = &rdev->mode_info;
2372 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2373 u8 frev, crev;
2374 u16 data_offset;
2375 union firmware_info *firmware_info;
2376
2377 *vddc = 0;
2378 *vddci = 0;
2379 *mvdd = 0;
2380
2381 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2382 &frev, &crev, &data_offset)) {
2383 firmware_info =
2384 (union firmware_info *)(mode_info->atom_context->bios +
2385 data_offset);
2386 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2387 if ((frev == 2) && (crev >= 2)) {
2388 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2389 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2390 }
2391 }
2392 }
2393
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2394 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2395 int state_index, int mode_index,
2396 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2397 {
2398 int j;
2399 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2400 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2401 u16 vddc, vddci, mvdd;
2402
2403 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2404
2405 rdev->pm.power_state[state_index].misc = misc;
2406 rdev->pm.power_state[state_index].misc2 = misc2;
2407 rdev->pm.power_state[state_index].pcie_lanes =
2408 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2409 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2410 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2411 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2412 rdev->pm.power_state[state_index].type =
2413 POWER_STATE_TYPE_BATTERY;
2414 break;
2415 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2416 rdev->pm.power_state[state_index].type =
2417 POWER_STATE_TYPE_BALANCED;
2418 break;
2419 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2420 rdev->pm.power_state[state_index].type =
2421 POWER_STATE_TYPE_PERFORMANCE;
2422 break;
2423 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2424 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2425 rdev->pm.power_state[state_index].type =
2426 POWER_STATE_TYPE_PERFORMANCE;
2427 break;
2428 }
2429 rdev->pm.power_state[state_index].flags = 0;
2430 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2431 rdev->pm.power_state[state_index].flags |=
2432 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2433 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2434 rdev->pm.power_state[state_index].type =
2435 POWER_STATE_TYPE_DEFAULT;
2436 rdev->pm.default_power_state_index = state_index;
2437 rdev->pm.power_state[state_index].default_clock_mode =
2438 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2439 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2440 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2441 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2442 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2443 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2444 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2445 } else {
2446 u16 max_vddci = 0;
2447
2448 if (ASIC_IS_DCE4(rdev))
2449 radeon_atom_get_max_voltage(rdev,
2450 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2451 &max_vddci);
2452 /* patch the table values with the default sclk/mclk from firmware info */
2453 for (j = 0; j < mode_index; j++) {
2454 rdev->pm.power_state[state_index].clock_info[j].mclk =
2455 rdev->clock.default_mclk;
2456 rdev->pm.power_state[state_index].clock_info[j].sclk =
2457 rdev->clock.default_sclk;
2458 if (vddc)
2459 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2460 vddc;
2461 if (max_vddci)
2462 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2463 max_vddci;
2464 }
2465 }
2466 }
2467 }
2468
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2469 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2470 int state_index, int mode_index,
2471 union pplib_clock_info *clock_info)
2472 {
2473 u32 sclk, mclk;
2474 u16 vddc;
2475
2476 if (rdev->flags & RADEON_IS_IGP) {
2477 if (rdev->family >= CHIP_PALM) {
2478 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2479 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2480 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2481 } else {
2482 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2483 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2484 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2485 }
2486 } else if (rdev->family >= CHIP_BONAIRE) {
2487 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2488 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2489 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2490 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2491 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2492 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2493 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2494 VOLTAGE_NONE;
2495 } else if (rdev->family >= CHIP_TAHITI) {
2496 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2497 sclk |= clock_info->si.ucEngineClockHigh << 16;
2498 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2499 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2500 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2501 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2503 VOLTAGE_SW;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2505 le16_to_cpu(clock_info->si.usVDDC);
2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2507 le16_to_cpu(clock_info->si.usVDDCI);
2508 } else if (rdev->family >= CHIP_CEDAR) {
2509 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2510 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2511 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2512 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2513 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2514 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2515 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2516 VOLTAGE_SW;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2518 le16_to_cpu(clock_info->evergreen.usVDDC);
2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2520 le16_to_cpu(clock_info->evergreen.usVDDCI);
2521 } else {
2522 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2523 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2524 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2525 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2526 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2527 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2528 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2529 VOLTAGE_SW;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2531 le16_to_cpu(clock_info->r600.usVDDC);
2532 }
2533
2534 /* patch up vddc if necessary */
2535 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2536 case ATOM_VIRTUAL_VOLTAGE_ID0:
2537 case ATOM_VIRTUAL_VOLTAGE_ID1:
2538 case ATOM_VIRTUAL_VOLTAGE_ID2:
2539 case ATOM_VIRTUAL_VOLTAGE_ID3:
2540 case ATOM_VIRTUAL_VOLTAGE_ID4:
2541 case ATOM_VIRTUAL_VOLTAGE_ID5:
2542 case ATOM_VIRTUAL_VOLTAGE_ID6:
2543 case ATOM_VIRTUAL_VOLTAGE_ID7:
2544 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2545 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2546 &vddc) == 0)
2547 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2548 break;
2549 default:
2550 break;
2551 }
2552
2553 if (rdev->flags & RADEON_IS_IGP) {
2554 /* skip invalid modes */
2555 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2556 return false;
2557 } else {
2558 /* skip invalid modes */
2559 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2560 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2561 return false;
2562 }
2563 return true;
2564 }
2565
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2566 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2567 {
2568 struct radeon_mode_info *mode_info = &rdev->mode_info;
2569 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2570 union pplib_power_state *power_state;
2571 int i, j;
2572 int state_index = 0, mode_index = 0;
2573 union pplib_clock_info *clock_info;
2574 bool valid;
2575 union power_info *power_info;
2576 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2577 u16 data_offset;
2578 u8 frev, crev;
2579
2580 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2581 &frev, &crev, &data_offset))
2582 return state_index;
2583 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2584
2585 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2586 if (power_info->pplib.ucNumStates == 0)
2587 return state_index;
2588 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2589 sizeof(struct radeon_power_state),
2590 GFP_KERNEL);
2591 if (!rdev->pm.power_state)
2592 return state_index;
2593 /* first mode is usually default, followed by low to high */
2594 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2595 mode_index = 0;
2596 power_state = (union pplib_power_state *)
2597 (mode_info->atom_context->bios + data_offset +
2598 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2599 i * power_info->pplib.ucStateEntrySize);
2600 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2601 (mode_info->atom_context->bios + data_offset +
2602 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2603 (power_state->v1.ucNonClockStateIndex *
2604 power_info->pplib.ucNonClockSize));
2605 rdev->pm.power_state[i].clock_info =
2606 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2607 (power_info->pplib.ucStateEntrySize - 1) : 1,
2608 sizeof(struct radeon_pm_clock_info),
2609 GFP_KERNEL);
2610 if (!rdev->pm.power_state[i].clock_info)
2611 return state_index;
2612 if (power_info->pplib.ucStateEntrySize - 1) {
2613 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2614 clock_info = (union pplib_clock_info *)
2615 (mode_info->atom_context->bios + data_offset +
2616 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2617 (power_state->v1.ucClockStateIndices[j] *
2618 power_info->pplib.ucClockInfoSize));
2619 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2620 state_index, mode_index,
2621 clock_info);
2622 if (valid)
2623 mode_index++;
2624 }
2625 } else {
2626 rdev->pm.power_state[state_index].clock_info[0].mclk =
2627 rdev->clock.default_mclk;
2628 rdev->pm.power_state[state_index].clock_info[0].sclk =
2629 rdev->clock.default_sclk;
2630 mode_index++;
2631 }
2632 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2633 if (mode_index) {
2634 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2635 non_clock_info);
2636 state_index++;
2637 }
2638 }
2639 /* if multiple clock modes, mark the lowest as no display */
2640 for (i = 0; i < state_index; i++) {
2641 if (rdev->pm.power_state[i].num_clock_modes > 1)
2642 rdev->pm.power_state[i].clock_info[0].flags |=
2643 RADEON_PM_MODE_NO_DISPLAY;
2644 }
2645 /* first mode is usually default */
2646 if (rdev->pm.default_power_state_index == -1) {
2647 rdev->pm.power_state[0].type =
2648 POWER_STATE_TYPE_DEFAULT;
2649 rdev->pm.default_power_state_index = 0;
2650 rdev->pm.power_state[0].default_clock_mode =
2651 &rdev->pm.power_state[0].clock_info[0];
2652 }
2653 return state_index;
2654 }
2655
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2656 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2657 {
2658 struct radeon_mode_info *mode_info = &rdev->mode_info;
2659 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2660 union pplib_power_state *power_state;
2661 int i, j, non_clock_array_index, clock_array_index;
2662 int state_index = 0, mode_index = 0;
2663 union pplib_clock_info *clock_info;
2664 struct _StateArray *state_array;
2665 struct _ClockInfoArray *clock_info_array;
2666 struct _NonClockInfoArray *non_clock_info_array;
2667 bool valid;
2668 union power_info *power_info;
2669 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2670 u16 data_offset;
2671 u8 frev, crev;
2672 u8 *power_state_offset;
2673
2674 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2675 &frev, &crev, &data_offset))
2676 return state_index;
2677 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2678
2679 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2680 state_array = (struct _StateArray *)
2681 (mode_info->atom_context->bios + data_offset +
2682 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2683 clock_info_array = (struct _ClockInfoArray *)
2684 (mode_info->atom_context->bios + data_offset +
2685 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2686 non_clock_info_array = (struct _NonClockInfoArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2689 if (state_array->ucNumEntries == 0)
2690 return state_index;
2691 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2692 sizeof(struct radeon_power_state),
2693 GFP_KERNEL);
2694 if (!rdev->pm.power_state)
2695 return state_index;
2696 power_state_offset = (u8 *)state_array->states;
2697 for (i = 0; i < state_array->ucNumEntries; i++) {
2698 mode_index = 0;
2699 power_state = (union pplib_power_state *)power_state_offset;
2700 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2701 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2702 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2703 rdev->pm.power_state[i].clock_info =
2704 kcalloc(power_state->v2.ucNumDPMLevels ?
2705 power_state->v2.ucNumDPMLevels : 1,
2706 sizeof(struct radeon_pm_clock_info),
2707 GFP_KERNEL);
2708 if (!rdev->pm.power_state[i].clock_info)
2709 return state_index;
2710 if (power_state->v2.ucNumDPMLevels) {
2711 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2712 clock_array_index = power_state->v2.clockInfoIndex[j];
2713 clock_info = (union pplib_clock_info *)
2714 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2715 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2716 state_index, mode_index,
2717 clock_info);
2718 if (valid)
2719 mode_index++;
2720 }
2721 } else {
2722 rdev->pm.power_state[state_index].clock_info[0].mclk =
2723 rdev->clock.default_mclk;
2724 rdev->pm.power_state[state_index].clock_info[0].sclk =
2725 rdev->clock.default_sclk;
2726 mode_index++;
2727 }
2728 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2729 if (mode_index) {
2730 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2731 non_clock_info);
2732 state_index++;
2733 }
2734 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2735 }
2736 /* if multiple clock modes, mark the lowest as no display */
2737 for (i = 0; i < state_index; i++) {
2738 if (rdev->pm.power_state[i].num_clock_modes > 1)
2739 rdev->pm.power_state[i].clock_info[0].flags |=
2740 RADEON_PM_MODE_NO_DISPLAY;
2741 }
2742 /* first mode is usually default */
2743 if (rdev->pm.default_power_state_index == -1) {
2744 rdev->pm.power_state[0].type =
2745 POWER_STATE_TYPE_DEFAULT;
2746 rdev->pm.default_power_state_index = 0;
2747 rdev->pm.power_state[0].default_clock_mode =
2748 &rdev->pm.power_state[0].clock_info[0];
2749 }
2750 return state_index;
2751 }
2752
radeon_atombios_get_power_modes(struct radeon_device * rdev)2753 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2754 {
2755 struct radeon_mode_info *mode_info = &rdev->mode_info;
2756 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2757 u16 data_offset;
2758 u8 frev, crev;
2759 int state_index = 0;
2760
2761 rdev->pm.default_power_state_index = -1;
2762
2763 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2764 &frev, &crev, &data_offset)) {
2765 switch (frev) {
2766 case 1:
2767 case 2:
2768 case 3:
2769 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2770 break;
2771 case 4:
2772 case 5:
2773 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2774 break;
2775 case 6:
2776 state_index = radeon_atombios_parse_power_table_6(rdev);
2777 break;
2778 default:
2779 break;
2780 }
2781 }
2782
2783 if (state_index == 0) {
2784 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2785 if (rdev->pm.power_state) {
2786 rdev->pm.power_state[0].clock_info =
2787 kcalloc(1,
2788 sizeof(struct radeon_pm_clock_info),
2789 GFP_KERNEL);
2790 if (rdev->pm.power_state[0].clock_info) {
2791 /* add the default mode */
2792 rdev->pm.power_state[state_index].type =
2793 POWER_STATE_TYPE_DEFAULT;
2794 rdev->pm.power_state[state_index].num_clock_modes = 1;
2795 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2796 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2797 rdev->pm.power_state[state_index].default_clock_mode =
2798 &rdev->pm.power_state[state_index].clock_info[0];
2799 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2800 rdev->pm.power_state[state_index].pcie_lanes = 16;
2801 rdev->pm.default_power_state_index = state_index;
2802 rdev->pm.power_state[state_index].flags = 0;
2803 state_index++;
2804 }
2805 }
2806 }
2807
2808 rdev->pm.num_power_states = state_index;
2809
2810 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2811 rdev->pm.current_clock_mode_index = 0;
2812 if (rdev->pm.default_power_state_index >= 0)
2813 rdev->pm.current_vddc =
2814 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2815 else
2816 rdev->pm.current_vddc = 0;
2817 }
2818
2819 union get_clock_dividers {
2820 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2821 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2822 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2823 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2824 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2825 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2826 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2827 };
2828
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2829 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2830 u8 clock_type,
2831 u32 clock,
2832 bool strobe_mode,
2833 struct atom_clock_dividers *dividers)
2834 {
2835 union get_clock_dividers args;
2836 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2837 u8 frev, crev;
2838
2839 memset(&args, 0, sizeof(args));
2840 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2841
2842 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2843 return -EINVAL;
2844
2845 switch (crev) {
2846 case 1:
2847 /* r4xx, r5xx */
2848 args.v1.ucAction = clock_type;
2849 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2850
2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2852
2853 dividers->post_div = args.v1.ucPostDiv;
2854 dividers->fb_div = args.v1.ucFbDiv;
2855 dividers->enable_post_div = true;
2856 break;
2857 case 2:
2858 case 3:
2859 case 5:
2860 /* r6xx, r7xx, evergreen, ni, si */
2861 if (rdev->family <= CHIP_RV770) {
2862 args.v2.ucAction = clock_type;
2863 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2864
2865 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2866
2867 dividers->post_div = args.v2.ucPostDiv;
2868 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2869 dividers->ref_div = args.v2.ucAction;
2870 if (rdev->family == CHIP_RV770) {
2871 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2872 true : false;
2873 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2874 } else
2875 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2876 } else {
2877 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2878 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2879
2880 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2881
2882 dividers->post_div = args.v3.ucPostDiv;
2883 dividers->enable_post_div = (args.v3.ucCntlFlag &
2884 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2885 dividers->enable_dithen = (args.v3.ucCntlFlag &
2886 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2887 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2888 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2889 dividers->ref_div = args.v3.ucRefDiv;
2890 dividers->vco_mode = (args.v3.ucCntlFlag &
2891 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2892 } else {
2893 /* for SI we use ComputeMemoryClockParam for memory plls */
2894 if (rdev->family >= CHIP_TAHITI)
2895 return -EINVAL;
2896 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2897 if (strobe_mode)
2898 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2899
2900 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2901
2902 dividers->post_div = args.v5.ucPostDiv;
2903 dividers->enable_post_div = (args.v5.ucCntlFlag &
2904 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2905 dividers->enable_dithen = (args.v5.ucCntlFlag &
2906 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2907 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2908 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2909 dividers->ref_div = args.v5.ucRefDiv;
2910 dividers->vco_mode = (args.v5.ucCntlFlag &
2911 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2912 }
2913 }
2914 break;
2915 case 4:
2916 /* fusion */
2917 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2918
2919 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2920
2921 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2922 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2923 break;
2924 case 6:
2925 /* CI */
2926 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2927 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2928 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2929
2930 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2931
2932 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2933 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2934 dividers->ref_div = args.v6_out.ucPllRefDiv;
2935 dividers->post_div = args.v6_out.ucPllPostDiv;
2936 dividers->flags = args.v6_out.ucPllCntlFlag;
2937 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2938 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2939 break;
2940 default:
2941 return -EINVAL;
2942 }
2943 return 0;
2944 }
2945
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2946 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2947 u32 clock,
2948 bool strobe_mode,
2949 struct atom_mpll_param *mpll_param)
2950 {
2951 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2952 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2953 u8 frev, crev;
2954
2955 memset(&args, 0, sizeof(args));
2956 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2957
2958 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2959 return -EINVAL;
2960
2961 switch (frev) {
2962 case 2:
2963 switch (crev) {
2964 case 1:
2965 /* SI */
2966 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2967 args.ucInputFlag = 0;
2968 if (strobe_mode)
2969 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2970
2971 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2972
2973 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2974 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2975 mpll_param->post_div = args.ucPostDiv;
2976 mpll_param->dll_speed = args.ucDllSpeed;
2977 mpll_param->bwcntl = args.ucBWCntl;
2978 mpll_param->vco_mode =
2979 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2980 mpll_param->yclk_sel =
2981 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2982 mpll_param->qdr =
2983 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2984 mpll_param->half_rate =
2985 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2986 break;
2987 default:
2988 return -EINVAL;
2989 }
2990 break;
2991 default:
2992 return -EINVAL;
2993 }
2994 return 0;
2995 }
2996
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2997 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2998 {
2999 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3000 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3001
3002 args.ucEnable = enable;
3003
3004 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3005 }
3006
radeon_atom_get_engine_clock(struct radeon_device * rdev)3007 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3008 {
3009 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3010 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3011
3012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3013 return le32_to_cpu(args.ulReturnEngineClock);
3014 }
3015
radeon_atom_get_memory_clock(struct radeon_device * rdev)3016 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3017 {
3018 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3019 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3020
3021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3022 return le32_to_cpu(args.ulReturnMemoryClock);
3023 }
3024
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3025 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3026 uint32_t eng_clock)
3027 {
3028 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3029 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3030
3031 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3032
3033 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3034 }
3035
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3036 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3037 uint32_t mem_clock)
3038 {
3039 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3040 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3041
3042 if (rdev->flags & RADEON_IS_IGP)
3043 return;
3044
3045 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3046
3047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3048 }
3049
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3050 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3051 u32 eng_clock, u32 mem_clock)
3052 {
3053 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3054 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3055 u32 tmp;
3056
3057 memset(&args, 0, sizeof(args));
3058
3059 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3060 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3061
3062 args.ulTargetEngineClock = cpu_to_le32(tmp);
3063 if (mem_clock)
3064 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3065
3066 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3067 }
3068
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3069 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3070 u32 mem_clock)
3071 {
3072 u32 args;
3073 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3074
3075 args = cpu_to_le32(mem_clock); /* 10 khz */
3076
3077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3078 }
3079
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3080 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3081 u32 mem_clock)
3082 {
3083 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3084 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3085 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3086
3087 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3088
3089 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3090 }
3091
3092 union set_voltage {
3093 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3094 struct _SET_VOLTAGE_PARAMETERS v1;
3095 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3096 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3097 };
3098
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3099 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3100 {
3101 union set_voltage args;
3102 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3103 u8 frev, crev, volt_index = voltage_level;
3104
3105 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3106 return;
3107
3108 /* 0xff01 is a flag rather then an actual voltage */
3109 if (voltage_level == 0xff01)
3110 return;
3111
3112 switch (crev) {
3113 case 1:
3114 args.v1.ucVoltageType = voltage_type;
3115 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3116 args.v1.ucVoltageIndex = volt_index;
3117 break;
3118 case 2:
3119 args.v2.ucVoltageType = voltage_type;
3120 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3121 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3122 break;
3123 case 3:
3124 args.v3.ucVoltageType = voltage_type;
3125 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3126 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3127 break;
3128 default:
3129 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3130 return;
3131 }
3132
3133 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3134 }
3135
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3136 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3137 u16 voltage_id, u16 *voltage)
3138 {
3139 union set_voltage args;
3140 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3141 u8 frev, crev;
3142
3143 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3144 return -EINVAL;
3145
3146 switch (crev) {
3147 case 1:
3148 return -EINVAL;
3149 case 2:
3150 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3151 args.v2.ucVoltageMode = 0;
3152 args.v2.usVoltageLevel = 0;
3153
3154 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3155
3156 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3157 break;
3158 case 3:
3159 args.v3.ucVoltageType = voltage_type;
3160 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3161 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3162
3163 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3164
3165 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3166 break;
3167 default:
3168 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3169 return -EINVAL;
3170 }
3171
3172 return 0;
3173 }
3174
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3175 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3176 u16 *voltage,
3177 u16 leakage_idx)
3178 {
3179 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3180 }
3181
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3182 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3183 u16 *leakage_id)
3184 {
3185 union set_voltage args;
3186 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3187 u8 frev, crev;
3188
3189 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3190 return -EINVAL;
3191
3192 switch (crev) {
3193 case 3:
3194 case 4:
3195 args.v3.ucVoltageType = 0;
3196 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3197 args.v3.usVoltageLevel = 0;
3198
3199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3200
3201 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3202 break;
3203 default:
3204 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3205 return -EINVAL;
3206 }
3207
3208 return 0;
3209 }
3210
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3211 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3212 u16 *vddc, u16 *vddci,
3213 u16 virtual_voltage_id,
3214 u16 vbios_voltage_id)
3215 {
3216 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3217 u8 frev, crev;
3218 u16 data_offset, size;
3219 int i, j;
3220 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3221 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3222
3223 *vddc = 0;
3224 *vddci = 0;
3225
3226 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3227 &frev, &crev, &data_offset))
3228 return -EINVAL;
3229
3230 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3231 (rdev->mode_info.atom_context->bios + data_offset);
3232
3233 switch (frev) {
3234 case 1:
3235 return -EINVAL;
3236 case 2:
3237 switch (crev) {
3238 case 1:
3239 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3240 return -EINVAL;
3241 leakage_bin = (u16 *)
3242 (rdev->mode_info.atom_context->bios + data_offset +
3243 le16_to_cpu(profile->usLeakageBinArrayOffset));
3244 vddc_id_buf = (u16 *)
3245 (rdev->mode_info.atom_context->bios + data_offset +
3246 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3247 vddc_buf = (u16 *)
3248 (rdev->mode_info.atom_context->bios + data_offset +
3249 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3250 vddci_id_buf = (u16 *)
3251 (rdev->mode_info.atom_context->bios + data_offset +
3252 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3253 vddci_buf = (u16 *)
3254 (rdev->mode_info.atom_context->bios + data_offset +
3255 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3256
3257 if (profile->ucElbVDDC_Num > 0) {
3258 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3259 if (vddc_id_buf[i] == virtual_voltage_id) {
3260 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3261 if (vbios_voltage_id <= leakage_bin[j]) {
3262 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3263 break;
3264 }
3265 }
3266 break;
3267 }
3268 }
3269 }
3270 if (profile->ucElbVDDCI_Num > 0) {
3271 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3272 if (vddci_id_buf[i] == virtual_voltage_id) {
3273 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3274 if (vbios_voltage_id <= leakage_bin[j]) {
3275 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3276 break;
3277 }
3278 }
3279 break;
3280 }
3281 }
3282 }
3283 break;
3284 default:
3285 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3286 return -EINVAL;
3287 }
3288 break;
3289 default:
3290 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3291 return -EINVAL;
3292 }
3293
3294 return 0;
3295 }
3296
3297 union get_voltage_info {
3298 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3299 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3300 };
3301
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3302 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3303 u16 virtual_voltage_id,
3304 u16 *voltage)
3305 {
3306 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3307 u32 entry_id;
3308 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3309 union get_voltage_info args;
3310
3311 for (entry_id = 0; entry_id < count; entry_id++) {
3312 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3313 virtual_voltage_id)
3314 break;
3315 }
3316
3317 if (entry_id >= count)
3318 return -EINVAL;
3319
3320 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3321 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3322 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3323 args.in.ulSCLKFreq =
3324 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3325
3326 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3327
3328 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3329
3330 return 0;
3331 }
3332
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3333 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3334 u16 voltage_level, u8 voltage_type,
3335 u32 *gpio_value, u32 *gpio_mask)
3336 {
3337 union set_voltage args;
3338 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3339 u8 frev, crev;
3340
3341 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3342 return -EINVAL;
3343
3344 switch (crev) {
3345 case 1:
3346 return -EINVAL;
3347 case 2:
3348 args.v2.ucVoltageType = voltage_type;
3349 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3350 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3351
3352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3353
3354 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3355
3356 args.v2.ucVoltageType = voltage_type;
3357 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3358 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3359
3360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3361
3362 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3363 break;
3364 default:
3365 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3366 return -EINVAL;
3367 }
3368
3369 return 0;
3370 }
3371
3372 union voltage_object_info {
3373 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3374 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3375 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3376 };
3377
3378 union voltage_object {
3379 struct _ATOM_VOLTAGE_OBJECT v1;
3380 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3381 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3382 };
3383
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3384 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3385 u8 voltage_type)
3386 {
3387 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3388 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3389 u8 *start = (u8 *)v1;
3390
3391 while (offset < size) {
3392 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3393 if (vo->ucVoltageType == voltage_type)
3394 return vo;
3395 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3396 vo->asFormula.ucNumOfVoltageEntries;
3397 }
3398 return NULL;
3399 }
3400
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3401 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3402 u8 voltage_type)
3403 {
3404 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3405 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3406 u8 *start = (u8*)v2;
3407
3408 while (offset < size) {
3409 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3410 if (vo->ucVoltageType == voltage_type)
3411 return vo;
3412 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3413 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3414 }
3415 return NULL;
3416 }
3417
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3418 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3419 u8 voltage_type, u8 voltage_mode)
3420 {
3421 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3422 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3423 u8 *start = (u8*)v3;
3424
3425 while (offset < size) {
3426 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3427 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3428 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3429 return vo;
3430 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3431 }
3432 return NULL;
3433 }
3434
3435 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3436 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3437 u8 voltage_type, u8 voltage_mode)
3438 {
3439 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3440 u8 frev, crev;
3441 u16 data_offset, size;
3442 union voltage_object_info *voltage_info;
3443 union voltage_object *voltage_object = NULL;
3444
3445 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3446 &frev, &crev, &data_offset)) {
3447 voltage_info = (union voltage_object_info *)
3448 (rdev->mode_info.atom_context->bios + data_offset);
3449
3450 switch (frev) {
3451 case 1:
3452 case 2:
3453 switch (crev) {
3454 case 1:
3455 voltage_object = (union voltage_object *)
3456 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3457 if (voltage_object &&
3458 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3459 return true;
3460 break;
3461 case 2:
3462 voltage_object = (union voltage_object *)
3463 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3464 if (voltage_object &&
3465 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3466 return true;
3467 break;
3468 default:
3469 DRM_ERROR("unknown voltage object table\n");
3470 return false;
3471 }
3472 break;
3473 case 3:
3474 switch (crev) {
3475 case 1:
3476 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3477 voltage_type, voltage_mode))
3478 return true;
3479 break;
3480 default:
3481 DRM_ERROR("unknown voltage object table\n");
3482 return false;
3483 }
3484 break;
3485 default:
3486 DRM_ERROR("unknown voltage object table\n");
3487 return false;
3488 }
3489
3490 }
3491 return false;
3492 }
3493
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3494 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3495 u8 voltage_type,
3496 u8 *svd_gpio_id, u8 *svc_gpio_id)
3497 {
3498 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3499 u8 frev, crev;
3500 u16 data_offset, size;
3501 union voltage_object_info *voltage_info;
3502 union voltage_object *voltage_object = NULL;
3503
3504 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3505 &frev, &crev, &data_offset)) {
3506 voltage_info = (union voltage_object_info *)
3507 (rdev->mode_info.atom_context->bios + data_offset);
3508
3509 switch (frev) {
3510 case 3:
3511 switch (crev) {
3512 case 1:
3513 voltage_object = (union voltage_object *)
3514 atom_lookup_voltage_object_v3(&voltage_info->v3,
3515 voltage_type,
3516 VOLTAGE_OBJ_SVID2);
3517 if (voltage_object) {
3518 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3519 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3520 } else {
3521 return -EINVAL;
3522 }
3523 break;
3524 default:
3525 DRM_ERROR("unknown voltage object table\n");
3526 return -EINVAL;
3527 }
3528 break;
3529 default:
3530 DRM_ERROR("unknown voltage object table\n");
3531 return -EINVAL;
3532 }
3533
3534 }
3535 return 0;
3536 }
3537
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3538 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3539 u8 voltage_type, u16 *max_voltage)
3540 {
3541 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3542 u8 frev, crev;
3543 u16 data_offset, size;
3544 union voltage_object_info *voltage_info;
3545 union voltage_object *voltage_object = NULL;
3546
3547 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3548 &frev, &crev, &data_offset)) {
3549 voltage_info = (union voltage_object_info *)
3550 (rdev->mode_info.atom_context->bios + data_offset);
3551
3552 switch (crev) {
3553 case 1:
3554 voltage_object = (union voltage_object *)
3555 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3556 if (voltage_object) {
3557 ATOM_VOLTAGE_FORMULA *formula =
3558 &voltage_object->v1.asFormula;
3559 if (formula->ucFlag & 1)
3560 *max_voltage =
3561 le16_to_cpu(formula->usVoltageBaseLevel) +
3562 formula->ucNumOfVoltageEntries / 2 *
3563 le16_to_cpu(formula->usVoltageStep);
3564 else
3565 *max_voltage =
3566 le16_to_cpu(formula->usVoltageBaseLevel) +
3567 (formula->ucNumOfVoltageEntries - 1) *
3568 le16_to_cpu(formula->usVoltageStep);
3569 return 0;
3570 }
3571 break;
3572 case 2:
3573 voltage_object = (union voltage_object *)
3574 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3575 if (voltage_object) {
3576 ATOM_VOLTAGE_FORMULA_V2 *formula =
3577 &voltage_object->v2.asFormula;
3578 if (formula->ucNumOfVoltageEntries) {
3579 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3580 ((u8 *)&formula->asVIDAdjustEntries[0] +
3581 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3582 *max_voltage =
3583 le16_to_cpu(lut->usVoltageValue);
3584 return 0;
3585 }
3586 }
3587 break;
3588 default:
3589 DRM_ERROR("unknown voltage object table\n");
3590 return -EINVAL;
3591 }
3592
3593 }
3594 return -EINVAL;
3595 }
3596
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3597 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3598 u8 voltage_type, u16 *min_voltage)
3599 {
3600 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3601 u8 frev, crev;
3602 u16 data_offset, size;
3603 union voltage_object_info *voltage_info;
3604 union voltage_object *voltage_object = NULL;
3605
3606 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3607 &frev, &crev, &data_offset)) {
3608 voltage_info = (union voltage_object_info *)
3609 (rdev->mode_info.atom_context->bios + data_offset);
3610
3611 switch (crev) {
3612 case 1:
3613 voltage_object = (union voltage_object *)
3614 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3615 if (voltage_object) {
3616 ATOM_VOLTAGE_FORMULA *formula =
3617 &voltage_object->v1.asFormula;
3618 *min_voltage =
3619 le16_to_cpu(formula->usVoltageBaseLevel);
3620 return 0;
3621 }
3622 break;
3623 case 2:
3624 voltage_object = (union voltage_object *)
3625 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3626 if (voltage_object) {
3627 ATOM_VOLTAGE_FORMULA_V2 *formula =
3628 &voltage_object->v2.asFormula;
3629 if (formula->ucNumOfVoltageEntries) {
3630 *min_voltage =
3631 le16_to_cpu(formula->asVIDAdjustEntries[
3632 0
3633 ].usVoltageValue);
3634 return 0;
3635 }
3636 }
3637 break;
3638 default:
3639 DRM_ERROR("unknown voltage object table\n");
3640 return -EINVAL;
3641 }
3642
3643 }
3644 return -EINVAL;
3645 }
3646
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3647 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3648 u8 voltage_type, u16 *voltage_step)
3649 {
3650 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3651 u8 frev, crev;
3652 u16 data_offset, size;
3653 union voltage_object_info *voltage_info;
3654 union voltage_object *voltage_object = NULL;
3655
3656 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3657 &frev, &crev, &data_offset)) {
3658 voltage_info = (union voltage_object_info *)
3659 (rdev->mode_info.atom_context->bios + data_offset);
3660
3661 switch (crev) {
3662 case 1:
3663 voltage_object = (union voltage_object *)
3664 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3665 if (voltage_object) {
3666 ATOM_VOLTAGE_FORMULA *formula =
3667 &voltage_object->v1.asFormula;
3668 if (formula->ucFlag & 1)
3669 *voltage_step =
3670 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3671 else
3672 *voltage_step =
3673 le16_to_cpu(formula->usVoltageStep);
3674 return 0;
3675 }
3676 break;
3677 case 2:
3678 return -EINVAL;
3679 default:
3680 DRM_ERROR("unknown voltage object table\n");
3681 return -EINVAL;
3682 }
3683
3684 }
3685 return -EINVAL;
3686 }
3687
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3688 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3689 u8 voltage_type,
3690 u16 nominal_voltage,
3691 u16 *true_voltage)
3692 {
3693 u16 min_voltage, max_voltage, voltage_step;
3694
3695 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3696 return -EINVAL;
3697 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3698 return -EINVAL;
3699 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3700 return -EINVAL;
3701
3702 if (nominal_voltage <= min_voltage)
3703 *true_voltage = min_voltage;
3704 else if (nominal_voltage >= max_voltage)
3705 *true_voltage = max_voltage;
3706 else
3707 *true_voltage = min_voltage +
3708 ((nominal_voltage - min_voltage) / voltage_step) *
3709 voltage_step;
3710
3711 return 0;
3712 }
3713
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3714 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3715 u8 voltage_type, u8 voltage_mode,
3716 struct atom_voltage_table *voltage_table)
3717 {
3718 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3719 u8 frev, crev;
3720 u16 data_offset, size;
3721 int i, ret;
3722 union voltage_object_info *voltage_info;
3723 union voltage_object *voltage_object = NULL;
3724
3725 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3726 &frev, &crev, &data_offset)) {
3727 voltage_info = (union voltage_object_info *)
3728 (rdev->mode_info.atom_context->bios + data_offset);
3729
3730 switch (frev) {
3731 case 1:
3732 case 2:
3733 switch (crev) {
3734 case 1:
3735 DRM_ERROR("old table version %d, %d\n", frev, crev);
3736 return -EINVAL;
3737 case 2:
3738 voltage_object = (union voltage_object *)
3739 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3740 if (voltage_object) {
3741 ATOM_VOLTAGE_FORMULA_V2 *formula =
3742 &voltage_object->v2.asFormula;
3743 VOLTAGE_LUT_ENTRY *lut;
3744 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3745 return -EINVAL;
3746 lut = &formula->asVIDAdjustEntries[0];
3747 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3748 voltage_table->entries[i].value =
3749 le16_to_cpu(lut->usVoltageValue);
3750 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3751 voltage_table->entries[i].value,
3752 voltage_type,
3753 &voltage_table->entries[i].smio_low,
3754 &voltage_table->mask_low);
3755 if (ret)
3756 return ret;
3757 lut = (VOLTAGE_LUT_ENTRY *)
3758 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3759 }
3760 voltage_table->count = formula->ucNumOfVoltageEntries;
3761 return 0;
3762 }
3763 break;
3764 default:
3765 DRM_ERROR("unknown voltage object table\n");
3766 return -EINVAL;
3767 }
3768 break;
3769 case 3:
3770 switch (crev) {
3771 case 1:
3772 voltage_object = (union voltage_object *)
3773 atom_lookup_voltage_object_v3(&voltage_info->v3,
3774 voltage_type, voltage_mode);
3775 if (voltage_object) {
3776 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3777 &voltage_object->v3.asGpioVoltageObj;
3778 VOLTAGE_LUT_ENTRY_V2 *lut;
3779 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3780 return -EINVAL;
3781 lut = &gpio->asVolGpioLut[0];
3782 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3783 voltage_table->entries[i].value =
3784 le16_to_cpu(lut->usVoltageValue);
3785 voltage_table->entries[i].smio_low =
3786 le32_to_cpu(lut->ulVoltageId);
3787 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3788 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3789 }
3790 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3791 voltage_table->count = gpio->ucGpioEntryNum;
3792 voltage_table->phase_delay = gpio->ucPhaseDelay;
3793 return 0;
3794 }
3795 break;
3796 default:
3797 DRM_ERROR("unknown voltage object table\n");
3798 return -EINVAL;
3799 }
3800 break;
3801 default:
3802 DRM_ERROR("unknown voltage object table\n");
3803 return -EINVAL;
3804 }
3805 }
3806 return -EINVAL;
3807 }
3808
3809 union vram_info {
3810 struct _ATOM_VRAM_INFO_V3 v1_3;
3811 struct _ATOM_VRAM_INFO_V4 v1_4;
3812 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3813 };
3814
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3815 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3816 u8 module_index, struct atom_memory_info *mem_info)
3817 {
3818 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3819 u8 frev, crev, i;
3820 u16 data_offset, size;
3821 union vram_info *vram_info;
3822
3823 memset(mem_info, 0, sizeof(struct atom_memory_info));
3824
3825 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3826 &frev, &crev, &data_offset)) {
3827 vram_info = (union vram_info *)
3828 (rdev->mode_info.atom_context->bios + data_offset);
3829 switch (frev) {
3830 case 1:
3831 switch (crev) {
3832 case 3:
3833 /* r6xx */
3834 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3835 ATOM_VRAM_MODULE_V3 *vram_module =
3836 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3837
3838 for (i = 0; i < module_index; i++) {
3839 if (le16_to_cpu(vram_module->usSize) == 0)
3840 return -EINVAL;
3841 vram_module = (ATOM_VRAM_MODULE_V3 *)
3842 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3843 }
3844 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3845 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3846 } else
3847 return -EINVAL;
3848 break;
3849 case 4:
3850 /* r7xx, evergreen */
3851 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3852 ATOM_VRAM_MODULE_V4 *vram_module =
3853 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3854
3855 for (i = 0; i < module_index; i++) {
3856 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3857 return -EINVAL;
3858 vram_module = (ATOM_VRAM_MODULE_V4 *)
3859 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3860 }
3861 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3862 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3863 } else
3864 return -EINVAL;
3865 break;
3866 default:
3867 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3868 return -EINVAL;
3869 }
3870 break;
3871 case 2:
3872 switch (crev) {
3873 case 1:
3874 /* ni */
3875 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3876 ATOM_VRAM_MODULE_V7 *vram_module =
3877 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3878
3879 for (i = 0; i < module_index; i++) {
3880 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3881 return -EINVAL;
3882 vram_module = (ATOM_VRAM_MODULE_V7 *)
3883 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3884 }
3885 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3886 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3887 } else
3888 return -EINVAL;
3889 break;
3890 default:
3891 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3892 return -EINVAL;
3893 }
3894 break;
3895 default:
3896 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3897 return -EINVAL;
3898 }
3899 return 0;
3900 }
3901 return -EINVAL;
3902 }
3903
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3904 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3905 bool gddr5, u8 module_index,
3906 struct atom_memory_clock_range_table *mclk_range_table)
3907 {
3908 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3909 u8 frev, crev, i;
3910 u16 data_offset, size;
3911 union vram_info *vram_info;
3912 u32 mem_timing_size = gddr5 ?
3913 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3914
3915 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3916
3917 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3918 &frev, &crev, &data_offset)) {
3919 vram_info = (union vram_info *)
3920 (rdev->mode_info.atom_context->bios + data_offset);
3921 switch (frev) {
3922 case 1:
3923 switch (crev) {
3924 case 3:
3925 DRM_ERROR("old table version %d, %d\n", frev, crev);
3926 return -EINVAL;
3927 case 4:
3928 /* r7xx, evergreen */
3929 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3930 ATOM_VRAM_MODULE_V4 *vram_module =
3931 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3932 ATOM_MEMORY_TIMING_FORMAT *format;
3933
3934 for (i = 0; i < module_index; i++) {
3935 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3936 return -EINVAL;
3937 vram_module = (ATOM_VRAM_MODULE_V4 *)
3938 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3939 }
3940 mclk_range_table->num_entries = (u8)
3941 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3942 mem_timing_size);
3943 format = &vram_module->asMemTiming[0];
3944 for (i = 0; i < mclk_range_table->num_entries; i++) {
3945 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3946 format = (ATOM_MEMORY_TIMING_FORMAT *)
3947 ((u8 *)format + mem_timing_size);
3948 }
3949 } else
3950 return -EINVAL;
3951 break;
3952 default:
3953 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3954 return -EINVAL;
3955 }
3956 break;
3957 case 2:
3958 DRM_ERROR("new table version %d, %d\n", frev, crev);
3959 return -EINVAL;
3960 default:
3961 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3962 return -EINVAL;
3963 }
3964 return 0;
3965 }
3966 return -EINVAL;
3967 }
3968
3969 #define MEM_ID_MASK 0xff000000
3970 #define MEM_ID_SHIFT 24
3971 #define CLOCK_RANGE_MASK 0x00ffffff
3972 #define CLOCK_RANGE_SHIFT 0
3973 #define LOW_NIBBLE_MASK 0xf
3974 #define DATA_EQU_PREV 0
3975 #define DATA_FROM_TABLE 4
3976
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3977 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3978 u8 module_index,
3979 struct atom_mc_reg_table *reg_table)
3980 {
3981 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3982 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3983 u32 i = 0, j;
3984 u16 data_offset, size;
3985 union vram_info *vram_info;
3986
3987 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3988
3989 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3990 &frev, &crev, &data_offset)) {
3991 vram_info = (union vram_info *)
3992 (rdev->mode_info.atom_context->bios + data_offset);
3993 switch (frev) {
3994 case 1:
3995 DRM_ERROR("old table version %d, %d\n", frev, crev);
3996 return -EINVAL;
3997 case 2:
3998 switch (crev) {
3999 case 1:
4000 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4001 ATOM_INIT_REG_BLOCK *reg_block =
4002 (ATOM_INIT_REG_BLOCK *)
4003 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4004 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4005 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4006 ((u8 *)reg_block + (2 * sizeof(u16)) +
4007 le16_to_cpu(reg_block->usRegIndexTblSize));
4008 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4009 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4010 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4011 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4012 return -EINVAL;
4013 while (i < num_entries) {
4014 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4015 break;
4016 reg_table->mc_reg_address[i].s1 =
4017 (u16)(le16_to_cpu(format->usRegIndex));
4018 reg_table->mc_reg_address[i].pre_reg_data =
4019 (u8)(format->ucPreRegDataLength);
4020 i++;
4021 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4022 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4023 }
4024 reg_table->last = i;
4025 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4026 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4027 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4028 >> MEM_ID_SHIFT);
4029 if (module_index == t_mem_id) {
4030 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4031 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4032 >> CLOCK_RANGE_SHIFT);
4033 for (i = 0, j = 1; i < reg_table->last; i++) {
4034 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4036 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4037 j++;
4038 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4039 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4040 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4041 }
4042 }
4043 num_ranges++;
4044 }
4045 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4046 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4047 }
4048 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4049 return -EINVAL;
4050 reg_table->num_entries = num_ranges;
4051 } else
4052 return -EINVAL;
4053 break;
4054 default:
4055 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4056 return -EINVAL;
4057 }
4058 break;
4059 default:
4060 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4061 return -EINVAL;
4062 }
4063 return 0;
4064 }
4065 return -EINVAL;
4066 }
4067
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4068 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4069 {
4070 struct radeon_device *rdev = dev->dev_private;
4071 uint32_t bios_2_scratch, bios_6_scratch;
4072
4073 if (rdev->family >= CHIP_R600) {
4074 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4075 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4076 } else {
4077 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4078 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4079 }
4080
4081 /* let the bios control the backlight */
4082 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4083
4084 /* tell the bios not to handle mode switching */
4085 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4086
4087 /* clear the vbios dpms state */
4088 if (ASIC_IS_DCE4(rdev))
4089 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4090
4091 if (rdev->family >= CHIP_R600) {
4092 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4093 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4094 } else {
4095 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4096 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4097 }
4098
4099 }
4100
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4101 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4102 {
4103 uint32_t scratch_reg;
4104 int i;
4105
4106 if (rdev->family >= CHIP_R600)
4107 scratch_reg = R600_BIOS_0_SCRATCH;
4108 else
4109 scratch_reg = RADEON_BIOS_0_SCRATCH;
4110
4111 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4112 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4113 }
4114
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4115 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4116 {
4117 uint32_t scratch_reg;
4118 int i;
4119
4120 if (rdev->family >= CHIP_R600)
4121 scratch_reg = R600_BIOS_0_SCRATCH;
4122 else
4123 scratch_reg = RADEON_BIOS_0_SCRATCH;
4124
4125 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4126 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4127 }
4128
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4129 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4130 {
4131 struct drm_device *dev = encoder->dev;
4132 struct radeon_device *rdev = dev->dev_private;
4133 uint32_t bios_6_scratch;
4134
4135 if (rdev->family >= CHIP_R600)
4136 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4137 else
4138 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4139
4140 if (lock) {
4141 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4142 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4143 } else {
4144 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4145 bios_6_scratch |= ATOM_S6_ACC_MODE;
4146 }
4147
4148 if (rdev->family >= CHIP_R600)
4149 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4150 else
4151 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4152 }
4153
4154 /* at some point we may want to break this out into individual functions */
4155 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4156 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4157 struct drm_encoder *encoder,
4158 bool connected)
4159 {
4160 struct drm_device *dev = connector->dev;
4161 struct radeon_device *rdev = dev->dev_private;
4162 struct radeon_connector *radeon_connector =
4163 to_radeon_connector(connector);
4164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4165 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4166
4167 if (rdev->family >= CHIP_R600) {
4168 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4169 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4170 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4171 } else {
4172 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4173 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4174 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4175 }
4176
4177 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4178 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4179 if (connected) {
4180 DRM_DEBUG_KMS("TV1 connected\n");
4181 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4182 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4183 } else {
4184 DRM_DEBUG_KMS("TV1 disconnected\n");
4185 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4186 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4187 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4188 }
4189 }
4190 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4191 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4192 if (connected) {
4193 DRM_DEBUG_KMS("CV connected\n");
4194 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4195 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4196 } else {
4197 DRM_DEBUG_KMS("CV disconnected\n");
4198 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4199 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4200 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4201 }
4202 }
4203 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4204 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4205 if (connected) {
4206 DRM_DEBUG_KMS("LCD1 connected\n");
4207 bios_0_scratch |= ATOM_S0_LCD1;
4208 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4209 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4210 } else {
4211 DRM_DEBUG_KMS("LCD1 disconnected\n");
4212 bios_0_scratch &= ~ATOM_S0_LCD1;
4213 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4214 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4215 }
4216 }
4217 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4218 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4219 if (connected) {
4220 DRM_DEBUG_KMS("CRT1 connected\n");
4221 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4222 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4223 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4224 } else {
4225 DRM_DEBUG_KMS("CRT1 disconnected\n");
4226 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4227 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4228 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4229 }
4230 }
4231 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4232 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4233 if (connected) {
4234 DRM_DEBUG_KMS("CRT2 connected\n");
4235 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4236 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4237 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4238 } else {
4239 DRM_DEBUG_KMS("CRT2 disconnected\n");
4240 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4241 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4242 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4243 }
4244 }
4245 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4246 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4247 if (connected) {
4248 DRM_DEBUG_KMS("DFP1 connected\n");
4249 bios_0_scratch |= ATOM_S0_DFP1;
4250 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4251 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4252 } else {
4253 DRM_DEBUG_KMS("DFP1 disconnected\n");
4254 bios_0_scratch &= ~ATOM_S0_DFP1;
4255 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4256 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4257 }
4258 }
4259 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4260 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4261 if (connected) {
4262 DRM_DEBUG_KMS("DFP2 connected\n");
4263 bios_0_scratch |= ATOM_S0_DFP2;
4264 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4265 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4266 } else {
4267 DRM_DEBUG_KMS("DFP2 disconnected\n");
4268 bios_0_scratch &= ~ATOM_S0_DFP2;
4269 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4270 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4271 }
4272 }
4273 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4274 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4275 if (connected) {
4276 DRM_DEBUG_KMS("DFP3 connected\n");
4277 bios_0_scratch |= ATOM_S0_DFP3;
4278 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4279 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4280 } else {
4281 DRM_DEBUG_KMS("DFP3 disconnected\n");
4282 bios_0_scratch &= ~ATOM_S0_DFP3;
4283 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4284 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4285 }
4286 }
4287 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4288 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4289 if (connected) {
4290 DRM_DEBUG_KMS("DFP4 connected\n");
4291 bios_0_scratch |= ATOM_S0_DFP4;
4292 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4293 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4294 } else {
4295 DRM_DEBUG_KMS("DFP4 disconnected\n");
4296 bios_0_scratch &= ~ATOM_S0_DFP4;
4297 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4298 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4299 }
4300 }
4301 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4302 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4303 if (connected) {
4304 DRM_DEBUG_KMS("DFP5 connected\n");
4305 bios_0_scratch |= ATOM_S0_DFP5;
4306 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4307 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4308 } else {
4309 DRM_DEBUG_KMS("DFP5 disconnected\n");
4310 bios_0_scratch &= ~ATOM_S0_DFP5;
4311 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4312 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4313 }
4314 }
4315 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4316 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4317 if (connected) {
4318 DRM_DEBUG_KMS("DFP6 connected\n");
4319 bios_0_scratch |= ATOM_S0_DFP6;
4320 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4321 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4322 } else {
4323 DRM_DEBUG_KMS("DFP6 disconnected\n");
4324 bios_0_scratch &= ~ATOM_S0_DFP6;
4325 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4326 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4327 }
4328 }
4329
4330 if (rdev->family >= CHIP_R600) {
4331 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4332 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4333 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4334 } else {
4335 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4336 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4337 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4338 }
4339 }
4340
4341 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4342 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4343 {
4344 struct drm_device *dev = encoder->dev;
4345 struct radeon_device *rdev = dev->dev_private;
4346 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4347 uint32_t bios_3_scratch;
4348
4349 if (ASIC_IS_DCE4(rdev))
4350 return;
4351
4352 if (rdev->family >= CHIP_R600)
4353 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4354 else
4355 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4356
4357 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4358 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4359 bios_3_scratch |= (crtc << 18);
4360 }
4361 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4362 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4363 bios_3_scratch |= (crtc << 24);
4364 }
4365 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4366 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4367 bios_3_scratch |= (crtc << 16);
4368 }
4369 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4370 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4371 bios_3_scratch |= (crtc << 20);
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4374 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4375 bios_3_scratch |= (crtc << 17);
4376 }
4377 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4378 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4379 bios_3_scratch |= (crtc << 19);
4380 }
4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4382 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4383 bios_3_scratch |= (crtc << 23);
4384 }
4385 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4386 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4387 bios_3_scratch |= (crtc << 25);
4388 }
4389
4390 if (rdev->family >= CHIP_R600)
4391 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4392 else
4393 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4394 }
4395
4396 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4397 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4398 {
4399 struct drm_device *dev = encoder->dev;
4400 struct radeon_device *rdev = dev->dev_private;
4401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4402 uint32_t bios_2_scratch;
4403
4404 if (ASIC_IS_DCE4(rdev))
4405 return;
4406
4407 if (rdev->family >= CHIP_R600)
4408 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4409 else
4410 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4411
4412 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4413 if (on)
4414 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4415 else
4416 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4417 }
4418 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4419 if (on)
4420 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4421 else
4422 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4423 }
4424 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4425 if (on)
4426 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4427 else
4428 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4429 }
4430 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4431 if (on)
4432 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4433 else
4434 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4435 }
4436 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4437 if (on)
4438 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4439 else
4440 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4441 }
4442 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4443 if (on)
4444 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4445 else
4446 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4447 }
4448 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4449 if (on)
4450 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4451 else
4452 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4453 }
4454 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4455 if (on)
4456 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4457 else
4458 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4459 }
4460 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4461 if (on)
4462 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4463 else
4464 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4465 }
4466 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4467 if (on)
4468 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4469 else
4470 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4471 }
4472
4473 if (rdev->family >= CHIP_R600)
4474 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4475 else
4476 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4477 }
4478