1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/drm_fixed.h>
30 #include <drm/drm_fourcc.h>
31 #include <drm/drm_framebuffer.h>
32 #include <drm/drm_vblank.h>
33 #include <drm/radeon_drm.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37
radeon_overscan_setup(struct drm_crtc * crtc,struct drm_display_mode * mode)38 static void radeon_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode)
40 {
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
44
45 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
46 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
47 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
48 }
49
radeon_legacy_rmx_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode)50 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
51 struct drm_display_mode *mode)
52 {
53 struct drm_device *dev = crtc->dev;
54 struct radeon_device *rdev = dev->dev_private;
55 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
56 int xres = mode->hdisplay;
57 int yres = mode->vdisplay;
58 bool hscale = true, vscale = true;
59 int hsync_wid;
60 int vsync_wid;
61 int hsync_start;
62 int blank_width;
63 u32 scale, inc, crtc_more_cntl;
64 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
65 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
66 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
67 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
68
69 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
70 (RADEON_VERT_STRETCH_RESERVED |
71 RADEON_VERT_AUTO_RATIO_INC);
72 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
73 (RADEON_HORZ_FP_LOOP_STRETCH |
74 RADEON_HORZ_AUTO_RATIO_INC);
75
76 crtc_more_cntl = 0;
77 if ((rdev->family == CHIP_RS100) ||
78 (rdev->family == CHIP_RS200)) {
79 /* This is to workaround the asic bug for RMX, some versions
80 of BIOS dosen't have this register initialized correctly. */
81 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
82 }
83
84
85 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
86 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
87
88 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
89 if (!hsync_wid)
90 hsync_wid = 1;
91 hsync_start = mode->crtc_hsync_start - 8;
92
93 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
94 | ((hsync_wid & 0x3f) << 16)
95 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
96 ? RADEON_CRTC_H_SYNC_POL
97 : 0));
98
99 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
100 | ((mode->crtc_vdisplay - 1) << 16));
101
102 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
103 if (!vsync_wid)
104 vsync_wid = 1;
105
106 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
107 | ((vsync_wid & 0x1f) << 16)
108 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
109 ? RADEON_CRTC_V_SYNC_POL
110 : 0));
111
112 fp_horz_vert_active = 0;
113
114 if (native_mode->hdisplay == 0 ||
115 native_mode->vdisplay == 0) {
116 hscale = false;
117 vscale = false;
118 } else {
119 if (xres > native_mode->hdisplay)
120 xres = native_mode->hdisplay;
121 if (yres > native_mode->vdisplay)
122 yres = native_mode->vdisplay;
123
124 if (xres == native_mode->hdisplay)
125 hscale = false;
126 if (yres == native_mode->vdisplay)
127 vscale = false;
128 }
129
130 switch (radeon_crtc->rmx_type) {
131 case RMX_FULL:
132 case RMX_ASPECT:
133 if (!hscale)
134 fp_horz_stretch |= ((xres/8-1) << 16);
135 else {
136 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
137 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
138 / native_mode->hdisplay + 1;
139 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
140 RADEON_HORZ_STRETCH_BLEND |
141 RADEON_HORZ_STRETCH_ENABLE |
142 ((native_mode->hdisplay/8-1) << 16));
143 }
144
145 if (!vscale)
146 fp_vert_stretch |= ((yres-1) << 12);
147 else {
148 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
149 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
150 / native_mode->vdisplay + 1;
151 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
152 RADEON_VERT_STRETCH_ENABLE |
153 RADEON_VERT_STRETCH_BLEND |
154 ((native_mode->vdisplay-1) << 12));
155 }
156 break;
157 case RMX_CENTER:
158 fp_horz_stretch |= ((xres/8-1) << 16);
159 fp_vert_stretch |= ((yres-1) << 12);
160
161 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
162 RADEON_CRTC_AUTO_VERT_CENTER_EN);
163
164 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
165 if (blank_width > 110)
166 blank_width = 110;
167
168 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
169 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
170
171 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
172 if (!hsync_wid)
173 hsync_wid = 1;
174
175 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
176 | ((hsync_wid & 0x3f) << 16)
177 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
178 ? RADEON_CRTC_H_SYNC_POL
179 : 0));
180
181 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
182 | ((mode->crtc_vdisplay - 1) << 16));
183
184 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
185 if (!vsync_wid)
186 vsync_wid = 1;
187
188 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
189 | ((vsync_wid & 0x1f) << 16)
190 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
191 ? RADEON_CRTC_V_SYNC_POL
192 : 0)));
193
194 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
195 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
196 break;
197 case RMX_OFF:
198 default:
199 fp_horz_stretch |= ((xres/8-1) << 16);
200 fp_vert_stretch |= ((yres-1) << 12);
201 break;
202 }
203
204 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
205 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
206 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
207 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
208 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
209 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
210 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
211 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
212 }
213
radeon_pll_wait_for_read_update_complete(struct drm_device * dev)214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215 {
216 struct radeon_device *rdev = dev->dev_private;
217 int i = 0;
218
219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
220 the cause yet, but this workaround will mask the problem for now.
221 Other chips usually will pass at the very first test, so the
222 workaround shouldn't have any effect on them. */
223 for (i = 0;
224 (i < 10000 &&
225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
226 i++);
227 }
228
radeon_pll_write_update(struct drm_device * dev)229 static void radeon_pll_write_update(struct drm_device *dev)
230 {
231 struct radeon_device *rdev = dev->dev_private;
232
233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
234
235 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236 RADEON_PPLL_ATOMIC_UPDATE_W,
237 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
238 }
239
radeon_pll2_wait_for_read_update_complete(struct drm_device * dev)240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
241 {
242 struct radeon_device *rdev = dev->dev_private;
243 int i = 0;
244
245
246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
247 the cause yet, but this workaround will mask the problem for now.
248 Other chips usually will pass at the very first test, so the
249 workaround shouldn't have any effect on them. */
250 for (i = 0;
251 (i < 10000 &&
252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
253 i++);
254 }
255
radeon_pll2_write_update(struct drm_device * dev)256 static void radeon_pll2_write_update(struct drm_device *dev)
257 {
258 struct radeon_device *rdev = dev->dev_private;
259
260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
261
262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263 RADEON_P2PLL_ATOMIC_UPDATE_W,
264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
265 }
266
radeon_compute_pll_gain(uint16_t ref_freq,uint16_t ref_div,uint16_t fb_div)267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
268 uint16_t fb_div)
269 {
270 unsigned int vcoFreq;
271
272 if (!ref_div)
273 return 1;
274
275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276
277 /*
278 * This is horribly crude: the VCO frequency range is divided into
279 * 3 parts, each part having a fixed PLL gain value.
280 */
281 if (vcoFreq >= 30000)
282 /*
283 * [300..max] MHz : 7
284 */
285 return 7;
286 else if (vcoFreq >= 18000)
287 /*
288 * [180..300) MHz : 4
289 */
290 return 4;
291 else
292 /*
293 * [0..180) MHz : 1
294 */
295 return 1;
296 }
297
radeon_crtc_dpms(struct drm_crtc * crtc,int mode)298 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299 {
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 uint32_t crtc_ext_cntl = 0;
304 uint32_t mask;
305
306 if (radeon_crtc->crtc_id)
307 mask = (RADEON_CRTC2_DISP_DIS |
308 RADEON_CRTC2_VSYNC_DIS |
309 RADEON_CRTC2_HSYNC_DIS |
310 RADEON_CRTC2_DISP_REQ_EN_B);
311 else
312 mask = (RADEON_CRTC_DISPLAY_DIS |
313 RADEON_CRTC_VSYNC_DIS |
314 RADEON_CRTC_HSYNC_DIS);
315
316 /*
317 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
318 * Therefore it is set in the DAC DMPS function.
319 * This is different for GPU's with a single CRTC but a primary and a
320 * TV DAC: here it controls the single CRTC no matter where it is
321 * routed. Therefore we set it here.
322 */
323 if (rdev->flags & RADEON_SINGLE_CRTC)
324 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
325
326 switch (mode) {
327 case DRM_MODE_DPMS_ON:
328 radeon_crtc->enabled = true;
329 /* adjust pm to dpms changes BEFORE enabling crtcs */
330 radeon_pm_compute_clocks(rdev);
331 if (radeon_crtc->crtc_id)
332 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
333 else {
334 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
335 RADEON_CRTC_DISP_REQ_EN_B));
336 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
337 }
338 if (dev->num_crtcs > radeon_crtc->crtc_id)
339 drm_crtc_vblank_on(crtc);
340 radeon_crtc_load_lut(crtc);
341 break;
342 case DRM_MODE_DPMS_STANDBY:
343 case DRM_MODE_DPMS_SUSPEND:
344 case DRM_MODE_DPMS_OFF:
345 if (dev->num_crtcs > radeon_crtc->crtc_id)
346 drm_crtc_vblank_off(crtc);
347 if (radeon_crtc->crtc_id)
348 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
349 else {
350 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
351 RADEON_CRTC_DISP_REQ_EN_B));
352 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
353 }
354 radeon_crtc->enabled = false;
355 /* adjust pm to dpms changes AFTER disabling crtcs */
356 radeon_pm_compute_clocks(rdev);
357 break;
358 }
359 }
360
radeon_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)361 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
362 struct drm_framebuffer *old_fb)
363 {
364 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
365 }
366
radeon_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)367 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
368 struct drm_framebuffer *fb,
369 int x, int y, enum mode_set_atomic state)
370 {
371 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
372 }
373
radeon_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)374 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
375 struct drm_framebuffer *fb,
376 int x, int y, int atomic)
377 {
378 struct drm_device *dev = crtc->dev;
379 struct radeon_device *rdev = dev->dev_private;
380 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
381 struct drm_framebuffer *target_fb;
382 struct drm_gem_object *obj;
383 struct radeon_bo *rbo;
384 uint64_t base;
385 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
386 uint32_t crtc_pitch, pitch_pixels;
387 uint32_t tiling_flags;
388 int format;
389 uint32_t gen_cntl_reg, gen_cntl_val;
390 int r;
391
392 DRM_DEBUG_KMS("\n");
393 /* no fb bound */
394 if (!atomic && !crtc->primary->fb) {
395 DRM_DEBUG_KMS("No FB bound\n");
396 return 0;
397 }
398
399 if (atomic)
400 target_fb = fb;
401 else
402 target_fb = crtc->primary->fb;
403
404 switch (target_fb->format->cpp[0] * 8) {
405 case 8:
406 format = 2;
407 break;
408 case 15: /* 555 */
409 format = 3;
410 break;
411 case 16: /* 565 */
412 format = 4;
413 break;
414 case 24: /* RGB */
415 format = 5;
416 break;
417 case 32: /* xRGB */
418 format = 6;
419 break;
420 default:
421 return false;
422 }
423
424 /* Pin framebuffer & get tilling informations */
425 obj = target_fb->obj[0];
426 rbo = gem_to_radeon_bo(obj);
427 retry:
428 r = radeon_bo_reserve(rbo, false);
429 if (unlikely(r != 0))
430 return r;
431 /* Only 27 bit offset for legacy CRTC */
432 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
433 &base);
434 if (unlikely(r != 0)) {
435 radeon_bo_unreserve(rbo);
436
437 /* On old GPU like RN50 with little vram pining can fails because
438 * current fb is taking all space needed. So instead of unpining
439 * the old buffer after pining the new one, first unpin old one
440 * and then retry pining new one.
441 *
442 * As only master can set mode only master can pin and it is
443 * unlikely the master client will race with itself especialy
444 * on those old gpu with single crtc.
445 *
446 * We don't shutdown the display controller because new buffer
447 * will end up in same spot.
448 */
449 if (!atomic && fb && fb != crtc->primary->fb) {
450 struct radeon_bo *old_rbo;
451 unsigned long nsize, osize;
452
453 old_rbo = gem_to_radeon_bo(fb->obj[0]);
454 osize = radeon_bo_size(old_rbo);
455 nsize = radeon_bo_size(rbo);
456 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
457 radeon_bo_unpin(old_rbo);
458 radeon_bo_unreserve(old_rbo);
459 fb = NULL;
460 goto retry;
461 }
462 }
463 return -EINVAL;
464 }
465 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
466 radeon_bo_unreserve(rbo);
467 if (tiling_flags & RADEON_TILING_MICRO)
468 DRM_ERROR("trying to scanout microtiled buffer\n");
469
470 /* if scanout was in GTT this really wouldn't work */
471 /* crtc offset is from display base addr not FB location */
472 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
473
474 base -= radeon_crtc->legacy_display_base_addr;
475
476 crtc_offset_cntl = 0;
477
478 pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
479 crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,
480 target_fb->format->cpp[0] * 8 * 8);
481 crtc_pitch |= crtc_pitch << 16;
482
483 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
484 if (tiling_flags & RADEON_TILING_MACRO) {
485 if (ASIC_IS_R300(rdev))
486 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
487 R300_CRTC_MICRO_TILE_BUFFER_DIS |
488 R300_CRTC_MACRO_TILE_EN);
489 else
490 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
491 } else {
492 if (ASIC_IS_R300(rdev))
493 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
494 R300_CRTC_MICRO_TILE_BUFFER_DIS |
495 R300_CRTC_MACRO_TILE_EN);
496 else
497 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
498 }
499
500 if (tiling_flags & RADEON_TILING_MACRO) {
501 if (ASIC_IS_R300(rdev)) {
502 crtc_tile_x0_y0 = x | (y << 16);
503 base &= ~0x7ff;
504 } else {
505 int byteshift = target_fb->format->cpp[0] * 8 >> 4;
506 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
507 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
508 crtc_offset_cntl |= (y % 16);
509 }
510 } else {
511 int offset = y * pitch_pixels + x;
512 switch (target_fb->format->cpp[0] * 8) {
513 case 8:
514 offset *= 1;
515 break;
516 case 15:
517 case 16:
518 offset *= 2;
519 break;
520 case 24:
521 offset *= 3;
522 break;
523 case 32:
524 offset *= 4;
525 break;
526 default:
527 return false;
528 }
529 base += offset;
530 }
531
532 base &= ~7;
533
534 if (radeon_crtc->crtc_id == 1)
535 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
536 else
537 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
538
539 gen_cntl_val = RREG32(gen_cntl_reg);
540 gen_cntl_val &= ~(0xf << 8);
541 gen_cntl_val |= (format << 8);
542 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
543 WREG32(gen_cntl_reg, gen_cntl_val);
544
545 crtc_offset = (u32)base;
546
547 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
548
549 if (ASIC_IS_R300(rdev)) {
550 if (radeon_crtc->crtc_id)
551 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
552 else
553 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
554 }
555 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
556 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
557 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
558
559 if (!atomic && fb && fb != crtc->primary->fb) {
560 rbo = gem_to_radeon_bo(fb->obj[0]);
561 r = radeon_bo_reserve(rbo, false);
562 if (unlikely(r != 0))
563 return r;
564 radeon_bo_unpin(rbo);
565 radeon_bo_unreserve(rbo);
566 }
567
568 /* Bytes per pixel may have changed */
569 radeon_bandwidth_update(rdev);
570
571 return 0;
572 }
573
radeon_set_crtc_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)574 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
575 {
576 struct drm_device *dev = crtc->dev;
577 struct radeon_device *rdev = dev->dev_private;
578 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
579 const struct drm_framebuffer *fb = crtc->primary->fb;
580 struct drm_encoder *encoder;
581 int format;
582 int hsync_start;
583 int hsync_wid;
584 int vsync_wid;
585 uint32_t crtc_h_total_disp;
586 uint32_t crtc_h_sync_strt_wid;
587 uint32_t crtc_v_total_disp;
588 uint32_t crtc_v_sync_strt_wid;
589 bool is_tv = false;
590
591 DRM_DEBUG_KMS("\n");
592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
593 if (encoder->crtc == crtc) {
594 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
595 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
596 is_tv = true;
597 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
598 break;
599 }
600 }
601 }
602
603 switch (fb->format->cpp[0] * 8) {
604 case 8:
605 format = 2;
606 break;
607 case 15: /* 555 */
608 format = 3;
609 break;
610 case 16: /* 565 */
611 format = 4;
612 break;
613 case 24: /* RGB */
614 format = 5;
615 break;
616 case 32: /* xRGB */
617 format = 6;
618 break;
619 default:
620 return false;
621 }
622
623 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
624 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
625
626 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
627 if (!hsync_wid)
628 hsync_wid = 1;
629 hsync_start = mode->crtc_hsync_start - 8;
630
631 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
632 | ((hsync_wid & 0x3f) << 16)
633 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
634 ? RADEON_CRTC_H_SYNC_POL
635 : 0));
636
637 /* This works for double scan mode. */
638 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
639 | ((mode->crtc_vdisplay - 1) << 16));
640
641 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
642 if (!vsync_wid)
643 vsync_wid = 1;
644
645 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
646 | ((vsync_wid & 0x1f) << 16)
647 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
648 ? RADEON_CRTC_V_SYNC_POL
649 : 0));
650
651 if (radeon_crtc->crtc_id) {
652 uint32_t crtc2_gen_cntl;
653 uint32_t disp2_merge_cntl;
654
655 /* if TV DAC is enabled for another crtc and keep it enabled */
656 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
657 crtc2_gen_cntl |= ((format << 8)
658 | RADEON_CRTC2_VSYNC_DIS
659 | RADEON_CRTC2_HSYNC_DIS
660 | RADEON_CRTC2_DISP_DIS
661 | RADEON_CRTC2_DISP_REQ_EN_B
662 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
663 ? RADEON_CRTC2_DBL_SCAN_EN
664 : 0)
665 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
666 ? RADEON_CRTC2_CSYNC_EN
667 : 0)
668 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
669 ? RADEON_CRTC2_INTERLACE_EN
670 : 0));
671
672 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
673 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
674 crtc2_gen_cntl |= RADEON_CRTC2_EN;
675
676 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
677 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
678
679 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
680 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
681
682 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
683 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
684 } else {
685 uint32_t crtc_gen_cntl;
686 uint32_t crtc_ext_cntl;
687 uint32_t disp_merge_cntl;
688
689 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
690 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
691 | (format << 8)
692 | RADEON_CRTC_DISP_REQ_EN_B
693 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
694 ? RADEON_CRTC_DBL_SCAN_EN
695 : 0)
696 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
697 ? RADEON_CRTC_CSYNC_EN
698 : 0)
699 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
700 ? RADEON_CRTC_INTERLACE_EN
701 : 0));
702
703 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
704 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
705 crtc_gen_cntl |= RADEON_CRTC_EN;
706
707 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
708 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
709 RADEON_CRTC_VSYNC_DIS |
710 RADEON_CRTC_HSYNC_DIS |
711 RADEON_CRTC_DISPLAY_DIS);
712
713 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
714 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
715
716 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
717 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
718 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
719 }
720
721 if (is_tv)
722 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
723 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
724 &crtc_v_sync_strt_wid);
725
726 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
727 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
728 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
729 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
730
731 return true;
732 }
733
radeon_set_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)734 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
735 {
736 struct drm_device *dev = crtc->dev;
737 struct radeon_device *rdev = dev->dev_private;
738 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
739 struct drm_encoder *encoder;
740 uint32_t feedback_div = 0;
741 uint32_t frac_fb_div = 0;
742 uint32_t reference_div = 0;
743 uint32_t post_divider = 0;
744 uint32_t freq = 0;
745 uint8_t pll_gain;
746 bool use_bios_divs = false;
747 /* PLL registers */
748 uint32_t pll_ref_div = 0;
749 uint32_t pll_fb_post_div = 0;
750 uint32_t htotal_cntl = 0;
751 bool is_tv = false;
752 struct radeon_pll *pll;
753
754 struct {
755 int divider;
756 int bitvalue;
757 } *post_div, post_divs[] = {
758 /* From RAGE 128 VR/RAGE 128 GL Register
759 * Reference Manual (Technical Reference
760 * Manual P/N RRG-G04100-C Rev. 0.04), page
761 * 3-17 (PLL_DIV_[3:0]).
762 */
763 { 1, 0 }, /* VCLK_SRC */
764 { 2, 1 }, /* VCLK_SRC/2 */
765 { 4, 2 }, /* VCLK_SRC/4 */
766 { 8, 3 }, /* VCLK_SRC/8 */
767 { 3, 4 }, /* VCLK_SRC/3 */
768 { 16, 5 }, /* VCLK_SRC/16 */
769 { 6, 6 }, /* VCLK_SRC/6 */
770 { 12, 7 }, /* VCLK_SRC/12 */
771 { 0, 0 }
772 };
773
774 if (radeon_crtc->crtc_id)
775 pll = &rdev->clock.p2pll;
776 else
777 pll = &rdev->clock.p1pll;
778
779 pll->flags = RADEON_PLL_LEGACY;
780
781 if (mode->clock > 200000) /* range limits??? */
782 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
783 else
784 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
785
786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
787 if (encoder->crtc == crtc) {
788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
789
790 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
791 is_tv = true;
792 break;
793 }
794
795 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
796 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
797 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
798 if (!rdev->is_atom_bios) {
799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
800 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
801 if (lvds) {
802 if (lvds->use_bios_dividers) {
803 pll_ref_div = lvds->panel_ref_divider;
804 pll_fb_post_div = (lvds->panel_fb_divider |
805 (lvds->panel_post_divider << 16));
806 htotal_cntl = 0;
807 use_bios_divs = true;
808 }
809 }
810 }
811 pll->flags |= RADEON_PLL_USE_REF_DIV;
812 }
813 }
814 }
815
816 DRM_DEBUG_KMS("\n");
817
818 if (!use_bios_divs) {
819 radeon_compute_pll_legacy(pll, mode->clock,
820 &freq, &feedback_div, &frac_fb_div,
821 &reference_div, &post_divider);
822
823 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
824 if (post_div->divider == post_divider)
825 break;
826 }
827
828 if (!post_div->divider)
829 post_div = &post_divs[0];
830
831 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
832 (unsigned)freq,
833 feedback_div,
834 reference_div,
835 post_divider);
836
837 pll_ref_div = reference_div;
838 #if defined(__powerpc__) && (0) /* TODO */
839 /* apparently programming this otherwise causes a hang??? */
840 if (info->MacModel == RADEON_MAC_IBOOK)
841 pll_fb_post_div = 0x000600ad;
842 else
843 #endif
844 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
845
846 htotal_cntl = mode->htotal & 0x7;
847
848 }
849
850 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
851 pll_ref_div & 0x3ff,
852 pll_fb_post_div & 0x7ff);
853
854 if (radeon_crtc->crtc_id) {
855 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
856 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
857 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
858
859 if (is_tv) {
860 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
861 &pll_ref_div, &pll_fb_post_div,
862 &pixclks_cntl);
863 }
864
865 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
866 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
867 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
868
869 WREG32_PLL_P(RADEON_P2PLL_CNTL,
870 RADEON_P2PLL_RESET
871 | RADEON_P2PLL_ATOMIC_UPDATE_EN
872 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
873 ~(RADEON_P2PLL_RESET
874 | RADEON_P2PLL_ATOMIC_UPDATE_EN
875 | RADEON_P2PLL_PVG_MASK));
876
877 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
878 pll_ref_div,
879 ~RADEON_P2PLL_REF_DIV_MASK);
880
881 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
882 pll_fb_post_div,
883 ~RADEON_P2PLL_FB0_DIV_MASK);
884
885 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
886 pll_fb_post_div,
887 ~RADEON_P2PLL_POST0_DIV_MASK);
888
889 radeon_pll2_write_update(dev);
890 radeon_pll2_wait_for_read_update_complete(dev);
891
892 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
893
894 WREG32_PLL_P(RADEON_P2PLL_CNTL,
895 0,
896 ~(RADEON_P2PLL_RESET
897 | RADEON_P2PLL_SLEEP
898 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
899
900 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
901 (unsigned)pll_ref_div,
902 (unsigned)pll_fb_post_div,
903 (unsigned)htotal_cntl,
904 RREG32_PLL(RADEON_P2PLL_CNTL));
905 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
906 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
907 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
908 (unsigned)((pll_fb_post_div &
909 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
910
911 mdelay(50); /* Let the clock to lock */
912
913 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
914 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
915 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
916
917 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
918 } else {
919 uint32_t pixclks_cntl;
920
921
922 if (is_tv) {
923 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
924 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
925 &pll_fb_post_div, &pixclks_cntl);
926 }
927
928 if (rdev->flags & RADEON_IS_MOBILITY) {
929 /* A temporal workaround for the occasional blanking on certain laptop panels.
930 This appears to related to the PLL divider registers (fail to lock?).
931 It occurs even when all dividers are the same with their old settings.
932 In this case we really don't need to fiddle with PLL registers.
933 By doing this we can avoid the blanking problem with some panels.
934 */
935 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
936 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
937 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
938 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
939 RADEON_PLL_DIV_SEL,
940 ~(RADEON_PLL_DIV_SEL));
941 r100_pll_errata_after_index(rdev);
942 return;
943 }
944 }
945
946 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
947 RADEON_VCLK_SRC_SEL_CPUCLK,
948 ~(RADEON_VCLK_SRC_SEL_MASK));
949 WREG32_PLL_P(RADEON_PPLL_CNTL,
950 RADEON_PPLL_RESET
951 | RADEON_PPLL_ATOMIC_UPDATE_EN
952 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
953 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
954 ~(RADEON_PPLL_RESET
955 | RADEON_PPLL_ATOMIC_UPDATE_EN
956 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
957 | RADEON_PPLL_PVG_MASK));
958
959 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
960 RADEON_PLL_DIV_SEL,
961 ~(RADEON_PLL_DIV_SEL));
962 r100_pll_errata_after_index(rdev);
963
964 if (ASIC_IS_R300(rdev) ||
965 (rdev->family == CHIP_RS300) ||
966 (rdev->family == CHIP_RS400) ||
967 (rdev->family == CHIP_RS480)) {
968 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
969 /* When restoring console mode, use saved PPLL_REF_DIV
970 * setting.
971 */
972 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
973 pll_ref_div,
974 0);
975 } else {
976 /* R300 uses ref_div_acc field as real ref divider */
977 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
978 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
979 ~R300_PPLL_REF_DIV_ACC_MASK);
980 }
981 } else
982 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
983 pll_ref_div,
984 ~RADEON_PPLL_REF_DIV_MASK);
985
986 WREG32_PLL_P(RADEON_PPLL_DIV_3,
987 pll_fb_post_div,
988 ~RADEON_PPLL_FB3_DIV_MASK);
989
990 WREG32_PLL_P(RADEON_PPLL_DIV_3,
991 pll_fb_post_div,
992 ~RADEON_PPLL_POST3_DIV_MASK);
993
994 radeon_pll_write_update(dev);
995 radeon_pll_wait_for_read_update_complete(dev);
996
997 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
998
999 WREG32_PLL_P(RADEON_PPLL_CNTL,
1000 0,
1001 ~(RADEON_PPLL_RESET
1002 | RADEON_PPLL_SLEEP
1003 | RADEON_PPLL_ATOMIC_UPDATE_EN
1004 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1005
1006 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1007 pll_ref_div,
1008 pll_fb_post_div,
1009 (unsigned)htotal_cntl,
1010 RREG32_PLL(RADEON_PPLL_CNTL));
1011 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1012 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1013 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1014 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1015
1016 mdelay(50); /* Let the clock to lock */
1017
1018 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1019 RADEON_VCLK_SRC_SEL_PPLLCLK,
1020 ~(RADEON_VCLK_SRC_SEL_MASK));
1021
1022 if (is_tv)
1023 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1024 }
1025 }
1026
radeon_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1027 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1028 const struct drm_display_mode *mode,
1029 struct drm_display_mode *adjusted_mode)
1030 {
1031 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1032 return false;
1033 return true;
1034 }
1035
radeon_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)1036 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1037 struct drm_display_mode *mode,
1038 struct drm_display_mode *adjusted_mode,
1039 int x, int y, struct drm_framebuffer *old_fb)
1040 {
1041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1042
1043 /* TODO TV */
1044 radeon_crtc_set_base(crtc, x, y, old_fb);
1045 radeon_set_crtc_timing(crtc, adjusted_mode);
1046 radeon_set_pll(crtc, adjusted_mode);
1047 radeon_overscan_setup(crtc, adjusted_mode);
1048 if (radeon_crtc->crtc_id == 0) {
1049 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1050 } else {
1051 if (radeon_crtc->rmx_type != RMX_OFF) {
1052 /* FIXME: only first crtc has rmx what should we
1053 * do ?
1054 */
1055 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1056 }
1057 }
1058 radeon_cursor_reset(crtc);
1059 return 0;
1060 }
1061
radeon_crtc_prepare(struct drm_crtc * crtc)1062 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1063 {
1064 struct drm_device *dev = crtc->dev;
1065 struct drm_crtc *crtci;
1066
1067 /*
1068 * The hardware wedges sometimes if you reconfigure one CRTC
1069 * whilst another is running (see fdo bug #24611).
1070 */
1071 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1072 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1073 }
1074
radeon_crtc_commit(struct drm_crtc * crtc)1075 static void radeon_crtc_commit(struct drm_crtc *crtc)
1076 {
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_crtc *crtci;
1079
1080 /*
1081 * Reenable the CRTCs that should be running.
1082 */
1083 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1084 if (crtci->enabled)
1085 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1086 }
1087 }
1088
radeon_crtc_disable(struct drm_crtc * crtc)1089 static void radeon_crtc_disable(struct drm_crtc *crtc)
1090 {
1091 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1092 if (crtc->primary->fb) {
1093 int r;
1094 struct radeon_bo *rbo;
1095
1096 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
1097 r = radeon_bo_reserve(rbo, false);
1098 if (unlikely(r))
1099 DRM_ERROR("failed to reserve rbo before unpin\n");
1100 else {
1101 radeon_bo_unpin(rbo);
1102 radeon_bo_unreserve(rbo);
1103 }
1104 }
1105 }
1106
1107 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1108 .dpms = radeon_crtc_dpms,
1109 .mode_fixup = radeon_crtc_mode_fixup,
1110 .mode_set = radeon_crtc_mode_set,
1111 .mode_set_base = radeon_crtc_set_base,
1112 .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1113 .prepare = radeon_crtc_prepare,
1114 .commit = radeon_crtc_commit,
1115 .disable = radeon_crtc_disable,
1116 .get_scanout_position = radeon_get_crtc_scanout_position,
1117 };
1118
1119
radeon_legacy_init_crtc(struct drm_device * dev,struct radeon_crtc * radeon_crtc)1120 void radeon_legacy_init_crtc(struct drm_device *dev,
1121 struct radeon_crtc *radeon_crtc)
1122 {
1123 if (radeon_crtc->crtc_id == 1)
1124 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1125 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1126 }
1127