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Searched defs:reg2 (Results 1 – 25 of 71) sorted by relevance

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/drivers/rtc/
Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn314/
Dirq_service_dcn314.c211 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
225 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/drivers/net/ethernet/sunplus/
Dspl2sw_mdio.c20 u32 reg, reg2; in spl2sw_mdio_access() local
/drivers/net/ethernet/netronome/nfp/bpf/
Dverifier.c50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head()
175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local
/drivers/media/dvb-frontends/
Dtua6100.c65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
Ds5h1409.c556 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode() local
594 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode_legacy() local
/drivers/clk/
Dclk-axi-clkgen.c321 unsigned int reg1, unsigned int reg2, unsigned int reg3, in axi_clkgen_set_div()
407 unsigned int reg1, unsigned int reg2) in axi_clkgen_get_div()
/drivers/mcb/
Dmcb-parse.c48 __le32 reg2; in chameleon_parse_gdd() local
Dmcb-internal.h67 __le32 reg2; member
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
Dirq_service_dcn201.c154 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/drivers/net/ethernet/mellanox/mlxbf_gige/
Dmlxbf_gige_mdio.c88 u32 reg1, reg2; in calculate_i1clk() local
/drivers/hwmon/
Dnct7904.c392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local
569 unsigned int reg1, reg2, reg3; in nct7904_write_temp() local
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_self_test.c41 u32 reg2; member
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs() local
/drivers/staging/rts5208/
Drtsx_card.c83 u8 reg1 = 0, reg2 = 0; in try_to_switch_sdio_ctrl() local

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