/drivers/rtc/ |
D | rtc-aspeed.c | 26 u32 reg1, reg2; in aspeed_rtc_read_time() local 56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
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/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
D | irq_service_dcn314.c | 211 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 225 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
D | irq_service_dcn21.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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/drivers/net/ethernet/sunplus/ |
D | spl2sw_mdio.c | 20 u32 reg, reg2; in spl2sw_mdio_access() local
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/drivers/net/ethernet/netronome/nfp/bpf/ |
D | verifier.c | 50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head() 175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local
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/drivers/media/dvb-frontends/ |
D | tua6100.c | 65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
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D | s5h1409.c | 556 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode() local 594 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode_legacy() local
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/drivers/clk/ |
D | clk-axi-clkgen.c | 321 unsigned int reg1, unsigned int reg2, unsigned int reg3, in axi_clkgen_set_div() 407 unsigned int reg1, unsigned int reg2) in axi_clkgen_get_div()
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/drivers/mcb/ |
D | mcb-parse.c | 48 __le32 reg2; in chameleon_parse_gdd() local
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D | mcb-internal.h | 67 __le32 reg2; member
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/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
D | irq_service_dce120.c | 103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
D | irq_service_dcn10.c | 200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
D | irq_service_dcn20.c | 205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
D | irq_service_dcn303.c | 119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
D | irq_service_dcn201.c | 154 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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/drivers/net/ethernet/mellanox/mlxbf_gige/ |
D | mlxbf_gige_mdio.c | 88 u32 reg1, reg2; in calculate_i1clk() local
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/drivers/hwmon/ |
D | nct7904.c | 392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local 569 unsigned int reg1, reg2, reg3; in nct7904_write_temp() local
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/drivers/net/ethernet/broadcom/bnx2x/ |
D | bnx2x_self_test.c | 41 u32 reg2; member
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/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
D | nv04.c | 204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs() local
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/drivers/staging/rts5208/ |
D | rtsx_card.c | 83 u8 reg1 = 0, reg2 = 0; in try_to_switch_sdio_ctrl() local
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