1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72 /*Update PCI ASPM setting */
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76 /*No ASPM */
77 break;
78
79 case 1:
80 /*ASPM dynamically enabled/disable. */
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85 /*ASPM with Clock Req dynamically enabled/disable. */
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91 /* Always enable ASPM and Clock Req
92 * from initialization to halt.
93 */
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100 /* Always enable ASPM without Clock Req
101 * from initialization to halt.
102 */
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111 /*Update Radio OFF setting */
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129 /*Set HW definition to determine if it supports ASPM. */
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132 /*Not support ASPM. */
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136 /*Support ASPM. */
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141 /*ASPM value set by chipset. */
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151 /* toshiba aspm issue, toshiba will set aspm selfly
152 * so we should not set aspm in driver
153 */
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158 }
159
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163 {
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 value &= PCI_EXP_LNKCTL_ASPMC;
168
169 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
170 value |= PCI_EXP_LNKCTL_CCC;
171
172 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
173 PCI_EXP_LNKCTL_ASPMC | value,
174 value);
175
176 return false;
177 }
178
179 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u16 value)180 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
181 {
182 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
184
185 value &= PCI_EXP_LNKCTL_CLKREQ_EN;
186
187 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
188 PCI_EXP_LNKCTL_CLKREQ_EN,
189 value);
190
191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
192 udelay(100);
193 }
194
195 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)196 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
197 {
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
199 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
200 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
202 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
203 /*Retrieve original configuration settings. */
204 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
205 u16 aspmlevel = 0;
206 u8 tmp_u1b = 0;
207
208 if (!ppsc->support_aspm)
209 return;
210
211 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
213 "PCI(Bridge) UNKNOWN\n");
214
215 return;
216 }
217
218 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
219 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
220 _rtl_pci_switch_clk_req(hw, 0x0);
221 }
222
223 /*for promising device will in L0 state after an I/O. */
224 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
225
226 /*Set corresponding value. */
227 aspmlevel |= BIT(0) | BIT(1);
228 linkctrl_reg &= ~aspmlevel;
229
230 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
231 }
232
233 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
234 *power saving We should follow the sequence to enable
235 *RTL8192SE first then enable Pci Bridge ASPM
236 *or the system will show bluescreen.
237 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)238 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
239 {
240 struct rtl_priv *rtlpriv = rtl_priv(hw);
241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
244 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
245 u16 aspmlevel;
246 u8 u_device_aspmsetting;
247
248 if (!ppsc->support_aspm)
249 return;
250
251 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
253 "PCI(Bridge) UNKNOWN\n");
254 return;
255 }
256
257 /*Get ASPM level (with/without Clock Req) */
258 aspmlevel = rtlpci->const_devicepci_aspm_setting;
259 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
260
261 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
262 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
263
264 u_device_aspmsetting |= aspmlevel;
265
266 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
267
268 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
269 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
270 RT_RF_OFF_LEVL_CLK_REQ) ?
271 PCI_EXP_LNKCTL_CLKREQ_EN : 0);
272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
273 }
274 udelay(100);
275 }
276
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)277 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
278 {
279 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
280
281 bool status = false;
282 u8 offset_e0;
283 unsigned int offset_e4;
284
285 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
286
287 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
288
289 if (offset_e0 == 0xA0) {
290 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
291 if (offset_e4 & BIT(23))
292 status = true;
293 }
294
295 return status;
296 }
297
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)298 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
299 struct rtl_priv **buddy_priv)
300 {
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
303 struct rtl_priv *tpriv = NULL, *iter;
304 struct rtl_pci_priv *tpcipriv = NULL;
305
306 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
307 list_for_each_entry(iter, &rtlpriv->glb_var->glb_priv_list,
308 list) {
309 tpcipriv = (struct rtl_pci_priv *)iter->priv;
310 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
311 "pcipriv->ndis_adapter.funcnumber %x\n",
312 pcipriv->ndis_adapter.funcnumber);
313 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
314 "tpcipriv->ndis_adapter.funcnumber %x\n",
315 tpcipriv->ndis_adapter.funcnumber);
316
317 if (pcipriv->ndis_adapter.busnumber ==
318 tpcipriv->ndis_adapter.busnumber &&
319 pcipriv->ndis_adapter.devnumber ==
320 tpcipriv->ndis_adapter.devnumber &&
321 pcipriv->ndis_adapter.funcnumber !=
322 tpcipriv->ndis_adapter.funcnumber) {
323 tpriv = iter;
324 break;
325 }
326 }
327 }
328
329 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
330 "find_buddy_priv %d\n", tpriv != NULL);
331
332 if (tpriv)
333 *buddy_priv = tpriv;
334
335 return tpriv != NULL;
336 }
337
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)338 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
339 struct ieee80211_hw *hw)
340 {
341 struct rtl_priv *rtlpriv = rtl_priv(hw);
342 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
343
344 u8 tmp;
345 u16 linkctrl_reg;
346
347 /*Link Control Register */
348 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
349 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
350
351 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
352 pcipriv->ndis_adapter.linkctrl_reg);
353
354 pci_read_config_byte(pdev, 0x98, &tmp);
355 tmp |= BIT(4);
356 pci_write_config_byte(pdev, 0x98, tmp);
357
358 tmp = 0x17;
359 pci_write_config_byte(pdev, 0x70f, tmp);
360 }
361
rtl_pci_init_aspm(struct ieee80211_hw * hw)362 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
363 {
364 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
365
366 _rtl_pci_update_default_setting(hw);
367
368 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
369 /*Always enable ASPM & Clock Req. */
370 rtl_pci_enable_aspm(hw);
371 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
372 }
373 }
374
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)375 static void _rtl_pci_io_handler_init(struct device *dev,
376 struct ieee80211_hw *hw)
377 {
378 struct rtl_priv *rtlpriv = rtl_priv(hw);
379
380 rtlpriv->io.dev = dev;
381
382 rtlpriv->io.write8_async = pci_write8_async;
383 rtlpriv->io.write16_async = pci_write16_async;
384 rtlpriv->io.write32_async = pci_write32_async;
385
386 rtlpriv->io.read8_sync = pci_read8_sync;
387 rtlpriv->io.read16_sync = pci_read16_sync;
388 rtlpriv->io.read32_sync = pci_read32_sync;
389 }
390
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)391 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
392 struct sk_buff *skb,
393 struct rtl_tcb_desc *tcb_desc, u8 tid)
394 {
395 struct rtl_priv *rtlpriv = rtl_priv(hw);
396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
397 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
398 struct sk_buff *next_skb;
399 u8 additionlen = FCS_LEN;
400
401 /* here open is 4, wep/tkip is 8, aes is 12*/
402 if (info->control.hw_key)
403 additionlen += info->control.hw_key->icv_len;
404
405 /* The most skb num is 6 */
406 tcb_desc->empkt_num = 0;
407 spin_lock_bh(&rtlpriv->locks.waitq_lock);
408 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
409 struct ieee80211_tx_info *next_info;
410
411 next_info = IEEE80211_SKB_CB(next_skb);
412 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
413 tcb_desc->empkt_len[tcb_desc->empkt_num] =
414 next_skb->len + additionlen;
415 tcb_desc->empkt_num++;
416 } else {
417 break;
418 }
419
420 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
421 next_skb))
422 break;
423
424 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
425 break;
426 }
427 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
428
429 return true;
430 }
431
432 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)433 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
434 {
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
437 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
438 struct sk_buff *skb = NULL;
439 struct ieee80211_tx_info *info = NULL;
440 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
441 int tid;
442
443 if (!rtlpriv->rtlhal.earlymode_enable)
444 return;
445
446 if (rtlpriv->dm.supp_phymode_switch &&
447 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
448 (rtlpriv->buddy_priv &&
449 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
450 return;
451 /* we just use em for BE/BK/VI/VO */
452 for (tid = 7; tid >= 0; tid--) {
453 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
454 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
455
456 while (!mac->act_scanning &&
457 rtlpriv->psc.rfpwr_state == ERFON) {
458 struct rtl_tcb_desc tcb_desc;
459
460 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
461
462 spin_lock(&rtlpriv->locks.waitq_lock);
463 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
464 (ring->entries - skb_queue_len(&ring->queue) >
465 rtlhal->max_earlymode_num)) {
466 skb = skb_dequeue(&mac->skb_waitq[tid]);
467 } else {
468 spin_unlock(&rtlpriv->locks.waitq_lock);
469 break;
470 }
471 spin_unlock(&rtlpriv->locks.waitq_lock);
472
473 /* Some macaddr can't do early mode. like
474 * multicast/broadcast/no_qos data
475 */
476 info = IEEE80211_SKB_CB(skb);
477 if (info->flags & IEEE80211_TX_CTL_AMPDU)
478 _rtl_update_earlymode_info(hw, skb,
479 &tcb_desc, tid);
480
481 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
482 }
483 }
484 }
485
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)486 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
487 {
488 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
490
491 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
492
493 while (skb_queue_len(&ring->queue)) {
494 struct sk_buff *skb;
495 struct ieee80211_tx_info *info;
496 __le16 fc;
497 u8 tid;
498 u8 *entry;
499
500 if (rtlpriv->use_new_trx_flow)
501 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
502 else
503 entry = (u8 *)(&ring->desc[ring->idx]);
504
505 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
506 return;
507 ring->idx = (ring->idx + 1) % ring->entries;
508
509 skb = __skb_dequeue(&ring->queue);
510 dma_unmap_single(&rtlpci->pdev->dev,
511 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
512 true, HW_DESC_TXBUFF_ADDR),
513 skb->len, DMA_TO_DEVICE);
514
515 /* remove early mode header */
516 if (rtlpriv->rtlhal.earlymode_enable)
517 skb_pull(skb, EM_HDR_LEN);
518
519 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
520 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
521 ring->idx,
522 skb_queue_len(&ring->queue),
523 *(u16 *)(skb->data + 22));
524
525 if (prio == TXCMD_QUEUE) {
526 dev_kfree_skb(skb);
527 goto tx_status_ok;
528 }
529
530 /* for sw LPS, just after NULL skb send out, we can
531 * sure AP knows we are sleeping, we should not let
532 * rf sleep
533 */
534 fc = rtl_get_fc(skb);
535 if (ieee80211_is_nullfunc(fc)) {
536 if (ieee80211_has_pm(fc)) {
537 rtlpriv->mac80211.offchan_delay = true;
538 rtlpriv->psc.state_inap = true;
539 } else {
540 rtlpriv->psc.state_inap = false;
541 }
542 }
543 if (ieee80211_is_action(fc)) {
544 struct ieee80211_mgmt *action_frame =
545 (struct ieee80211_mgmt *)skb->data;
546 if (action_frame->u.action.u.ht_smps.action ==
547 WLAN_HT_ACTION_SMPS) {
548 dev_kfree_skb(skb);
549 goto tx_status_ok;
550 }
551 }
552
553 /* update tid tx pkt num */
554 tid = rtl_get_tid(skb);
555 if (tid <= 7)
556 rtlpriv->link_info.tidtx_inperiod[tid]++;
557
558 info = IEEE80211_SKB_CB(skb);
559
560 if (likely(!ieee80211_is_nullfunc(fc))) {
561 ieee80211_tx_info_clear_status(info);
562 info->flags |= IEEE80211_TX_STAT_ACK;
563 /*info->status.rates[0].count = 1; */
564 ieee80211_tx_status_irqsafe(hw, skb);
565 } else {
566 rtl_tx_ackqueue(hw, skb);
567 }
568
569 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
570 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
571 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
572 prio, ring->idx,
573 skb_queue_len(&ring->queue));
574
575 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
576 }
577 tx_status_ok:
578 skb = NULL;
579 }
580
581 if (((rtlpriv->link_info.num_rx_inperiod +
582 rtlpriv->link_info.num_tx_inperiod) > 8) ||
583 rtlpriv->link_info.num_rx_inperiod > 2)
584 rtl_lps_leave(hw, false);
585 }
586
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)587 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
588 struct sk_buff *new_skb, u8 *entry,
589 int rxring_idx, int desc_idx)
590 {
591 struct rtl_priv *rtlpriv = rtl_priv(hw);
592 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
593 u32 bufferaddress;
594 u8 tmp_one = 1;
595 struct sk_buff *skb;
596
597 if (likely(new_skb)) {
598 skb = new_skb;
599 goto remap;
600 }
601 skb = dev_alloc_skb(rtlpci->rxbuffersize);
602 if (!skb)
603 return 0;
604
605 remap:
606 /* just set skb->cb to mapping addr for pci_unmap_single use */
607 *((dma_addr_t *)skb->cb) =
608 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
609 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
610 bufferaddress = *((dma_addr_t *)skb->cb);
611 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
612 return 0;
613 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
614 if (rtlpriv->use_new_trx_flow) {
615 /* skb->cb may be 64 bit address */
616 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
617 HW_DESC_RX_PREPARE,
618 (u8 *)(dma_addr_t *)skb->cb);
619 } else {
620 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
621 HW_DESC_RXBUFF_ADDR,
622 (u8 *)&bufferaddress);
623 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
624 HW_DESC_RXPKT_LEN,
625 (u8 *)&rtlpci->rxbuffersize);
626 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
627 HW_DESC_RXOWN,
628 (u8 *)&tmp_one);
629 }
630 return 1;
631 }
632
633 /* inorder to receive 8K AMSDU we have set skb to
634 * 9100bytes in init rx ring, but if this packet is
635 * not a AMSDU, this large packet will be sent to
636 * TCP/IP directly, this cause big packet ping fail
637 * like: "ping -s 65507", so here we will realloc skb
638 * based on the true size of packet, Mac80211
639 * Probably will do it better, but does not yet.
640 *
641 * Some platform will fail when alloc skb sometimes.
642 * in this condition, we will send the old skb to
643 * mac80211 directly, this will not cause any other
644 * issues, but only this packet will be lost by TCP/IP
645 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)646 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
647 struct sk_buff *skb,
648 struct ieee80211_rx_status rx_status)
649 {
650 if (unlikely(!rtl_action_proc(hw, skb, false))) {
651 dev_kfree_skb_any(skb);
652 } else {
653 struct sk_buff *uskb = NULL;
654
655 uskb = dev_alloc_skb(skb->len + 128);
656 if (likely(uskb)) {
657 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
658 sizeof(rx_status));
659 skb_put_data(uskb, skb->data, skb->len);
660 dev_kfree_skb_any(skb);
661 ieee80211_rx_irqsafe(hw, uskb);
662 } else {
663 ieee80211_rx_irqsafe(hw, skb);
664 }
665 }
666 }
667
668 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)669 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
670 {
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
673
674 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
675 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
676 rtlpci->sys_irq_mask);
677 }
678
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)679 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
680 {
681 struct rtl_priv *rtlpriv = rtl_priv(hw);
682 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
683 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
684 struct ieee80211_rx_status rx_status = { 0 };
685 unsigned int count = rtlpci->rxringcount;
686 u8 own;
687 u8 tmp_one;
688 bool unicast = false;
689 u8 hw_queue = 0;
690 unsigned int rx_remained_cnt = 0;
691 struct rtl_stats stats = {
692 .signal = 0,
693 .rate = 0,
694 };
695
696 /*RX NORMAL PKT */
697 while (count--) {
698 struct ieee80211_hdr *hdr;
699 __le16 fc;
700 u16 len;
701 /*rx buffer descriptor */
702 struct rtl_rx_buffer_desc *buffer_desc = NULL;
703 /*if use new trx flow, it means wifi info */
704 struct rtl_rx_desc *pdesc = NULL;
705 /*rx pkt */
706 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
707 rtlpci->rx_ring[rxring_idx].idx];
708 struct sk_buff *new_skb;
709
710 if (rtlpriv->use_new_trx_flow) {
711 if (rx_remained_cnt == 0)
712 rx_remained_cnt =
713 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
714 hw_queue);
715 if (rx_remained_cnt == 0)
716 return;
717 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
718 rtlpci->rx_ring[rxring_idx].idx];
719 pdesc = (struct rtl_rx_desc *)skb->data;
720 } else { /* rx descriptor */
721 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
722 rtlpci->rx_ring[rxring_idx].idx];
723
724 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
725 false,
726 HW_DESC_OWN);
727 if (own) /* wait data to be filled by hardware */
728 return;
729 }
730
731 /* Reaching this point means: data is filled already
732 * AAAAAAttention !!!
733 * We can NOT access 'skb' before 'pci_unmap_single'
734 */
735 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
736 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
737
738 /* get a new skb - if fail, old one will be reused */
739 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
740 if (unlikely(!new_skb))
741 goto no_new;
742 memset(&rx_status, 0, sizeof(rx_status));
743 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
744 &rx_status, (u8 *)pdesc, skb);
745
746 if (rtlpriv->use_new_trx_flow)
747 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
748 (u8 *)buffer_desc,
749 hw_queue);
750
751 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
752 HW_DESC_RXPKT_LEN);
753
754 if (skb->end - skb->tail > len) {
755 skb_put(skb, len);
756 if (rtlpriv->use_new_trx_flow)
757 skb_reserve(skb, stats.rx_drvinfo_size +
758 stats.rx_bufshift + 24);
759 else
760 skb_reserve(skb, stats.rx_drvinfo_size +
761 stats.rx_bufshift);
762 } else {
763 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
764 "skb->end - skb->tail = %d, len is %d\n",
765 skb->end - skb->tail, len);
766 dev_kfree_skb_any(skb);
767 goto new_trx_end;
768 }
769 /* handle command packet here */
770 if (stats.packet_report_type == C2H_PACKET) {
771 rtl_c2hcmd_enqueue(hw, skb);
772 goto new_trx_end;
773 }
774
775 /* NOTICE This can not be use for mac80211,
776 * this is done in mac80211 code,
777 * if done here sec DHCP will fail
778 * skb_trim(skb, skb->len - 4);
779 */
780
781 hdr = rtl_get_hdr(skb);
782 fc = rtl_get_fc(skb);
783
784 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
785 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
786 sizeof(rx_status));
787
788 if (is_broadcast_ether_addr(hdr->addr1)) {
789 ;/*TODO*/
790 } else if (is_multicast_ether_addr(hdr->addr1)) {
791 ;/*TODO*/
792 } else {
793 unicast = true;
794 rtlpriv->stats.rxbytesunicast += skb->len;
795 }
796 rtl_is_special_data(hw, skb, false, true);
797
798 if (ieee80211_is_data(fc)) {
799 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
800 if (unicast)
801 rtlpriv->link_info.num_rx_inperiod++;
802 }
803
804 rtl_collect_scan_list(hw, skb);
805
806 /* static bcn for roaming */
807 rtl_beacon_statistic(hw, skb);
808 rtl_p2p_info(hw, (void *)skb->data, skb->len);
809 /* for sw lps */
810 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
811 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
812 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
813 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
814 (ieee80211_is_beacon(fc) ||
815 ieee80211_is_probe_resp(fc))) {
816 dev_kfree_skb_any(skb);
817 } else {
818 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
819 }
820 } else {
821 /* drop packets with errors or those too short */
822 dev_kfree_skb_any(skb);
823 }
824 new_trx_end:
825 if (rtlpriv->use_new_trx_flow) {
826 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
827 rtlpci->rx_ring[hw_queue].next_rx_rp %=
828 RTL_PCI_MAX_RX_COUNT;
829
830 rx_remained_cnt--;
831 rtl_write_word(rtlpriv, 0x3B4,
832 rtlpci->rx_ring[hw_queue].next_rx_rp);
833 }
834 if (((rtlpriv->link_info.num_rx_inperiod +
835 rtlpriv->link_info.num_tx_inperiod) > 8) ||
836 rtlpriv->link_info.num_rx_inperiod > 2)
837 rtl_lps_leave(hw, false);
838 skb = new_skb;
839 no_new:
840 if (rtlpriv->use_new_trx_flow) {
841 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
842 rxring_idx,
843 rtlpci->rx_ring[rxring_idx].idx);
844 } else {
845 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
846 rxring_idx,
847 rtlpci->rx_ring[rxring_idx].idx);
848 if (rtlpci->rx_ring[rxring_idx].idx ==
849 rtlpci->rxringcount - 1)
850 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
851 false,
852 HW_DESC_RXERO,
853 (u8 *)&tmp_one);
854 }
855 rtlpci->rx_ring[rxring_idx].idx =
856 (rtlpci->rx_ring[rxring_idx].idx + 1) %
857 rtlpci->rxringcount;
858 }
859 }
860
_rtl_pci_interrupt(int irq,void * dev_id)861 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
862 {
863 struct ieee80211_hw *hw = dev_id;
864 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
865 struct rtl_priv *rtlpriv = rtl_priv(hw);
866 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
867 unsigned long flags;
868 struct rtl_int intvec = {0};
869
870 irqreturn_t ret = IRQ_HANDLED;
871
872 if (rtlpci->irq_enabled == 0)
873 return ret;
874
875 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
876 rtlpriv->cfg->ops->disable_interrupt(hw);
877
878 /*read ISR: 4/8bytes */
879 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
880
881 /*Shared IRQ or HW disappeared */
882 if (!intvec.inta || intvec.inta == 0xffff)
883 goto done;
884
885 /*<1> beacon related */
886 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
887 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
888 "beacon ok interrupt!\n");
889
890 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
891 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
892 "beacon err interrupt!\n");
893
894 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
895 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
896
897 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
898 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
899 "prepare beacon for interrupt!\n");
900 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
901 }
902
903 /*<2> Tx related */
904 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
905 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
906
907 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
908 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
909 "Manage ok interrupt!\n");
910 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
911 }
912
913 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
914 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
915 "HIGH_QUEUE ok interrupt!\n");
916 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
917 }
918
919 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
920 rtlpriv->link_info.num_tx_inperiod++;
921
922 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
923 "BK Tx OK interrupt!\n");
924 _rtl_pci_tx_isr(hw, BK_QUEUE);
925 }
926
927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
928 rtlpriv->link_info.num_tx_inperiod++;
929
930 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
931 "BE TX OK interrupt!\n");
932 _rtl_pci_tx_isr(hw, BE_QUEUE);
933 }
934
935 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
936 rtlpriv->link_info.num_tx_inperiod++;
937
938 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
939 "VI TX OK interrupt!\n");
940 _rtl_pci_tx_isr(hw, VI_QUEUE);
941 }
942
943 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
944 rtlpriv->link_info.num_tx_inperiod++;
945
946 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
947 "Vo TX OK interrupt!\n");
948 _rtl_pci_tx_isr(hw, VO_QUEUE);
949 }
950
951 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
952 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
953 rtlpriv->link_info.num_tx_inperiod++;
954
955 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
956 "H2C TX OK interrupt!\n");
957 _rtl_pci_tx_isr(hw, H2C_QUEUE);
958 }
959 }
960
961 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
962 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
963 rtlpriv->link_info.num_tx_inperiod++;
964
965 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
966 "CMD TX OK interrupt!\n");
967 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
968 }
969 }
970
971 /*<3> Rx related */
972 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
973 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
974 _rtl_pci_rx_interrupt(hw);
975 }
976
977 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
978 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
979 "rx descriptor unavailable!\n");
980 _rtl_pci_rx_interrupt(hw);
981 }
982
983 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
984 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
985 _rtl_pci_rx_interrupt(hw);
986 }
987
988 /*<4> fw related*/
989 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
990 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
991 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
992 "firmware interrupt!\n");
993 queue_delayed_work(rtlpriv->works.rtl_wq,
994 &rtlpriv->works.fwevt_wq, 0);
995 }
996 }
997
998 /*<5> hsisr related*/
999 /* Only 8188EE & 8723BE Supported.
1000 * If Other ICs Come in, System will corrupt,
1001 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1002 * are not initialized
1003 */
1004 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1005 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1006 if (unlikely(intvec.inta &
1007 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1008 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1009 "hsisr interrupt!\n");
1010 _rtl_pci_hs_interrupt(hw);
1011 }
1012 }
1013
1014 if (rtlpriv->rtlhal.earlymode_enable)
1015 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1016
1017 done:
1018 rtlpriv->cfg->ops->enable_interrupt(hw);
1019 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1020 return ret;
1021 }
1022
_rtl_pci_irq_tasklet(struct tasklet_struct * t)1023 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1024 {
1025 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1026 struct ieee80211_hw *hw = rtlpriv->hw;
1027 _rtl_pci_tx_chk_waitq(hw);
1028 }
1029
_rtl_pci_prepare_bcn_tasklet(struct tasklet_struct * t)1030 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1031 {
1032 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1033 works.irq_prepare_bcn_tasklet);
1034 struct ieee80211_hw *hw = rtlpriv->hw;
1035 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1037 struct rtl8192_tx_ring *ring = NULL;
1038 struct ieee80211_hdr *hdr = NULL;
1039 struct ieee80211_tx_info *info = NULL;
1040 struct sk_buff *pskb = NULL;
1041 struct rtl_tx_desc *pdesc = NULL;
1042 struct rtl_tcb_desc tcb_desc;
1043 /*This is for new trx flow*/
1044 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1045 u8 temp_one = 1;
1046 u8 *entry;
1047
1048 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1049 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1050 pskb = __skb_dequeue(&ring->queue);
1051 if (rtlpriv->use_new_trx_flow)
1052 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1053 else
1054 entry = (u8 *)(&ring->desc[ring->idx]);
1055 if (pskb) {
1056 dma_unmap_single(&rtlpci->pdev->dev,
1057 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1058 true, HW_DESC_TXBUFF_ADDR),
1059 pskb->len, DMA_TO_DEVICE);
1060 kfree_skb(pskb);
1061 }
1062
1063 /*NB: the beacon data buffer must be 32-bit aligned. */
1064 pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1065 if (!pskb)
1066 return;
1067 hdr = rtl_get_hdr(pskb);
1068 info = IEEE80211_SKB_CB(pskb);
1069 pdesc = &ring->desc[0];
1070 if (rtlpriv->use_new_trx_flow)
1071 pbuffer_desc = &ring->buffer_desc[0];
1072
1073 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1074 (u8 *)pbuffer_desc, info, NULL, pskb,
1075 BEACON_QUEUE, &tcb_desc);
1076
1077 __skb_queue_tail(&ring->queue, pskb);
1078
1079 if (rtlpriv->use_new_trx_flow) {
1080 temp_one = 4;
1081 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1082 HW_DESC_OWN, (u8 *)&temp_one);
1083 } else {
1084 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1085 &temp_one);
1086 }
1087 }
1088
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1089 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1090 {
1091 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1092 struct rtl_priv *rtlpriv = rtl_priv(hw);
1093 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1094 u8 i;
1095 u16 desc_num;
1096
1097 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1098 desc_num = TX_DESC_NUM_92E;
1099 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1100 desc_num = TX_DESC_NUM_8822B;
1101 else
1102 desc_num = RT_TXDESC_NUM;
1103
1104 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1105 rtlpci->txringcount[i] = desc_num;
1106
1107 /*we just alloc 2 desc for beacon queue,
1108 *because we just need first desc in hw beacon.
1109 */
1110 rtlpci->txringcount[BEACON_QUEUE] = 2;
1111
1112 /*BE queue need more descriptor for performance
1113 *consideration or, No more tx desc will happen,
1114 *and may cause mac80211 mem leakage.
1115 */
1116 if (!rtl_priv(hw)->use_new_trx_flow)
1117 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1118
1119 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1120 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1121 }
1122
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1123 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1124 struct pci_dev *pdev)
1125 {
1126 struct rtl_priv *rtlpriv = rtl_priv(hw);
1127 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1128 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1129 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1130
1131 rtlpci->up_first_time = true;
1132 rtlpci->being_init_adapter = false;
1133
1134 rtlhal->hw = hw;
1135 rtlpci->pdev = pdev;
1136
1137 /*Tx/Rx related var */
1138 _rtl_pci_init_trx_var(hw);
1139
1140 /*IBSS*/
1141 mac->beacon_interval = 100;
1142
1143 /*AMPDU*/
1144 mac->min_space_cfg = 0;
1145 mac->max_mss_density = 0;
1146 /*set sane AMPDU defaults */
1147 mac->current_ampdu_density = 7;
1148 mac->current_ampdu_factor = 3;
1149
1150 /*Retry Limit*/
1151 mac->retry_short = 7;
1152 mac->retry_long = 7;
1153
1154 /*QOS*/
1155 rtlpci->acm_method = EACMWAY2_SW;
1156
1157 /*task */
1158 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1159 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1160 _rtl_pci_prepare_bcn_tasklet);
1161 INIT_WORK(&rtlpriv->works.lps_change_work,
1162 rtl_lps_change_work_callback);
1163 }
1164
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1165 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1166 unsigned int prio, unsigned int entries)
1167 {
1168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 struct rtl_tx_buffer_desc *buffer_desc;
1171 struct rtl_tx_desc *desc;
1172 dma_addr_t buffer_desc_dma, desc_dma;
1173 u32 nextdescaddress;
1174 int i;
1175
1176 /* alloc tx buffer desc for new trx flow*/
1177 if (rtlpriv->use_new_trx_flow) {
1178 buffer_desc =
1179 dma_alloc_coherent(&rtlpci->pdev->dev,
1180 sizeof(*buffer_desc) * entries,
1181 &buffer_desc_dma, GFP_KERNEL);
1182
1183 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1184 pr_err("Cannot allocate TX ring (prio = %d)\n",
1185 prio);
1186 return -ENOMEM;
1187 }
1188
1189 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1190 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1191
1192 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1193 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1194 }
1195
1196 /* alloc dma for this ring */
1197 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1198 &desc_dma, GFP_KERNEL);
1199
1200 if (!desc || (unsigned long)desc & 0xFF) {
1201 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1202 return -ENOMEM;
1203 }
1204
1205 rtlpci->tx_ring[prio].desc = desc;
1206 rtlpci->tx_ring[prio].dma = desc_dma;
1207
1208 rtlpci->tx_ring[prio].idx = 0;
1209 rtlpci->tx_ring[prio].entries = entries;
1210 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1211
1212 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1213 prio, desc);
1214
1215 /* init every desc in this ring */
1216 if (!rtlpriv->use_new_trx_flow) {
1217 for (i = 0; i < entries; i++) {
1218 nextdescaddress = (u32)desc_dma +
1219 ((i + 1) % entries) *
1220 sizeof(*desc);
1221
1222 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1223 true,
1224 HW_DESC_TX_NEXTDESC_ADDR,
1225 (u8 *)&nextdescaddress);
1226 }
1227 }
1228 return 0;
1229 }
1230
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1231 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1232 {
1233 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1234 struct rtl_priv *rtlpriv = rtl_priv(hw);
1235 int i;
1236
1237 if (rtlpriv->use_new_trx_flow) {
1238 struct rtl_rx_buffer_desc *entry = NULL;
1239 /* alloc dma for this ring */
1240 rtlpci->rx_ring[rxring_idx].buffer_desc =
1241 dma_alloc_coherent(&rtlpci->pdev->dev,
1242 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1243 rtlpci->rxringcount,
1244 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1245 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1246 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1247 pr_err("Cannot allocate RX ring\n");
1248 return -ENOMEM;
1249 }
1250
1251 /* init every desc in this ring */
1252 rtlpci->rx_ring[rxring_idx].idx = 0;
1253 for (i = 0; i < rtlpci->rxringcount; i++) {
1254 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1255 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1256 rxring_idx, i))
1257 return -ENOMEM;
1258 }
1259 } else {
1260 struct rtl_rx_desc *entry = NULL;
1261 u8 tmp_one = 1;
1262 /* alloc dma for this ring */
1263 rtlpci->rx_ring[rxring_idx].desc =
1264 dma_alloc_coherent(&rtlpci->pdev->dev,
1265 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1266 rtlpci->rxringcount,
1267 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1268 if (!rtlpci->rx_ring[rxring_idx].desc ||
1269 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1270 pr_err("Cannot allocate RX ring\n");
1271 return -ENOMEM;
1272 }
1273
1274 /* init every desc in this ring */
1275 rtlpci->rx_ring[rxring_idx].idx = 0;
1276
1277 for (i = 0; i < rtlpci->rxringcount; i++) {
1278 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1279 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1280 rxring_idx, i))
1281 return -ENOMEM;
1282 }
1283
1284 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1285 HW_DESC_RXERO, &tmp_one);
1286 }
1287 return 0;
1288 }
1289
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1290 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1291 unsigned int prio)
1292 {
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1294 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1295 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1296
1297 /* free every desc in this ring */
1298 while (skb_queue_len(&ring->queue)) {
1299 u8 *entry;
1300 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1301
1302 if (rtlpriv->use_new_trx_flow)
1303 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1304 else
1305 entry = (u8 *)(&ring->desc[ring->idx]);
1306
1307 dma_unmap_single(&rtlpci->pdev->dev,
1308 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1309 true, HW_DESC_TXBUFF_ADDR),
1310 skb->len, DMA_TO_DEVICE);
1311 kfree_skb(skb);
1312 ring->idx = (ring->idx + 1) % ring->entries;
1313 }
1314
1315 /* free dma of this ring */
1316 dma_free_coherent(&rtlpci->pdev->dev,
1317 sizeof(*ring->desc) * ring->entries, ring->desc,
1318 ring->dma);
1319 ring->desc = NULL;
1320 if (rtlpriv->use_new_trx_flow) {
1321 dma_free_coherent(&rtlpci->pdev->dev,
1322 sizeof(*ring->buffer_desc) * ring->entries,
1323 ring->buffer_desc, ring->buffer_desc_dma);
1324 ring->buffer_desc = NULL;
1325 }
1326 }
1327
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1328 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1329 {
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1332 int i;
1333
1334 /* free every desc in this ring */
1335 for (i = 0; i < rtlpci->rxringcount; i++) {
1336 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1337
1338 if (!skb)
1339 continue;
1340 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1341 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1342 kfree_skb(skb);
1343 }
1344
1345 /* free dma of this ring */
1346 if (rtlpriv->use_new_trx_flow) {
1347 dma_free_coherent(&rtlpci->pdev->dev,
1348 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1349 rtlpci->rxringcount,
1350 rtlpci->rx_ring[rxring_idx].buffer_desc,
1351 rtlpci->rx_ring[rxring_idx].dma);
1352 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1353 } else {
1354 dma_free_coherent(&rtlpci->pdev->dev,
1355 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1356 rtlpci->rxringcount,
1357 rtlpci->rx_ring[rxring_idx].desc,
1358 rtlpci->rx_ring[rxring_idx].dma);
1359 rtlpci->rx_ring[rxring_idx].desc = NULL;
1360 }
1361 }
1362
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1363 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1364 {
1365 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366 int ret;
1367 int i, rxring_idx;
1368
1369 /* rxring_idx 0:RX_MPDU_QUEUE
1370 * rxring_idx 1:RX_CMD_QUEUE
1371 */
1372 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1373 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1374 if (ret)
1375 return ret;
1376 }
1377
1378 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1379 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1380 if (ret)
1381 goto err_free_rings;
1382 }
1383
1384 return 0;
1385
1386 err_free_rings:
1387 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1388 _rtl_pci_free_rx_ring(hw, rxring_idx);
1389
1390 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1391 if (rtlpci->tx_ring[i].desc ||
1392 rtlpci->tx_ring[i].buffer_desc)
1393 _rtl_pci_free_tx_ring(hw, i);
1394
1395 return 1;
1396 }
1397
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1398 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1399 {
1400 u32 i, rxring_idx;
1401
1402 /*free rx rings */
1403 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1404 _rtl_pci_free_rx_ring(hw, rxring_idx);
1405
1406 /*free tx rings */
1407 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1408 _rtl_pci_free_tx_ring(hw, i);
1409
1410 return 0;
1411 }
1412
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1413 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1414 {
1415 struct rtl_priv *rtlpriv = rtl_priv(hw);
1416 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1417 int i, rxring_idx;
1418 unsigned long flags;
1419 u8 tmp_one = 1;
1420 u32 bufferaddress;
1421 /* rxring_idx 0:RX_MPDU_QUEUE */
1422 /* rxring_idx 1:RX_CMD_QUEUE */
1423 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1424 /* force the rx_ring[RX_MPDU_QUEUE/
1425 * RX_CMD_QUEUE].idx to the first one
1426 *new trx flow, do nothing
1427 */
1428 if (!rtlpriv->use_new_trx_flow &&
1429 rtlpci->rx_ring[rxring_idx].desc) {
1430 struct rtl_rx_desc *entry = NULL;
1431
1432 rtlpci->rx_ring[rxring_idx].idx = 0;
1433 for (i = 0; i < rtlpci->rxringcount; i++) {
1434 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1435 bufferaddress =
1436 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1437 false, HW_DESC_RXBUFF_ADDR);
1438 memset((u8 *)entry, 0,
1439 sizeof(*rtlpci->rx_ring
1440 [rxring_idx].desc));/*clear one entry*/
1441 if (rtlpriv->use_new_trx_flow) {
1442 rtlpriv->cfg->ops->set_desc(hw,
1443 (u8 *)entry, false,
1444 HW_DESC_RX_PREPARE,
1445 (u8 *)&bufferaddress);
1446 } else {
1447 rtlpriv->cfg->ops->set_desc(hw,
1448 (u8 *)entry, false,
1449 HW_DESC_RXBUFF_ADDR,
1450 (u8 *)&bufferaddress);
1451 rtlpriv->cfg->ops->set_desc(hw,
1452 (u8 *)entry, false,
1453 HW_DESC_RXPKT_LEN,
1454 (u8 *)&rtlpci->rxbuffersize);
1455 rtlpriv->cfg->ops->set_desc(hw,
1456 (u8 *)entry, false,
1457 HW_DESC_RXOWN,
1458 (u8 *)&tmp_one);
1459 }
1460 }
1461 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1462 HW_DESC_RXERO, (u8 *)&tmp_one);
1463 }
1464 rtlpci->rx_ring[rxring_idx].idx = 0;
1465 }
1466
1467 /*after reset, release previous pending packet,
1468 *and force the tx idx to the first one
1469 */
1470 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1471 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1472 if (rtlpci->tx_ring[i].desc ||
1473 rtlpci->tx_ring[i].buffer_desc) {
1474 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1475
1476 while (skb_queue_len(&ring->queue)) {
1477 u8 *entry;
1478 struct sk_buff *skb =
1479 __skb_dequeue(&ring->queue);
1480 if (rtlpriv->use_new_trx_flow)
1481 entry = (u8 *)(&ring->buffer_desc
1482 [ring->idx]);
1483 else
1484 entry = (u8 *)(&ring->desc[ring->idx]);
1485
1486 dma_unmap_single(&rtlpci->pdev->dev,
1487 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1488 true, HW_DESC_TXBUFF_ADDR),
1489 skb->len, DMA_TO_DEVICE);
1490 dev_kfree_skb_irq(skb);
1491 ring->idx = (ring->idx + 1) % ring->entries;
1492 }
1493
1494 if (rtlpriv->use_new_trx_flow) {
1495 rtlpci->tx_ring[i].cur_tx_rp = 0;
1496 rtlpci->tx_ring[i].cur_tx_wp = 0;
1497 }
1498
1499 ring->idx = 0;
1500 ring->entries = rtlpci->txringcount[i];
1501 }
1502 }
1503 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1504
1505 return 0;
1506 }
1507
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1508 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1509 struct ieee80211_sta *sta,
1510 struct sk_buff *skb)
1511 {
1512 struct rtl_priv *rtlpriv = rtl_priv(hw);
1513 struct rtl_sta_info *sta_entry = NULL;
1514 u8 tid = rtl_get_tid(skb);
1515 __le16 fc = rtl_get_fc(skb);
1516
1517 if (!sta)
1518 return false;
1519 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1520
1521 if (!rtlpriv->rtlhal.earlymode_enable)
1522 return false;
1523 if (ieee80211_is_nullfunc(fc))
1524 return false;
1525 if (ieee80211_is_qos_nullfunc(fc))
1526 return false;
1527 if (ieee80211_is_pspoll(fc))
1528 return false;
1529 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1530 return false;
1531 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1532 return false;
1533 if (tid > 7)
1534 return false;
1535
1536 /* maybe every tid should be checked */
1537 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1538 return false;
1539
1540 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1541 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1542 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1543
1544 return true;
1545 }
1546
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1547 static int rtl_pci_tx(struct ieee80211_hw *hw,
1548 struct ieee80211_sta *sta,
1549 struct sk_buff *skb,
1550 struct rtl_tcb_desc *ptcb_desc)
1551 {
1552 struct rtl_priv *rtlpriv = rtl_priv(hw);
1553 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1554 struct rtl8192_tx_ring *ring;
1555 struct rtl_tx_desc *pdesc;
1556 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1557 u16 idx;
1558 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1559 unsigned long flags;
1560 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1561 __le16 fc = rtl_get_fc(skb);
1562 u8 *pda_addr = hdr->addr1;
1563 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1564 u8 own;
1565 u8 temp_one = 1;
1566
1567 if (ieee80211_is_mgmt(fc))
1568 rtl_tx_mgmt_proc(hw, skb);
1569
1570 if (rtlpriv->psc.sw_ps_enabled) {
1571 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1572 !ieee80211_has_pm(fc))
1573 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1574 }
1575
1576 rtl_action_proc(hw, skb, true);
1577
1578 if (is_multicast_ether_addr(pda_addr))
1579 rtlpriv->stats.txbytesmulticast += skb->len;
1580 else if (is_broadcast_ether_addr(pda_addr))
1581 rtlpriv->stats.txbytesbroadcast += skb->len;
1582 else
1583 rtlpriv->stats.txbytesunicast += skb->len;
1584
1585 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1586 ring = &rtlpci->tx_ring[hw_queue];
1587 if (hw_queue != BEACON_QUEUE) {
1588 if (rtlpriv->use_new_trx_flow)
1589 idx = ring->cur_tx_wp;
1590 else
1591 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1592 ring->entries;
1593 } else {
1594 idx = 0;
1595 }
1596
1597 pdesc = &ring->desc[idx];
1598 if (rtlpriv->use_new_trx_flow) {
1599 ptx_bd_desc = &ring->buffer_desc[idx];
1600 } else {
1601 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1602 true, HW_DESC_OWN);
1603
1604 if (own == 1 && hw_queue != BEACON_QUEUE) {
1605 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1606 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1607 hw_queue, ring->idx, idx,
1608 skb_queue_len(&ring->queue));
1609
1610 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1611 flags);
1612 return skb->len;
1613 }
1614 }
1615
1616 if (rtlpriv->cfg->ops->get_available_desc &&
1617 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1618 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1619 "get_available_desc fail\n");
1620 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1621 return skb->len;
1622 }
1623
1624 if (ieee80211_is_data(fc))
1625 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1626
1627 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1628 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1629
1630 __skb_queue_tail(&ring->queue, skb);
1631
1632 if (rtlpriv->use_new_trx_flow) {
1633 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1634 HW_DESC_OWN, &hw_queue);
1635 } else {
1636 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1637 HW_DESC_OWN, &temp_one);
1638 }
1639
1640 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1641 hw_queue != BEACON_QUEUE) {
1642 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1643 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1644 hw_queue, ring->idx, idx,
1645 skb_queue_len(&ring->queue));
1646
1647 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1648 }
1649
1650 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1651
1652 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1653
1654 return 0;
1655 }
1656
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1657 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1658 {
1659 struct rtl_priv *rtlpriv = rtl_priv(hw);
1660 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1662 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1663 u16 i = 0;
1664 int queue_id;
1665 struct rtl8192_tx_ring *ring;
1666
1667 if (mac->skip_scan)
1668 return;
1669
1670 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1671 u32 queue_len;
1672
1673 if (((queues >> queue_id) & 0x1) == 0) {
1674 queue_id--;
1675 continue;
1676 }
1677 ring = &pcipriv->dev.tx_ring[queue_id];
1678 queue_len = skb_queue_len(&ring->queue);
1679 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1680 queue_id == TXCMD_QUEUE) {
1681 queue_id--;
1682 continue;
1683 } else {
1684 msleep(20);
1685 i++;
1686 }
1687
1688 /* we just wait 1s for all queues */
1689 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1690 is_hal_stop(rtlhal) || i >= 200)
1691 return;
1692 }
1693 }
1694
rtl_pci_deinit(struct ieee80211_hw * hw)1695 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1696 {
1697 struct rtl_priv *rtlpriv = rtl_priv(hw);
1698 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1699
1700 _rtl_pci_deinit_trx_ring(hw);
1701
1702 synchronize_irq(rtlpci->pdev->irq);
1703 tasklet_kill(&rtlpriv->works.irq_tasklet);
1704 cancel_work_sync(&rtlpriv->works.lps_change_work);
1705
1706 destroy_workqueue(rtlpriv->works.rtl_wq);
1707 }
1708
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1709 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1710 {
1711 int err;
1712
1713 _rtl_pci_init_struct(hw, pdev);
1714
1715 err = _rtl_pci_init_trx_ring(hw);
1716 if (err) {
1717 pr_err("tx ring initialization failed\n");
1718 return err;
1719 }
1720
1721 return 0;
1722 }
1723
rtl_pci_start(struct ieee80211_hw * hw)1724 static int rtl_pci_start(struct ieee80211_hw *hw)
1725 {
1726 struct rtl_priv *rtlpriv = rtl_priv(hw);
1727 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1728 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1729 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1730 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1731 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1732
1733 int err;
1734
1735 rtl_pci_reset_trx_ring(hw);
1736
1737 rtlpci->driver_is_goingto_unload = false;
1738 if (rtlpriv->cfg->ops->get_btc_status &&
1739 rtlpriv->cfg->ops->get_btc_status()) {
1740 rtlpriv->btcoexist.btc_info.ap_num = 36;
1741 btc_ops->btc_init_variables(rtlpriv);
1742 btc_ops->btc_init_hal_vars(rtlpriv);
1743 } else if (btc_ops) {
1744 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1745 }
1746
1747 err = rtlpriv->cfg->ops->hw_init(hw);
1748 if (err) {
1749 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1750 "Failed to config hardware!\n");
1751 kfree(rtlpriv->btcoexist.btc_context);
1752 kfree(rtlpriv->btcoexist.wifi_only_context);
1753 return err;
1754 }
1755 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1756 &rtlmac->retry_long);
1757
1758 rtlpriv->cfg->ops->enable_interrupt(hw);
1759 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1760
1761 rtl_init_rx_config(hw);
1762
1763 /*should be after adapter start and interrupt enable. */
1764 set_hal_start(rtlhal);
1765
1766 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1767
1768 rtlpci->up_first_time = false;
1769
1770 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1771 return 0;
1772 }
1773
rtl_pci_stop(struct ieee80211_hw * hw)1774 static void rtl_pci_stop(struct ieee80211_hw *hw)
1775 {
1776 struct rtl_priv *rtlpriv = rtl_priv(hw);
1777 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1778 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1779 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1780 unsigned long flags;
1781 u8 rf_timeout = 0;
1782
1783 if (rtlpriv->cfg->ops->get_btc_status())
1784 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1785
1786 if (rtlpriv->btcoexist.btc_ops)
1787 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1788
1789 /*should be before disable interrupt&adapter
1790 *and will do it immediately.
1791 */
1792 set_hal_stop(rtlhal);
1793
1794 rtlpci->driver_is_goingto_unload = true;
1795 rtlpriv->cfg->ops->disable_interrupt(hw);
1796 cancel_work_sync(&rtlpriv->works.lps_change_work);
1797
1798 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1799 while (ppsc->rfchange_inprogress) {
1800 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1801 if (rf_timeout > 100) {
1802 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1803 break;
1804 }
1805 mdelay(1);
1806 rf_timeout++;
1807 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1808 }
1809 ppsc->rfchange_inprogress = true;
1810 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1811
1812 rtlpriv->cfg->ops->hw_disable(hw);
1813 /* some things are not needed if firmware not available */
1814 if (!rtlpriv->max_fw_size)
1815 return;
1816 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1817
1818 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1819 ppsc->rfchange_inprogress = false;
1820 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1821
1822 rtl_pci_enable_aspm(hw);
1823 }
1824
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1825 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1826 struct ieee80211_hw *hw)
1827 {
1828 struct rtl_priv *rtlpriv = rtl_priv(hw);
1829 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1831 struct pci_dev *bridge_pdev = pdev->bus->self;
1832 u16 venderid;
1833 u16 deviceid;
1834 u8 revisionid;
1835 u16 irqline;
1836 u8 tmp;
1837
1838 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1839 venderid = pdev->vendor;
1840 deviceid = pdev->device;
1841 pci_read_config_byte(pdev, 0x8, &revisionid);
1842 pci_read_config_word(pdev, 0x3C, &irqline);
1843
1844 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1845 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1846 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1847 * the correct driver is r8192e_pci, thus this routine should
1848 * return false.
1849 */
1850 if (deviceid == RTL_PCI_8192SE_DID &&
1851 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1852 return false;
1853
1854 if (deviceid == RTL_PCI_8192_DID ||
1855 deviceid == RTL_PCI_0044_DID ||
1856 deviceid == RTL_PCI_0047_DID ||
1857 deviceid == RTL_PCI_8192SE_DID ||
1858 deviceid == RTL_PCI_8174_DID ||
1859 deviceid == RTL_PCI_8173_DID ||
1860 deviceid == RTL_PCI_8172_DID ||
1861 deviceid == RTL_PCI_8171_DID) {
1862 switch (revisionid) {
1863 case RTL_PCI_REVISION_ID_8192PCIE:
1864 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1865 "8192 PCI-E is found - vid/did=%x/%x\n",
1866 venderid, deviceid);
1867 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1868 return false;
1869 case RTL_PCI_REVISION_ID_8192SE:
1870 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1871 "8192SE is found - vid/did=%x/%x\n",
1872 venderid, deviceid);
1873 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1874 break;
1875 default:
1876 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1877 "Err: Unknown device - vid/did=%x/%x\n",
1878 venderid, deviceid);
1879 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1880 break;
1881 }
1882 } else if (deviceid == RTL_PCI_8723AE_DID) {
1883 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1884 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1885 "8723AE PCI-E is found - vid/did=%x/%x\n",
1886 venderid, deviceid);
1887 } else if (deviceid == RTL_PCI_8192CET_DID ||
1888 deviceid == RTL_PCI_8192CE_DID ||
1889 deviceid == RTL_PCI_8191CE_DID ||
1890 deviceid == RTL_PCI_8188CE_DID) {
1891 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1892 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1893 "8192C PCI-E is found - vid/did=%x/%x\n",
1894 venderid, deviceid);
1895 } else if (deviceid == RTL_PCI_8192DE_DID ||
1896 deviceid == RTL_PCI_8192DE_DID2) {
1897 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1898 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1899 "8192D PCI-E is found - vid/did=%x/%x\n",
1900 venderid, deviceid);
1901 } else if (deviceid == RTL_PCI_8188EE_DID) {
1902 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1903 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1904 "Find adapter, Hardware type is 8188EE\n");
1905 } else if (deviceid == RTL_PCI_8723BE_DID) {
1906 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1907 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1908 "Find adapter, Hardware type is 8723BE\n");
1909 } else if (deviceid == RTL_PCI_8192EE_DID) {
1910 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1911 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1912 "Find adapter, Hardware type is 8192EE\n");
1913 } else if (deviceid == RTL_PCI_8821AE_DID) {
1914 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1915 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1916 "Find adapter, Hardware type is 8821AE\n");
1917 } else if (deviceid == RTL_PCI_8812AE_DID) {
1918 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1919 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1920 "Find adapter, Hardware type is 8812AE\n");
1921 } else if (deviceid == RTL_PCI_8822BE_DID) {
1922 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1923 rtlhal->bandset = BAND_ON_BOTH;
1924 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1925 "Find adapter, Hardware type is 8822BE\n");
1926 } else {
1927 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1928 "Err: Unknown device - vid/did=%x/%x\n",
1929 venderid, deviceid);
1930
1931 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1932 }
1933
1934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1935 if (revisionid == 0 || revisionid == 1) {
1936 if (revisionid == 0) {
1937 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1938 "Find 92DE MAC0\n");
1939 rtlhal->interfaceindex = 0;
1940 } else if (revisionid == 1) {
1941 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1942 "Find 92DE MAC1\n");
1943 rtlhal->interfaceindex = 1;
1944 }
1945 } else {
1946 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1947 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1948 venderid, deviceid, revisionid);
1949 rtlhal->interfaceindex = 0;
1950 }
1951 }
1952
1953 switch (rtlhal->hw_type) {
1954 case HARDWARE_TYPE_RTL8192EE:
1955 case HARDWARE_TYPE_RTL8822BE:
1956 /* use new trx flow */
1957 rtlpriv->use_new_trx_flow = true;
1958 break;
1959
1960 default:
1961 rtlpriv->use_new_trx_flow = false;
1962 break;
1963 }
1964
1965 /*find bus info */
1966 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1967 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1968 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1969
1970 /*find bridge info */
1971 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1972 /* some ARM have no bridge_pdev and will crash here
1973 * so we should check if bridge_pdev is NULL
1974 */
1975 if (bridge_pdev) {
1976 /*find bridge info if available */
1977 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1978 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1979 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1980 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1981 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1982 "Pci Bridge Vendor is found index: %d\n",
1983 tmp);
1984 break;
1985 }
1986 }
1987 }
1988
1989 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1990 PCI_BRIDGE_VENDOR_UNKNOWN) {
1991 pcipriv->ndis_adapter.pcibridge_busnum =
1992 bridge_pdev->bus->number;
1993 pcipriv->ndis_adapter.pcibridge_devnum =
1994 PCI_SLOT(bridge_pdev->devfn);
1995 pcipriv->ndis_adapter.pcibridge_funcnum =
1996 PCI_FUNC(bridge_pdev->devfn);
1997
1998 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1999 PCI_BRIDGE_VENDOR_AMD) {
2000 pcipriv->ndis_adapter.amd_l1_patch =
2001 rtl_pci_get_amd_l1_patch(hw);
2002 }
2003 }
2004
2005 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2006 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2007 pcipriv->ndis_adapter.busnumber,
2008 pcipriv->ndis_adapter.devnumber,
2009 pcipriv->ndis_adapter.funcnumber,
2010 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2011
2012 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2013 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n",
2014 pcipriv->ndis_adapter.pcibridge_busnum,
2015 pcipriv->ndis_adapter.pcibridge_devnum,
2016 pcipriv->ndis_adapter.pcibridge_funcnum,
2017 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2018 pcipriv->ndis_adapter.amd_l1_patch);
2019
2020 rtl_pci_parse_configuration(pdev, hw);
2021 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2022
2023 return true;
2024 }
2025
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)2026 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2027 {
2028 struct rtl_priv *rtlpriv = rtl_priv(hw);
2029 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2030 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2031 int ret;
2032
2033 ret = pci_enable_msi(rtlpci->pdev);
2034 if (ret < 0)
2035 return ret;
2036
2037 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2038 IRQF_SHARED, KBUILD_MODNAME, hw);
2039 if (ret < 0) {
2040 pci_disable_msi(rtlpci->pdev);
2041 return ret;
2042 }
2043
2044 rtlpci->using_msi = true;
2045
2046 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2047 "MSI Interrupt Mode!\n");
2048 return 0;
2049 }
2050
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2051 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2052 {
2053 struct rtl_priv *rtlpriv = rtl_priv(hw);
2054 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2055 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2056 int ret;
2057
2058 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2059 IRQF_SHARED, KBUILD_MODNAME, hw);
2060 if (ret < 0)
2061 return ret;
2062
2063 rtlpci->using_msi = false;
2064 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2065 "Pin-based Interrupt Mode!\n");
2066 return 0;
2067 }
2068
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2069 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2070 {
2071 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2072 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2073 int ret;
2074
2075 if (rtlpci->msi_support) {
2076 ret = rtl_pci_intr_mode_msi(hw);
2077 if (ret < 0)
2078 ret = rtl_pci_intr_mode_legacy(hw);
2079 } else {
2080 ret = rtl_pci_intr_mode_legacy(hw);
2081 }
2082 return ret;
2083 }
2084
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2085 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2086 {
2087 u8 value;
2088
2089 pci_read_config_byte(pdev, 0x719, &value);
2090
2091 /* 0x719 Bit5 is DMA64 bit fetch. */
2092 if (dma64)
2093 value |= BIT(5);
2094 else
2095 value &= ~BIT(5);
2096
2097 pci_write_config_byte(pdev, 0x719, value);
2098 }
2099
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2100 int rtl_pci_probe(struct pci_dev *pdev,
2101 const struct pci_device_id *id)
2102 {
2103 struct ieee80211_hw *hw = NULL;
2104
2105 struct rtl_priv *rtlpriv = NULL;
2106 struct rtl_pci_priv *pcipriv = NULL;
2107 struct rtl_pci *rtlpci;
2108 unsigned long pmem_start, pmem_len, pmem_flags;
2109 int err;
2110
2111 err = pci_enable_device(pdev);
2112 if (err) {
2113 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2114 pci_name(pdev));
2115 return err;
2116 }
2117
2118 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2119 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2120 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2121 WARN_ONCE(true,
2122 "Unable to obtain 64bit DMA for consistent allocations\n");
2123 err = -ENOMEM;
2124 goto fail1;
2125 }
2126
2127 platform_enable_dma64(pdev, true);
2128 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2129 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2130 WARN_ONCE(true,
2131 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2132 err = -ENOMEM;
2133 goto fail1;
2134 }
2135
2136 platform_enable_dma64(pdev, false);
2137 }
2138
2139 pci_set_master(pdev);
2140
2141 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2142 sizeof(struct rtl_priv), &rtl_ops);
2143 if (!hw) {
2144 WARN_ONCE(true,
2145 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2146 err = -ENOMEM;
2147 goto fail1;
2148 }
2149
2150 SET_IEEE80211_DEV(hw, &pdev->dev);
2151 pci_set_drvdata(pdev, hw);
2152
2153 rtlpriv = hw->priv;
2154 rtlpriv->hw = hw;
2155 pcipriv = (void *)rtlpriv->priv;
2156 pcipriv->dev.pdev = pdev;
2157 init_completion(&rtlpriv->firmware_loading_complete);
2158 /*proximity init here*/
2159 rtlpriv->proximity.proxim_on = false;
2160
2161 pcipriv = (void *)rtlpriv->priv;
2162 pcipriv->dev.pdev = pdev;
2163
2164 /* init cfg & intf_ops */
2165 rtlpriv->rtlhal.interface = INTF_PCI;
2166 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2167 rtlpriv->intf_ops = &rtl_pci_ops;
2168 rtlpriv->glb_var = &rtl_global_var;
2169 rtl_efuse_ops_init(hw);
2170
2171 /* MEM map */
2172 err = pci_request_regions(pdev, KBUILD_MODNAME);
2173 if (err) {
2174 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2175 goto fail1;
2176 }
2177
2178 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2179 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2180 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2181
2182 /*shared mem start */
2183 rtlpriv->io.pci_mem_start =
2184 (unsigned long)pci_iomap(pdev,
2185 rtlpriv->cfg->bar_id, pmem_len);
2186 if (rtlpriv->io.pci_mem_start == 0) {
2187 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2188 err = -ENOMEM;
2189 goto fail2;
2190 }
2191
2192 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2193 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2194 pmem_start, pmem_len, pmem_flags,
2195 rtlpriv->io.pci_mem_start);
2196
2197 /* Disable Clk Request */
2198 pci_write_config_byte(pdev, 0x81, 0);
2199 /* leave D3 mode */
2200 pci_write_config_byte(pdev, 0x44, 0);
2201 pci_write_config_byte(pdev, 0x04, 0x06);
2202 pci_write_config_byte(pdev, 0x04, 0x07);
2203
2204 /* find adapter */
2205 if (!_rtl_pci_find_adapter(pdev, hw)) {
2206 err = -ENODEV;
2207 goto fail2;
2208 }
2209
2210 /* Init IO handler */
2211 _rtl_pci_io_handler_init(&pdev->dev, hw);
2212
2213 /*like read eeprom and so on */
2214 rtlpriv->cfg->ops->read_eeprom_info(hw);
2215
2216 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2217 pr_err("Can't init_sw_vars\n");
2218 err = -ENODEV;
2219 goto fail3;
2220 }
2221 rtlpriv->cfg->ops->init_sw_leds(hw);
2222
2223 /*aspm */
2224 rtl_pci_init_aspm(hw);
2225
2226 /* Init mac80211 sw */
2227 err = rtl_init_core(hw);
2228 if (err) {
2229 pr_err("Can't allocate sw for mac80211\n");
2230 goto fail3;
2231 }
2232
2233 /* Init PCI sw */
2234 err = rtl_pci_init(hw, pdev);
2235 if (err) {
2236 pr_err("Failed to init PCI\n");
2237 goto fail3;
2238 }
2239
2240 err = ieee80211_register_hw(hw);
2241 if (err) {
2242 pr_err("Can't register mac80211 hw.\n");
2243 err = -ENODEV;
2244 goto fail3;
2245 }
2246 rtlpriv->mac80211.mac80211_registered = 1;
2247
2248 /* add for debug */
2249 rtl_debug_add_one(hw);
2250
2251 /*init rfkill */
2252 rtl_init_rfkill(hw); /* Init PCI sw */
2253
2254 rtlpci = rtl_pcidev(pcipriv);
2255 err = rtl_pci_intr_mode_decide(hw);
2256 if (err) {
2257 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2258 "%s: failed to register IRQ handler\n",
2259 wiphy_name(hw->wiphy));
2260 goto fail3;
2261 }
2262 rtlpci->irq_alloc = 1;
2263
2264 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2265 return 0;
2266
2267 fail3:
2268 pci_set_drvdata(pdev, NULL);
2269 rtl_deinit_core(hw);
2270
2271 fail2:
2272 if (rtlpriv->io.pci_mem_start != 0)
2273 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2274
2275 pci_release_regions(pdev);
2276 complete(&rtlpriv->firmware_loading_complete);
2277
2278 fail1:
2279 if (hw)
2280 ieee80211_free_hw(hw);
2281 pci_disable_device(pdev);
2282
2283 return err;
2284 }
2285 EXPORT_SYMBOL(rtl_pci_probe);
2286
rtl_pci_disconnect(struct pci_dev * pdev)2287 void rtl_pci_disconnect(struct pci_dev *pdev)
2288 {
2289 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2290 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2291 struct rtl_priv *rtlpriv = rtl_priv(hw);
2292 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2293 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2294
2295 /* just in case driver is removed before firmware callback */
2296 wait_for_completion(&rtlpriv->firmware_loading_complete);
2297 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2298
2299 /* remove form debug */
2300 rtl_debug_remove_one(hw);
2301
2302 /*ieee80211_unregister_hw will call ops_stop */
2303 if (rtlmac->mac80211_registered == 1) {
2304 ieee80211_unregister_hw(hw);
2305 rtlmac->mac80211_registered = 0;
2306 } else {
2307 rtl_deinit_deferred_work(hw, false);
2308 rtlpriv->intf_ops->adapter_stop(hw);
2309 }
2310 rtlpriv->cfg->ops->disable_interrupt(hw);
2311
2312 /*deinit rfkill */
2313 rtl_deinit_rfkill(hw);
2314
2315 rtl_pci_deinit(hw);
2316 rtl_deinit_core(hw);
2317 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2318
2319 if (rtlpci->irq_alloc) {
2320 free_irq(rtlpci->pdev->irq, hw);
2321 rtlpci->irq_alloc = 0;
2322 }
2323
2324 if (rtlpci->using_msi)
2325 pci_disable_msi(rtlpci->pdev);
2326
2327 list_del(&rtlpriv->list);
2328 if (rtlpriv->io.pci_mem_start != 0) {
2329 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2330 pci_release_regions(pdev);
2331 }
2332
2333 pci_disable_device(pdev);
2334
2335 rtl_pci_disable_aspm(hw);
2336
2337 pci_set_drvdata(pdev, NULL);
2338
2339 ieee80211_free_hw(hw);
2340 }
2341 EXPORT_SYMBOL(rtl_pci_disconnect);
2342
2343 #ifdef CONFIG_PM_SLEEP
2344 /***************************************
2345 * kernel pci power state define:
2346 * PCI_D0 ((pci_power_t __force) 0)
2347 * PCI_D1 ((pci_power_t __force) 1)
2348 * PCI_D2 ((pci_power_t __force) 2)
2349 * PCI_D3hot ((pci_power_t __force) 3)
2350 * PCI_D3cold ((pci_power_t __force) 4)
2351 * PCI_UNKNOWN ((pci_power_t __force) 5)
2352
2353 * This function is called when system
2354 * goes into suspend state mac80211 will
2355 * call rtl_mac_stop() from the mac80211
2356 * suspend function first, So there is
2357 * no need to call hw_disable here.
2358 ****************************************/
rtl_pci_suspend(struct device * dev)2359 int rtl_pci_suspend(struct device *dev)
2360 {
2361 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2362 struct rtl_priv *rtlpriv = rtl_priv(hw);
2363
2364 rtlpriv->cfg->ops->hw_suspend(hw);
2365 rtl_deinit_rfkill(hw);
2366
2367 return 0;
2368 }
2369 EXPORT_SYMBOL(rtl_pci_suspend);
2370
rtl_pci_resume(struct device * dev)2371 int rtl_pci_resume(struct device *dev)
2372 {
2373 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2374 struct rtl_priv *rtlpriv = rtl_priv(hw);
2375
2376 rtlpriv->cfg->ops->hw_resume(hw);
2377 rtl_init_rfkill(hw);
2378 return 0;
2379 }
2380 EXPORT_SYMBOL(rtl_pci_resume);
2381 #endif /* CONFIG_PM_SLEEP */
2382
2383 const struct rtl_intf_ops rtl_pci_ops = {
2384 .read_efuse_byte = read_efuse_byte,
2385 .adapter_start = rtl_pci_start,
2386 .adapter_stop = rtl_pci_stop,
2387 .check_buddy_priv = rtl_pci_check_buddy_priv,
2388 .adapter_tx = rtl_pci_tx,
2389 .flush = rtl_pci_flush,
2390 .reset_trx_ring = rtl_pci_reset_trx_ring,
2391 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2392
2393 .disable_aspm = rtl_pci_disable_aspm,
2394 .enable_aspm = rtl_pci_enable_aspm,
2395 };
2396