1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Driver for the MMC / SD / SDIO cell found in:
4 *
5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
6 *
7 * Copyright (C) 2015-19 Renesas Electronics Corporation
8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
10 * Copyright (C) 2007 Ian Molton
11 * Copyright (C) 2004 Ian Molton
12 */
13
14 #ifndef TMIO_MMC_H
15 #define TMIO_MMC_H
16
17 #include <linux/dmaengine.h>
18 #include <linux/highmem.h>
19 #include <linux/mutex.h>
20 #include <linux/pagemap.h>
21 #include <linux/scatterlist.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24
25 #define CTL_SD_CMD 0x00
26 #define CTL_ARG_REG 0x04
27 #define CTL_STOP_INTERNAL_ACTION 0x08
28 #define CTL_XFER_BLK_COUNT 0xa
29 #define CTL_RESPONSE 0x0c
30 /* driver merges STATUS and following STATUS2 */
31 #define CTL_STATUS 0x1c
32 /* driver merges IRQ_MASK and following IRQ_MASK2 */
33 #define CTL_IRQ_MASK 0x20
34 #define CTL_SD_CARD_CLK_CTL 0x24
35 #define CTL_SD_XFER_LEN 0x26
36 #define CTL_SD_MEM_CARD_OPT 0x28
37 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
38 #define CTL_SD_DATA_PORT 0x30
39 #define CTL_TRANSACTION_CTL 0x34
40 #define CTL_SDIO_STATUS 0x36
41 #define CTL_SDIO_IRQ_MASK 0x38
42 #define CTL_DMA_ENABLE 0xd8
43 #define CTL_RESET_SD 0xe0
44 #define CTL_VERSION 0xe2
45 #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */
46
47 /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
48 #define TMIO_STOP_STP BIT(0)
49 #define TMIO_STOP_SEC BIT(8)
50
51 /* Definitions for values the CTL_STATUS register can take */
52 #define TMIO_STAT_CMDRESPEND BIT(0)
53 #define TMIO_STAT_DATAEND BIT(2)
54 #define TMIO_STAT_CARD_REMOVE BIT(3)
55 #define TMIO_STAT_CARD_INSERT BIT(4)
56 #define TMIO_STAT_SIGSTATE BIT(5)
57 #define TMIO_STAT_WRPROTECT BIT(7)
58 #define TMIO_STAT_CARD_REMOVE_A BIT(8)
59 #define TMIO_STAT_CARD_INSERT_A BIT(9)
60 #define TMIO_STAT_SIGSTATE_A BIT(10)
61
62 /* These belong technically to CTL_STATUS2, but the driver merges them */
63 #define TMIO_STAT_CMD_IDX_ERR BIT(16)
64 #define TMIO_STAT_CRCFAIL BIT(17)
65 #define TMIO_STAT_STOPBIT_ERR BIT(18)
66 #define TMIO_STAT_DATATIMEOUT BIT(19)
67 #define TMIO_STAT_RXOVERFLOW BIT(20)
68 #define TMIO_STAT_TXUNDERRUN BIT(21)
69 #define TMIO_STAT_CMDTIMEOUT BIT(22)
70 #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
71 #define TMIO_STAT_RXRDY BIT(24)
72 #define TMIO_STAT_TXRQ BIT(25)
73 #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */
74 #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
75 #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
76 #define TMIO_STAT_CMD_BUSY BIT(30)
77 #define TMIO_STAT_ILL_ACCESS BIT(31)
78
79 /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
80 #define CLK_CTL_DIV_MASK 0xff
81 #define CLK_CTL_SCLKEN BIT(8)
82
83 /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
84 #define CARD_OPT_TOP_MASK 0xf0
85 #define CARD_OPT_TOP_SHIFT 4
86 #define CARD_OPT_EXTOP BIT(9) /* first appeared on R-Car Gen3 SDHI */
87 #define CARD_OPT_WIDTH8 BIT(13)
88 #define CARD_OPT_ALWAYS1 BIT(14)
89 #define CARD_OPT_WIDTH BIT(15)
90
91 /* Definitions for values the CTL_SDIO_STATUS register can take */
92 #define TMIO_SDIO_STAT_IOIRQ 0x0001
93 #define TMIO_SDIO_STAT_EXPUB52 0x4000
94 #define TMIO_SDIO_STAT_EXWT 0x8000
95 #define TMIO_SDIO_MASK_ALL 0xc007
96
97 #define TMIO_SDIO_SETBITS_MASK 0x0006
98
99 /* Definitions for values the CTL_DMA_ENABLE register can take */
100 #define DMA_ENABLE_DMASDRW BIT(1)
101
102 /* Definitions for values the CTL_SDIF_MODE register can take */
103 #define SDIF_MODE_HS400 BIT(0) /* only known on R-Car 2+ */
104
105 /* Define some IRQ masks */
106 /* This is the mask used at reset by the chip */
107 #define TMIO_MASK_ALL 0x837f031d
108 #define TMIO_MASK_ALL_RCAR2 0x8b7f031d
109 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
110 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
111 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
112 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
113 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
114
115 #define TMIO_MAX_BLK_SIZE 512
116
117 struct tmio_mmc_data;
118 struct tmio_mmc_host;
119
120 struct tmio_mmc_dma_ops {
121 void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
122 void (*enable)(struct tmio_mmc_host *host, bool enable);
123 void (*request)(struct tmio_mmc_host *host,
124 struct tmio_mmc_data *pdata);
125 void (*release)(struct tmio_mmc_host *host);
126 void (*abort)(struct tmio_mmc_host *host);
127 void (*dataend)(struct tmio_mmc_host *host);
128
129 /* optional */
130 void (*end)(struct tmio_mmc_host *host); /* held host->lock */
131 };
132
133 struct tmio_mmc_host {
134 void __iomem *ctl;
135 struct mmc_command *cmd;
136 struct mmc_request *mrq;
137 struct mmc_data *data;
138 struct mmc_host *mmc;
139 struct mmc_host_ops ops;
140
141 /* Callbacks for clock / power control */
142 void (*set_pwr)(struct platform_device *host, int state);
143
144 /* pio related stuff */
145 struct scatterlist *sg_ptr;
146 struct scatterlist *sg_orig;
147 unsigned int sg_len;
148 unsigned int sg_off;
149 unsigned int bus_shift;
150
151 struct platform_device *pdev;
152 struct tmio_mmc_data *pdata;
153
154 /* DMA support */
155 bool dma_on;
156 struct dma_chan *chan_rx;
157 struct dma_chan *chan_tx;
158 struct tasklet_struct dma_issue;
159 struct scatterlist bounce_sg;
160 u8 *bounce_buf;
161
162 /* Track lost interrupts */
163 struct delayed_work delayed_reset_work;
164 struct work_struct done;
165
166 /* Cache */
167 u32 sdcard_irq_mask;
168 u32 sdio_irq_mask;
169 unsigned int clk_cache;
170 u32 sdcard_irq_setbit_mask;
171 u32 sdcard_irq_mask_all;
172
173 spinlock_t lock; /* protect host private data */
174 unsigned long last_req_ts;
175 struct mutex ios_lock; /* protect set_ios() context */
176 bool native_hotplug;
177 bool sdio_irq_enabled;
178
179 /* Mandatory callback */
180 int (*clk_enable)(struct tmio_mmc_host *host);
181 void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
182
183 /* Optional callbacks */
184 void (*clk_disable)(struct tmio_mmc_host *host);
185 int (*multi_io_quirk)(struct mmc_card *card,
186 unsigned int direction, int blk_size);
187 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
188 void (*reset)(struct tmio_mmc_host *host, bool preserve);
189 bool (*check_retune)(struct tmio_mmc_host *host, struct mmc_request *mrq);
190 void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq);
191 unsigned int (*get_timeout_cycles)(struct tmio_mmc_host *host);
192
193 const struct tmio_mmc_dma_ops *dma_ops;
194 };
195
196 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
197 struct tmio_mmc_data *pdata);
198 void tmio_mmc_host_free(struct tmio_mmc_host *host);
199 int tmio_mmc_host_probe(struct tmio_mmc_host *host);
200 void tmio_mmc_host_remove(struct tmio_mmc_host *host);
201 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
202
203 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
204 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
205 irqreturn_t tmio_mmc_irq(int irq, void *devid);
206
tmio_mmc_kmap_atomic(struct scatterlist * sg,unsigned long * flags)207 static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
208 unsigned long *flags)
209 {
210 local_irq_save(*flags);
211 return kmap_atomic(sg_page(sg)) + sg->offset;
212 }
213
tmio_mmc_kunmap_atomic(struct scatterlist * sg,unsigned long * flags,void * virt)214 static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
215 unsigned long *flags, void *virt)
216 {
217 kunmap_atomic(virt - sg->offset);
218 local_irq_restore(*flags);
219 }
220
221 #ifdef CONFIG_PM
222 int tmio_mmc_host_runtime_suspend(struct device *dev);
223 int tmio_mmc_host_runtime_resume(struct device *dev);
224 #endif
225
sd_ctrl_read16(struct tmio_mmc_host * host,int addr)226 static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
227 {
228 return ioread16(host->ctl + (addr << host->bus_shift));
229 }
230
sd_ctrl_read16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)231 static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
232 u16 *buf, int count)
233 {
234 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
235 }
236
sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host * host,int addr)237 static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
238 int addr)
239 {
240 return ioread16(host->ctl + (addr << host->bus_shift)) |
241 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
242 }
243
sd_ctrl_read32_rep(struct tmio_mmc_host * host,int addr,u32 * buf,int count)244 static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
245 u32 *buf, int count)
246 {
247 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
248 }
249
sd_ctrl_write16(struct tmio_mmc_host * host,int addr,u16 val)250 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
251 u16 val)
252 {
253 /* If there is a hook and it returns non-zero then there
254 * is an error and the write should be skipped
255 */
256 if (host->write16_hook && host->write16_hook(host, addr))
257 return;
258 iowrite16(val, host->ctl + (addr << host->bus_shift));
259 }
260
sd_ctrl_write16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)261 static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
262 u16 *buf, int count)
263 {
264 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
265 }
266
sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host * host,int addr,u32 val)267 static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
268 int addr, u32 val)
269 {
270 if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
271 val |= host->sdcard_irq_setbit_mask;
272
273 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
274 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
275 }
276
sd_ctrl_write32(struct tmio_mmc_host * host,int addr,u32 val)277 static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
278 {
279 iowrite32(val, host->ctl + (addr << host->bus_shift));
280 }
281
sd_ctrl_write32_rep(struct tmio_mmc_host * host,int addr,const u32 * buf,int count)282 static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
283 const u32 *buf, int count)
284 {
285 iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
286 }
287
288 #endif
289