1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63
64 #define mmMP1_SMN_C2PMSG_66 0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66
67 #define mmMP1_SMN_C2PMSG_82 0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69
70 #define mmMP1_SMN_C2PMSG_90 0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72
73 #define SMU13_VOLTAGE_SCALE 4
74
75 #define LINK_WIDTH_MAX 6
76 #define LINK_SPEED_MAX 3
77
78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL 0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84
85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
86 static const int link_speed[] = {25, 50, 80, 160};
87
smu_v13_0_init_microcode(struct smu_context * smu)88 int smu_v13_0_init_microcode(struct smu_context *smu)
89 {
90 struct amdgpu_device *adev = smu->adev;
91 const char *chip_name;
92 char fw_name[30];
93 char ucode_prefix[30];
94 int err = 0;
95 const struct smc_firmware_header_v1_0 *hdr;
96 const struct common_firmware_header *header;
97 struct amdgpu_firmware_info *ucode = NULL;
98
99 /* doesn't need to load smu firmware in IOV mode */
100 if (amdgpu_sriov_vf(adev))
101 return 0;
102
103 switch (adev->ip_versions[MP1_HWIP][0]) {
104 case IP_VERSION(13, 0, 2):
105 chip_name = "aldebaran_smc";
106 break;
107 default:
108 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
109 chip_name = ucode_prefix;
110 }
111
112 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
113
114 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
115 if (err)
116 goto out;
117 err = amdgpu_ucode_validate(adev->pm.fw);
118 if (err)
119 goto out;
120
121 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
122 amdgpu_ucode_print_smc_hdr(&hdr->header);
123 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
124
125 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
126 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
127 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
128 ucode->fw = adev->pm.fw;
129 header = (const struct common_firmware_header *)ucode->fw->data;
130 adev->firmware.fw_size +=
131 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
132 }
133
134 out:
135 if (err) {
136 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
137 fw_name);
138 release_firmware(adev->pm.fw);
139 adev->pm.fw = NULL;
140 }
141 return err;
142 }
143
smu_v13_0_fini_microcode(struct smu_context * smu)144 void smu_v13_0_fini_microcode(struct smu_context *smu)
145 {
146 struct amdgpu_device *adev = smu->adev;
147
148 release_firmware(adev->pm.fw);
149 adev->pm.fw = NULL;
150 adev->pm.fw_version = 0;
151 }
152
smu_v13_0_load_microcode(struct smu_context * smu)153 int smu_v13_0_load_microcode(struct smu_context *smu)
154 {
155 #if 0
156 struct amdgpu_device *adev = smu->adev;
157 const uint32_t *src;
158 const struct smc_firmware_header_v1_0 *hdr;
159 uint32_t addr_start = MP1_SRAM;
160 uint32_t i;
161 uint32_t smc_fw_size;
162 uint32_t mp1_fw_flags;
163
164 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
165 src = (const uint32_t *)(adev->pm.fw->data +
166 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
167 smc_fw_size = hdr->header.ucode_size_bytes;
168
169 for (i = 1; i < smc_fw_size/4 - 1; i++) {
170 WREG32_PCIE(addr_start, src[i]);
171 addr_start += 4;
172 }
173
174 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
175 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
177 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
178
179 for (i = 0; i < adev->usec_timeout; i++) {
180 mp1_fw_flags = RREG32_PCIE(MP1_Public |
181 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
182 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
183 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
184 break;
185 udelay(1);
186 }
187
188 if (i == adev->usec_timeout)
189 return -ETIME;
190 #endif
191
192 return 0;
193 }
194
smu_v13_0_init_pptable_microcode(struct smu_context * smu)195 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
196 {
197 struct amdgpu_device *adev = smu->adev;
198 struct amdgpu_firmware_info *ucode = NULL;
199 uint32_t size = 0, pptable_id = 0;
200 int ret = 0;
201 void *table;
202
203 /* doesn't need to load smu firmware in IOV mode */
204 if (amdgpu_sriov_vf(adev))
205 return 0;
206
207 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
208 return 0;
209
210 if (!adev->scpm_enabled)
211 return 0;
212
213 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
214 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
215 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
216 return 0;
217
218 /* override pptable_id from driver parameter */
219 if (amdgpu_smu_pptable_id >= 0) {
220 pptable_id = amdgpu_smu_pptable_id;
221 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
222 } else {
223 pptable_id = smu->smu_table.boot_values.pp_table_id;
224 }
225
226 /* "pptable_id == 0" means vbios carries the pptable. */
227 if (!pptable_id)
228 return 0;
229
230 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
231 if (ret)
232 return ret;
233
234 smu->pptable_firmware.data = table;
235 smu->pptable_firmware.size = size;
236
237 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
238 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
239 ucode->fw = &smu->pptable_firmware;
240 adev->firmware.fw_size +=
241 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
242
243 return 0;
244 }
245
smu_v13_0_check_fw_status(struct smu_context * smu)246 int smu_v13_0_check_fw_status(struct smu_context *smu)
247 {
248 struct amdgpu_device *adev = smu->adev;
249 uint32_t mp1_fw_flags;
250
251 switch (adev->ip_versions[MP1_HWIP][0]) {
252 case IP_VERSION(13, 0, 4):
253 case IP_VERSION(13, 0, 11):
254 mp1_fw_flags = RREG32_PCIE(MP1_Public |
255 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
256 break;
257 default:
258 mp1_fw_flags = RREG32_PCIE(MP1_Public |
259 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
260 break;
261 }
262
263 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
264 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
265 return 0;
266
267 return -EIO;
268 }
269
smu_v13_0_check_fw_version(struct smu_context * smu)270 int smu_v13_0_check_fw_version(struct smu_context *smu)
271 {
272 struct amdgpu_device *adev = smu->adev;
273 uint32_t if_version = 0xff, smu_version = 0xff;
274 uint8_t smu_program, smu_major, smu_minor, smu_debug;
275 int ret = 0;
276
277 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
278 if (ret)
279 return ret;
280
281 smu_program = (smu_version >> 24) & 0xff;
282 smu_major = (smu_version >> 16) & 0xff;
283 smu_minor = (smu_version >> 8) & 0xff;
284 smu_debug = (smu_version >> 0) & 0xff;
285 if (smu->is_apu)
286 adev->pm.fw_version = smu_version;
287
288 switch (adev->ip_versions[MP1_HWIP][0]) {
289 case IP_VERSION(13, 0, 2):
290 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
291 break;
292 case IP_VERSION(13, 0, 0):
293 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0;
294 break;
295 case IP_VERSION(13, 0, 10):
296 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10;
297 break;
298 case IP_VERSION(13, 0, 7):
299 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
300 break;
301 case IP_VERSION(13, 0, 1):
302 case IP_VERSION(13, 0, 3):
303 case IP_VERSION(13, 0, 8):
304 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
305 break;
306 case IP_VERSION(13, 0, 4):
307 case IP_VERSION(13, 0, 11):
308 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
309 break;
310 case IP_VERSION(13, 0, 5):
311 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
312 break;
313 default:
314 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
315 adev->ip_versions[MP1_HWIP][0]);
316 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
317 break;
318 }
319
320 /* only for dGPU w/ SMU13*/
321 if (adev->pm.fw)
322 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
323 smu_program, smu_version, smu_major, smu_minor, smu_debug);
324
325 /*
326 * 1. if_version mismatch is not critical as our fw is designed
327 * to be backward compatible.
328 * 2. New fw usually brings some optimizations. But that's visible
329 * only on the paired driver.
330 * Considering above, we just leave user a warning message instead
331 * of halt driver loading.
332 */
333 if (if_version != smu->smc_driver_if_version) {
334 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
335 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
336 smu->smc_driver_if_version, if_version,
337 smu_program, smu_version, smu_major, smu_minor, smu_debug);
338 dev_warn(adev->dev, "SMU driver if version not matched\n");
339 }
340
341 return ret;
342 }
343
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)344 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
345 {
346 struct amdgpu_device *adev = smu->adev;
347 uint32_t ppt_offset_bytes;
348 const struct smc_firmware_header_v2_0 *v2;
349
350 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
351
352 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
353 *size = le32_to_cpu(v2->ppt_size_bytes);
354 *table = (uint8_t *)v2 + ppt_offset_bytes;
355
356 return 0;
357 }
358
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)359 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
360 uint32_t *size, uint32_t pptable_id)
361 {
362 struct amdgpu_device *adev = smu->adev;
363 const struct smc_firmware_header_v2_1 *v2_1;
364 struct smc_soft_pptable_entry *entries;
365 uint32_t pptable_count = 0;
366 int i = 0;
367
368 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
369 entries = (struct smc_soft_pptable_entry *)
370 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
371 pptable_count = le32_to_cpu(v2_1->pptable_count);
372 for (i = 0; i < pptable_count; i++) {
373 if (le32_to_cpu(entries[i].id) == pptable_id) {
374 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
375 *size = le32_to_cpu(entries[i].ppt_size_bytes);
376 break;
377 }
378 }
379
380 if (i == pptable_count)
381 return -EINVAL;
382
383 return 0;
384 }
385
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)386 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
387 {
388 struct amdgpu_device *adev = smu->adev;
389 uint16_t atom_table_size;
390 uint8_t frev, crev;
391 int ret, index;
392
393 dev_info(adev->dev, "use vbios provided pptable\n");
394 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
395 powerplayinfo);
396
397 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
398 (uint8_t **)table);
399 if (ret)
400 return ret;
401
402 if (size)
403 *size = atom_table_size;
404
405 return 0;
406 }
407
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)408 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
409 void **table,
410 uint32_t *size,
411 uint32_t pptable_id)
412 {
413 const struct smc_firmware_header_v1_0 *hdr;
414 struct amdgpu_device *adev = smu->adev;
415 uint16_t version_major, version_minor;
416 int ret;
417
418 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
419 if (!hdr)
420 return -EINVAL;
421
422 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
423
424 version_major = le16_to_cpu(hdr->header.header_version_major);
425 version_minor = le16_to_cpu(hdr->header.header_version_minor);
426 if (version_major != 2) {
427 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
428 version_major, version_minor);
429 return -EINVAL;
430 }
431
432 switch (version_minor) {
433 case 0:
434 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
435 break;
436 case 1:
437 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
438 break;
439 default:
440 ret = -EINVAL;
441 break;
442 }
443
444 return ret;
445 }
446
smu_v13_0_setup_pptable(struct smu_context * smu)447 int smu_v13_0_setup_pptable(struct smu_context *smu)
448 {
449 struct amdgpu_device *adev = smu->adev;
450 uint32_t size = 0, pptable_id = 0;
451 void *table;
452 int ret = 0;
453
454 /* override pptable_id from driver parameter */
455 if (amdgpu_smu_pptable_id >= 0) {
456 pptable_id = amdgpu_smu_pptable_id;
457 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
458 } else {
459 pptable_id = smu->smu_table.boot_values.pp_table_id;
460 }
461
462 /* force using vbios pptable in sriov mode */
463 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
464 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
465 else
466 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
467
468 if (ret)
469 return ret;
470
471 if (!smu->smu_table.power_play_table)
472 smu->smu_table.power_play_table = table;
473 if (!smu->smu_table.power_play_table_size)
474 smu->smu_table.power_play_table_size = size;
475
476 return 0;
477 }
478
smu_v13_0_init_smc_tables(struct smu_context * smu)479 int smu_v13_0_init_smc_tables(struct smu_context *smu)
480 {
481 struct smu_table_context *smu_table = &smu->smu_table;
482 struct smu_table *tables = smu_table->tables;
483 int ret = 0;
484
485 smu_table->driver_pptable =
486 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
487 if (!smu_table->driver_pptable) {
488 ret = -ENOMEM;
489 goto err0_out;
490 }
491
492 smu_table->max_sustainable_clocks =
493 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
494 if (!smu_table->max_sustainable_clocks) {
495 ret = -ENOMEM;
496 goto err1_out;
497 }
498
499 /* Aldebaran does not support OVERDRIVE */
500 if (tables[SMU_TABLE_OVERDRIVE].size) {
501 smu_table->overdrive_table =
502 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
503 if (!smu_table->overdrive_table) {
504 ret = -ENOMEM;
505 goto err2_out;
506 }
507
508 smu_table->boot_overdrive_table =
509 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
510 if (!smu_table->boot_overdrive_table) {
511 ret = -ENOMEM;
512 goto err3_out;
513 }
514 }
515
516 smu_table->combo_pptable =
517 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
518 if (!smu_table->combo_pptable) {
519 ret = -ENOMEM;
520 goto err4_out;
521 }
522
523 return 0;
524
525 err4_out:
526 kfree(smu_table->boot_overdrive_table);
527 err3_out:
528 kfree(smu_table->overdrive_table);
529 err2_out:
530 kfree(smu_table->max_sustainable_clocks);
531 err1_out:
532 kfree(smu_table->driver_pptable);
533 err0_out:
534 return ret;
535 }
536
smu_v13_0_fini_smc_tables(struct smu_context * smu)537 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
538 {
539 struct smu_table_context *smu_table = &smu->smu_table;
540 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
541
542 kfree(smu_table->gpu_metrics_table);
543 kfree(smu_table->combo_pptable);
544 kfree(smu_table->boot_overdrive_table);
545 kfree(smu_table->overdrive_table);
546 kfree(smu_table->max_sustainable_clocks);
547 kfree(smu_table->driver_pptable);
548 smu_table->gpu_metrics_table = NULL;
549 smu_table->combo_pptable = NULL;
550 smu_table->boot_overdrive_table = NULL;
551 smu_table->overdrive_table = NULL;
552 smu_table->max_sustainable_clocks = NULL;
553 smu_table->driver_pptable = NULL;
554 kfree(smu_table->hardcode_pptable);
555 smu_table->hardcode_pptable = NULL;
556
557 kfree(smu_table->ecc_table);
558 kfree(smu_table->metrics_table);
559 kfree(smu_table->watermarks_table);
560 smu_table->ecc_table = NULL;
561 smu_table->metrics_table = NULL;
562 smu_table->watermarks_table = NULL;
563 smu_table->metrics_time = 0;
564
565 kfree(smu_dpm->dpm_context);
566 kfree(smu_dpm->golden_dpm_context);
567 kfree(smu_dpm->dpm_current_power_state);
568 kfree(smu_dpm->dpm_request_power_state);
569 smu_dpm->dpm_context = NULL;
570 smu_dpm->golden_dpm_context = NULL;
571 smu_dpm->dpm_context_size = 0;
572 smu_dpm->dpm_current_power_state = NULL;
573 smu_dpm->dpm_request_power_state = NULL;
574
575 return 0;
576 }
577
smu_v13_0_init_power(struct smu_context * smu)578 int smu_v13_0_init_power(struct smu_context *smu)
579 {
580 struct smu_power_context *smu_power = &smu->smu_power;
581
582 if (smu_power->power_context || smu_power->power_context_size != 0)
583 return -EINVAL;
584
585 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
586 GFP_KERNEL);
587 if (!smu_power->power_context)
588 return -ENOMEM;
589 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
590
591 return 0;
592 }
593
smu_v13_0_fini_power(struct smu_context * smu)594 int smu_v13_0_fini_power(struct smu_context *smu)
595 {
596 struct smu_power_context *smu_power = &smu->smu_power;
597
598 if (!smu_power->power_context || smu_power->power_context_size == 0)
599 return -EINVAL;
600
601 kfree(smu_power->power_context);
602 smu_power->power_context = NULL;
603 smu_power->power_context_size = 0;
604
605 return 0;
606 }
607
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)608 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
609 {
610 int ret, index;
611 uint16_t size;
612 uint8_t frev, crev;
613 struct atom_common_table_header *header;
614 struct atom_firmware_info_v3_4 *v_3_4;
615 struct atom_firmware_info_v3_3 *v_3_3;
616 struct atom_firmware_info_v3_1 *v_3_1;
617 struct atom_smu_info_v3_6 *smu_info_v3_6;
618 struct atom_smu_info_v4_0 *smu_info_v4_0;
619
620 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
621 firmwareinfo);
622
623 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
624 (uint8_t **)&header);
625 if (ret)
626 return ret;
627
628 if (header->format_revision != 3) {
629 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
630 return -EINVAL;
631 }
632
633 switch (header->content_revision) {
634 case 0:
635 case 1:
636 case 2:
637 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
638 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
639 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
640 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
641 smu->smu_table.boot_values.socclk = 0;
642 smu->smu_table.boot_values.dcefclk = 0;
643 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
644 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
645 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
646 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
647 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
648 smu->smu_table.boot_values.pp_table_id = 0;
649 break;
650 case 3:
651 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
652 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
653 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
654 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
655 smu->smu_table.boot_values.socclk = 0;
656 smu->smu_table.boot_values.dcefclk = 0;
657 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
658 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
659 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
660 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
661 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
662 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
663 break;
664 case 4:
665 default:
666 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
667 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
668 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
669 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
670 smu->smu_table.boot_values.socclk = 0;
671 smu->smu_table.boot_values.dcefclk = 0;
672 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
673 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
674 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
675 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
676 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
677 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
678 break;
679 }
680
681 smu->smu_table.boot_values.format_revision = header->format_revision;
682 smu->smu_table.boot_values.content_revision = header->content_revision;
683
684 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
685 smu_info);
686 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
687 (uint8_t **)&header)) {
688
689 if ((frev == 3) && (crev == 6)) {
690 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
691
692 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
693 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
694 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
695 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
696 } else if ((frev == 3) && (crev == 1)) {
697 return 0;
698 } else if ((frev == 4) && (crev == 0)) {
699 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
700
701 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
702 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
703 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
704 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
705 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
706 } else {
707 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
708 (uint32_t)frev, (uint32_t)crev);
709 }
710 }
711
712 return 0;
713 }
714
715
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)716 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
717 {
718 struct smu_table_context *smu_table = &smu->smu_table;
719 struct smu_table *memory_pool = &smu_table->memory_pool;
720 int ret = 0;
721 uint64_t address;
722 uint32_t address_low, address_high;
723
724 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
725 return ret;
726
727 address = memory_pool->mc_address;
728 address_high = (uint32_t)upper_32_bits(address);
729 address_low = (uint32_t)lower_32_bits(address);
730
731 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
732 address_high, NULL);
733 if (ret)
734 return ret;
735 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
736 address_low, NULL);
737 if (ret)
738 return ret;
739 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
740 (uint32_t)memory_pool->size, NULL);
741 if (ret)
742 return ret;
743
744 return ret;
745 }
746
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)747 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
748 {
749 int ret;
750
751 ret = smu_cmn_send_smc_msg_with_param(smu,
752 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
753 if (ret)
754 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
755
756 return ret;
757 }
758
smu_v13_0_set_driver_table_location(struct smu_context * smu)759 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
760 {
761 struct smu_table *driver_table = &smu->smu_table.driver_table;
762 int ret = 0;
763
764 if (driver_table->mc_address) {
765 ret = smu_cmn_send_smc_msg_with_param(smu,
766 SMU_MSG_SetDriverDramAddrHigh,
767 upper_32_bits(driver_table->mc_address),
768 NULL);
769 if (!ret)
770 ret = smu_cmn_send_smc_msg_with_param(smu,
771 SMU_MSG_SetDriverDramAddrLow,
772 lower_32_bits(driver_table->mc_address),
773 NULL);
774 }
775
776 return ret;
777 }
778
smu_v13_0_set_tool_table_location(struct smu_context * smu)779 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
780 {
781 int ret = 0;
782 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
783
784 if (tool_table->mc_address) {
785 ret = smu_cmn_send_smc_msg_with_param(smu,
786 SMU_MSG_SetToolsDramAddrHigh,
787 upper_32_bits(tool_table->mc_address),
788 NULL);
789 if (!ret)
790 ret = smu_cmn_send_smc_msg_with_param(smu,
791 SMU_MSG_SetToolsDramAddrLow,
792 lower_32_bits(tool_table->mc_address),
793 NULL);
794 }
795
796 return ret;
797 }
798
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)799 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
800 {
801 int ret = 0;
802
803 if (!smu->pm_enabled)
804 return ret;
805
806 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
807
808 return ret;
809 }
810
smu_v13_0_set_allowed_mask(struct smu_context * smu)811 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
812 {
813 struct smu_feature *feature = &smu->smu_feature;
814 int ret = 0;
815 uint32_t feature_mask[2];
816
817 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
818 feature->feature_num < 64)
819 return -EINVAL;
820
821 bitmap_to_arr32(feature_mask, feature->allowed, 64);
822
823 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
824 feature_mask[1], NULL);
825 if (ret)
826 return ret;
827
828 return smu_cmn_send_smc_msg_with_param(smu,
829 SMU_MSG_SetAllowedFeaturesMaskLow,
830 feature_mask[0],
831 NULL);
832 }
833
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)834 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
835 {
836 int ret = 0;
837 struct amdgpu_device *adev = smu->adev;
838
839 switch (adev->ip_versions[MP1_HWIP][0]) {
840 case IP_VERSION(13, 0, 0):
841 case IP_VERSION(13, 0, 1):
842 case IP_VERSION(13, 0, 3):
843 case IP_VERSION(13, 0, 4):
844 case IP_VERSION(13, 0, 5):
845 case IP_VERSION(13, 0, 7):
846 case IP_VERSION(13, 0, 8):
847 case IP_VERSION(13, 0, 10):
848 case IP_VERSION(13, 0, 11):
849 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
850 return 0;
851 if (enable)
852 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
853 else
854 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
855 break;
856 default:
857 break;
858 }
859
860 return ret;
861 }
862
smu_v13_0_system_features_control(struct smu_context * smu,bool en)863 int smu_v13_0_system_features_control(struct smu_context *smu,
864 bool en)
865 {
866 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
867 SMU_MSG_DisableAllSmuFeatures), NULL);
868 }
869
smu_v13_0_notify_display_change(struct smu_context * smu)870 int smu_v13_0_notify_display_change(struct smu_context *smu)
871 {
872 int ret = 0;
873
874 if (!smu->pm_enabled)
875 return ret;
876
877 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
878 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
879 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
880
881 return ret;
882 }
883
884 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)885 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
886 enum smu_clk_type clock_select)
887 {
888 int ret = 0;
889 int clk_id;
890
891 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
892 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
893 return 0;
894
895 clk_id = smu_cmn_to_asic_specific_index(smu,
896 CMN2ASIC_MAPPING_CLK,
897 clock_select);
898 if (clk_id < 0)
899 return -EINVAL;
900
901 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
902 clk_id << 16, clock);
903 if (ret) {
904 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
905 return ret;
906 }
907
908 if (*clock != 0)
909 return 0;
910
911 /* if DC limit is zero, return AC limit */
912 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
913 clk_id << 16, clock);
914 if (ret) {
915 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
916 return ret;
917 }
918
919 return 0;
920 }
921
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)922 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
923 {
924 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
925 smu->smu_table.max_sustainable_clocks;
926 int ret = 0;
927
928 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
929 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
930 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
931 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
932 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
933 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
934
935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
936 ret = smu_v13_0_get_max_sustainable_clock(smu,
937 &(max_sustainable_clocks->uclock),
938 SMU_UCLK);
939 if (ret) {
940 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
941 __func__);
942 return ret;
943 }
944 }
945
946 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
947 ret = smu_v13_0_get_max_sustainable_clock(smu,
948 &(max_sustainable_clocks->soc_clock),
949 SMU_SOCCLK);
950 if (ret) {
951 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
952 __func__);
953 return ret;
954 }
955 }
956
957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
958 ret = smu_v13_0_get_max_sustainable_clock(smu,
959 &(max_sustainable_clocks->dcef_clock),
960 SMU_DCEFCLK);
961 if (ret) {
962 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
963 __func__);
964 return ret;
965 }
966
967 ret = smu_v13_0_get_max_sustainable_clock(smu,
968 &(max_sustainable_clocks->display_clock),
969 SMU_DISPCLK);
970 if (ret) {
971 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
972 __func__);
973 return ret;
974 }
975 ret = smu_v13_0_get_max_sustainable_clock(smu,
976 &(max_sustainable_clocks->phy_clock),
977 SMU_PHYCLK);
978 if (ret) {
979 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
980 __func__);
981 return ret;
982 }
983 ret = smu_v13_0_get_max_sustainable_clock(smu,
984 &(max_sustainable_clocks->pixel_clock),
985 SMU_PIXCLK);
986 if (ret) {
987 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
988 __func__);
989 return ret;
990 }
991 }
992
993 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
994 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
995
996 return 0;
997 }
998
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)999 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1000 uint32_t *power_limit)
1001 {
1002 int power_src;
1003 int ret = 0;
1004
1005 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1006 return -EINVAL;
1007
1008 power_src = smu_cmn_to_asic_specific_index(smu,
1009 CMN2ASIC_MAPPING_PWR,
1010 smu->adev->pm.ac_power ?
1011 SMU_POWER_SOURCE_AC :
1012 SMU_POWER_SOURCE_DC);
1013 if (power_src < 0)
1014 return -EINVAL;
1015
1016 ret = smu_cmn_send_smc_msg_with_param(smu,
1017 SMU_MSG_GetPptLimit,
1018 power_src << 16,
1019 power_limit);
1020 if (ret)
1021 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1022
1023 return ret;
1024 }
1025
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1026 int smu_v13_0_set_power_limit(struct smu_context *smu,
1027 enum smu_ppt_limit_type limit_type,
1028 uint32_t limit)
1029 {
1030 int ret = 0;
1031
1032 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1033 return -EINVAL;
1034
1035 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1036 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1037 return -EOPNOTSUPP;
1038 }
1039
1040 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1041 if (ret) {
1042 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1043 return ret;
1044 }
1045
1046 smu->current_power_limit = limit;
1047
1048 return 0;
1049 }
1050
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1051 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1052 {
1053 return smu_cmn_send_smc_msg(smu,
1054 SMU_MSG_AllowIHHostInterrupt,
1055 NULL);
1056 }
1057
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1058 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1059 {
1060 int ret = 0;
1061
1062 if (smu->dc_controlled_by_gpio &&
1063 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1064 ret = smu_v13_0_allow_ih_interrupt(smu);
1065
1066 return ret;
1067 }
1068
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1069 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1070 {
1071 int ret = 0;
1072
1073 if (!smu->irq_source.num_types)
1074 return 0;
1075
1076 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1077 if (ret)
1078 return ret;
1079
1080 return smu_v13_0_process_pending_interrupt(smu);
1081 }
1082
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1083 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1084 {
1085 if (!smu->irq_source.num_types)
1086 return 0;
1087
1088 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1089 }
1090
convert_to_vddc(uint8_t vid)1091 static uint16_t convert_to_vddc(uint8_t vid)
1092 {
1093 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1094 }
1095
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1096 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1097 {
1098 struct amdgpu_device *adev = smu->adev;
1099 uint32_t vdd = 0, val_vid = 0;
1100
1101 if (!value)
1102 return -EINVAL;
1103 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1104 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1105 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1106
1107 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1108
1109 *value = vdd;
1110
1111 return 0;
1112
1113 }
1114
1115 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1116 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1117 struct pp_display_clock_request
1118 *clock_req)
1119 {
1120 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1121 int ret = 0;
1122 enum smu_clk_type clk_select = 0;
1123 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1124
1125 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1126 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1127 switch (clk_type) {
1128 case amd_pp_dcef_clock:
1129 clk_select = SMU_DCEFCLK;
1130 break;
1131 case amd_pp_disp_clock:
1132 clk_select = SMU_DISPCLK;
1133 break;
1134 case amd_pp_pixel_clock:
1135 clk_select = SMU_PIXCLK;
1136 break;
1137 case amd_pp_phy_clock:
1138 clk_select = SMU_PHYCLK;
1139 break;
1140 case amd_pp_mem_clock:
1141 clk_select = SMU_UCLK;
1142 break;
1143 default:
1144 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1145 ret = -EINVAL;
1146 break;
1147 }
1148
1149 if (ret)
1150 goto failed;
1151
1152 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1153 return 0;
1154
1155 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1156
1157 if(clk_select == SMU_UCLK)
1158 smu->hard_min_uclk_req_from_dal = clk_freq;
1159 }
1160
1161 failed:
1162 return ret;
1163 }
1164
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1165 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1166 {
1167 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1168 return AMD_FAN_CTRL_MANUAL;
1169 else
1170 return AMD_FAN_CTRL_AUTO;
1171 }
1172
1173 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1174 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1175 {
1176 int ret = 0;
1177
1178 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1179 return 0;
1180
1181 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1182 if (ret)
1183 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1184 __func__, (auto_fan_control ? "Start" : "Stop"));
1185
1186 return ret;
1187 }
1188
1189 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1190 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1191 {
1192 struct amdgpu_device *adev = smu->adev;
1193
1194 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1195 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1196 CG_FDO_CTRL2, TMIN, 0));
1197 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1198 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1199 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1200
1201 return 0;
1202 }
1203
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1204 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1205 uint32_t speed)
1206 {
1207 struct amdgpu_device *adev = smu->adev;
1208 uint32_t duty100, duty;
1209 uint64_t tmp64;
1210
1211 speed = MIN(speed, 255);
1212
1213 if (smu_v13_0_auto_fan_control(smu, 0))
1214 return -EINVAL;
1215
1216 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1217 CG_FDO_CTRL1, FMAX_DUTY100);
1218 if (!duty100)
1219 return -EINVAL;
1220
1221 tmp64 = (uint64_t)speed * duty100;
1222 do_div(tmp64, 255);
1223 duty = (uint32_t)tmp64;
1224
1225 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1226 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1227 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1228
1229 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1230 }
1231
1232 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1233 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1234 uint32_t mode)
1235 {
1236 int ret = 0;
1237
1238 switch (mode) {
1239 case AMD_FAN_CTRL_NONE:
1240 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1241 break;
1242 case AMD_FAN_CTRL_MANUAL:
1243 ret = smu_v13_0_auto_fan_control(smu, 0);
1244 break;
1245 case AMD_FAN_CTRL_AUTO:
1246 ret = smu_v13_0_auto_fan_control(smu, 1);
1247 break;
1248 default:
1249 break;
1250 }
1251
1252 if (ret) {
1253 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1254 return -EINVAL;
1255 }
1256
1257 return ret;
1258 }
1259
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1260 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1261 uint32_t speed)
1262 {
1263 struct amdgpu_device *adev = smu->adev;
1264 uint32_t crystal_clock_freq = 2500;
1265 uint32_t tach_period;
1266 int ret;
1267
1268 if (!speed)
1269 return -EINVAL;
1270
1271 ret = smu_v13_0_auto_fan_control(smu, 0);
1272 if (ret)
1273 return ret;
1274
1275 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1276 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1277 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1278 CG_TACH_CTRL, TARGET_PERIOD,
1279 tach_period));
1280
1281 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1282 }
1283
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1284 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1285 uint32_t pstate)
1286 {
1287 int ret = 0;
1288 ret = smu_cmn_send_smc_msg_with_param(smu,
1289 SMU_MSG_SetXgmiMode,
1290 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1291 NULL);
1292 return ret;
1293 }
1294
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1295 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1296 struct amdgpu_irq_src *source,
1297 unsigned tyep,
1298 enum amdgpu_interrupt_state state)
1299 {
1300 struct smu_context *smu = adev->powerplay.pp_handle;
1301 uint32_t low, high;
1302 uint32_t val = 0;
1303
1304 switch (state) {
1305 case AMDGPU_IRQ_STATE_DISABLE:
1306 /* For THM irqs */
1307 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1308 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1309 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1310 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1311
1312 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1313
1314 /* For MP1 SW irqs */
1315 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1316 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1317 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1318
1319 break;
1320 case AMDGPU_IRQ_STATE_ENABLE:
1321 /* For THM irqs */
1322 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1323 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1324 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1325 smu->thermal_range.software_shutdown_temp);
1326
1327 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1328 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1329 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1330 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1331 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1332 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1333 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1334 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1335 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1336
1337 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1338 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1339 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1340 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1341
1342 /* For MP1 SW irqs */
1343 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1344 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1345 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1346 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1347
1348 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1349 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1350 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1351
1352 break;
1353 default:
1354 break;
1355 }
1356
1357 return 0;
1358 }
1359
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1360 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1361 {
1362 return smu_cmn_send_smc_msg(smu,
1363 SMU_MSG_ReenableAcDcInterrupt,
1364 NULL);
1365 }
1366
1367 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1368 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1369 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1370
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1371 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1372 struct amdgpu_irq_src *source,
1373 struct amdgpu_iv_entry *entry)
1374 {
1375 struct smu_context *smu = adev->powerplay.pp_handle;
1376 uint32_t client_id = entry->client_id;
1377 uint32_t src_id = entry->src_id;
1378 /*
1379 * ctxid is used to distinguish different
1380 * events for SMCToHost interrupt.
1381 */
1382 uint32_t ctxid = entry->src_data[0];
1383 uint32_t data;
1384 uint32_t high;
1385
1386 if (client_id == SOC15_IH_CLIENTID_THM) {
1387 switch (src_id) {
1388 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1389 schedule_delayed_work(&smu->swctf_delayed_work,
1390 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1391 break;
1392 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1393 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1394 break;
1395 default:
1396 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1397 src_id);
1398 break;
1399 }
1400 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1401 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1402 /*
1403 * HW CTF just occurred. Shutdown to prevent further damage.
1404 */
1405 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1406 orderly_poweroff(true);
1407 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1408 if (src_id == 0xfe) {
1409 /* ACK SMUToHost interrupt */
1410 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1411 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1412 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1413
1414 switch (ctxid) {
1415 case 0x3:
1416 dev_dbg(adev->dev, "Switched to AC mode!\n");
1417 smu_v13_0_ack_ac_dc_interrupt(smu);
1418 adev->pm.ac_power = true;
1419 break;
1420 case 0x4:
1421 dev_dbg(adev->dev, "Switched to DC mode!\n");
1422 smu_v13_0_ack_ac_dc_interrupt(smu);
1423 adev->pm.ac_power = false;
1424 break;
1425 case 0x7:
1426 /*
1427 * Increment the throttle interrupt counter
1428 */
1429 atomic64_inc(&smu->throttle_int_counter);
1430
1431 if (!atomic_read(&adev->throttling_logging_enabled))
1432 return 0;
1433
1434 if (__ratelimit(&adev->throttling_logging_rs))
1435 schedule_work(&smu->throttling_logging_work);
1436
1437 break;
1438 case 0x8:
1439 high = smu->thermal_range.software_shutdown_temp +
1440 smu->thermal_range.software_shutdown_temp_offset;
1441 high = min_t(typeof(high),
1442 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1443 high);
1444 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1445 high,
1446 smu->thermal_range.software_shutdown_temp_offset);
1447
1448 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1449 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1450 DIG_THERM_INTH,
1451 (high & 0xff));
1452 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1453 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1454 break;
1455 case 0x9:
1456 high = min_t(typeof(high),
1457 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1458 smu->thermal_range.software_shutdown_temp);
1459 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1460
1461 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1462 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1463 DIG_THERM_INTH,
1464 (high & 0xff));
1465 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1466 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1467 break;
1468 }
1469 }
1470 }
1471
1472 return 0;
1473 }
1474
1475 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1476 {
1477 .set = smu_v13_0_set_irq_state,
1478 .process = smu_v13_0_irq_process,
1479 };
1480
smu_v13_0_register_irq_handler(struct smu_context * smu)1481 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1482 {
1483 struct amdgpu_device *adev = smu->adev;
1484 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1485 int ret = 0;
1486
1487 if (amdgpu_sriov_vf(adev))
1488 return 0;
1489
1490 irq_src->num_types = 1;
1491 irq_src->funcs = &smu_v13_0_irq_funcs;
1492
1493 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1494 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1495 irq_src);
1496 if (ret)
1497 return ret;
1498
1499 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1500 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1501 irq_src);
1502 if (ret)
1503 return ret;
1504
1505 /* Register CTF(GPIO_19) interrupt */
1506 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1507 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1508 irq_src);
1509 if (ret)
1510 return ret;
1511
1512 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1513 0xfe,
1514 irq_src);
1515 if (ret)
1516 return ret;
1517
1518 return ret;
1519 }
1520
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1521 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1522 struct pp_smu_nv_clock_table *max_clocks)
1523 {
1524 struct smu_table_context *table_context = &smu->smu_table;
1525 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1526
1527 if (!max_clocks || !table_context->max_sustainable_clocks)
1528 return -EINVAL;
1529
1530 sustainable_clocks = table_context->max_sustainable_clocks;
1531
1532 max_clocks->dcfClockInKhz =
1533 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1534 max_clocks->displayClockInKhz =
1535 (unsigned int) sustainable_clocks->display_clock * 1000;
1536 max_clocks->phyClockInKhz =
1537 (unsigned int) sustainable_clocks->phy_clock * 1000;
1538 max_clocks->pixelClockInKhz =
1539 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1540 max_clocks->uClockInKhz =
1541 (unsigned int) sustainable_clocks->uclock * 1000;
1542 max_clocks->socClockInKhz =
1543 (unsigned int) sustainable_clocks->soc_clock * 1000;
1544 max_clocks->dscClockInKhz = 0;
1545 max_clocks->dppClockInKhz = 0;
1546 max_clocks->fabricClockInKhz = 0;
1547
1548 return 0;
1549 }
1550
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1551 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1552 {
1553 int ret = 0;
1554
1555 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1556
1557 return ret;
1558 }
1559
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1560 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1561 uint64_t event_arg)
1562 {
1563 int ret = 0;
1564
1565 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1566 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1567
1568 return ret;
1569 }
1570
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1571 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1572 uint64_t event_arg)
1573 {
1574 int ret = -EINVAL;
1575
1576 switch (event) {
1577 case SMU_EVENT_RESET_COMPLETE:
1578 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1579 break;
1580 default:
1581 break;
1582 }
1583
1584 return ret;
1585 }
1586
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1587 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1588 uint32_t *min, uint32_t *max)
1589 {
1590 int ret = 0, clk_id = 0;
1591 uint32_t param = 0;
1592 uint32_t clock_limit;
1593
1594 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1595 switch (clk_type) {
1596 case SMU_MCLK:
1597 case SMU_UCLK:
1598 clock_limit = smu->smu_table.boot_values.uclk;
1599 break;
1600 case SMU_GFXCLK:
1601 case SMU_SCLK:
1602 clock_limit = smu->smu_table.boot_values.gfxclk;
1603 break;
1604 case SMU_SOCCLK:
1605 clock_limit = smu->smu_table.boot_values.socclk;
1606 break;
1607 default:
1608 clock_limit = 0;
1609 break;
1610 }
1611
1612 /* clock in Mhz unit */
1613 if (min)
1614 *min = clock_limit / 100;
1615 if (max)
1616 *max = clock_limit / 100;
1617
1618 return 0;
1619 }
1620
1621 clk_id = smu_cmn_to_asic_specific_index(smu,
1622 CMN2ASIC_MAPPING_CLK,
1623 clk_type);
1624 if (clk_id < 0) {
1625 ret = -EINVAL;
1626 goto failed;
1627 }
1628 param = (clk_id & 0xffff) << 16;
1629
1630 if (max) {
1631 if (smu->adev->pm.ac_power)
1632 ret = smu_cmn_send_smc_msg_with_param(smu,
1633 SMU_MSG_GetMaxDpmFreq,
1634 param,
1635 max);
1636 else
1637 ret = smu_cmn_send_smc_msg_with_param(smu,
1638 SMU_MSG_GetDcModeMaxDpmFreq,
1639 param,
1640 max);
1641 if (ret)
1642 goto failed;
1643 }
1644
1645 if (min) {
1646 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1647 if (ret)
1648 goto failed;
1649 }
1650
1651 failed:
1652 return ret;
1653 }
1654
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1655 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1656 enum smu_clk_type clk_type,
1657 uint32_t min,
1658 uint32_t max)
1659 {
1660 int ret = 0, clk_id = 0;
1661 uint32_t param;
1662
1663 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1664 return 0;
1665
1666 clk_id = smu_cmn_to_asic_specific_index(smu,
1667 CMN2ASIC_MAPPING_CLK,
1668 clk_type);
1669 if (clk_id < 0)
1670 return clk_id;
1671
1672 if (max > 0) {
1673 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1674 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1675 param, NULL);
1676 if (ret)
1677 goto out;
1678 }
1679
1680 if (min > 0) {
1681 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1682 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1683 param, NULL);
1684 if (ret)
1685 goto out;
1686 }
1687
1688 out:
1689 return ret;
1690 }
1691
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1692 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1693 enum smu_clk_type clk_type,
1694 uint32_t min,
1695 uint32_t max)
1696 {
1697 int ret = 0, clk_id = 0;
1698 uint32_t param;
1699
1700 if (min <= 0 && max <= 0)
1701 return -EINVAL;
1702
1703 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1704 return 0;
1705
1706 clk_id = smu_cmn_to_asic_specific_index(smu,
1707 CMN2ASIC_MAPPING_CLK,
1708 clk_type);
1709 if (clk_id < 0)
1710 return clk_id;
1711
1712 if (max > 0) {
1713 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1714 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1715 param, NULL);
1716 if (ret)
1717 return ret;
1718 }
1719
1720 if (min > 0) {
1721 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1722 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1723 param, NULL);
1724 if (ret)
1725 return ret;
1726 }
1727
1728 return ret;
1729 }
1730
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1731 int smu_v13_0_set_performance_level(struct smu_context *smu,
1732 enum amd_dpm_forced_level level)
1733 {
1734 struct smu_13_0_dpm_context *dpm_context =
1735 smu->smu_dpm.dpm_context;
1736 struct smu_13_0_dpm_table *gfx_table =
1737 &dpm_context->dpm_tables.gfx_table;
1738 struct smu_13_0_dpm_table *mem_table =
1739 &dpm_context->dpm_tables.uclk_table;
1740 struct smu_13_0_dpm_table *soc_table =
1741 &dpm_context->dpm_tables.soc_table;
1742 struct smu_13_0_dpm_table *vclk_table =
1743 &dpm_context->dpm_tables.vclk_table;
1744 struct smu_13_0_dpm_table *dclk_table =
1745 &dpm_context->dpm_tables.dclk_table;
1746 struct smu_13_0_dpm_table *fclk_table =
1747 &dpm_context->dpm_tables.fclk_table;
1748 struct smu_umd_pstate_table *pstate_table =
1749 &smu->pstate_table;
1750 struct amdgpu_device *adev = smu->adev;
1751 uint32_t sclk_min = 0, sclk_max = 0;
1752 uint32_t mclk_min = 0, mclk_max = 0;
1753 uint32_t socclk_min = 0, socclk_max = 0;
1754 uint32_t vclk_min = 0, vclk_max = 0;
1755 uint32_t dclk_min = 0, dclk_max = 0;
1756 uint32_t fclk_min = 0, fclk_max = 0;
1757 int ret = 0, i;
1758
1759 switch (level) {
1760 case AMD_DPM_FORCED_LEVEL_HIGH:
1761 sclk_min = sclk_max = gfx_table->max;
1762 mclk_min = mclk_max = mem_table->max;
1763 socclk_min = socclk_max = soc_table->max;
1764 vclk_min = vclk_max = vclk_table->max;
1765 dclk_min = dclk_max = dclk_table->max;
1766 fclk_min = fclk_max = fclk_table->max;
1767 break;
1768 case AMD_DPM_FORCED_LEVEL_LOW:
1769 sclk_min = sclk_max = gfx_table->min;
1770 mclk_min = mclk_max = mem_table->min;
1771 socclk_min = socclk_max = soc_table->min;
1772 vclk_min = vclk_max = vclk_table->min;
1773 dclk_min = dclk_max = dclk_table->min;
1774 fclk_min = fclk_max = fclk_table->min;
1775 break;
1776 case AMD_DPM_FORCED_LEVEL_AUTO:
1777 sclk_min = gfx_table->min;
1778 sclk_max = gfx_table->max;
1779 mclk_min = mem_table->min;
1780 mclk_max = mem_table->max;
1781 socclk_min = soc_table->min;
1782 socclk_max = soc_table->max;
1783 vclk_min = vclk_table->min;
1784 vclk_max = vclk_table->max;
1785 dclk_min = dclk_table->min;
1786 dclk_max = dclk_table->max;
1787 fclk_min = fclk_table->min;
1788 fclk_max = fclk_table->max;
1789 break;
1790 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1791 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1792 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1793 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1794 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1795 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1796 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1797 break;
1798 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1799 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1800 break;
1801 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1802 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1803 break;
1804 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1805 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1806 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1807 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1808 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1809 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1810 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1811 break;
1812 case AMD_DPM_FORCED_LEVEL_MANUAL:
1813 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1814 return 0;
1815 default:
1816 dev_err(adev->dev, "Invalid performance level %d\n", level);
1817 return -EINVAL;
1818 }
1819
1820 /*
1821 * Unset those settings for SMU 13.0.2. As soft limits settings
1822 * for those clock domains are not supported.
1823 */
1824 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1825 mclk_min = mclk_max = 0;
1826 socclk_min = socclk_max = 0;
1827 vclk_min = vclk_max = 0;
1828 dclk_min = dclk_max = 0;
1829 fclk_min = fclk_max = 0;
1830 }
1831
1832 if (sclk_min && sclk_max) {
1833 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1834 SMU_GFXCLK,
1835 sclk_min,
1836 sclk_max);
1837 if (ret)
1838 return ret;
1839
1840 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1841 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1842 }
1843
1844 if (mclk_min && mclk_max) {
1845 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1846 SMU_MCLK,
1847 mclk_min,
1848 mclk_max);
1849 if (ret)
1850 return ret;
1851
1852 pstate_table->uclk_pstate.curr.min = mclk_min;
1853 pstate_table->uclk_pstate.curr.max = mclk_max;
1854 }
1855
1856 if (socclk_min && socclk_max) {
1857 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1858 SMU_SOCCLK,
1859 socclk_min,
1860 socclk_max);
1861 if (ret)
1862 return ret;
1863
1864 pstate_table->socclk_pstate.curr.min = socclk_min;
1865 pstate_table->socclk_pstate.curr.max = socclk_max;
1866 }
1867
1868 if (vclk_min && vclk_max) {
1869 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1870 if (adev->vcn.harvest_config & (1 << i))
1871 continue;
1872 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1873 i ? SMU_VCLK1 : SMU_VCLK,
1874 vclk_min,
1875 vclk_max);
1876 if (ret)
1877 return ret;
1878 }
1879 pstate_table->vclk_pstate.curr.min = vclk_min;
1880 pstate_table->vclk_pstate.curr.max = vclk_max;
1881 }
1882
1883 if (dclk_min && dclk_max) {
1884 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1885 if (adev->vcn.harvest_config & (1 << i))
1886 continue;
1887 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1888 i ? SMU_DCLK1 : SMU_DCLK,
1889 dclk_min,
1890 dclk_max);
1891 if (ret)
1892 return ret;
1893 }
1894 pstate_table->dclk_pstate.curr.min = dclk_min;
1895 pstate_table->dclk_pstate.curr.max = dclk_max;
1896 }
1897
1898 if (fclk_min && fclk_max) {
1899 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1900 SMU_FCLK,
1901 fclk_min,
1902 fclk_max);
1903 if (ret)
1904 return ret;
1905
1906 pstate_table->fclk_pstate.curr.min = fclk_min;
1907 pstate_table->fclk_pstate.curr.max = fclk_max;
1908 }
1909
1910 return ret;
1911 }
1912
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1913 int smu_v13_0_set_power_source(struct smu_context *smu,
1914 enum smu_power_src_type power_src)
1915 {
1916 int pwr_source;
1917
1918 pwr_source = smu_cmn_to_asic_specific_index(smu,
1919 CMN2ASIC_MAPPING_PWR,
1920 (uint32_t)power_src);
1921 if (pwr_source < 0)
1922 return -EINVAL;
1923
1924 return smu_cmn_send_smc_msg_with_param(smu,
1925 SMU_MSG_NotifyPowerSource,
1926 pwr_source,
1927 NULL);
1928 }
1929
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1930 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1931 enum smu_clk_type clk_type,
1932 uint16_t level,
1933 uint32_t *value)
1934 {
1935 int ret = 0, clk_id = 0;
1936 uint32_t param;
1937
1938 if (!value)
1939 return -EINVAL;
1940
1941 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1942 return 0;
1943
1944 clk_id = smu_cmn_to_asic_specific_index(smu,
1945 CMN2ASIC_MAPPING_CLK,
1946 clk_type);
1947 if (clk_id < 0)
1948 return clk_id;
1949
1950 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1951
1952 ret = smu_cmn_send_smc_msg_with_param(smu,
1953 SMU_MSG_GetDpmFreqByIndex,
1954 param,
1955 value);
1956 if (ret)
1957 return ret;
1958
1959 *value = *value & 0x7fffffff;
1960
1961 return ret;
1962 }
1963
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1964 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1965 enum smu_clk_type clk_type,
1966 uint32_t *value)
1967 {
1968 int ret;
1969
1970 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1971 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1972 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1973 ++(*value);
1974
1975 return ret;
1976 }
1977
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1978 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1979 enum smu_clk_type clk_type,
1980 bool *is_fine_grained_dpm)
1981 {
1982 int ret = 0, clk_id = 0;
1983 uint32_t param;
1984 uint32_t value;
1985
1986 if (!is_fine_grained_dpm)
1987 return -EINVAL;
1988
1989 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1990 return 0;
1991
1992 clk_id = smu_cmn_to_asic_specific_index(smu,
1993 CMN2ASIC_MAPPING_CLK,
1994 clk_type);
1995 if (clk_id < 0)
1996 return clk_id;
1997
1998 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1999
2000 ret = smu_cmn_send_smc_msg_with_param(smu,
2001 SMU_MSG_GetDpmFreqByIndex,
2002 param,
2003 &value);
2004 if (ret)
2005 return ret;
2006
2007 /*
2008 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
2009 * now, we un-support it
2010 */
2011 *is_fine_grained_dpm = value & 0x80000000;
2012
2013 return 0;
2014 }
2015
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)2016 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2017 enum smu_clk_type clk_type,
2018 struct smu_13_0_dpm_table *single_dpm_table)
2019 {
2020 int ret = 0;
2021 uint32_t clk;
2022 int i;
2023
2024 ret = smu_v13_0_get_dpm_level_count(smu,
2025 clk_type,
2026 &single_dpm_table->count);
2027 if (ret) {
2028 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2029 return ret;
2030 }
2031
2032 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2033 ret = smu_v13_0_get_fine_grained_status(smu,
2034 clk_type,
2035 &single_dpm_table->is_fine_grained);
2036 if (ret) {
2037 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2038 return ret;
2039 }
2040 }
2041
2042 for (i = 0; i < single_dpm_table->count; i++) {
2043 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2044 clk_type,
2045 i,
2046 &clk);
2047 if (ret) {
2048 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2049 return ret;
2050 }
2051
2052 single_dpm_table->dpm_levels[i].value = clk;
2053 single_dpm_table->dpm_levels[i].enabled = true;
2054
2055 if (i == 0)
2056 single_dpm_table->min = clk;
2057 else if (i == single_dpm_table->count - 1)
2058 single_dpm_table->max = clk;
2059 }
2060
2061 return 0;
2062 }
2063
smu_v13_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)2064 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2065 enum smu_clk_type clk_type,
2066 uint32_t *min_value,
2067 uint32_t *max_value)
2068 {
2069 uint32_t level_count = 0;
2070 int ret = 0;
2071
2072 if (!min_value && !max_value)
2073 return -EINVAL;
2074
2075 if (min_value) {
2076 /* by default, level 0 clock value as min value */
2077 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2078 clk_type,
2079 0,
2080 min_value);
2081 if (ret)
2082 return ret;
2083 }
2084
2085 if (max_value) {
2086 ret = smu_v13_0_get_dpm_level_count(smu,
2087 clk_type,
2088 &level_count);
2089 if (ret)
2090 return ret;
2091
2092 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2093 clk_type,
2094 level_count - 1,
2095 max_value);
2096 if (ret)
2097 return ret;
2098 }
2099
2100 return ret;
2101 }
2102
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2103 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2104 {
2105 struct amdgpu_device *adev = smu->adev;
2106
2107 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2108 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2109 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2110 }
2111
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2112 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2113 {
2114 uint32_t width_level;
2115
2116 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2117 if (width_level > LINK_WIDTH_MAX)
2118 width_level = 0;
2119
2120 return link_width[width_level];
2121 }
2122
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2123 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2124 {
2125 struct amdgpu_device *adev = smu->adev;
2126
2127 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2128 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2129 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2130 }
2131
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2132 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2133 {
2134 uint32_t speed_level;
2135
2136 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2137 if (speed_level > LINK_SPEED_MAX)
2138 speed_level = 0;
2139
2140 return link_speed[speed_level];
2141 }
2142
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2143 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2144 bool enable)
2145 {
2146 struct amdgpu_device *adev = smu->adev;
2147 int i, ret = 0;
2148
2149 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2150 if (adev->vcn.harvest_config & (1 << i))
2151 continue;
2152
2153 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2154 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2155 i << 16U, NULL);
2156 if (ret)
2157 return ret;
2158 }
2159
2160 return ret;
2161 }
2162
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2163 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2164 bool enable)
2165 {
2166 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2167 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2168 0, NULL);
2169 }
2170
smu_v13_0_run_btc(struct smu_context * smu)2171 int smu_v13_0_run_btc(struct smu_context *smu)
2172 {
2173 int res;
2174
2175 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2176 if (res)
2177 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2178
2179 return res;
2180 }
2181
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2182 int smu_v13_0_gpo_control(struct smu_context *smu,
2183 bool enablement)
2184 {
2185 int res;
2186
2187 res = smu_cmn_send_smc_msg_with_param(smu,
2188 SMU_MSG_AllowGpo,
2189 enablement ? 1 : 0,
2190 NULL);
2191 if (res)
2192 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2193
2194 return res;
2195 }
2196
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2197 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2198 bool enablement)
2199 {
2200 struct amdgpu_device *adev = smu->adev;
2201 int ret = 0;
2202
2203 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2204 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2205 if (ret) {
2206 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2207 return ret;
2208 }
2209 }
2210
2211 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2212 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2213 if (ret) {
2214 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2215 return ret;
2216 }
2217 }
2218
2219 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2220 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2221 if (ret) {
2222 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2223 return ret;
2224 }
2225 }
2226
2227 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2228 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2229 if (ret) {
2230 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2231 return ret;
2232 }
2233 }
2234
2235 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2236 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2237 if (ret) {
2238 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2239 return ret;
2240 }
2241 }
2242
2243 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2244 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2245 if (ret) {
2246 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2247 return ret;
2248 }
2249 }
2250
2251 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2252 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2253 if (ret) {
2254 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2255 return ret;
2256 }
2257 }
2258
2259 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2260 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2261 if (ret) {
2262 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2263 return ret;
2264 }
2265 }
2266
2267 return ret;
2268 }
2269
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2270 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2271 bool enablement)
2272 {
2273 int ret = 0;
2274
2275 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2276 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2277
2278 return ret;
2279 }
2280
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2281 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2282 enum smu_baco_seq baco_seq)
2283 {
2284 return smu_cmn_send_smc_msg_with_param(smu,
2285 SMU_MSG_ArmD3,
2286 baco_seq,
2287 NULL);
2288 }
2289
smu_v13_0_baco_is_support(struct smu_context * smu)2290 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2291 {
2292 struct smu_baco_context *smu_baco = &smu->smu_baco;
2293
2294 if (amdgpu_sriov_vf(smu->adev) ||
2295 !smu_baco->platform_support)
2296 return false;
2297
2298 /* return true if ASIC is in BACO state already */
2299 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2300 return true;
2301
2302 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2303 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2304 return false;
2305
2306 return true;
2307 }
2308
smu_v13_0_baco_get_state(struct smu_context * smu)2309 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2310 {
2311 struct smu_baco_context *smu_baco = &smu->smu_baco;
2312
2313 return smu_baco->state;
2314 }
2315
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2316 int smu_v13_0_baco_set_state(struct smu_context *smu,
2317 enum smu_baco_state state)
2318 {
2319 struct smu_baco_context *smu_baco = &smu->smu_baco;
2320 struct amdgpu_device *adev = smu->adev;
2321 int ret = 0;
2322
2323 if (smu_v13_0_baco_get_state(smu) == state)
2324 return 0;
2325
2326 if (state == SMU_BACO_STATE_ENTER) {
2327 ret = smu_cmn_send_smc_msg_with_param(smu,
2328 SMU_MSG_EnterBaco,
2329 smu_baco->maco_support ?
2330 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2331 NULL);
2332 } else {
2333 ret = smu_cmn_send_smc_msg(smu,
2334 SMU_MSG_ExitBaco,
2335 NULL);
2336 if (ret)
2337 return ret;
2338
2339 /* clear vbios scratch 6 and 7 for coming asic reinit */
2340 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2341 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2342 }
2343
2344 if (!ret)
2345 smu_baco->state = state;
2346
2347 return ret;
2348 }
2349
smu_v13_0_baco_enter(struct smu_context * smu)2350 int smu_v13_0_baco_enter(struct smu_context *smu)
2351 {
2352 int ret = 0;
2353
2354 ret = smu_v13_0_baco_set_state(smu,
2355 SMU_BACO_STATE_ENTER);
2356 if (ret)
2357 return ret;
2358
2359 msleep(10);
2360
2361 return ret;
2362 }
2363
smu_v13_0_baco_exit(struct smu_context * smu)2364 int smu_v13_0_baco_exit(struct smu_context *smu)
2365 {
2366 return smu_v13_0_baco_set_state(smu,
2367 SMU_BACO_STATE_EXIT);
2368 }
2369
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2370 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2371 {
2372 uint16_t index;
2373
2374 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2375 SMU_MSG_EnableGfxImu);
2376 /* Param 1 to tell PMFW to enable GFXOFF feature */
2377 return smu_cmn_send_msg_without_waiting(smu, index, 1);
2378 }
2379
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2380 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2381 enum PP_OD_DPM_TABLE_COMMAND type,
2382 long input[], uint32_t size)
2383 {
2384 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2385 int ret = 0;
2386
2387 /* Only allowed in manual mode */
2388 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2389 return -EINVAL;
2390
2391 switch (type) {
2392 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2393 if (size != 2) {
2394 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2395 return -EINVAL;
2396 }
2397
2398 if (input[0] == 0) {
2399 if (input[1] < smu->gfx_default_hard_min_freq) {
2400 dev_warn(smu->adev->dev,
2401 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2402 input[1], smu->gfx_default_hard_min_freq);
2403 return -EINVAL;
2404 }
2405 smu->gfx_actual_hard_min_freq = input[1];
2406 } else if (input[0] == 1) {
2407 if (input[1] > smu->gfx_default_soft_max_freq) {
2408 dev_warn(smu->adev->dev,
2409 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2410 input[1], smu->gfx_default_soft_max_freq);
2411 return -EINVAL;
2412 }
2413 smu->gfx_actual_soft_max_freq = input[1];
2414 } else {
2415 return -EINVAL;
2416 }
2417 break;
2418 case PP_OD_RESTORE_DEFAULT_TABLE:
2419 if (size != 0) {
2420 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2421 return -EINVAL;
2422 }
2423 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2424 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2425 break;
2426 case PP_OD_COMMIT_DPM_TABLE:
2427 if (size != 0) {
2428 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2429 return -EINVAL;
2430 }
2431 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2432 dev_err(smu->adev->dev,
2433 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2434 smu->gfx_actual_hard_min_freq,
2435 smu->gfx_actual_soft_max_freq);
2436 return -EINVAL;
2437 }
2438
2439 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2440 smu->gfx_actual_hard_min_freq,
2441 NULL);
2442 if (ret) {
2443 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2444 return ret;
2445 }
2446
2447 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2448 smu->gfx_actual_soft_max_freq,
2449 NULL);
2450 if (ret) {
2451 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2452 return ret;
2453 }
2454 break;
2455 default:
2456 return -ENOSYS;
2457 }
2458
2459 return ret;
2460 }
2461
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2462 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2463 {
2464 struct smu_table_context *smu_table = &smu->smu_table;
2465
2466 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2467 smu_table->clocks_table, false);
2468 }
2469
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2470 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2471 {
2472 struct amdgpu_device *adev = smu->adev;
2473
2474 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2475 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2476 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2477 }
2478
smu_v13_0_mode1_reset(struct smu_context * smu)2479 int smu_v13_0_mode1_reset(struct smu_context *smu)
2480 {
2481 int ret = 0;
2482
2483 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2484 if (!ret)
2485 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2486
2487 return ret;
2488 }
2489
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2490 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2491 uint8_t pcie_gen_cap,
2492 uint8_t pcie_width_cap)
2493 {
2494 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2495 struct smu_13_0_pcie_table *pcie_table =
2496 &dpm_context->dpm_tables.pcie_table;
2497 int num_of_levels = pcie_table->num_of_link_levels;
2498 uint32_t smu_pcie_arg;
2499 int ret, i;
2500
2501 if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2502 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2503 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2504
2505 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2506 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2507
2508 /* Force all levels to use the same settings */
2509 for (i = 0; i < num_of_levels; i++) {
2510 pcie_table->pcie_gen[i] = pcie_gen_cap;
2511 pcie_table->pcie_lane[i] = pcie_width_cap;
2512 }
2513 } else {
2514 for (i = 0; i < num_of_levels; i++) {
2515 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2516 pcie_table->pcie_gen[i] = pcie_gen_cap;
2517 if (pcie_table->pcie_lane[i] > pcie_width_cap)
2518 pcie_table->pcie_lane[i] = pcie_width_cap;
2519 }
2520 }
2521
2522 for (i = 0; i < num_of_levels; i++) {
2523 smu_pcie_arg = i << 16;
2524 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2525 smu_pcie_arg |= pcie_table->pcie_lane[i];
2526
2527 ret = smu_cmn_send_smc_msg_with_param(smu,
2528 SMU_MSG_OverridePcieParameters,
2529 smu_pcie_arg,
2530 NULL);
2531 if (ret)
2532 return ret;
2533 }
2534
2535 return 0;
2536 }
2537