1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11 #ifndef __SOF_AMD_ACP_H
12 #define __SOF_AMD_ACP_H
13
14 #include "../sof-priv.h"
15
16 #define ACP_MAX_STREAM 8
17
18 #define ACP_DSP_BAR 0
19
20 #define ACP_HW_SEM_RETRY_COUNT 10000
21 #define ACP_REG_POLL_INTERVAL 500
22 #define ACP_REG_POLL_TIMEOUT_US 2000
23 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000
24
25 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
26 #define ACP_PGFSM_STATUS_MASK 0x03
27 #define ACP_POWERED_ON 0x00
28 #define ACP_ASSERT_RESET 0x01
29 #define ACP_RELEASE_RESET 0x00
30 #define ACP_SOFT_RESET_DONE_MASK 0x00010001
31
32 #define ACP_DSP_INTR_EN_MASK 0x00000001
33 #define ACP3X_SRAM_PTE_OFFSET 0x02050000
34 #define ACP6X_SRAM_PTE_OFFSET 0x03800000
35 #define PAGE_SIZE_4K_ENABLE 0x2
36 #define ACP_PAGE_SIZE 0x1000
37 #define ACP_DMA_CH_RUN 0x02
38 #define ACP_MAX_DESC_CNT 0x02
39 #define DSP_FW_RUN_ENABLE 0x01
40 #define ACP_SHA_RUN 0x01
41 #define ACP_SHA_RESET 0x02
42 #define ACP_DMA_CH_RST 0x01
43 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
44 #define ACP_ATU_CACHE_INVALID 0x01
45 #define ACP_MAX_DESC 128
46 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
47
48 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000
49 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
50 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
51 #define ACP_IRAM_BASE_ADDRESS 0x000000
52 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000
53 #define ACP_DRAM_PAGE_COUNT 128
54
55 #define ACP_DSP_TO_HOST_IRQ 0x04
56
57 #define ACP_RN_PCI_ID 0x01
58 #define ACP_RMB_PCI_ID 0x6F
59
60 #define HOST_BRIDGE_CZN 0x1630
61 #define HOST_BRIDGE_RMB 0x14B5
62 #define ACP_SHA_STAT 0x8000
63 #define ACP_PSP_TIMEOUT_COUNTER 5
64 #define ACP_EXT_INTR_ERROR_STAT 0x20000000
65 #define MP0_C2PMSG_114_REG 0x3810AC8
66 #define MP0_C2PMSG_73_REG 0x3810A24
67 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000
68 #define MBOX_DELAY 1000
69 #define MBOX_READY_MASK 0x80000000
70 #define MBOX_STATUS_MASK 0xFFFF
71
72 #define BOX_SIZE_512 0x200
73 #define BOX_SIZE_1024 0x400
74
75 struct acp_atu_grp_pte {
76 u32 low;
77 u32 high;
78 };
79
80 union dma_tx_cnt {
81 struct {
82 unsigned int count : 19;
83 unsigned int reserved : 12;
84 unsigned ioc : 1;
85 } bitfields, bits;
86 unsigned int u32_all;
87 signed int i32_all;
88 };
89
90 struct dma_descriptor {
91 unsigned int src_addr;
92 unsigned int dest_addr;
93 union dma_tx_cnt tx_cnt;
94 unsigned int reserved;
95 };
96
97 /* Scratch memory structure for communication b/w host and dsp */
98 struct scratch_ipc_conf {
99 /* Debug memory */
100 u8 sof_debug_box[1024];
101 /* Exception memory*/
102 u8 sof_except_box[1024];
103 /* Stream buffer */
104 u8 sof_stream_box[1024];
105 /* Trace buffer */
106 u8 sof_trace_box[1024];
107 /* Host msg flag */
108 u32 sof_host_msg_write;
109 /* Host ack flag*/
110 u32 sof_host_ack_write;
111 /* DSP msg flag */
112 u32 sof_dsp_msg_write;
113 /* Dsp ack flag */
114 u32 sof_dsp_ack_write;
115 };
116
117 struct scratch_reg_conf {
118 struct scratch_ipc_conf info;
119 struct acp_atu_grp_pte grp1_pte[16];
120 struct acp_atu_grp_pte grp2_pte[16];
121 struct acp_atu_grp_pte grp3_pte[16];
122 struct acp_atu_grp_pte grp4_pte[16];
123 struct acp_atu_grp_pte grp5_pte[16];
124 struct acp_atu_grp_pte grp6_pte[16];
125 struct acp_atu_grp_pte grp7_pte[16];
126 struct acp_atu_grp_pte grp8_pte[16];
127 struct dma_descriptor dma_desc[64];
128 unsigned int reg_offset[8];
129 unsigned int buf_size[8];
130 u8 acp_tx_fifo_buf[256];
131 u8 acp_rx_fifo_buf[256];
132 unsigned int reserve[];
133 };
134
135 struct acp_dsp_stream {
136 struct list_head list;
137 struct snd_sof_dev *sdev;
138 struct snd_pcm_substream *substream;
139 struct snd_dma_buffer *dmab;
140 int num_pages;
141 int stream_tag;
142 int active;
143 unsigned int reg_offset;
144 };
145
146 struct sof_amd_acp_desc {
147 unsigned int rev;
148 unsigned int host_bridge_id;
149 unsigned int i2s_mode;
150 u32 pgfsm_base;
151 u32 ext_intr_stat;
152 u32 dsp_intr_base;
153 u32 sram_pte_offset;
154 u32 i2s_pin_config_offset;
155 u32 hw_semaphore_offset;
156 u32 acp_clkmux_sel;
157 u32 fusion_dsp_offset;
158 };
159
160 /* Common device data struct for ACP devices */
161 struct acp_dev_data {
162 struct snd_sof_dev *dev;
163 unsigned int fw_bin_size;
164 unsigned int fw_data_bin_size;
165 u32 fw_bin_page_count;
166 dma_addr_t sha_dma_addr;
167 u8 *bin_buf;
168 dma_addr_t dma_addr;
169 u8 *data_buf;
170 struct dma_descriptor dscr_info[ACP_MAX_DESC];
171 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
172 struct acp_dsp_stream *dtrace_stream;
173 struct pci_dev *smn_dev;
174 };
175
176 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
177 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
178
179 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
180 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
181 unsigned int dest_addr, int dsp_data_size);
182 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
183 unsigned int start_addr, unsigned int dest_addr,
184 unsigned int image_length);
185
186 /* ACP device probe/remove */
187 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
188 int amd_sof_acp_remove(struct snd_sof_dev *sdev);
189
190 /* DSP Loader callbacks */
191 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
192 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
193 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
194
195 /* Block IO callbacks */
196 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
197 u32 offset, void *src, size_t size);
198 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
199 u32 offset, void *dest, size_t size);
200
201 /* IPC callbacks */
202 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
203 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
204 void *p, size_t sz);
205 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
206 struct snd_sof_ipc_msg *msg);
207 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
208 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
209 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
210 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
211
212 /* ACP - DSP stream callbacks */
213 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
214 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
215 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
216 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
217
218 /*
219 * DSP PCM Operations.
220 */
221 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
222 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
223 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
224 struct snd_pcm_hw_params *params,
225 struct snd_sof_platform_stream_params *platform_params);
226
227 extern struct snd_sof_dsp_ops sof_acp_common_ops;
228
229 extern struct snd_sof_dsp_ops sof_renoir_ops;
230 int sof_renoir_ops_init(struct snd_sof_dev *sdev);
231 extern struct snd_sof_dsp_ops sof_rembrandt_ops;
232 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
233
234 int acp_dai_probe(struct snd_soc_dai *dai);
235 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
236 /* Machine configuration */
237 int snd_amd_acp_find_config(struct pci_dev *pci);
238
239 /* Trace */
240 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
241 struct sof_ipc_dma_trace_params_ext *dtrace_params);
242 int acp_sof_trace_release(struct snd_sof_dev *sdev);
243
244 /* PM Callbacks */
245 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
246 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
247
get_chip_info(struct snd_sof_pdata * pdata)248 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
249 {
250 const struct sof_dev_desc *desc = pdata->desc;
251
252 return desc->chip_info;
253 }
254 #endif
255