1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #ifndef __iwl_trans_h__
8 #define __iwl_trans_h__
9
10 #include <linux/ieee80211.h>
11 #include <linux/mm.h> /* for page_address */
12 #include <linux/lockdep.h>
13 #include <linux/kernel.h>
14
15 #include "iwl-debug.h"
16 #include "iwl-config.h"
17 #include "fw/img.h"
18 #include "iwl-op-mode.h"
19 #include <linux/firmware.h>
20 #include "fw/api/cmdhdr.h"
21 #include "fw/api/txq.h"
22 #include "fw/api/dbg-tlv.h"
23 #include "iwl-dbg-tlv.h"
24
25 /**
26 * DOC: Transport layer - what is it ?
27 *
28 * The transport layer is the layer that deals with the HW directly. It provides
29 * an abstraction of the underlying HW to the upper layer. The transport layer
30 * doesn't provide any policy, algorithm or anything of this kind, but only
31 * mechanisms to make the HW do something. It is not completely stateless but
32 * close to it.
33 * We will have an implementation for each different supported bus.
34 */
35
36 /**
37 * DOC: Life cycle of the transport layer
38 *
39 * The transport layer has a very precise life cycle.
40 *
41 * 1) A helper function is called during the module initialization and
42 * registers the bus driver's ops with the transport's alloc function.
43 * 2) Bus's probe calls to the transport layer's allocation functions.
44 * Of course this function is bus specific.
45 * 3) This allocation functions will spawn the upper layer which will
46 * register mac80211.
47 *
48 * 4) At some point (i.e. mac80211's start call), the op_mode will call
49 * the following sequence:
50 * start_hw
51 * start_fw
52 *
53 * 5) Then when finished (or reset):
54 * stop_device
55 *
56 * 6) Eventually, the free function will be called.
57 */
58
59 /* default preset 0 (start from bit 16)*/
60 #define IWL_FW_DBG_DOMAIN_POS 16
61 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS)
62
63 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON
64
65 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
66 #define FH_RSCSR_FRAME_INVALID 0x55550000
67 #define FH_RSCSR_FRAME_ALIGN 0x40
68 #define FH_RSCSR_RPA_EN BIT(25)
69 #define FH_RSCSR_RADA_EN BIT(26)
70 #define FH_RSCSR_RXQ_POS 16
71 #define FH_RSCSR_RXQ_MASK 0x3F0000
72
73 struct iwl_rx_packet {
74 /*
75 * The first 4 bytes of the RX frame header contain both the RX frame
76 * size and some flags.
77 * Bit fields:
78 * 31: flag flush RB request
79 * 30: flag ignore TC (terminal counter) request
80 * 29: flag fast IRQ request
81 * 28-27: Reserved
82 * 26: RADA enabled
83 * 25: Offload enabled
84 * 24: RPF enabled
85 * 23: RSS enabled
86 * 22: Checksum enabled
87 * 21-16: RX queue
88 * 15-14: Reserved
89 * 13-00: RX frame size
90 */
91 __le32 len_n_flags;
92 struct iwl_cmd_header hdr;
93 u8 data[];
94 } __packed;
95
iwl_rx_packet_len(const struct iwl_rx_packet * pkt)96 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
97 {
98 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
99 }
100
iwl_rx_packet_payload_len(const struct iwl_rx_packet * pkt)101 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
102 {
103 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
104 }
105
106 /**
107 * enum CMD_MODE - how to send the host commands ?
108 *
109 * @CMD_ASYNC: Return right away and don't wait for the response
110 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
111 * the response. The caller needs to call iwl_free_resp when done.
112 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
113 * called after this command completes. Valid only with CMD_ASYNC.
114 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to
115 * SUSPEND and RESUME commands. We are in D3 mode when we set
116 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.
117 */
118 enum CMD_MODE {
119 CMD_ASYNC = BIT(0),
120 CMD_WANT_SKB = BIT(1),
121 CMD_SEND_IN_RFKILL = BIT(2),
122 CMD_WANT_ASYNC_CALLBACK = BIT(3),
123 CMD_SEND_IN_D3 = BIT(4),
124 };
125
126 #define DEF_CMD_PAYLOAD_SIZE 320
127
128 /**
129 * struct iwl_device_cmd
130 *
131 * For allocation of the command and tx queues, this establishes the overall
132 * size of the largest command we send to uCode, except for commands that
133 * aren't fully copied and use other TFD space.
134 */
135 struct iwl_device_cmd {
136 union {
137 struct {
138 struct iwl_cmd_header hdr; /* uCode API */
139 u8 payload[DEF_CMD_PAYLOAD_SIZE];
140 };
141 struct {
142 struct iwl_cmd_header_wide hdr_wide;
143 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
144 sizeof(struct iwl_cmd_header_wide) +
145 sizeof(struct iwl_cmd_header)];
146 };
147 };
148 } __packed;
149
150 /**
151 * struct iwl_device_tx_cmd - buffer for TX command
152 * @hdr: the header
153 * @payload: the payload placeholder
154 *
155 * The actual structure is sized dynamically according to need.
156 */
157 struct iwl_device_tx_cmd {
158 struct iwl_cmd_header hdr;
159 u8 payload[];
160 } __packed;
161
162 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
163
164 /*
165 * number of transfer buffers (fragments) per transmit frame descriptor;
166 * this is just the driver's idea, the hardware supports 20
167 */
168 #define IWL_MAX_CMD_TBS_PER_TFD 2
169
170 /* We need 2 entries for the TX command and header, and another one might
171 * be needed for potential data in the SKB's head. The remaining ones can
172 * be used for frags.
173 */
174 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3)
175
176 /**
177 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
178 *
179 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
180 * ring. The transport layer doesn't map the command's buffer to DMA, but
181 * rather copies it to a previously allocated DMA buffer. This flag tells
182 * the transport layer not to copy the command, but to map the existing
183 * buffer (that is passed in) instead. This saves the memcpy and allows
184 * commands that are bigger than the fixed buffer to be submitted.
185 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
186 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
187 * chunk internally and free it again after the command completes. This
188 * can (currently) be used only once per command.
189 * Note that a TFD entry after a DUP one cannot be a normal copied one.
190 */
191 enum iwl_hcmd_dataflag {
192 IWL_HCMD_DFL_NOCOPY = BIT(0),
193 IWL_HCMD_DFL_DUP = BIT(1),
194 };
195
196 enum iwl_error_event_table_status {
197 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
198 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
199 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
200 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),
201 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),
202 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),
203 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),
204 };
205
206 /**
207 * struct iwl_host_cmd - Host command to the uCode
208 *
209 * @data: array of chunks that composes the data of the host command
210 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
211 * @_rx_page_order: (internally used to free response packet)
212 * @_rx_page_addr: (internally used to free response packet)
213 * @flags: can be CMD_*
214 * @len: array of the lengths of the chunks in data
215 * @dataflags: IWL_HCMD_DFL_*
216 * @id: command id of the host command, for wide commands encoding the
217 * version and group as well
218 */
219 struct iwl_host_cmd {
220 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
221 struct iwl_rx_packet *resp_pkt;
222 unsigned long _rx_page_addr;
223 u32 _rx_page_order;
224
225 u32 flags;
226 u32 id;
227 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
228 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
229 };
230
iwl_free_resp(struct iwl_host_cmd * cmd)231 static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
232 {
233 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
234 }
235
236 struct iwl_rx_cmd_buffer {
237 struct page *_page;
238 int _offset;
239 bool _page_stolen;
240 u32 _rx_page_order;
241 unsigned int truesize;
242 };
243
rxb_addr(struct iwl_rx_cmd_buffer * r)244 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
245 {
246 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
247 }
248
rxb_offset(struct iwl_rx_cmd_buffer * r)249 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
250 {
251 return r->_offset;
252 }
253
rxb_steal_page(struct iwl_rx_cmd_buffer * r)254 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
255 {
256 r->_page_stolen = true;
257 get_page(r->_page);
258 return r->_page;
259 }
260
iwl_free_rxb(struct iwl_rx_cmd_buffer * r)261 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
262 {
263 __free_pages(r->_page, r->_rx_page_order);
264 }
265
266 #define MAX_NO_RECLAIM_CMDS 6
267
268 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
269
270 /*
271 * Maximum number of HW queues the transport layer
272 * currently supports
273 */
274 #define IWL_MAX_HW_QUEUES 32
275 #define IWL_MAX_TVQM_QUEUES 512
276
277 #define IWL_MAX_TID_COUNT 8
278 #define IWL_MGMT_TID 15
279 #define IWL_FRAME_LIMIT 64
280 #define IWL_MAX_RX_HW_QUEUES 16
281 #define IWL_9000_MAX_RX_HW_QUEUES 6
282
283 /**
284 * enum iwl_wowlan_status - WoWLAN image/device status
285 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
286 * @IWL_D3_STATUS_RESET: device was reset while suspended
287 */
288 enum iwl_d3_status {
289 IWL_D3_STATUS_ALIVE,
290 IWL_D3_STATUS_RESET,
291 };
292
293 /**
294 * enum iwl_trans_status: transport status flags
295 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
296 * @STATUS_DEVICE_ENABLED: APM is enabled
297 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
298 * @STATUS_INT_ENABLED: interrupts are enabled
299 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
300 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
301 * @STATUS_FW_ERROR: the fw is in error state
302 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
303 * are sent
304 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
305 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
306 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,
307 * e.g. for testing
308 */
309 enum iwl_trans_status {
310 STATUS_SYNC_HCMD_ACTIVE,
311 STATUS_DEVICE_ENABLED,
312 STATUS_TPOWER_PMI,
313 STATUS_INT_ENABLED,
314 STATUS_RFKILL_HW,
315 STATUS_RFKILL_OPMODE,
316 STATUS_FW_ERROR,
317 STATUS_TRANS_GOING_IDLE,
318 STATUS_TRANS_IDLE,
319 STATUS_TRANS_DEAD,
320 STATUS_SUPPRESS_CMD_ERROR_ONCE,
321 };
322
323 static inline int
iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)324 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
325 {
326 switch (rb_size) {
327 case IWL_AMSDU_2K:
328 return get_order(2 * 1024);
329 case IWL_AMSDU_4K:
330 return get_order(4 * 1024);
331 case IWL_AMSDU_8K:
332 return get_order(8 * 1024);
333 case IWL_AMSDU_12K:
334 return get_order(16 * 1024);
335 default:
336 WARN_ON(1);
337 return -1;
338 }
339 }
340
341 static inline int
iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)342 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)
343 {
344 switch (rb_size) {
345 case IWL_AMSDU_2K:
346 return 2 * 1024;
347 case IWL_AMSDU_4K:
348 return 4 * 1024;
349 case IWL_AMSDU_8K:
350 return 8 * 1024;
351 case IWL_AMSDU_12K:
352 return 16 * 1024;
353 default:
354 WARN_ON(1);
355 return 0;
356 }
357 }
358
359 struct iwl_hcmd_names {
360 u8 cmd_id;
361 const char *const cmd_name;
362 };
363
364 #define HCMD_NAME(x) \
365 { .cmd_id = x, .cmd_name = #x }
366
367 struct iwl_hcmd_arr {
368 const struct iwl_hcmd_names *arr;
369 int size;
370 };
371
372 #define HCMD_ARR(x) \
373 { .arr = x, .size = ARRAY_SIZE(x) }
374
375 /**
376 * struct iwl_dump_sanitize_ops - dump sanitization operations
377 * @frob_txf: Scrub the TX FIFO data
378 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header
379 * but that might be short or long (&struct iwl_cmd_header or
380 * &struct iwl_cmd_header_wide)
381 * @frob_mem: Scrub memory data
382 */
383 struct iwl_dump_sanitize_ops {
384 void (*frob_txf)(void *ctx, void *buf, size_t buflen);
385 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);
386 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);
387 };
388
389 /**
390 * struct iwl_trans_config - transport configuration
391 *
392 * @op_mode: pointer to the upper layer.
393 * @cmd_queue: the index of the command queue.
394 * Must be set before start_fw.
395 * @cmd_fifo: the fifo for host commands
396 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
397 * @no_reclaim_cmds: Some devices erroneously don't set the
398 * SEQ_RX_FRAME bit on some notifications, this is the
399 * list of such notifications to filter. Max length is
400 * %MAX_NO_RECLAIM_CMDS.
401 * @n_no_reclaim_cmds: # of commands in list
402 * @rx_buf_size: RX buffer size needed for A-MSDUs
403 * if unset 4k will be the RX buffer size
404 * @bc_table_dword: set to true if the BC table expects the byte count to be
405 * in DWORD (as opposed to bytes)
406 * @scd_set_active: should the transport configure the SCD for HCMD queue
407 * @command_groups: array of command groups, each member is an array of the
408 * commands in the group; for debugging only
409 * @command_groups_size: number of command groups, to avoid illegal access
410 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
411 * space for at least two pointers
412 * @fw_reset_handshake: firmware supports reset flow handshake
413 * @queue_alloc_cmd_ver: queue allocation command version, set to 0
414 * for using the older SCD_QUEUE_CFG, set to the version of
415 * SCD_QUEUE_CONFIG_CMD otherwise.
416 */
417 struct iwl_trans_config {
418 struct iwl_op_mode *op_mode;
419
420 u8 cmd_queue;
421 u8 cmd_fifo;
422 unsigned int cmd_q_wdg_timeout;
423 const u8 *no_reclaim_cmds;
424 unsigned int n_no_reclaim_cmds;
425
426 enum iwl_amsdu_size rx_buf_size;
427 bool bc_table_dword;
428 bool scd_set_active;
429 const struct iwl_hcmd_arr *command_groups;
430 int command_groups_size;
431
432 u8 cb_data_offs;
433 bool fw_reset_handshake;
434 u8 queue_alloc_cmd_ver;
435 };
436
437 struct iwl_trans_dump_data {
438 u32 len;
439 u8 data[];
440 };
441
442 struct iwl_trans;
443
444 struct iwl_trans_txq_scd_cfg {
445 u8 fifo;
446 u8 sta_id;
447 u8 tid;
448 bool aggregate;
449 int frame_limit;
450 };
451
452 /**
453 * struct iwl_trans_rxq_dma_data - RX queue DMA data
454 * @fr_bd_cb: DMA address of free BD cyclic buffer
455 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
456 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
457 * @ur_bd_cb: DMA address of used BD cyclic buffer
458 */
459 struct iwl_trans_rxq_dma_data {
460 u64 fr_bd_cb;
461 u32 fr_bd_wid;
462 u64 urbd_stts_wrptr;
463 u64 ur_bd_cb;
464 };
465
466 /**
467 * struct iwl_trans_ops - transport specific operations
468 *
469 * All the handlers MUST be implemented
470 *
471 * @start_hw: starts the HW. From that point on, the HW can send interrupts.
472 * May sleep.
473 * @op_mode_leave: Turn off the HW RF kill indication if on
474 * May sleep
475 * @start_fw: allocates and inits all the resources for the transport
476 * layer. Also kick a fw image.
477 * May sleep
478 * @fw_alive: called when the fw sends alive notification. If the fw provides
479 * the SCD base address in SRAM, then provide it here, or 0 otherwise.
480 * May sleep
481 * @stop_device: stops the whole device (embedded CPU put to reset) and stops
482 * the HW. From that point on, the HW will be stopped but will still issue
483 * an interrupt if the HW RF kill switch is triggered.
484 * This callback must do the right thing and not crash even if %start_hw()
485 * was called but not &start_fw(). May sleep.
486 * @d3_suspend: put the device into the correct mode for WoWLAN during
487 * suspend. This is optional, if not implemented WoWLAN will not be
488 * supported. This callback may sleep.
489 * @d3_resume: resume the device after WoWLAN, enabling the opmode to
490 * talk to the WoWLAN image to get its status. This is optional, if not
491 * implemented WoWLAN will not be supported. This callback may sleep.
492 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
493 * If RFkill is asserted in the middle of a SYNC host command, it must
494 * return -ERFKILL straight away.
495 * May sleep only if CMD_ASYNC is not set
496 * @tx: send an skb. The transport relies on the op_mode to zero the
497 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
498 * the CSUM will be taken care of (TCP CSUM and IP header in case of
499 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
500 * header if it is IPv4.
501 * Must be atomic
502 * @reclaim: free packet until ssn. Returns a list of freed packets.
503 * Must be atomic
504 * @txq_enable: setup a queue. To setup an AC queue, use the
505 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
506 * this one. The op_mode must not configure the HCMD queue. The scheduler
507 * configuration may be %NULL, in which case the hardware will not be
508 * configured. If true is returned, the operation mode needs to increment
509 * the sequence number of the packets routed to this queue because of a
510 * hardware scheduler bug. May sleep.
511 * @txq_disable: de-configure a Tx queue to send AMPDUs
512 * Must be atomic
513 * @txq_set_shared_mode: change Tx queue shared/unshared marking
514 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
515 * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
516 * @freeze_txq_timer: prevents the timer of the queue from firing until the
517 * queue is set to awake. Must be atomic.
518 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
519 * that the transport needs to refcount the calls since this function
520 * will be called several times with block = true, and then the queues
521 * need to be unblocked only after the same number of calls with
522 * block = false.
523 * @write8: write a u8 to a register at offset ofs from the BAR
524 * @write32: write a u32 to a register at offset ofs from the BAR
525 * @read32: read a u32 register at offset ofs from the BAR
526 * @read_prph: read a DWORD from a periphery register
527 * @write_prph: write a DWORD to a periphery register
528 * @read_mem: read device's SRAM in DWORD
529 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
530 * will be zeroed.
531 * @read_config32: read a u32 value from the device's config space at
532 * the given offset.
533 * @configure: configure parameters required by the transport layer from
534 * the op_mode. May be called several times before start_fw, can't be
535 * called after that.
536 * @set_pmi: set the power pmi state
537 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
538 * Sleeping is not allowed between grab_nic_access and
539 * release_nic_access.
540 * @release_nic_access: let the NIC go to sleep. The "flags" parameter
541 * must be the same one that was sent before to the grab_nic_access.
542 * @set_bits_mask - set SRAM register according to value and mask.
543 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
544 * TX'ed commands and similar. The buffer will be vfree'd by the caller.
545 * Note that the transport must fill in the proper file headers.
546 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
547 * of the trans debugfs
548 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the
549 * context info.
550 * @interrupts: disable/enable interrupts to transport
551 */
552 struct iwl_trans_ops {
553
554 int (*start_hw)(struct iwl_trans *iwl_trans);
555 void (*op_mode_leave)(struct iwl_trans *iwl_trans);
556 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
557 bool run_in_rfkill);
558 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
559 void (*stop_device)(struct iwl_trans *trans);
560
561 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
562 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
563 bool test, bool reset);
564
565 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
566
567 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
568 struct iwl_device_tx_cmd *dev_cmd, int queue);
569 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
570 struct sk_buff_head *skbs, bool is_flush);
571
572 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
573
574 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
575 const struct iwl_trans_txq_scd_cfg *cfg,
576 unsigned int queue_wdg_timeout);
577 void (*txq_disable)(struct iwl_trans *trans, int queue,
578 bool configure_scd);
579 /* 22000 functions */
580 int (*txq_alloc)(struct iwl_trans *trans, u32 flags,
581 u32 sta_mask, u8 tid,
582 int size, unsigned int queue_wdg_timeout);
583 void (*txq_free)(struct iwl_trans *trans, int queue);
584 int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
585 struct iwl_trans_rxq_dma_data *data);
586
587 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
588 bool shared);
589
590 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
591 int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
592 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
593 bool freeze);
594 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
595
596 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
597 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
598 u32 (*read32)(struct iwl_trans *trans, u32 ofs);
599 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
600 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
601 int (*read_mem)(struct iwl_trans *trans, u32 addr,
602 void *buf, int dwords);
603 int (*write_mem)(struct iwl_trans *trans, u32 addr,
604 const void *buf, int dwords);
605 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val);
606 void (*configure)(struct iwl_trans *trans,
607 const struct iwl_trans_config *trans_cfg);
608 void (*set_pmi)(struct iwl_trans *trans, bool state);
609 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership);
610 bool (*grab_nic_access)(struct iwl_trans *trans);
611 void (*release_nic_access)(struct iwl_trans *trans);
612 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
613 u32 value);
614
615 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
616 u32 dump_mask,
617 const struct iwl_dump_sanitize_ops *sanitize_ops,
618 void *sanitize_ctx);
619 void (*debugfs_cleanup)(struct iwl_trans *trans);
620 void (*sync_nmi)(struct iwl_trans *trans);
621 int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len);
622 int (*set_reduce_power)(struct iwl_trans *trans,
623 const void *data, u32 len);
624 void (*interrupts)(struct iwl_trans *trans, bool enable);
625 int (*imr_dma_data)(struct iwl_trans *trans,
626 u32 dst_addr, u64 src_addr,
627 u32 byte_cnt);
628
629 };
630
631 /**
632 * enum iwl_trans_state - state of the transport layer
633 *
634 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed
635 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet
636 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response
637 */
638 enum iwl_trans_state {
639 IWL_TRANS_NO_FW,
640 IWL_TRANS_FW_STARTED,
641 IWL_TRANS_FW_ALIVE,
642 };
643
644 /**
645 * DOC: Platform power management
646 *
647 * In system-wide power management the entire platform goes into a low
648 * power state (e.g. idle or suspend to RAM) at the same time and the
649 * device is configured as a wakeup source for the entire platform.
650 * This is usually triggered by userspace activity (e.g. the user
651 * presses the suspend button or a power management daemon decides to
652 * put the platform in low power mode). The device's behavior in this
653 * mode is dictated by the wake-on-WLAN configuration.
654 *
655 * The terms used for the device's behavior are as follows:
656 *
657 * - D0: the device is fully powered and the host is awake;
658 * - D3: the device is in low power mode and only reacts to
659 * specific events (e.g. magic-packet received or scan
660 * results found);
661 *
662 * These terms reflect the power modes in the firmware and are not to
663 * be confused with the physical device power state.
664 */
665
666 /**
667 * enum iwl_plat_pm_mode - platform power management mode
668 *
669 * This enumeration describes the device's platform power management
670 * behavior when in system-wide suspend (i.e WoWLAN).
671 *
672 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
673 * device. In system-wide suspend mode, it means that the all
674 * connections will be closed automatically by mac80211 before
675 * the platform is suspended.
676 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
677 */
678 enum iwl_plat_pm_mode {
679 IWL_PLAT_PM_MODE_DISABLED,
680 IWL_PLAT_PM_MODE_D3,
681 };
682
683 /**
684 * enum iwl_ini_cfg_state
685 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
686 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
687 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
688 * are corrupted. The rest of the debug TLVs will still be used
689 */
690 enum iwl_ini_cfg_state {
691 IWL_INI_CFG_STATE_NOT_LOADED,
692 IWL_INI_CFG_STATE_LOADED,
693 IWL_INI_CFG_STATE_CORRUPTED,
694 };
695
696 /* Max time to wait for nmi interrupt */
697 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
698
699 /**
700 * struct iwl_dram_data
701 * @physical: page phy pointer
702 * @block: pointer to the allocated block/page
703 * @size: size of the block/page
704 */
705 struct iwl_dram_data {
706 dma_addr_t physical;
707 void *block;
708 int size;
709 };
710
711 /**
712 * struct iwl_fw_mon - fw monitor per allocation id
713 * @num_frags: number of fragments
714 * @frags: an array of DRAM buffer fragments
715 */
716 struct iwl_fw_mon {
717 u32 num_frags;
718 struct iwl_dram_data *frags;
719 };
720
721 /**
722 * struct iwl_self_init_dram - dram data used by self init process
723 * @fw: lmac and umac dram data
724 * @fw_cnt: total number of items in array
725 * @paging: paging dram data
726 * @paging_cnt: total number of items in array
727 */
728 struct iwl_self_init_dram {
729 struct iwl_dram_data *fw;
730 int fw_cnt;
731 struct iwl_dram_data *paging;
732 int paging_cnt;
733 };
734
735 /**
736 * struct iwl_imr_data - imr dram data used during debug process
737 * @imr_enable: imr enable status received from fw
738 * @imr_size: imr dram size received from fw
739 * @sram_addr: sram address from debug tlv
740 * @sram_size: sram size from debug tlv
741 * @imr2sram_remainbyte`: size remained after each dma transfer
742 * @imr_curr_addr: current dst address used during dma transfer
743 * @imr_base_addr: imr address received from fw
744 */
745 struct iwl_imr_data {
746 u32 imr_enable;
747 u32 imr_size;
748 u32 sram_addr;
749 u32 sram_size;
750 u32 imr2sram_remainbyte;
751 u64 imr_curr_addr;
752 __le64 imr_base_addr;
753 };
754
755 /**
756 * struct iwl_trans_debug - transport debug related data
757 *
758 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
759 * @rec_on: true iff there is a fw debug recording currently active
760 * @dest_tlv: points to the destination TLV for debug
761 * @conf_tlv: array of pointers to configuration TLVs for debug
762 * @trigger_tlv: array of pointers to triggers TLVs for debug
763 * @lmac_error_event_table: addrs of lmacs error tables
764 * @umac_error_event_table: addr of umac error table
765 * @tcm_error_event_table: address(es) of TCM error table(s)
766 * @rcm_error_event_table: address(es) of RCM error table(s)
767 * @error_event_table_tlv_status: bitmap that indicates what error table
768 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
769 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
770 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
771 * @fw_mon_cfg: debug buffer allocation configuration
772 * @fw_mon_ini: DRAM buffer fragments per allocation id
773 * @fw_mon: DRAM buffer for firmware monitor
774 * @hw_error: equals true if hw error interrupt was received from the FW
775 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
776 * @active_regions: active regions
777 * @debug_info_tlv_list: list of debug info TLVs
778 * @time_point: array of debug time points
779 * @periodic_trig_list: periodic triggers list
780 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON
781 * @ucode_preset: preset based on ucode
782 */
783 struct iwl_trans_debug {
784 u8 n_dest_reg;
785 bool rec_on;
786
787 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
788 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
789 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
790
791 u32 lmac_error_event_table[2];
792 u32 umac_error_event_table;
793 u32 tcm_error_event_table[2];
794 u32 rcm_error_event_table[2];
795 unsigned int error_event_table_tlv_status;
796
797 enum iwl_ini_cfg_state internal_ini_cfg;
798 enum iwl_ini_cfg_state external_ini_cfg;
799
800 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
801 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
802
803 struct iwl_dram_data fw_mon;
804
805 bool hw_error;
806 enum iwl_fw_ini_buffer_location ini_dest;
807
808 u64 unsupported_region_msk;
809 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
810 struct list_head debug_info_tlv_list;
811 struct iwl_dbg_tlv_time_point_data
812 time_point[IWL_FW_INI_TIME_POINT_NUM];
813 struct list_head periodic_trig_list;
814
815 u32 domains_bitmap;
816 u32 ucode_preset;
817 bool restart_required;
818 u32 last_tp_resetfw;
819 struct iwl_imr_data imr_data;
820 };
821
822 struct iwl_dma_ptr {
823 dma_addr_t dma;
824 void *addr;
825 size_t size;
826 };
827
828 struct iwl_cmd_meta {
829 /* only for SYNC commands, iff the reply skb is wanted */
830 struct iwl_host_cmd *source;
831 u32 flags;
832 u32 tbs;
833 };
834
835 /*
836 * The FH will write back to the first TB only, so we need to copy some data
837 * into the buffer regardless of whether it should be mapped or not.
838 * This indicates how big the first TB must be to include the scratch buffer
839 * and the assigned PN.
840 * Since PN location is 8 bytes at offset 12, it's 20 now.
841 * If we make it bigger then allocations will be bigger and copy slower, so
842 * that's probably not useful.
843 */
844 #define IWL_FIRST_TB_SIZE 20
845 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
846
847 struct iwl_pcie_txq_entry {
848 void *cmd;
849 struct sk_buff *skb;
850 /* buffer to free after command completes */
851 const void *free_buf;
852 struct iwl_cmd_meta meta;
853 };
854
855 struct iwl_pcie_first_tb_buf {
856 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
857 };
858
859 /**
860 * struct iwl_txq - Tx Queue for DMA
861 * @q: generic Rx/Tx queue descriptor
862 * @tfds: transmit frame descriptors (DMA memory)
863 * @first_tb_bufs: start of command headers, including scratch buffers, for
864 * the writeback -- this is DMA memory and an array holding one buffer
865 * for each command on the queue
866 * @first_tb_dma: DMA address for the first_tb_bufs start
867 * @entries: transmit entries (driver state)
868 * @lock: queue lock
869 * @stuck_timer: timer that fires if queue gets stuck
870 * @trans: pointer back to transport (for timer)
871 * @need_update: indicates need to update read/write index
872 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
873 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
874 * @frozen: tx stuck queue timer is frozen
875 * @frozen_expiry_remainder: remember how long until the timer fires
876 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
877 * @write_ptr: 1-st empty entry (index) host_w
878 * @read_ptr: last used entry (index) host_r
879 * @dma_addr: physical addr for BD's
880 * @n_window: safe queue window
881 * @id: queue id
882 * @low_mark: low watermark, resume queue if free space more than this
883 * @high_mark: high watermark, stop queue if free space less than this
884 *
885 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
886 * descriptors) and required locking structures.
887 *
888 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
889 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
890 * there might be HW changes in the future). For the normal TX
891 * queues, n_window, which is the size of the software queue data
892 * is also 256; however, for the command queue, n_window is only
893 * 32 since we don't need so many commands pending. Since the HW
894 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
895 * This means that we end up with the following:
896 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
897 * SW entries: | 0 | ... | 31 |
898 * where N is a number between 0 and 7. This means that the SW
899 * data is a window overlayed over the HW queue.
900 */
901 struct iwl_txq {
902 void *tfds;
903 struct iwl_pcie_first_tb_buf *first_tb_bufs;
904 dma_addr_t first_tb_dma;
905 struct iwl_pcie_txq_entry *entries;
906 /* lock for syncing changes on the queue */
907 spinlock_t lock;
908 unsigned long frozen_expiry_remainder;
909 struct timer_list stuck_timer;
910 struct iwl_trans *trans;
911 bool need_update;
912 bool frozen;
913 bool ampdu;
914 int block;
915 unsigned long wd_timeout;
916 struct sk_buff_head overflow_q;
917 struct iwl_dma_ptr bc_tbl;
918
919 int write_ptr;
920 int read_ptr;
921 dma_addr_t dma_addr;
922 int n_window;
923 u32 id;
924 int low_mark;
925 int high_mark;
926
927 bool overflow_tx;
928 };
929
930 /**
931 * struct iwl_trans_txqs - transport tx queues data
932 *
933 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
934 * @page_offs: offset from skb->cb to mac header page pointer
935 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer
936 * @queue_used - bit mask of used queues
937 * @queue_stopped - bit mask of stopped queues
938 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
939 * @queue_alloc_cmd_ver: queue allocation command version
940 */
941 struct iwl_trans_txqs {
942 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
943 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
944 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
945 struct dma_pool *bc_pool;
946 size_t bc_tbl_size;
947 bool bc_table_dword;
948 u8 page_offs;
949 u8 dev_cmd_offs;
950 struct iwl_tso_hdr_page __percpu *tso_hdr_page;
951
952 struct {
953 u8 fifo;
954 u8 q_id;
955 unsigned int wdg_timeout;
956 } cmd;
957
958 struct {
959 u8 max_tbs;
960 u16 size;
961 u8 addr_size;
962 } tfd;
963
964 struct iwl_dma_ptr scd_bc_tbls;
965
966 u8 queue_alloc_cmd_ver;
967 };
968
969 /**
970 * struct iwl_trans - transport common data
971 *
972 * @csme_own - true if we couldn't get ownership on the device
973 * @ops - pointer to iwl_trans_ops
974 * @op_mode - pointer to the op_mode
975 * @trans_cfg: the trans-specific configuration part
976 * @cfg - pointer to the configuration
977 * @drv - pointer to iwl_drv
978 * @status: a bit-mask of transport status flags
979 * @dev - pointer to struct device * that represents the device
980 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
981 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
982 * @hw_rf_id a u32 with the device RF ID
983 * @hw_id: a u32 with the ID of the device / sub-device.
984 * Set during transport allocation.
985 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
986 * @hw_rev_step: The mac step of the HW
987 * @pm_support: set to true in start_hw if link pm is supported
988 * @ltr_enabled: set to true if the LTR is enabled
989 * @wide_cmd_header: true when ucode supports wide command header format
990 * @wait_command_queue: wait queue for sync commands
991 * @num_rx_queues: number of RX queues allocated by the transport;
992 * the transport must set this before calling iwl_drv_start()
993 * @iml_len: the length of the image loader
994 * @iml: a pointer to the image loader itself
995 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
996 * The user should use iwl_trans_{alloc,free}_tx_cmd.
997 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
998 * starting the firmware, used for tracing
999 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
1000 * start of the 802.11 header in the @rx_mpdu_cmd
1001 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
1002 * @system_pm_mode: the system-wide power management mode in use.
1003 * This mode is set dynamically, depending on the WoWLAN values
1004 * configured from the userspace at runtime.
1005 * @iwl_trans_txqs: transport tx queues data.
1006 */
1007 struct iwl_trans {
1008 bool csme_own;
1009 const struct iwl_trans_ops *ops;
1010 struct iwl_op_mode *op_mode;
1011 const struct iwl_cfg_trans_params *trans_cfg;
1012 const struct iwl_cfg *cfg;
1013 struct iwl_drv *drv;
1014 enum iwl_trans_state state;
1015 unsigned long status;
1016
1017 struct device *dev;
1018 u32 max_skb_frags;
1019 u32 hw_rev;
1020 u32 hw_rev_step;
1021 u32 hw_rf_id;
1022 u32 hw_id;
1023 char hw_id_str[52];
1024 u32 sku_id[3];
1025
1026 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
1027
1028 bool pm_support;
1029 bool ltr_enabled;
1030 u8 pnvm_loaded:1;
1031 u8 reduce_power_loaded:1;
1032
1033 const struct iwl_hcmd_arr *command_groups;
1034 int command_groups_size;
1035 bool wide_cmd_header;
1036
1037 wait_queue_head_t wait_command_queue;
1038 u8 num_rx_queues;
1039
1040 size_t iml_len;
1041 u8 *iml;
1042
1043 /* The following fields are internal only */
1044 struct kmem_cache *dev_cmd_pool;
1045 char dev_cmd_pool_name[50];
1046
1047 struct dentry *dbgfs_dir;
1048
1049 #ifdef CONFIG_LOCKDEP
1050 struct lockdep_map sync_cmd_lockdep_map;
1051 #endif
1052
1053 struct iwl_trans_debug dbg;
1054 struct iwl_self_init_dram init_dram;
1055
1056 enum iwl_plat_pm_mode system_pm_mode;
1057
1058 const char *name;
1059 struct iwl_trans_txqs txqs;
1060
1061 /* pointer to trans specific struct */
1062 /*Ensure that this pointer will always be aligned to sizeof pointer */
1063 char trans_specific[] __aligned(sizeof(void *));
1064 };
1065
1066 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
1067 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
1068
iwl_trans_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1069 static inline void iwl_trans_configure(struct iwl_trans *trans,
1070 const struct iwl_trans_config *trans_cfg)
1071 {
1072 trans->op_mode = trans_cfg->op_mode;
1073
1074 trans->ops->configure(trans, trans_cfg);
1075 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
1076 }
1077
iwl_trans_start_hw(struct iwl_trans * trans)1078 static inline int iwl_trans_start_hw(struct iwl_trans *trans)
1079 {
1080 might_sleep();
1081
1082 return trans->ops->start_hw(trans);
1083 }
1084
iwl_trans_op_mode_leave(struct iwl_trans * trans)1085 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
1086 {
1087 might_sleep();
1088
1089 if (trans->ops->op_mode_leave)
1090 trans->ops->op_mode_leave(trans);
1091
1092 trans->op_mode = NULL;
1093
1094 trans->state = IWL_TRANS_NO_FW;
1095 }
1096
iwl_trans_fw_alive(struct iwl_trans * trans,u32 scd_addr)1097 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1098 {
1099 might_sleep();
1100
1101 trans->state = IWL_TRANS_FW_ALIVE;
1102
1103 trans->ops->fw_alive(trans, scd_addr);
1104 }
1105
iwl_trans_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)1106 static inline int iwl_trans_start_fw(struct iwl_trans *trans,
1107 const struct fw_img *fw,
1108 bool run_in_rfkill)
1109 {
1110 int ret;
1111
1112 might_sleep();
1113
1114 WARN_ON_ONCE(!trans->rx_mpdu_cmd);
1115
1116 clear_bit(STATUS_FW_ERROR, &trans->status);
1117 ret = trans->ops->start_fw(trans, fw, run_in_rfkill);
1118 if (ret == 0)
1119 trans->state = IWL_TRANS_FW_STARTED;
1120
1121 return ret;
1122 }
1123
iwl_trans_stop_device(struct iwl_trans * trans)1124 static inline void iwl_trans_stop_device(struct iwl_trans *trans)
1125 {
1126 might_sleep();
1127
1128 trans->ops->stop_device(trans);
1129
1130 trans->state = IWL_TRANS_NO_FW;
1131 }
1132
iwl_trans_d3_suspend(struct iwl_trans * trans,bool test,bool reset)1133 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
1134 bool reset)
1135 {
1136 might_sleep();
1137 if (!trans->ops->d3_suspend)
1138 return 0;
1139
1140 return trans->ops->d3_suspend(trans, test, reset);
1141 }
1142
iwl_trans_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test,bool reset)1143 static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
1144 enum iwl_d3_status *status,
1145 bool test, bool reset)
1146 {
1147 might_sleep();
1148 if (!trans->ops->d3_resume)
1149 return 0;
1150
1151 return trans->ops->d3_resume(trans, status, test, reset);
1152 }
1153
1154 static inline struct iwl_trans_dump_data *
iwl_trans_dump_data(struct iwl_trans * trans,u32 dump_mask,const struct iwl_dump_sanitize_ops * sanitize_ops,void * sanitize_ctx)1155 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,
1156 const struct iwl_dump_sanitize_ops *sanitize_ops,
1157 void *sanitize_ctx)
1158 {
1159 if (!trans->ops->dump_data)
1160 return NULL;
1161 return trans->ops->dump_data(trans, dump_mask,
1162 sanitize_ops, sanitize_ctx);
1163 }
1164
1165 static inline struct iwl_device_tx_cmd *
iwl_trans_alloc_tx_cmd(struct iwl_trans * trans)1166 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
1167 {
1168 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);
1169 }
1170
1171 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
1172
iwl_trans_free_tx_cmd(struct iwl_trans * trans,struct iwl_device_tx_cmd * dev_cmd)1173 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
1174 struct iwl_device_tx_cmd *dev_cmd)
1175 {
1176 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
1177 }
1178
iwl_trans_tx(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_device_tx_cmd * dev_cmd,int queue)1179 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
1180 struct iwl_device_tx_cmd *dev_cmd, int queue)
1181 {
1182 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
1183 return -EIO;
1184
1185 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1186 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1187 return -EIO;
1188 }
1189
1190 return trans->ops->tx(trans, skb, dev_cmd, queue);
1191 }
1192
iwl_trans_reclaim(struct iwl_trans * trans,int queue,int ssn,struct sk_buff_head * skbs,bool is_flush)1193 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
1194 int ssn, struct sk_buff_head *skbs,
1195 bool is_flush)
1196 {
1197 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1198 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1199 return;
1200 }
1201
1202 trans->ops->reclaim(trans, queue, ssn, skbs, is_flush);
1203 }
1204
iwl_trans_set_q_ptrs(struct iwl_trans * trans,int queue,int ptr)1205 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
1206 int ptr)
1207 {
1208 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1209 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1210 return;
1211 }
1212
1213 trans->ops->set_q_ptrs(trans, queue, ptr);
1214 }
1215
iwl_trans_txq_disable(struct iwl_trans * trans,int queue,bool configure_scd)1216 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1217 bool configure_scd)
1218 {
1219 trans->ops->txq_disable(trans, queue, configure_scd);
1220 }
1221
1222 static inline bool
iwl_trans_txq_enable_cfg(struct iwl_trans * trans,int queue,u16 ssn,const struct iwl_trans_txq_scd_cfg * cfg,unsigned int queue_wdg_timeout)1223 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1224 const struct iwl_trans_txq_scd_cfg *cfg,
1225 unsigned int queue_wdg_timeout)
1226 {
1227 might_sleep();
1228
1229 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1230 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1231 return false;
1232 }
1233
1234 return trans->ops->txq_enable(trans, queue, ssn,
1235 cfg, queue_wdg_timeout);
1236 }
1237
1238 static inline int
iwl_trans_get_rxq_dma_data(struct iwl_trans * trans,int queue,struct iwl_trans_rxq_dma_data * data)1239 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1240 struct iwl_trans_rxq_dma_data *data)
1241 {
1242 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1243 return -ENOTSUPP;
1244
1245 return trans->ops->rxq_dma_data(trans, queue, data);
1246 }
1247
1248 static inline void
iwl_trans_txq_free(struct iwl_trans * trans,int queue)1249 iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1250 {
1251 if (WARN_ON_ONCE(!trans->ops->txq_free))
1252 return;
1253
1254 trans->ops->txq_free(trans, queue);
1255 }
1256
1257 static inline int
iwl_trans_txq_alloc(struct iwl_trans * trans,u32 flags,u32 sta_mask,u8 tid,int size,unsigned int wdg_timeout)1258 iwl_trans_txq_alloc(struct iwl_trans *trans,
1259 u32 flags, u32 sta_mask, u8 tid,
1260 int size, unsigned int wdg_timeout)
1261 {
1262 might_sleep();
1263
1264 if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1265 return -ENOTSUPP;
1266
1267 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1268 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1269 return -EIO;
1270 }
1271
1272 return trans->ops->txq_alloc(trans, flags, sta_mask, tid,
1273 size, wdg_timeout);
1274 }
1275
iwl_trans_txq_set_shared_mode(struct iwl_trans * trans,int queue,bool shared_mode)1276 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1277 int queue, bool shared_mode)
1278 {
1279 if (trans->ops->txq_set_shared_mode)
1280 trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1281 }
1282
iwl_trans_txq_enable(struct iwl_trans * trans,int queue,int fifo,int sta_id,int tid,int frame_limit,u16 ssn,unsigned int queue_wdg_timeout)1283 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1284 int fifo, int sta_id, int tid,
1285 int frame_limit, u16 ssn,
1286 unsigned int queue_wdg_timeout)
1287 {
1288 struct iwl_trans_txq_scd_cfg cfg = {
1289 .fifo = fifo,
1290 .sta_id = sta_id,
1291 .tid = tid,
1292 .frame_limit = frame_limit,
1293 .aggregate = sta_id >= 0,
1294 };
1295
1296 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1297 }
1298
1299 static inline
iwl_trans_ac_txq_enable(struct iwl_trans * trans,int queue,int fifo,unsigned int queue_wdg_timeout)1300 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1301 unsigned int queue_wdg_timeout)
1302 {
1303 struct iwl_trans_txq_scd_cfg cfg = {
1304 .fifo = fifo,
1305 .sta_id = -1,
1306 .tid = IWL_MAX_TID_COUNT,
1307 .frame_limit = IWL_FRAME_LIMIT,
1308 .aggregate = false,
1309 };
1310
1311 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1312 }
1313
iwl_trans_freeze_txq_timer(struct iwl_trans * trans,unsigned long txqs,bool freeze)1314 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1315 unsigned long txqs,
1316 bool freeze)
1317 {
1318 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1319 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1320 return;
1321 }
1322
1323 if (trans->ops->freeze_txq_timer)
1324 trans->ops->freeze_txq_timer(trans, txqs, freeze);
1325 }
1326
iwl_trans_block_txq_ptrs(struct iwl_trans * trans,bool block)1327 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1328 bool block)
1329 {
1330 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1331 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1332 return;
1333 }
1334
1335 if (trans->ops->block_txq_ptrs)
1336 trans->ops->block_txq_ptrs(trans, block);
1337 }
1338
iwl_trans_wait_tx_queues_empty(struct iwl_trans * trans,u32 txqs)1339 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1340 u32 txqs)
1341 {
1342 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1343 return -ENOTSUPP;
1344
1345 /* No need to wait if the firmware is not alive */
1346 if (trans->state != IWL_TRANS_FW_ALIVE) {
1347 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1348 return -EIO;
1349 }
1350
1351 return trans->ops->wait_tx_queues_empty(trans, txqs);
1352 }
1353
iwl_trans_wait_txq_empty(struct iwl_trans * trans,int queue)1354 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1355 {
1356 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1357 return -ENOTSUPP;
1358
1359 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1360 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1361 return -EIO;
1362 }
1363
1364 return trans->ops->wait_txq_empty(trans, queue);
1365 }
1366
iwl_trans_write8(struct iwl_trans * trans,u32 ofs,u8 val)1367 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1368 {
1369 trans->ops->write8(trans, ofs, val);
1370 }
1371
iwl_trans_write32(struct iwl_trans * trans,u32 ofs,u32 val)1372 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1373 {
1374 trans->ops->write32(trans, ofs, val);
1375 }
1376
iwl_trans_read32(struct iwl_trans * trans,u32 ofs)1377 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1378 {
1379 return trans->ops->read32(trans, ofs);
1380 }
1381
iwl_trans_read_prph(struct iwl_trans * trans,u32 ofs)1382 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1383 {
1384 return trans->ops->read_prph(trans, ofs);
1385 }
1386
iwl_trans_write_prph(struct iwl_trans * trans,u32 ofs,u32 val)1387 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1388 u32 val)
1389 {
1390 return trans->ops->write_prph(trans, ofs, val);
1391 }
1392
iwl_trans_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)1393 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1394 void *buf, int dwords)
1395 {
1396 return trans->ops->read_mem(trans, addr, buf, dwords);
1397 }
1398
1399 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1400 do { \
1401 if (__builtin_constant_p(bufsize)) \
1402 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1403 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1404 } while (0)
1405
iwl_trans_write_imr_mem(struct iwl_trans * trans,u32 dst_addr,u64 src_addr,u32 byte_cnt)1406 static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans,
1407 u32 dst_addr, u64 src_addr,
1408 u32 byte_cnt)
1409 {
1410 if (trans->ops->imr_dma_data)
1411 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt);
1412 return 0;
1413 }
1414
iwl_trans_read_mem32(struct iwl_trans * trans,u32 addr)1415 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1416 {
1417 u32 value;
1418
1419 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1420 return 0xa5a5a5a5;
1421
1422 return value;
1423 }
1424
iwl_trans_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)1425 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1426 const void *buf, int dwords)
1427 {
1428 return trans->ops->write_mem(trans, addr, buf, dwords);
1429 }
1430
iwl_trans_write_mem32(struct iwl_trans * trans,u32 addr,u32 val)1431 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1432 u32 val)
1433 {
1434 return iwl_trans_write_mem(trans, addr, &val, 1);
1435 }
1436
iwl_trans_set_pmi(struct iwl_trans * trans,bool state)1437 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1438 {
1439 if (trans->ops->set_pmi)
1440 trans->ops->set_pmi(trans, state);
1441 }
1442
iwl_trans_sw_reset(struct iwl_trans * trans,bool retake_ownership)1443 static inline int iwl_trans_sw_reset(struct iwl_trans *trans,
1444 bool retake_ownership)
1445 {
1446 if (trans->ops->sw_reset)
1447 return trans->ops->sw_reset(trans, retake_ownership);
1448 return 0;
1449 }
1450
1451 static inline void
iwl_trans_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1452 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1453 {
1454 trans->ops->set_bits_mask(trans, reg, mask, value);
1455 }
1456
1457 #define iwl_trans_grab_nic_access(trans) \
1458 __cond_lock(nic_access, \
1459 likely((trans)->ops->grab_nic_access(trans)))
1460
__releases(nic_access)1461 static inline void __releases(nic_access)
1462 iwl_trans_release_nic_access(struct iwl_trans *trans)
1463 {
1464 trans->ops->release_nic_access(trans);
1465 __release(nic_access);
1466 }
1467
iwl_trans_fw_error(struct iwl_trans * trans,bool sync)1468 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync)
1469 {
1470 if (WARN_ON_ONCE(!trans->op_mode))
1471 return;
1472
1473 /* prevent double restarts due to the same erroneous FW */
1474 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {
1475 iwl_op_mode_nic_error(trans->op_mode, sync);
1476 trans->state = IWL_TRANS_NO_FW;
1477 }
1478 }
1479
iwl_trans_fw_running(struct iwl_trans * trans)1480 static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1481 {
1482 return trans->state == IWL_TRANS_FW_ALIVE;
1483 }
1484
iwl_trans_sync_nmi(struct iwl_trans * trans)1485 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1486 {
1487 if (trans->ops->sync_nmi)
1488 trans->ops->sync_nmi(trans);
1489 }
1490
1491 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
1492 u32 sw_err_bit);
1493
iwl_trans_set_pnvm(struct iwl_trans * trans,const void * data,u32 len)1494 static inline int iwl_trans_set_pnvm(struct iwl_trans *trans,
1495 const void *data, u32 len)
1496 {
1497 if (trans->ops->set_pnvm) {
1498 int ret = trans->ops->set_pnvm(trans, data, len);
1499
1500 if (ret)
1501 return ret;
1502 }
1503
1504 trans->pnvm_loaded = true;
1505
1506 return 0;
1507 }
1508
iwl_trans_set_reduce_power(struct iwl_trans * trans,const void * data,u32 len)1509 static inline int iwl_trans_set_reduce_power(struct iwl_trans *trans,
1510 const void *data, u32 len)
1511 {
1512 if (trans->ops->set_reduce_power) {
1513 int ret = trans->ops->set_reduce_power(trans, data, len);
1514
1515 if (ret)
1516 return ret;
1517 }
1518
1519 trans->reduce_power_loaded = true;
1520 return 0;
1521 }
1522
iwl_trans_dbg_ini_valid(struct iwl_trans * trans)1523 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1524 {
1525 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1526 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1527 }
1528
iwl_trans_interrupts(struct iwl_trans * trans,bool enable)1529 static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable)
1530 {
1531 if (trans->ops->interrupts)
1532 trans->ops->interrupts(trans, enable);
1533 }
1534
1535 /*****************************************************
1536 * transport helper functions
1537 *****************************************************/
1538 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1539 struct device *dev,
1540 const struct iwl_trans_ops *ops,
1541 const struct iwl_cfg_trans_params *cfg_trans);
1542 int iwl_trans_init(struct iwl_trans *trans);
1543 void iwl_trans_free(struct iwl_trans *trans);
1544
1545 /*****************************************************
1546 * driver (transport) register/unregister functions
1547 ******************************************************/
1548 int __must_check iwl_pci_register_driver(void);
1549 void iwl_pci_unregister_driver(void);
1550
1551 #endif /* __iwl_trans_h__ */
1552