1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.207" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /* Display Core Interfaces */ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 // Sizes defined as multiples of 64KB 77 enum det_size { 78 DET_SIZE_DEFAULT = 0, 79 DET_SIZE_192KB = 3, 80 DET_SIZE_256KB = 4, 81 DET_SIZE_320KB = 5, 82 DET_SIZE_384KB = 6 83 }; 84 85 86 struct dc_plane_cap { 87 enum dc_plane_type type; 88 uint32_t blends_with_above : 1; 89 uint32_t blends_with_below : 1; 90 uint32_t per_pixel_alpha : 1; 91 struct { 92 uint32_t argb8888 : 1; 93 uint32_t nv12 : 1; 94 uint32_t fp16 : 1; 95 uint32_t p010 : 1; 96 uint32_t ayuv : 1; 97 } pixel_format_support; 98 // max upscaling factor x1000 99 // upscaling factors are always >= 1 100 // for example, 1080p -> 8K is 4.0, or 4000 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_upscale_factor; 106 // max downscale factor x1000 107 // downscale factors are always <= 1 108 // for example, 8K -> 1080p is 0.25, or 250 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_downscale_factor; 114 // minimal width/height 115 uint32_t min_width; 116 uint32_t min_height; 117 }; 118 119 /** 120 * DOC: color-management-caps 121 * 122 * **Color management caps (DPP and MPC)** 123 * 124 * Modules/color calculates various color operations which are translated to 125 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 126 * DCN1, every new generation comes with fairly major differences in color 127 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 128 * decide mapping to HW block based on logical capabilities. 129 */ 130 131 /** 132 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 133 * @srgb: RGB color space transfer func 134 * @bt2020: BT.2020 transfer func 135 * @gamma2_2: standard gamma 136 * @pq: perceptual quantizer transfer function 137 * @hlg: hybrid log–gamma transfer function 138 */ 139 struct rom_curve_caps { 140 uint16_t srgb : 1; 141 uint16_t bt2020 : 1; 142 uint16_t gamma2_2 : 1; 143 uint16_t pq : 1; 144 uint16_t hlg : 1; 145 }; 146 147 /** 148 * struct dpp_color_caps - color pipeline capabilities for display pipe and 149 * plane blocks 150 * 151 * @dcn_arch: all DCE generations treated the same 152 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 153 * just plain 256-entry lookup 154 * @icsc: input color space conversion 155 * @dgam_ram: programmable degamma LUT 156 * @post_csc: post color space conversion, before gamut remap 157 * @gamma_corr: degamma correction 158 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 159 * with MPC by setting mpc:shared_3d_lut flag 160 * @ogam_ram: programmable out/blend gamma LUT 161 * @ocsc: output color space conversion 162 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 163 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 164 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 165 * 166 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 167 */ 168 struct dpp_color_caps { 169 uint16_t dcn_arch : 1; 170 uint16_t input_lut_shared : 1; 171 uint16_t icsc : 1; 172 uint16_t dgam_ram : 1; 173 uint16_t post_csc : 1; 174 uint16_t gamma_corr : 1; 175 uint16_t hw_3d_lut : 1; 176 uint16_t ogam_ram : 1; 177 uint16_t ocsc : 1; 178 uint16_t dgam_rom_for_yuv : 1; 179 struct rom_curve_caps dgam_rom_caps; 180 struct rom_curve_caps ogam_rom_caps; 181 }; 182 183 /** 184 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 185 * plane combined blocks 186 * 187 * @gamut_remap: color transformation matrix 188 * @ogam_ram: programmable out gamma LUT 189 * @ocsc: output color space conversion matrix 190 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 191 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 192 * instance 193 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 194 */ 195 struct mpc_color_caps { 196 uint16_t gamut_remap : 1; 197 uint16_t ogam_ram : 1; 198 uint16_t ocsc : 1; 199 uint16_t num_3dluts : 3; 200 uint16_t shared_3d_lut:1; 201 struct rom_curve_caps ogam_rom_caps; 202 }; 203 204 /** 205 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 206 * @dpp: color pipes caps for DPP 207 * @mpc: color pipes caps for MPC 208 */ 209 struct dc_color_caps { 210 struct dpp_color_caps dpp; 211 struct mpc_color_caps mpc; 212 }; 213 214 struct dc_dmub_caps { 215 bool psr; 216 bool mclk_sw; 217 }; 218 219 struct dc_caps { 220 uint32_t max_streams; 221 uint32_t max_links; 222 uint32_t max_audios; 223 uint32_t max_slave_planes; 224 uint32_t max_slave_yuv_planes; 225 uint32_t max_slave_rgb_planes; 226 uint32_t max_planes; 227 uint32_t max_downscale_ratio; 228 uint32_t i2c_speed_in_khz; 229 uint32_t i2c_speed_in_khz_hdcp; 230 uint32_t dmdata_alloc_size; 231 unsigned int max_cursor_size; 232 unsigned int max_video_width; 233 /* 234 * max video plane width that can be safely assumed to be always 235 * supported by single DPP pipe. 236 */ 237 unsigned int max_optimizable_video_width; 238 unsigned int min_horizontal_blanking_period; 239 int linear_pitch_alignment; 240 bool dcc_const_color; 241 bool dynamic_audio; 242 bool is_apu; 243 bool dual_link_dvi; 244 bool post_blend_color_processing; 245 bool force_dp_tps4_for_cp2520; 246 bool disable_dp_clk_share; 247 bool psp_setup_panel_mode; 248 bool extended_aux_timeout_support; 249 bool dmcub_support; 250 bool zstate_support; 251 uint32_t num_of_internal_disp; 252 enum dp_protocol_version max_dp_protocol_version; 253 unsigned int mall_size_per_mem_channel; 254 unsigned int mall_size_total; 255 unsigned int cursor_cache_size; 256 struct dc_plane_cap planes[MAX_PLANES]; 257 struct dc_color_caps color; 258 struct dc_dmub_caps dmub_caps; 259 bool dp_hpo; 260 bool dp_hdmi21_pcon_support; 261 bool edp_dsc_support; 262 bool vbios_lttpr_aware; 263 bool vbios_lttpr_enable; 264 uint32_t max_otg_num; 265 uint32_t max_cab_allocation_bytes; 266 uint32_t cache_line_size; 267 uint32_t cache_num_ways; 268 uint16_t subvp_fw_processing_delay_us; 269 uint16_t subvp_prefetch_end_to_mall_start_us; 270 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 271 uint16_t subvp_pstate_allow_width_us; 272 uint16_t subvp_vertical_int_margin_us; 273 bool seamless_odm; 274 }; 275 276 struct dc_bug_wa { 277 bool no_connect_phy_config; 278 bool dedcn20_305_wa; 279 bool skip_clock_update; 280 bool lt_early_cr_pattern; 281 }; 282 283 struct dc_dcc_surface_param { 284 struct dc_size surface_size; 285 enum surface_pixel_format format; 286 enum swizzle_mode_values swizzle_mode; 287 enum dc_scan_direction scan; 288 }; 289 290 struct dc_dcc_setting { 291 unsigned int max_compressed_blk_size; 292 unsigned int max_uncompressed_blk_size; 293 bool independent_64b_blks; 294 //These bitfields to be used starting with DCN 295 struct { 296 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 297 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 298 uint32_t dcc_256_128_128 : 1; //available starting with DCN 299 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 300 } dcc_controls; 301 }; 302 303 struct dc_surface_dcc_cap { 304 union { 305 struct { 306 struct dc_dcc_setting rgb; 307 } grph; 308 309 struct { 310 struct dc_dcc_setting luma; 311 struct dc_dcc_setting chroma; 312 } video; 313 }; 314 315 bool capable; 316 bool const_color_support; 317 }; 318 319 struct dc_static_screen_params { 320 struct { 321 bool force_trigger; 322 bool cursor_update; 323 bool surface_update; 324 bool overlay_update; 325 } triggers; 326 unsigned int num_frames; 327 }; 328 329 330 /* Surface update type is used by dc_update_surfaces_and_stream 331 * The update type is determined at the very beginning of the function based 332 * on parameters passed in and decides how much programming (or updating) is 333 * going to be done during the call. 334 * 335 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 336 * logical calculations or hardware register programming. This update MUST be 337 * ISR safe on windows. Currently fast update will only be used to flip surface 338 * address. 339 * 340 * UPDATE_TYPE_MED is used for slower updates which require significant hw 341 * re-programming however do not affect bandwidth consumption or clock 342 * requirements. At present, this is the level at which front end updates 343 * that do not require us to run bw_calcs happen. These are in/out transfer func 344 * updates, viewport offset changes, recout size changes and pixel depth changes. 345 * This update can be done at ISR, but we want to minimize how often this happens. 346 * 347 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 348 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 349 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 350 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 351 * a full update. This cannot be done at ISR level and should be a rare event. 352 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 353 * underscan we don't expect to see this call at all. 354 */ 355 356 enum surface_update_type { 357 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 358 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 359 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 360 }; 361 362 /* Forward declaration*/ 363 struct dc; 364 struct dc_plane_state; 365 struct dc_state; 366 367 368 struct dc_cap_funcs { 369 bool (*get_dcc_compression_cap)(const struct dc *dc, 370 const struct dc_dcc_surface_param *input, 371 struct dc_surface_dcc_cap *output); 372 }; 373 374 struct link_training_settings; 375 376 union allow_lttpr_non_transparent_mode { 377 struct { 378 bool DP1_4A : 1; 379 bool DP2_0 : 1; 380 } bits; 381 unsigned char raw; 382 }; 383 384 /* Structure to hold configuration flags set by dm at dc creation. */ 385 struct dc_config { 386 bool gpu_vm_support; 387 bool disable_disp_pll_sharing; 388 bool fbc_support; 389 bool disable_fractional_pwm; 390 bool allow_seamless_boot_optimization; 391 bool seamless_boot_edp_requested; 392 bool edp_not_connected; 393 bool edp_no_power_sequencing; 394 bool force_enum_edp; 395 bool forced_clocks; 396 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 397 bool multi_mon_pp_mclk_switch; 398 bool disable_dmcu; 399 bool enable_4to1MPC; 400 bool enable_windowed_mpo_odm; 401 uint32_t allow_edp_hotplug_detection; 402 bool clamp_min_dcfclk; 403 uint64_t vblank_alignment_dto_params; 404 uint8_t vblank_alignment_max_frame_time_diff; 405 bool is_asymmetric_memory; 406 bool is_single_rank_dimm; 407 bool is_vmin_only_asic; 408 bool use_pipe_ctx_sync_logic; 409 bool ignore_dpref_ss; 410 bool enable_mipi_converter_optimization; 411 bool use_default_clock_table; 412 bool force_bios_enable_lttpr; 413 uint8_t force_bios_fixed_vs; 414 415 }; 416 417 enum visual_confirm { 418 VISUAL_CONFIRM_DISABLE = 0, 419 VISUAL_CONFIRM_SURFACE = 1, 420 VISUAL_CONFIRM_HDR = 2, 421 VISUAL_CONFIRM_MPCTREE = 4, 422 VISUAL_CONFIRM_PSR = 5, 423 VISUAL_CONFIRM_SWAPCHAIN = 6, 424 VISUAL_CONFIRM_FAMS = 7, 425 VISUAL_CONFIRM_SWIZZLE = 9, 426 VISUAL_CONFIRM_SUBVP = 14, 427 }; 428 429 enum dc_psr_power_opts { 430 psr_power_opt_invalid = 0x0, 431 psr_power_opt_smu_opt_static_screen = 0x1, 432 psr_power_opt_z10_static_screen = 0x10, 433 psr_power_opt_ds_disable_allow = 0x100, 434 }; 435 436 enum dml_hostvm_override_opts { 437 DML_HOSTVM_NO_OVERRIDE = 0x0, 438 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 439 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 440 }; 441 442 enum dcc_option { 443 DCC_ENABLE = 0, 444 DCC_DISABLE = 1, 445 DCC_HALF_REQ_DISALBE = 2, 446 }; 447 448 /** 449 * enum pipe_split_policy - Pipe split strategy supported by DCN 450 * 451 * This enum is used to define the pipe split policy supported by DCN. By 452 * default, DC favors MPC_SPLIT_DYNAMIC. 453 */ 454 enum pipe_split_policy { 455 /** 456 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 457 * pipe in order to bring the best trade-off between performance and 458 * power consumption. This is the recommended option. 459 */ 460 MPC_SPLIT_DYNAMIC = 0, 461 462 /** 463 * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not 464 * try any sort of split optimization. 465 */ 466 MPC_SPLIT_AVOID = 1, 467 468 /** 469 * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize 470 * the pipe utilization when using a single display; if the user 471 * connects to a second display, DC will avoid pipe split. 472 */ 473 MPC_SPLIT_AVOID_MULT_DISP = 2, 474 }; 475 476 enum wm_report_mode { 477 WM_REPORT_DEFAULT = 0, 478 WM_REPORT_OVERRIDE = 1, 479 }; 480 enum dtm_pstate{ 481 dtm_level_p0 = 0,/*highest voltage*/ 482 dtm_level_p1, 483 dtm_level_p2, 484 dtm_level_p3, 485 dtm_level_p4,/*when active_display_count = 0*/ 486 }; 487 488 enum dcn_pwr_state { 489 DCN_PWR_STATE_UNKNOWN = -1, 490 DCN_PWR_STATE_MISSION_MODE = 0, 491 DCN_PWR_STATE_LOW_POWER = 3, 492 }; 493 494 enum dcn_zstate_support_state { 495 DCN_ZSTATE_SUPPORT_UNKNOWN, 496 DCN_ZSTATE_SUPPORT_ALLOW, 497 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 498 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 499 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 500 DCN_ZSTATE_SUPPORT_DISALLOW, 501 }; 502 503 /** 504 * dc_clocks - DC pipe clocks 505 * 506 * For any clocks that may differ per pipe only the max is stored in this 507 * structure 508 */ 509 struct dc_clocks { 510 int dispclk_khz; 511 int actual_dispclk_khz; 512 int dppclk_khz; 513 int actual_dppclk_khz; 514 int disp_dpp_voltage_level_khz; 515 int dcfclk_khz; 516 int socclk_khz; 517 int dcfclk_deep_sleep_khz; 518 int fclk_khz; 519 int phyclk_khz; 520 int dramclk_khz; 521 bool p_state_change_support; 522 enum dcn_zstate_support_state zstate_support; 523 bool dtbclk_en; 524 int ref_dtbclk_khz; 525 bool fclk_p_state_change_support; 526 enum dcn_pwr_state pwr_state; 527 /* 528 * Elements below are not compared for the purposes of 529 * optimization required 530 */ 531 bool prev_p_state_change_support; 532 bool fclk_prev_p_state_change_support; 533 int num_ways; 534 535 /** 536 * @fw_based_mclk_switching 537 * 538 * DC has a mechanism that leverage the variable refresh rate to switch 539 * memory clock in cases that we have a large latency to achieve the 540 * memory clock change and a short vblank window. DC has some 541 * requirements to enable this feature, and this field describes if the 542 * system support or not such a feature. 543 */ 544 bool fw_based_mclk_switching; 545 bool fw_based_mclk_switching_shut_down; 546 int prev_num_ways; 547 enum dtm_pstate dtm_level; 548 int max_supported_dppclk_khz; 549 int max_supported_dispclk_khz; 550 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 551 int bw_dispclk_khz; 552 }; 553 554 struct dc_bw_validation_profile { 555 bool enable; 556 557 unsigned long long total_ticks; 558 unsigned long long voltage_level_ticks; 559 unsigned long long watermark_ticks; 560 unsigned long long rq_dlg_ticks; 561 562 unsigned long long total_count; 563 unsigned long long skip_fast_count; 564 unsigned long long skip_pass_count; 565 unsigned long long skip_fail_count; 566 }; 567 568 #define BW_VAL_TRACE_SETUP() \ 569 unsigned long long end_tick = 0; \ 570 unsigned long long voltage_level_tick = 0; \ 571 unsigned long long watermark_tick = 0; \ 572 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 573 dm_get_timestamp(dc->ctx) : 0 574 575 #define BW_VAL_TRACE_COUNT() \ 576 if (dc->debug.bw_val_profile.enable) \ 577 dc->debug.bw_val_profile.total_count++ 578 579 #define BW_VAL_TRACE_SKIP(status) \ 580 if (dc->debug.bw_val_profile.enable) { \ 581 if (!voltage_level_tick) \ 582 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 583 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 584 } 585 586 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 587 if (dc->debug.bw_val_profile.enable) \ 588 voltage_level_tick = dm_get_timestamp(dc->ctx) 589 590 #define BW_VAL_TRACE_END_WATERMARKS() \ 591 if (dc->debug.bw_val_profile.enable) \ 592 watermark_tick = dm_get_timestamp(dc->ctx) 593 594 #define BW_VAL_TRACE_FINISH() \ 595 if (dc->debug.bw_val_profile.enable) { \ 596 end_tick = dm_get_timestamp(dc->ctx); \ 597 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 598 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 599 if (watermark_tick) { \ 600 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 601 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 602 } \ 603 } 604 605 union mem_low_power_enable_options { 606 struct { 607 bool vga: 1; 608 bool i2c: 1; 609 bool dmcu: 1; 610 bool dscl: 1; 611 bool cm: 1; 612 bool mpc: 1; 613 bool optc: 1; 614 bool vpg: 1; 615 bool afmt: 1; 616 } bits; 617 uint32_t u32All; 618 }; 619 620 union root_clock_optimization_options { 621 struct { 622 bool dpp: 1; 623 bool dsc: 1; 624 bool hdmistream: 1; 625 bool hdmichar: 1; 626 bool dpstream: 1; 627 bool symclk32_se: 1; 628 bool symclk32_le: 1; 629 bool symclk_fe: 1; 630 bool physymclk: 1; 631 bool dpiasymclk: 1; 632 uint32_t reserved: 22; 633 } bits; 634 uint32_t u32All; 635 }; 636 637 union dpia_debug_options { 638 struct { 639 uint32_t disable_dpia:1; /* bit 0 */ 640 uint32_t force_non_lttpr:1; /* bit 1 */ 641 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 642 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 643 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 644 uint32_t reserved:27; 645 } bits; 646 uint32_t raw; 647 }; 648 649 /* AUX wake work around options 650 * 0: enable/disable work around 651 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 652 * 15-2: reserved 653 * 31-16: timeout in ms 654 */ 655 union aux_wake_wa_options { 656 struct { 657 uint32_t enable_wa : 1; 658 uint32_t use_default_timeout : 1; 659 uint32_t rsvd: 14; 660 uint32_t timeout_ms : 16; 661 } bits; 662 uint32_t raw; 663 }; 664 665 struct dc_debug_data { 666 uint32_t ltFailCount; 667 uint32_t i2cErrorCount; 668 uint32_t auxErrorCount; 669 }; 670 671 struct dc_phy_addr_space_config { 672 struct { 673 uint64_t start_addr; 674 uint64_t end_addr; 675 uint64_t fb_top; 676 uint64_t fb_offset; 677 uint64_t fb_base; 678 uint64_t agp_top; 679 uint64_t agp_bot; 680 uint64_t agp_base; 681 } system_aperture; 682 683 struct { 684 uint64_t page_table_start_addr; 685 uint64_t page_table_end_addr; 686 uint64_t page_table_base_addr; 687 bool base_addr_is_mc_addr; 688 } gart_config; 689 690 bool valid; 691 bool is_hvm_enabled; 692 uint64_t page_table_default_page_addr; 693 }; 694 695 struct dc_virtual_addr_space_config { 696 uint64_t page_table_base_addr; 697 uint64_t page_table_start_addr; 698 uint64_t page_table_end_addr; 699 uint32_t page_table_block_size_in_bytes; 700 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 701 }; 702 703 struct dc_bounding_box_overrides { 704 int sr_exit_time_ns; 705 int sr_enter_plus_exit_time_ns; 706 int urgent_latency_ns; 707 int percent_of_ideal_drambw; 708 int dram_clock_change_latency_ns; 709 int dummy_clock_change_latency_ns; 710 int fclk_clock_change_latency_ns; 711 /* This forces a hard min on the DCFCLK we use 712 * for DML. Unlike the debug option for forcing 713 * DCFCLK, this override affects watermark calculations 714 */ 715 int min_dcfclk_mhz; 716 }; 717 718 struct dc_state; 719 struct resource_pool; 720 struct dce_hwseq; 721 722 /** 723 * struct dc_debug_options - DC debug struct 724 * 725 * This struct provides a simple mechanism for developers to change some 726 * configurations, enable/disable features, and activate extra debug options. 727 * This can be very handy to narrow down whether some specific feature is 728 * causing an issue or not. 729 */ 730 struct dc_debug_options { 731 bool native422_support; 732 bool disable_dsc; 733 enum visual_confirm visual_confirm; 734 int visual_confirm_rect_height; 735 736 bool sanity_checks; 737 bool max_disp_clk; 738 bool surface_trace; 739 bool timing_trace; 740 bool clock_trace; 741 bool validation_trace; 742 bool bandwidth_calcs_trace; 743 int max_downscale_src_width; 744 745 /* stutter efficiency related */ 746 bool disable_stutter; 747 bool use_max_lb; 748 enum dcc_option disable_dcc; 749 750 /** 751 * @pipe_split_policy: Define which pipe split policy is used by the 752 * display core. 753 */ 754 enum pipe_split_policy pipe_split_policy; 755 bool force_single_disp_pipe_split; 756 bool voltage_align_fclk; 757 bool disable_min_fclk; 758 759 bool disable_dfs_bypass; 760 bool disable_dpp_power_gate; 761 bool disable_hubp_power_gate; 762 bool disable_dsc_power_gate; 763 int dsc_min_slice_height_override; 764 int dsc_bpp_increment_div; 765 bool disable_pplib_wm_range; 766 enum wm_report_mode pplib_wm_report_mode; 767 unsigned int min_disp_clk_khz; 768 unsigned int min_dpp_clk_khz; 769 unsigned int min_dram_clk_khz; 770 int sr_exit_time_dpm0_ns; 771 int sr_enter_plus_exit_time_dpm0_ns; 772 int sr_exit_time_ns; 773 int sr_enter_plus_exit_time_ns; 774 int urgent_latency_ns; 775 uint32_t underflow_assert_delay_us; 776 int percent_of_ideal_drambw; 777 int dram_clock_change_latency_ns; 778 bool optimized_watermark; 779 int always_scale; 780 bool disable_pplib_clock_request; 781 bool disable_clock_gate; 782 bool disable_mem_low_power; 783 bool pstate_enabled; 784 bool disable_dmcu; 785 bool force_abm_enable; 786 bool disable_stereo_support; 787 bool vsr_support; 788 bool performance_trace; 789 bool az_endpoint_mute_only; 790 bool always_use_regamma; 791 bool recovery_enabled; 792 bool avoid_vbios_exec_table; 793 bool scl_reset_length10; 794 bool hdmi20_disable; 795 bool skip_detection_link_training; 796 uint32_t edid_read_retry_times; 797 unsigned int force_odm_combine; //bit vector based on otg inst 798 unsigned int seamless_boot_odm_combine; 799 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 800 int minimum_z8_residency_time; 801 bool disable_z9_mpc; 802 unsigned int force_fclk_khz; 803 bool enable_tri_buf; 804 bool dmub_offload_enabled; 805 bool dmcub_emulation; 806 bool disable_idle_power_optimizations; 807 unsigned int mall_size_override; 808 unsigned int mall_additional_timer_percent; 809 bool mall_error_as_fatal; 810 bool dmub_command_table; /* for testing only */ 811 struct dc_bw_validation_profile bw_val_profile; 812 bool disable_fec; 813 bool disable_48mhz_pwrdwn; 814 /* This forces a hard min on the DCFCLK requested to SMU/PP 815 * watermarks are not affected. 816 */ 817 unsigned int force_min_dcfclk_mhz; 818 int dwb_fi_phase; 819 bool disable_timing_sync; 820 bool cm_in_bypass; 821 int force_clock_mode;/*every mode change.*/ 822 823 bool disable_dram_clock_change_vactive_support; 824 bool validate_dml_output; 825 bool enable_dmcub_surface_flip; 826 bool usbc_combo_phy_reset_wa; 827 bool enable_dram_clock_change_one_display_vactive; 828 /* TODO - remove once tested */ 829 bool legacy_dp2_lt; 830 bool set_mst_en_for_sst; 831 bool disable_uhbr; 832 bool force_dp2_lt_fallback_method; 833 bool ignore_cable_id; 834 union mem_low_power_enable_options enable_mem_low_power; 835 union root_clock_optimization_options root_clock_optimization; 836 bool hpo_optimization; 837 bool force_vblank_alignment; 838 839 /* Enable dmub aux for legacy ddc */ 840 bool enable_dmub_aux_for_legacy_ddc; 841 bool disable_fams; 842 /* FEC/PSR1 sequence enable delay in 100us */ 843 uint8_t fec_enable_delay_in100us; 844 bool enable_driver_sequence_debug; 845 enum det_size crb_alloc_policy; 846 int crb_alloc_policy_min_disp_count; 847 bool disable_z10; 848 bool enable_z9_disable_interface; 849 bool psr_skip_crtc_disable; 850 union dpia_debug_options dpia_debug; 851 bool disable_fixed_vs_aux_timeout_wa; 852 bool force_disable_subvp; 853 bool force_subvp_mclk_switch; 854 bool allow_sw_cursor_fallback; 855 unsigned int force_subvp_num_ways; 856 unsigned int force_mall_ss_num_ways; 857 bool alloc_extra_way_for_cursor; 858 bool force_usr_allow; 859 /* uses value at boot and disables switch */ 860 bool disable_dtb_ref_clk_switch; 861 uint32_t fixed_vs_aux_delay_config_wa; 862 bool extended_blank_optimization; 863 union aux_wake_wa_options aux_wake_wa; 864 uint32_t mst_start_top_delay; 865 uint8_t psr_power_use_phy_fsm; 866 enum dml_hostvm_override_opts dml_hostvm_override; 867 bool dml_disallow_alternate_prefetch_modes; 868 bool use_legacy_soc_bb_mechanism; 869 bool exit_idle_opt_for_cursor_updates; 870 bool enable_single_display_2to1_odm_policy; 871 bool enable_double_buffered_dsc_pg_support; 872 bool enable_dp_dig_pixel_rate_div_policy; 873 enum lttpr_mode lttpr_mode_override; 874 unsigned int dsc_delay_factor_wa_x1000; 875 unsigned int min_prefetch_in_strobe_ns; 876 }; 877 878 struct gpu_info_soc_bounding_box_v1_0; 879 struct dc { 880 struct dc_debug_options debug; 881 struct dc_versions versions; 882 struct dc_caps caps; 883 struct dc_cap_funcs cap_funcs; 884 struct dc_config config; 885 struct dc_bounding_box_overrides bb_overrides; 886 struct dc_bug_wa work_arounds; 887 struct dc_context *ctx; 888 struct dc_phy_addr_space_config vm_pa_config; 889 890 uint8_t link_count; 891 struct dc_link *links[MAX_PIPES * 2]; 892 893 struct dc_state *current_state; 894 struct resource_pool *res_pool; 895 896 struct clk_mgr *clk_mgr; 897 898 /* Display Engine Clock levels */ 899 struct dm_pp_clock_levels sclk_lvls; 900 901 /* Inputs into BW and WM calculations. */ 902 struct bw_calcs_dceip *bw_dceip; 903 struct bw_calcs_vbios *bw_vbios; 904 struct dcn_soc_bounding_box *dcn_soc; 905 struct dcn_ip_params *dcn_ip; 906 struct display_mode_lib dml; 907 908 /* HW functions */ 909 struct hw_sequencer_funcs hwss; 910 struct dce_hwseq *hwseq; 911 912 /* Require to optimize clocks and bandwidth for added/removed planes */ 913 bool optimized_required; 914 bool wm_optimized_required; 915 bool idle_optimizations_allowed; 916 bool enable_c20_dtm_b0; 917 918 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 919 920 /* FBC compressor */ 921 struct compressor *fbc_compressor; 922 923 struct dc_debug_data debug_data; 924 struct dpcd_vendor_signature vendor_signature; 925 926 const char *build_id; 927 struct vm_helper *vm_helper; 928 929 uint32_t *dcn_reg_offsets; 930 uint32_t *nbio_reg_offsets; 931 932 /* Scratch memory */ 933 struct { 934 struct { 935 /* 936 * For matching clock_limits table in driver with table 937 * from PMFW. 938 */ 939 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 940 } update_bw_bounding_box; 941 } scratch; 942 }; 943 944 enum frame_buffer_mode { 945 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 946 FRAME_BUFFER_MODE_ZFB_ONLY, 947 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 948 } ; 949 950 struct dchub_init_data { 951 int64_t zfb_phys_addr_base; 952 int64_t zfb_mc_base_addr; 953 uint64_t zfb_size_in_byte; 954 enum frame_buffer_mode fb_mode; 955 bool dchub_initialzied; 956 bool dchub_info_valid; 957 }; 958 959 struct dc_init_data { 960 struct hw_asic_id asic_id; 961 void *driver; /* ctx */ 962 struct cgs_device *cgs_device; 963 struct dc_bounding_box_overrides bb_overrides; 964 965 int num_virtual_links; 966 /* 967 * If 'vbios_override' not NULL, it will be called instead 968 * of the real VBIOS. Intended use is Diagnostics on FPGA. 969 */ 970 struct dc_bios *vbios_override; 971 enum dce_environment dce_environment; 972 973 struct dmub_offload_funcs *dmub_if; 974 struct dc_reg_helper_state *dmub_offload; 975 976 struct dc_config flags; 977 uint64_t log_mask; 978 979 struct dpcd_vendor_signature vendor_signature; 980 bool force_smu_not_present; 981 /* 982 * IP offset for run time initializaion of register addresses 983 * 984 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 985 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 986 * before them. 987 */ 988 uint32_t *dcn_reg_offsets; 989 uint32_t *nbio_reg_offsets; 990 }; 991 992 struct dc_callback_init { 993 #ifdef CONFIG_DRM_AMD_DC_HDCP 994 struct cp_psp cp_psp; 995 #else 996 uint8_t reserved; 997 #endif 998 }; 999 1000 struct dc *dc_create(const struct dc_init_data *init_params); 1001 void dc_hardware_init(struct dc *dc); 1002 1003 int dc_get_vmid_use_vector(struct dc *dc); 1004 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1005 /* Returns the number of vmids supported */ 1006 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1007 void dc_init_callbacks(struct dc *dc, 1008 const struct dc_callback_init *init_params); 1009 void dc_deinit_callbacks(struct dc *dc); 1010 void dc_destroy(struct dc **dc); 1011 1012 /* Surface Interfaces */ 1013 1014 enum { 1015 TRANSFER_FUNC_POINTS = 1025 1016 }; 1017 1018 struct dc_hdr_static_metadata { 1019 /* display chromaticities and white point in units of 0.00001 */ 1020 unsigned int chromaticity_green_x; 1021 unsigned int chromaticity_green_y; 1022 unsigned int chromaticity_blue_x; 1023 unsigned int chromaticity_blue_y; 1024 unsigned int chromaticity_red_x; 1025 unsigned int chromaticity_red_y; 1026 unsigned int chromaticity_white_point_x; 1027 unsigned int chromaticity_white_point_y; 1028 1029 uint32_t min_luminance; 1030 uint32_t max_luminance; 1031 uint32_t maximum_content_light_level; 1032 uint32_t maximum_frame_average_light_level; 1033 }; 1034 1035 enum dc_transfer_func_type { 1036 TF_TYPE_PREDEFINED, 1037 TF_TYPE_DISTRIBUTED_POINTS, 1038 TF_TYPE_BYPASS, 1039 TF_TYPE_HWPWL 1040 }; 1041 1042 struct dc_transfer_func_distributed_points { 1043 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1044 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1045 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1046 1047 uint16_t end_exponent; 1048 uint16_t x_point_at_y1_red; 1049 uint16_t x_point_at_y1_green; 1050 uint16_t x_point_at_y1_blue; 1051 }; 1052 1053 enum dc_transfer_func_predefined { 1054 TRANSFER_FUNCTION_SRGB, 1055 TRANSFER_FUNCTION_BT709, 1056 TRANSFER_FUNCTION_PQ, 1057 TRANSFER_FUNCTION_LINEAR, 1058 TRANSFER_FUNCTION_UNITY, 1059 TRANSFER_FUNCTION_HLG, 1060 TRANSFER_FUNCTION_HLG12, 1061 TRANSFER_FUNCTION_GAMMA22, 1062 TRANSFER_FUNCTION_GAMMA24, 1063 TRANSFER_FUNCTION_GAMMA26 1064 }; 1065 1066 1067 struct dc_transfer_func { 1068 struct kref refcount; 1069 enum dc_transfer_func_type type; 1070 enum dc_transfer_func_predefined tf; 1071 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1072 uint32_t sdr_ref_white_level; 1073 union { 1074 struct pwl_params pwl; 1075 struct dc_transfer_func_distributed_points tf_pts; 1076 }; 1077 }; 1078 1079 1080 union dc_3dlut_state { 1081 struct { 1082 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1083 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1084 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1085 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1086 uint32_t mpc_rmu1_mux:4; 1087 uint32_t mpc_rmu2_mux:4; 1088 uint32_t reserved:15; 1089 } bits; 1090 uint32_t raw; 1091 }; 1092 1093 1094 struct dc_3dlut { 1095 struct kref refcount; 1096 struct tetrahedral_params lut_3d; 1097 struct fixed31_32 hdr_multiplier; 1098 union dc_3dlut_state state; 1099 }; 1100 /* 1101 * This structure is filled in by dc_surface_get_status and contains 1102 * the last requested address and the currently active address so the called 1103 * can determine if there are any outstanding flips 1104 */ 1105 struct dc_plane_status { 1106 struct dc_plane_address requested_address; 1107 struct dc_plane_address current_address; 1108 bool is_flip_pending; 1109 bool is_right_eye; 1110 }; 1111 1112 union surface_update_flags { 1113 1114 struct { 1115 uint32_t addr_update:1; 1116 /* Medium updates */ 1117 uint32_t dcc_change:1; 1118 uint32_t color_space_change:1; 1119 uint32_t horizontal_mirror_change:1; 1120 uint32_t per_pixel_alpha_change:1; 1121 uint32_t global_alpha_change:1; 1122 uint32_t hdr_mult:1; 1123 uint32_t rotation_change:1; 1124 uint32_t swizzle_change:1; 1125 uint32_t scaling_change:1; 1126 uint32_t position_change:1; 1127 uint32_t in_transfer_func_change:1; 1128 uint32_t input_csc_change:1; 1129 uint32_t coeff_reduction_change:1; 1130 uint32_t output_tf_change:1; 1131 uint32_t pixel_format_change:1; 1132 uint32_t plane_size_change:1; 1133 uint32_t gamut_remap_change:1; 1134 1135 /* Full updates */ 1136 uint32_t new_plane:1; 1137 uint32_t bpp_change:1; 1138 uint32_t gamma_change:1; 1139 uint32_t bandwidth_change:1; 1140 uint32_t clock_change:1; 1141 uint32_t stereo_format_change:1; 1142 uint32_t lut_3d:1; 1143 uint32_t tmz_changed:1; 1144 uint32_t full_update:1; 1145 } bits; 1146 1147 uint32_t raw; 1148 }; 1149 1150 struct dc_plane_state { 1151 struct dc_plane_address address; 1152 struct dc_plane_flip_time time; 1153 bool triplebuffer_flips; 1154 struct scaling_taps scaling_quality; 1155 struct rect src_rect; 1156 struct rect dst_rect; 1157 struct rect clip_rect; 1158 1159 struct plane_size plane_size; 1160 union dc_tiling_info tiling_info; 1161 1162 struct dc_plane_dcc_param dcc; 1163 1164 struct dc_gamma *gamma_correction; 1165 struct dc_transfer_func *in_transfer_func; 1166 struct dc_bias_and_scale *bias_and_scale; 1167 struct dc_csc_transform input_csc_color_matrix; 1168 struct fixed31_32 coeff_reduction_factor; 1169 struct fixed31_32 hdr_mult; 1170 struct colorspace_transform gamut_remap_matrix; 1171 1172 // TODO: No longer used, remove 1173 struct dc_hdr_static_metadata hdr_static_ctx; 1174 1175 enum dc_color_space color_space; 1176 1177 struct dc_3dlut *lut3d_func; 1178 struct dc_transfer_func *in_shaper_func; 1179 struct dc_transfer_func *blend_tf; 1180 1181 struct dc_transfer_func *gamcor_tf; 1182 enum surface_pixel_format format; 1183 enum dc_rotation_angle rotation; 1184 enum plane_stereo_format stereo_format; 1185 1186 bool is_tiling_rotated; 1187 bool per_pixel_alpha; 1188 bool pre_multiplied_alpha; 1189 bool global_alpha; 1190 int global_alpha_value; 1191 bool visible; 1192 bool flip_immediate; 1193 bool horizontal_mirror; 1194 int layer_index; 1195 1196 union surface_update_flags update_flags; 1197 bool flip_int_enabled; 1198 bool skip_manual_trigger; 1199 1200 /* private to DC core */ 1201 struct dc_plane_status status; 1202 struct dc_context *ctx; 1203 1204 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1205 bool force_full_update; 1206 1207 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1208 1209 /* private to dc_surface.c */ 1210 enum dc_irq_source irq_source; 1211 struct kref refcount; 1212 struct tg_color visual_confirm_color; 1213 1214 bool is_statically_allocated; 1215 }; 1216 1217 struct dc_plane_info { 1218 struct plane_size plane_size; 1219 union dc_tiling_info tiling_info; 1220 struct dc_plane_dcc_param dcc; 1221 enum surface_pixel_format format; 1222 enum dc_rotation_angle rotation; 1223 enum plane_stereo_format stereo_format; 1224 enum dc_color_space color_space; 1225 bool horizontal_mirror; 1226 bool visible; 1227 bool per_pixel_alpha; 1228 bool pre_multiplied_alpha; 1229 bool global_alpha; 1230 int global_alpha_value; 1231 bool input_csc_enabled; 1232 int layer_index; 1233 }; 1234 1235 struct dc_scaling_info { 1236 struct rect src_rect; 1237 struct rect dst_rect; 1238 struct rect clip_rect; 1239 struct scaling_taps scaling_quality; 1240 }; 1241 1242 struct dc_surface_update { 1243 struct dc_plane_state *surface; 1244 1245 /* isr safe update parameters. null means no updates */ 1246 const struct dc_flip_addrs *flip_addr; 1247 const struct dc_plane_info *plane_info; 1248 const struct dc_scaling_info *scaling_info; 1249 struct fixed31_32 hdr_mult; 1250 /* following updates require alloc/sleep/spin that is not isr safe, 1251 * null means no updates 1252 */ 1253 const struct dc_gamma *gamma; 1254 const struct dc_transfer_func *in_transfer_func; 1255 1256 const struct dc_csc_transform *input_csc_color_matrix; 1257 const struct fixed31_32 *coeff_reduction_factor; 1258 const struct dc_transfer_func *func_shaper; 1259 const struct dc_3dlut *lut3d_func; 1260 const struct dc_transfer_func *blend_tf; 1261 const struct colorspace_transform *gamut_remap_matrix; 1262 }; 1263 1264 /* 1265 * Create a new surface with default parameters; 1266 */ 1267 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1268 const struct dc_plane_status *dc_plane_get_status( 1269 const struct dc_plane_state *plane_state); 1270 1271 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1272 void dc_plane_state_release(struct dc_plane_state *plane_state); 1273 1274 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1275 void dc_gamma_release(struct dc_gamma **dc_gamma); 1276 struct dc_gamma *dc_create_gamma(void); 1277 1278 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1279 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1280 struct dc_transfer_func *dc_create_transfer_func(void); 1281 1282 struct dc_3dlut *dc_create_3dlut_func(void); 1283 void dc_3dlut_func_release(struct dc_3dlut *lut); 1284 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1285 1286 void dc_post_update_surfaces_to_stream( 1287 struct dc *dc); 1288 1289 #include "dc_stream.h" 1290 1291 /** 1292 * struct dc_validation_set - Struct to store surface/stream associations for validation 1293 */ 1294 struct dc_validation_set { 1295 /** 1296 * @stream: Stream state properties 1297 */ 1298 struct dc_stream_state *stream; 1299 1300 /** 1301 * @plane_state: Surface state 1302 */ 1303 struct dc_plane_state *plane_states[MAX_SURFACES]; 1304 1305 /** 1306 * @plane_count: Total of active planes 1307 */ 1308 uint8_t plane_count; 1309 }; 1310 1311 bool dc_validate_boot_timing(const struct dc *dc, 1312 const struct dc_sink *sink, 1313 struct dc_crtc_timing *crtc_timing); 1314 1315 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1316 1317 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1318 1319 enum dc_status dc_validate_with_context(struct dc *dc, 1320 const struct dc_validation_set set[], 1321 int set_count, 1322 struct dc_state *context, 1323 bool fast_validate); 1324 1325 bool dc_set_generic_gpio_for_stereo(bool enable, 1326 struct gpio_service *gpio_service); 1327 1328 /* 1329 * fast_validate: we return after determining if we can support the new state, 1330 * but before we populate the programming info 1331 */ 1332 enum dc_status dc_validate_global_state( 1333 struct dc *dc, 1334 struct dc_state *new_ctx, 1335 bool fast_validate); 1336 1337 1338 void dc_resource_state_construct( 1339 const struct dc *dc, 1340 struct dc_state *dst_ctx); 1341 1342 bool dc_acquire_release_mpc_3dlut( 1343 struct dc *dc, bool acquire, 1344 struct dc_stream_state *stream, 1345 struct dc_3dlut **lut, 1346 struct dc_transfer_func **shaper); 1347 1348 void dc_resource_state_copy_construct( 1349 const struct dc_state *src_ctx, 1350 struct dc_state *dst_ctx); 1351 1352 void dc_resource_state_copy_construct_current( 1353 const struct dc *dc, 1354 struct dc_state *dst_ctx); 1355 1356 void dc_resource_state_destruct(struct dc_state *context); 1357 1358 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1359 1360 enum dc_status dc_commit_streams(struct dc *dc, 1361 struct dc_stream_state *streams[], 1362 uint8_t stream_count); 1363 1364 /* TODO: When the transition to the new commit sequence is done, remove this 1365 * function in favor of dc_commit_streams. */ 1366 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1367 1368 struct dc_state *dc_create_state(struct dc *dc); 1369 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1370 void dc_retain_state(struct dc_state *context); 1371 void dc_release_state(struct dc_state *context); 1372 1373 /* Link Interfaces */ 1374 1375 struct dpcd_caps { 1376 union dpcd_rev dpcd_rev; 1377 union max_lane_count max_ln_count; 1378 union max_down_spread max_down_spread; 1379 union dprx_feature dprx_feature; 1380 1381 /* valid only for eDP v1.4 or higher*/ 1382 uint8_t edp_supported_link_rates_count; 1383 enum dc_link_rate edp_supported_link_rates[8]; 1384 1385 /* dongle type (DP converter, CV smart dongle) */ 1386 enum display_dongle_type dongle_type; 1387 bool is_dongle_type_one; 1388 /* branch device or sink device */ 1389 bool is_branch_dev; 1390 /* Dongle's downstream count. */ 1391 union sink_count sink_count; 1392 bool is_mst_capable; 1393 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1394 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1395 struct dc_dongle_caps dongle_caps; 1396 1397 uint32_t sink_dev_id; 1398 int8_t sink_dev_id_str[6]; 1399 int8_t sink_hw_revision; 1400 int8_t sink_fw_revision[2]; 1401 1402 uint32_t branch_dev_id; 1403 int8_t branch_dev_name[6]; 1404 int8_t branch_hw_revision; 1405 int8_t branch_fw_revision[2]; 1406 1407 bool allow_invalid_MSA_timing_param; 1408 bool panel_mode_edp; 1409 bool dpcd_display_control_capable; 1410 bool ext_receiver_cap_field_present; 1411 bool set_power_state_capable_edp; 1412 bool dynamic_backlight_capable_edp; 1413 union dpcd_fec_capability fec_cap; 1414 struct dpcd_dsc_capabilities dsc_caps; 1415 struct dc_lttpr_caps lttpr_caps; 1416 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1417 1418 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1419 union dp_main_line_channel_coding_cap channel_coding_cap; 1420 union dp_sink_video_fallback_formats fallback_formats; 1421 union dp_fec_capability1 fec_cap1; 1422 union dp_cable_id cable_id; 1423 uint8_t edp_rev; 1424 union edp_alpm_caps alpm_caps; 1425 struct edp_psr_info psr_info; 1426 }; 1427 1428 union dpcd_sink_ext_caps { 1429 struct { 1430 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1431 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1432 */ 1433 uint8_t sdr_aux_backlight_control : 1; 1434 uint8_t hdr_aux_backlight_control : 1; 1435 uint8_t reserved_1 : 2; 1436 uint8_t oled : 1; 1437 uint8_t reserved : 3; 1438 } bits; 1439 uint8_t raw; 1440 }; 1441 1442 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1443 union hdcp_rx_caps { 1444 struct { 1445 uint8_t version; 1446 uint8_t reserved; 1447 struct { 1448 uint8_t repeater : 1; 1449 uint8_t hdcp_capable : 1; 1450 uint8_t reserved : 6; 1451 } byte0; 1452 } fields; 1453 uint8_t raw[3]; 1454 }; 1455 1456 union hdcp_bcaps { 1457 struct { 1458 uint8_t HDCP_CAPABLE:1; 1459 uint8_t REPEATER:1; 1460 uint8_t RESERVED:6; 1461 } bits; 1462 uint8_t raw; 1463 }; 1464 1465 struct hdcp_caps { 1466 union hdcp_rx_caps rx_caps; 1467 union hdcp_bcaps bcaps; 1468 }; 1469 #endif 1470 1471 #include "dc_link.h" 1472 1473 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1474 1475 /* Sink Interfaces - A sink corresponds to a display output device */ 1476 1477 struct dc_container_id { 1478 // 128bit GUID in binary form 1479 unsigned char guid[16]; 1480 // 8 byte port ID -> ELD.PortID 1481 unsigned int portId[2]; 1482 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1483 unsigned short manufacturerName; 1484 // 2 byte product code -> ELD.ProductCode 1485 unsigned short productCode; 1486 }; 1487 1488 1489 struct dc_sink_dsc_caps { 1490 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1491 // 'false' if they are sink's DSC caps 1492 bool is_virtual_dpcd_dsc; 1493 #if defined(CONFIG_DRM_AMD_DC_DCN) 1494 // 'true' if MST topology supports DSC passthrough for sink 1495 // 'false' if MST topology does not support DSC passthrough 1496 bool is_dsc_passthrough_supported; 1497 #endif 1498 struct dsc_dec_dpcd_caps dsc_dec_caps; 1499 }; 1500 1501 struct dc_sink_fec_caps { 1502 bool is_rx_fec_supported; 1503 bool is_topology_fec_supported; 1504 }; 1505 1506 /* 1507 * The sink structure contains EDID and other display device properties 1508 */ 1509 struct dc_sink { 1510 enum signal_type sink_signal; 1511 struct dc_edid dc_edid; /* raw edid */ 1512 struct dc_edid_caps edid_caps; /* parse display caps */ 1513 struct dc_container_id *dc_container_id; 1514 uint32_t dongle_max_pix_clk; 1515 void *priv; 1516 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1517 bool converter_disable_audio; 1518 1519 struct dc_sink_dsc_caps dsc_caps; 1520 struct dc_sink_fec_caps fec_caps; 1521 1522 bool is_vsc_sdp_colorimetry_supported; 1523 1524 /* private to DC core */ 1525 struct dc_link *link; 1526 struct dc_context *ctx; 1527 1528 uint32_t sink_id; 1529 1530 /* private to dc_sink.c */ 1531 // refcount must be the last member in dc_sink, since we want the 1532 // sink structure to be logically cloneable up to (but not including) 1533 // refcount 1534 struct kref refcount; 1535 }; 1536 1537 void dc_sink_retain(struct dc_sink *sink); 1538 void dc_sink_release(struct dc_sink *sink); 1539 1540 struct dc_sink_init_data { 1541 enum signal_type sink_signal; 1542 struct dc_link *link; 1543 uint32_t dongle_max_pix_clk; 1544 bool converter_disable_audio; 1545 }; 1546 1547 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1548 1549 /* Newer interfaces */ 1550 struct dc_cursor { 1551 struct dc_plane_address address; 1552 struct dc_cursor_attributes attributes; 1553 }; 1554 1555 1556 /* Interrupt interfaces */ 1557 enum dc_irq_source dc_interrupt_to_irq_source( 1558 struct dc *dc, 1559 uint32_t src_id, 1560 uint32_t ext_id); 1561 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1562 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1563 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1564 struct dc *dc, uint32_t link_index); 1565 1566 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1567 1568 /* Power Interfaces */ 1569 1570 void dc_set_power_state( 1571 struct dc *dc, 1572 enum dc_acpi_cm_power_state power_state); 1573 void dc_resume(struct dc *dc); 1574 1575 void dc_power_down_on_boot(struct dc *dc); 1576 1577 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1578 /* 1579 * HDCP Interfaces 1580 */ 1581 enum hdcp_message_status dc_process_hdcp_msg( 1582 enum signal_type signal, 1583 struct dc_link *link, 1584 struct hdcp_protection_message *message_info); 1585 #endif 1586 bool dc_is_dmcu_initialized(struct dc *dc); 1587 1588 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1589 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1590 1591 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1592 struct dc_cursor_attributes *cursor_attr); 1593 1594 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1595 1596 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1597 void dc_unlock_memory_clock_frequency(struct dc *dc); 1598 1599 /* set min memory clock to the min required for current mode, max to maxDPM */ 1600 void dc_lock_memory_clock_frequency(struct dc *dc); 1601 1602 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1603 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1604 1605 /* cleanup on driver unload */ 1606 void dc_hardware_release(struct dc *dc); 1607 1608 /* disables fw based mclk switch */ 1609 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1610 1611 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1612 void dc_z10_restore(const struct dc *dc); 1613 void dc_z10_save_init(struct dc *dc); 1614 1615 bool dc_is_dmub_outbox_supported(struct dc *dc); 1616 bool dc_enable_dmub_notifications(struct dc *dc); 1617 1618 void dc_enable_dmub_outbox(struct dc *dc); 1619 1620 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1621 uint32_t link_index, 1622 struct aux_payload *payload); 1623 1624 /* Get dc link index from dpia port index */ 1625 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1626 uint8_t dpia_port_index); 1627 1628 bool dc_process_dmub_set_config_async(struct dc *dc, 1629 uint32_t link_index, 1630 struct set_config_cmd_payload *payload, 1631 struct dmub_notification *notify); 1632 1633 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1634 uint32_t link_index, 1635 uint8_t mst_alloc_slots, 1636 uint8_t *mst_slots_in_use); 1637 1638 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 1639 uint32_t hpd_int_enable); 1640 1641 /* DSC Interfaces */ 1642 #include "dc_dsc.h" 1643 1644 /* Disable acc mode Interfaces */ 1645 void dc_disable_accelerated_mode(struct dc *dc); 1646 1647 #endif /* DC_INTERFACE_H_ */ 1648