1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7915_H
5 #define __MT7915_H
6
7 #include <linux/interrupt.h>
8 #include <linux/ktime.h>
9 #include "../mt76_connac.h"
10 #include "regs.h"
11
12 #define MT7915_MAX_INTERFACES 19
13 #define MT7915_WTBL_SIZE 288
14 #define MT7916_WTBL_SIZE 544
15 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1)
16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \
17 MT7915_MAX_INTERFACES)
18
19 #define MT7915_WATCHDOG_TIME (HZ / 10)
20 #define MT7915_RESET_TIMEOUT (30 * HZ)
21
22 #define MT7915_TX_RING_SIZE 2048
23 #define MT7915_TX_MCU_RING_SIZE 256
24 #define MT7915_TX_FWDL_RING_SIZE 128
25
26 #define MT7915_RX_RING_SIZE 1536
27 #define MT7915_RX_MCU_RING_SIZE 512
28
29 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin"
30 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin"
31 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin"
32
33 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin"
34 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin"
35 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin"
36
37 #define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin"
38 #define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin"
39 #define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin"
40 #define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin"
41 #define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin"
42
43 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"
44 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"
45 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin"
46 #define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin"
47 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin"
48 #define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin"
49 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin"
50 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin"
51
52 #define MT7915_EEPROM_SIZE 3584
53 #define MT7916_EEPROM_SIZE 4096
54
55 #define MT7915_EEPROM_BLOCK_SIZE 16
56 #define MT7915_TOKEN_SIZE 8192
57
58 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
59 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
60
61 #define MT7915_THERMAL_THROTTLE_MAX 100
62 #define MT7915_CDEV_THROTTLE_MAX 99
63
64 #define MT7915_SKU_RATE_NUM 161
65
66 #define MT7915_MAX_TWT_AGRT 16
67 #define MT7915_MAX_STA_TWT_AGRT 8
68 #define MT7915_MIN_TWT_DUR 64
69 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
70
71 struct mt7915_vif;
72 struct mt7915_sta;
73 struct mt7915_dfs_pulse;
74 struct mt7915_dfs_pattern;
75
76 enum mt7915_txq_id {
77 MT7915_TXQ_FWDL = 16,
78 MT7915_TXQ_MCU_WM,
79 MT7915_TXQ_BAND0,
80 MT7915_TXQ_BAND1,
81 MT7915_TXQ_MCU_WA,
82 };
83
84 enum mt7915_rxq_id {
85 MT7915_RXQ_BAND0 = 0,
86 MT7915_RXQ_BAND1,
87 MT7915_RXQ_MCU_WM = 0,
88 MT7915_RXQ_MCU_WA,
89 MT7915_RXQ_MCU_WA_EXT,
90 };
91
92 enum mt7916_rxq_id {
93 MT7916_RXQ_MCU_WM = 0,
94 MT7916_RXQ_MCU_WA,
95 MT7916_RXQ_MCU_WA_MAIN,
96 MT7916_RXQ_MCU_WA_EXT,
97 MT7916_RXQ_BAND0,
98 MT7916_RXQ_BAND1,
99 };
100
101 struct mt7915_twt_flow {
102 struct list_head list;
103 u64 start_tsf;
104 u64 tsf;
105 u32 duration;
106 u16 wcid;
107 __le16 mantissa;
108 u8 exp;
109 u8 table_id;
110 u8 id;
111 u8 protection:1;
112 u8 flowtype:1;
113 u8 trigger:1;
114 u8 sched:1;
115 };
116
117 struct mt7915_sta {
118 struct mt76_wcid wcid; /* must be first */
119
120 struct mt7915_vif *vif;
121
122 struct list_head poll_list;
123 struct list_head rc_list;
124 u32 airtime_ac[8];
125
126 unsigned long changed;
127 unsigned long jiffies;
128 unsigned long ampdu_state;
129
130 struct mt76_connac_sta_key_conf bip;
131
132 struct {
133 u8 flowid_mask;
134 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT];
135 } twt;
136 };
137
138 struct mt7915_vif_cap {
139 bool ht_ldpc:1;
140 bool vht_ldpc:1;
141 bool he_ldpc:1;
142 bool vht_su_ebfer:1;
143 bool vht_su_ebfee:1;
144 bool vht_mu_ebfer:1;
145 bool vht_mu_ebfee:1;
146 bool he_su_ebfer:1;
147 bool he_su_ebfee:1;
148 bool he_mu_ebfer:1;
149 };
150
151 struct mt7915_vif {
152 struct mt76_vif mt76; /* must be first */
153
154 struct mt7915_vif_cap cap;
155 struct mt7915_sta sta;
156 struct mt7915_phy *phy;
157
158 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
159 struct cfg80211_bitrate_mask bitrate_mask;
160 };
161
162 /* per-phy stats. */
163 struct mib_stats {
164 u32 ack_fail_cnt;
165 u32 fcs_err_cnt;
166 u32 rts_cnt;
167 u32 rts_retries_cnt;
168 u32 ba_miss_cnt;
169 u32 tx_bf_cnt;
170 u32 tx_mu_mpdu_cnt;
171 u32 tx_mu_acked_mpdu_cnt;
172 u32 tx_su_acked_mpdu_cnt;
173 u32 tx_bf_ibf_ppdu_cnt;
174 u32 tx_bf_ebf_ppdu_cnt;
175
176 u32 tx_bf_rx_fb_all_cnt;
177 u32 tx_bf_rx_fb_he_cnt;
178 u32 tx_bf_rx_fb_vht_cnt;
179 u32 tx_bf_rx_fb_ht_cnt;
180
181 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
182 u32 tx_bf_rx_fb_nc_cnt;
183 u32 tx_bf_rx_fb_nr_cnt;
184 u32 tx_bf_fb_cpl_cnt;
185 u32 tx_bf_fb_trig_cnt;
186
187 u32 tx_ampdu_cnt;
188 u32 tx_stop_q_empty_cnt;
189 u32 tx_mpdu_attempts_cnt;
190 u32 tx_mpdu_success_cnt;
191 u32 tx_pkt_ebf_cnt;
192 u32 tx_pkt_ibf_cnt;
193
194 u32 tx_rwp_fail_cnt;
195 u32 tx_rwp_need_cnt;
196
197 /* rx stats */
198 u32 rx_fifo_full_cnt;
199 u32 channel_idle_cnt;
200 u32 primary_cca_busy_time;
201 u32 secondary_cca_busy_time;
202 u32 primary_energy_detect_time;
203 u32 cck_mdrdy_time;
204 u32 ofdm_mdrdy_time;
205 u32 green_mdrdy_time;
206 u32 rx_vector_mismatch_cnt;
207 u32 rx_delimiter_fail_cnt;
208 u32 rx_mrdy_cnt;
209 u32 rx_len_mismatch_cnt;
210 u32 rx_mpdu_cnt;
211 u32 rx_ampdu_cnt;
212 u32 rx_ampdu_bytes_cnt;
213 u32 rx_ampdu_valid_subframe_cnt;
214 u32 rx_ampdu_valid_subframe_bytes_cnt;
215 u32 rx_pfdrop_cnt;
216 u32 rx_vec_queue_overflow_drop_cnt;
217 u32 rx_ba_cnt;
218
219 u32 tx_amsdu[8];
220 u32 tx_amsdu_cnt;
221 };
222
223 struct mt7915_hif {
224 struct list_head list;
225
226 struct device *dev;
227 void __iomem *regs;
228 int irq;
229 };
230
231 struct mt7915_phy {
232 struct mt76_phy *mt76;
233 struct mt7915_dev *dev;
234
235 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
236
237 struct ieee80211_vif *monitor_vif;
238
239 struct thermal_cooling_device *cdev;
240 u8 cdev_state;
241 u8 throttle_state;
242 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
243
244 u32 rxfilter;
245 u64 omac_mask;
246 u8 band_idx;
247
248 u16 noise;
249
250 s16 coverage_class;
251 u8 slottime;
252
253 u8 rdd_state;
254
255 u32 trb_ts;
256
257 u32 rx_ampdu_ts;
258 u32 ampdu_ref;
259
260 struct mib_stats mib;
261 struct mt76_channel_state state_ts;
262
263 #ifdef CONFIG_NL80211_TESTMODE
264 struct {
265 u32 *reg_backup;
266
267 s32 last_freq_offset;
268 u8 last_rcpi[4];
269 s8 last_ib_rssi[4];
270 s8 last_wb_rssi[4];
271 u8 last_snr;
272
273 u8 spe_idx;
274 } test;
275 #endif
276 };
277
278 struct mt7915_dev {
279 union { /* must be first */
280 struct mt76_dev mt76;
281 struct mt76_phy mphy;
282 };
283
284 struct mt7915_hif *hif2;
285 struct mt7915_reg_desc reg;
286 u8 q_id[MT7915_MAX_QUEUE];
287 u32 q_int_mask[MT7915_MAX_QUEUE];
288 u32 wfdma_mask;
289
290 const struct mt76_bus_ops *bus_ops;
291 struct tasklet_struct irq_tasklet;
292 struct mt7915_phy phy;
293
294 /* monitor rx chain configured channel */
295 struct cfg80211_chan_def rdd2_chandef;
296 struct mt7915_phy *rdd2_phy;
297
298 u16 chainmask;
299 u16 chainshift;
300 u32 hif_idx;
301
302 struct work_struct init_work;
303 struct work_struct rc_work;
304 struct work_struct reset_work;
305 wait_queue_head_t reset_wait;
306 u32 reset_state;
307
308 struct list_head sta_rc_list;
309 struct list_head sta_poll_list;
310 struct list_head twt_list;
311 spinlock_t sta_poll_lock;
312
313 u32 hw_pattern;
314
315 bool dbdc_support;
316 bool flash_mode;
317 bool muru_debug;
318 bool ibf;
319
320 struct dentry *debugfs_dir;
321 struct rchan *relay_fwlog;
322
323 void *cal;
324
325 struct {
326 u8 debug_wm;
327 u8 debug_wa;
328 u8 debug_bin;
329 } fw;
330
331 struct {
332 u16 table_mask;
333 u8 n_agrt;
334 } twt;
335
336 struct reset_control *rstc;
337 void __iomem *dcm;
338 void __iomem *sku;
339 };
340
341 enum {
342 WFDMA0 = 0x0,
343 WFDMA1,
344 WFDMA_EXT,
345 __MT_WFDMA_MAX,
346 };
347
348 enum {
349 MT_RX_SEL0,
350 MT_RX_SEL1,
351 MT_RX_SEL2, /* monitor chain */
352 };
353
354 enum mt7915_rdd_cmd {
355 RDD_STOP,
356 RDD_START,
357 RDD_DET_MODE,
358 RDD_RADAR_EMULATE,
359 RDD_START_TXQ = 20,
360 RDD_CAC_START = 50,
361 RDD_CAC_END,
362 RDD_NORMAL_START,
363 RDD_DISABLE_DFS_CAL,
364 RDD_PULSE_DBG,
365 RDD_READ_PULSE,
366 RDD_RESUME_BF,
367 RDD_IRQ_OFF,
368 };
369
370 static inline struct mt7915_phy *
mt7915_hw_phy(struct ieee80211_hw * hw)371 mt7915_hw_phy(struct ieee80211_hw *hw)
372 {
373 struct mt76_phy *phy = hw->priv;
374
375 return phy->priv;
376 }
377
378 static inline struct mt7915_dev *
mt7915_hw_dev(struct ieee80211_hw * hw)379 mt7915_hw_dev(struct ieee80211_hw *hw)
380 {
381 struct mt76_phy *phy = hw->priv;
382
383 return container_of(phy->dev, struct mt7915_dev, mt76);
384 }
385
386 static inline struct mt7915_phy *
mt7915_ext_phy(struct mt7915_dev * dev)387 mt7915_ext_phy(struct mt7915_dev *dev)
388 {
389 struct mt76_phy *phy = dev->mt76.phys[MT_BAND1];
390
391 if (!phy)
392 return NULL;
393
394 return phy->priv;
395 }
396
mt7915_check_adie(struct mt7915_dev * dev,bool sku)397 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)
398 {
399 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;
400
401 if (!is_mt7986(&dev->mt76))
402 return 0;
403
404 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;
405 }
406
407 extern const struct ieee80211_ops mt7915_ops;
408 extern const struct mt76_testmode_ops mt7915_testmode_ops;
409 extern struct pci_driver mt7915_pci_driver;
410 extern struct pci_driver mt7915_hif_driver;
411 extern struct platform_driver mt7986_wmac_driver;
412
413 #ifdef CONFIG_MT7986_WMAC
414 int mt7986_wmac_enable(struct mt7915_dev *dev);
415 void mt7986_wmac_disable(struct mt7915_dev *dev);
416 #else
mt7986_wmac_enable(struct mt7915_dev * dev)417 static inline int mt7986_wmac_enable(struct mt7915_dev *dev)
418 {
419 return 0;
420 }
421
mt7986_wmac_disable(struct mt7915_dev * dev)422 static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
423 {
424 }
425 #endif
426 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
427 void __iomem *mem_base, u32 device_id);
428 void mt7915_wfsys_reset(struct mt7915_dev *dev);
429 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
430 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
431 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
432
433 int mt7915_register_device(struct mt7915_dev *dev);
434 void mt7915_unregister_device(struct mt7915_dev *dev);
435 int mt7915_eeprom_init(struct mt7915_dev *dev);
436 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
437 struct mt7915_phy *phy);
438 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
439 struct ieee80211_channel *chan,
440 u8 chain_idx);
441 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band);
442 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);
443 void mt7915_dma_prefetch(struct mt7915_dev *dev);
444 void mt7915_dma_cleanup(struct mt7915_dev *dev);
445 int mt7915_mcu_init(struct mt7915_dev *dev);
446 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
447 struct mt7915_vif *mvif,
448 struct mt7915_twt_flow *flow,
449 int cmd);
450 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy,
451 struct ieee80211_vif *vif, bool enable);
452 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
453 struct ieee80211_vif *vif, int enable);
454 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
455 struct ieee80211_sta *sta, bool enable);
456 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
457 struct ieee80211_ampdu_params *params,
458 bool add);
459 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
460 struct ieee80211_ampdu_params *params,
461 bool add);
462 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif,
463 struct cfg80211_he_bss_color *he_bss_color);
464 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
465 int enable, u32 changed);
466 int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif,
467 bool enable);
468 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
469 struct ieee80211_sta *sta, bool changed);
470 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
471 struct ieee80211_sta *sta);
472 int mt7915_set_channel(struct mt7915_phy *phy);
473 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);
474 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);
475 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req);
476 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
477 struct ieee80211_vif *vif,
478 struct ieee80211_sta *sta,
479 void *data, u32 field);
480 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
481 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
482 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
483 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
484 bool hdr_trans);
485 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode,
486 u8 en);
487 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);
488 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable);
489 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy);
490 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len);
491 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action);
492 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);
493 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
494 const struct mt7915_dfs_pulse *pulse);
495 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
496 const struct mt7915_dfs_pattern *pattern);
497 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val);
498 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev);
499 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy);
500 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch);
501 int mt7915_mcu_get_temperature(struct mt7915_phy *phy);
502 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state);
503 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif,
504 struct ieee80211_sta *sta, struct rate_info *rate);
505 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy,
506 struct cfg80211_chan_def *chandef);
507 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set);
508 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
509 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
510 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
511 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
512 void mt7915_mcu_exit(struct mt7915_dev *dev);
513
mt7915_wtbl_size(struct mt7915_dev * dev)514 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
515 {
516 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
517 }
518
mt7915_eeprom_size(struct mt7915_dev * dev)519 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)
520 {
521 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;
522 }
523
524 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
525 u32 clear, u32 set);
526
mt7915_irq_enable(struct mt7915_dev * dev,u32 mask)527 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)
528 {
529 if (dev->hif2)
530 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask);
531 else
532 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
533
534 tasklet_schedule(&dev->irq_tasklet);
535 }
536
mt7915_irq_disable(struct mt7915_dev * dev,u32 mask)537 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)
538 {
539 if (dev->hif2)
540 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0);
541 else
542 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
543 }
544
545 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw);
546 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);
547 void mt7915_mac_reset_counters(struct mt7915_phy *phy);
548 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);
549 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy);
550 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
551 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
552 struct ieee80211_key_conf *key,
553 enum mt76_txq_id qid, u32 changed);
554 void mt7915_mac_set_timing(struct mt7915_phy *phy);
555 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
556 struct ieee80211_sta *sta);
557 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
558 struct ieee80211_sta *sta);
559 void mt7915_mac_work(struct work_struct *work);
560 void mt7915_mac_reset_work(struct work_struct *work);
561 void mt7915_mac_sta_rc_work(struct work_struct *work);
562 void mt7915_mac_update_stats(struct mt7915_phy *phy);
563 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
564 struct mt7915_sta *msta,
565 u8 flowid);
566 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
567 struct ieee80211_sta *sta,
568 struct ieee80211_twt_setup *twt);
569 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
570 enum mt76_txq_id qid, struct mt76_wcid *wcid,
571 struct ieee80211_sta *sta,
572 struct mt76_tx_info *tx_info);
573 void mt7915_tx_token_put(struct mt7915_dev *dev);
574 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
575 struct sk_buff *skb);
576 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
577 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
578 void mt7915_stats_work(struct work_struct *work);
579 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);
580 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);
581 void mt7915_set_stream_he_caps(struct mt7915_phy *phy);
582 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);
583 void mt7915_update_channel(struct mt76_phy *mphy);
584 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable);
585 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy, void *ms);
586 int mt7915_init_debugfs(struct mt7915_phy *phy);
587 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len);
588 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len);
589 #ifdef CONFIG_MAC80211_DEBUGFS
590 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
591 struct ieee80211_sta *sta, struct dentry *dir);
592 #endif
593
594 #endif
595